WO2014172973A1 - 像素电路和有机发光显示器 - Google Patents

像素电路和有机发光显示器 Download PDF

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Publication number
WO2014172973A1
WO2014172973A1 PCT/CN2013/077428 CN2013077428W WO2014172973A1 WO 2014172973 A1 WO2014172973 A1 WO 2014172973A1 CN 2013077428 W CN2013077428 W CN 2013077428W WO 2014172973 A1 WO2014172973 A1 WO 2014172973A1
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Prior art keywords
thin film
transistor
driving
film transistor
capacitor
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PCT/CN2013/077428
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English (en)
French (fr)
Inventor
王颖
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/344,491 priority Critical patent/US9311852B2/en
Publication of WO2014172973A1 publication Critical patent/WO2014172973A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of organic light emitting display, and in particular to a pixel circuit and an organic light emitting display including the pixel circuit. Background technique
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • OLED Organic Light-Emitting Diode
  • a large driving current is required.
  • Low temperature polysilicon technology is the best choice for AMOLED display backplanes due to its high mobility.
  • the problem of the threshold voltage Vth drift of the thin film transistor inherent in the low-temperature polysilicon technology causes the output current of the pixel circuit to be uneven, thereby also causing uneven display brightness.
  • the pixel circuit can output a uniform current, thereby making the brightness of the light emitting diode in the pixel circuit uniform, thereby making the display brightness of the organic light emitting display including the pixel circuit uniform.
  • a pixel circuit includes a driving thin film transistor and a light emitting diode, wherein the light emitting diode is connected in series between a low level input end and a high level input end of a driving power source, wherein
  • the pixel circuit further includes a first capacitor and a driving control unit, wherein the first end of the first capacitor is electrically connected to the first pole of the driving thin film transistor through the driving control unit, and the second end of the first capacitor
  • the terminal is connected to the gate of the driving thin film transistor, and the second electrode of the driving thin film transistor and the gate of the driving thin film transistor are electrically connected by the driving control unit, the driving control unit and the gate line and the data line Connecting, the driving control unit controls a connection between a first end of the first capacitor and a first electrode of the driving thin film transistor, and turns on a gate of the driving thin film transistor in a data writing phase
  • the connection between the second poles of the driving thin film transistor is turned on, and the driving thin film transistor
  • the pixel circuit further includes a second capacitor, the first end of the second capacitor and the first A second end of the capacitor is connected, and the second end of the second capacitor is electrically connected to the data line through the driving control unit.
  • the driving control unit further includes a first driving control transistor, a gate of the first driving control transistor is connected to the gate line, and a first pole of the first driving control transistor is connected to a data line, The second pole of the first drive control transistor is coupled to the second end of the second capacitor.
  • the pixel circuit further includes an initialization unit that provides a low level, the initialization unit being electrically connected to the second end of the first capacitor and the first end of the second capacitor.
  • the initialization unit includes an initialization transistor, a first pole of the initialization transistor is connected to a second end of the first capacitor and a first end of the second capacitor, and a second pole of the initialization transistor is The low level input terminal is connected, and the gate of the initialization transistor is connected to the reset signal input end.
  • the driving control unit includes a second driving control transistor and a third driving control transistor, a gate of the second driving control transistor is connected to the gate line, and a first pole of the second driving control transistor is a second pole of the driving thin film transistor is connected, a second pole of the second driving control transistor is connected to a gate of the driving thin film transistor, and a gate of the third driving control transistor is connected to a gate line, A first pole of the third driving control transistor is connected to the first end of the first capacitor, and a second pole of the third driving control transistor is connected to the first pole of the driving thin film transistor.
  • the pixel circuit further includes a light emission control unit, the light emission control unit is connected to the light emission control line, and the light emission control unit is capable of turning on the high level input end of the driving power source according to the signal given by the light emission control line. a connection to the first pole of the driving thin film transistor, and/or a connection between the low level input terminal of the driving power source and the second electrode of the driving thin film transistor.
  • the light emission control unit includes a first light emission control transistor and a second light emission control transistor, a gate of the first light emission control transistor is connected to the light emission control line, and a first pole of the first light emission control transistor Connected to the first pole of the driving thin film transistor, the second pole of the first light emitting control transistor is connected to a high level input end of the driving power source, and the gate of the second light emitting control transistor and the light emitting a control line is connected, a first pole of the second light emission control transistor is connected to a second pole of the driving thin film transistor, and a second pole of the second light emitting control transistor is connected to an anode of the light emitting diode, the light emitting A cathode of the diode is coupled to a low level input of the drive power source.
  • the driving thin film transistor, the first driving control transistor, the second driving The motion control transistor, the third drive control transistor, the initialization transistor, the first light emission control transistor, and the second light emission control transistor are all p-type transistors.
  • an organic light emitting display wherein the organic light emitting display comprises the above pixel circuit provided by the present invention.
  • the first capacitor records the gate voltage of the driving thin film transistor and holds it to the LED lighting stage of the pixel circuit.
  • the driving thin film transistor In the LED OLED illumination stage of the pixel circuit, the driving thin film transistor is in a saturated state, the gate voltage of the driving thin film transistor is the voltage V N1 -V th held by the first capacitor, the DTFT , the gate of the driving thin film transistor
  • the formula for calculating the drain current of the driving thin film transistor is as follows:
  • the drain current of the driving thin film transistor is independent of the threshold voltage of the driving thin film transistor (in other words, the threshold voltage of the driving thin film transistor is compensated), thereby solving the brightness unevenness and brightness of the AMOLED panel.
  • FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit provided by the present invention.
  • FIG. 2 is a circuit diagram of a second embodiment of a pixel circuit provided by the present invention.
  • 3 is a timing diagram of control signals of a pixel circuit provided by the present invention
  • 4 is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 at a stage of tl;
  • Figure 5 is an equivalent circuit diagram of the pixel circuit shown in Figure 2 at the stage t2;
  • Fig. 6 is an equivalent circuit diagram of the pixel circuit shown in Fig. 2 at the stage t3. Description of the reference numerals
  • T1 first drive control transistor
  • T2 second drive control transistor
  • T3 Initialization transistor
  • T4 Second illumination control transistor
  • T5 first light control transistor
  • T6 third drive control transistor
  • ELVSS Low-level input of the driver supply
  • the embodiment of the present invention provides a pixel circuit.
  • the pixel circuit includes a driving thin film transistor DTFT and a light emitting diode OLED.
  • the light emitting diode OLED is connected in series with a low level input terminal ELVSS and a high level input terminal ELVDD of the driving power source. between.
  • the pixel circuit further includes a first capacitor C1 and a driving control unit 10, and the first end of the first capacitor C1 passes through the driving control unit 10 and drives the first pole of the thin film transistor DTFT (the source and the drain of the driving thin film transistor DTFT) One of the poles is electrically connected, the second end of the first capacitor C1 is connected to the gate of the driving thin film transistor DTFT, and the second pole of the driving thin film transistor DTFT (the other of the source and the drain of the driving thin film transistor DTFT)
  • the gate of the driving thin film transistor DTFT is electrically connected through the driving control unit 10, and the driving control unit 10 is connected to the gate line GATE and the data line DATA, and the driving control unit 10 is controlled in the data writing phase (ie, the t2 phase in FIG.
  • the first and second poles of the driving thin film transistor DTFT are connected in series between the low level input terminal ELVSS and the high level input terminal ELVDD of the driving power source.
  • the connection between the gate of the driving thin film transistor DTFT and the first electrode of the driving thin film transistor DTFT, and the gate of the driving thin film transistor DTFT and the second electrode of the driving thin film transistor DTFT is broken.
  • the driving control unit 10 is configured to turn on the first end of the first capacitor C1 and the first pole of the driving thin film transistor DTFT.
  • V N1 refers to the voltage at the node N1 where the second end of the first capacitor C1 is connected to the data line DATA.
  • V N1 is independent of the threshold voltage V th of the driving thin film transistor DTFT and the DTFT .
  • the light emitting diode OLED light emitting phase ie, the t3 phase in FIG.
  • the gate voltage (V N1 - V th , DTFT ) of the driving thin film transistor DTFT is held by the first capacitor C1, and therefore, in the light emitting diode OLED light emitting stage,
  • the current I d passing between the first pole of the driving thin film transistor DTFT and the second electrode of the driving thin film transistor DTFT is: V t DTFT f
  • ⁇ is the field effect mobility of the driving thin film transistor DTFT
  • C. x is a capacitance per unit area of the gate insulating layer of the driving thin film transistor DTFT
  • W is the channel width of the driving thin film transistor DTFT
  • L is the channel length of the driving thin film transistor DTFT
  • V dd is the voltage input to the high level input of the drive power supply.
  • the threshold voltage Vth , DTF1 ⁇ drift of the driving thin film transistor DTFT does not affect the current outputted by the driving thin film transistor DTFT (ie, the drain current of the driving thin film transistor DTFT), and the brightness of the light emitting diode OLED is not affected. influences.
  • the pixel circuit may further include a second capacitor C2, the first end of the second capacitor C2 is connected to the second end of the first capacitor C1, and the second end of the second capacitor C2 is driven by the control unit 10 and the data.
  • Line DATA is electrically connected.
  • the data line DATA is charged to the second capacitor C2 through the drive control unit 10.
  • the second capacitor C2 blocks the gate of the driving thin film transistor DTFT from the data line DATA, thereby preventing leakage.
  • the driving control unit 10 may further include a first driving control transistor T1.
  • a gate of the first driving control transistor T1 is connected to the gate line GATE, and a first electrode of the first driving control transistor T1 (one of a source and a drain of the first driving control transistor T1) is connected to the data line DATA, The second electrode of the first driving control transistor T1 (the other of the source and the drain of the first driving control transistor T1) is connected to the second terminal of the second capacitor C2.
  • the signal of the gate line GATE and the signal of the data line DATA are valid, and the first driving control transistor T1 is turned on (the first pole and the second of the first driving control transistor T1) The pole line is turned on, and the data line DATA is charged to the second capacitor C2 through the first driving control transistor T1.
  • the first driving control transistor T1 is turned off (ie, the source and the drain of the first driving control transistor T1 are turned off), thereby preventing the driving of the thin film transistor DTFT.
  • the gate leaks to the data line DATA.
  • the pixel circuit may further include an initializing unit 30 that supplies a low level.
  • the initializing unit 30 is electrically connected to the common terminal side of the first capacitor C1 and the second capacitor C2, and the second end of the first capacitor C1 and the first end of the second capacitor C2 are common ends.
  • the initialization phase ie, the tl phase in FIG. 3
  • the first capacitor C1 and the second capacitor C2 are discharged by the initializing unit 30, and the completion is completed.
  • Initialization of the pixel circuit may include an initialization transistor T3, and a first pole of the initialization transistor T3 (one of a source and a drain of the initialization transistor T3) is connected to the second end of the first capacitor C1.
  • a second pole of the transistor T3 (the other one of the source and the drain of the initialization transistor T3) is initialized with the first terminal of the second capacitor C2 and the low level input terminal REF (the low level input terminal REF can The low level connection is provided, and the gate of the initialization transistor T3 is connected to the reset signal input terminal RESET.
  • the reset signal input to the reset signal input terminal RESET is asserted, and the initialization transistor T3 is turned on, thereby discharging the first capacitor C1 and the second capacitor C2 to complete the initialization of the pixel state.
  • the drive control unit 10 may further include a second drive control transistor T2 and a third drive control transistor T6.
  • the gate of the second driving control transistor T2 is connected to the gate line GATE, and the second driving control transistor T2 has a first electrode (one of a source and a drain of the second driving control transistor T2) and a second driving thin film transistor DTFT
  • the second connection of the second driving control transistor T2 (the other of the source and the drain of the second driving control transistor T2) is electrically connected to the gate of the driving thin film transistor DTFT, and the gate of the third driving control transistor T6 is connected.
  • the pole is connected to the gate line GATE, and the first pole of the third driving control transistor T6 (one of the source and the drain of the third driving control transistor T6) is connected to the first end of the first capacitor C1, and the third driving control transistor
  • the second pole of T6 (the other of the source and the drain of the third drive control transistor T6) is connected to the first pole of the driving thin film transistor DTFT.
  • the signals of the gate line GATE and the data line DATA are valid, and the second driving control transistor T2 and the third driving control transistor T6 are turned on to form a diode connection for driving the thin film transistor DTFT.
  • the initialization phase i.e., the t2 phase shown in Fig. 3
  • the LED OLED lighting phase 13
  • the second drive control transistor T2 and the third drive control transistor T6 are turned off.
  • the light emitting diode OLED is connected in series between the low level input terminal ELVSS and the high level input terminal ELVDD of the driving power source, and the first pole and the second pole of the driving thin film transistor DTFT are also connected in series to the low level of the driving power source.
  • the driving thin film transistor DTFT when the driving thin film transistor DTFT is turned on, current can flow from the high level input terminal ELVDD of the driving power source to the low level input terminal ELVSS of the driving power source, thereby flowing through the light emitting diode
  • the OLED enables the light emitting diode OLED to emit light.
  • the pixel circuit further includes an illumination control unit 20, and the illumination control unit 20 is connected to the illumination control line EM, and the illumination control The unit 20 can turn on the high-level input terminal ELVDD of the driving power source and the first electrode of the driving thin film transistor DTFT according to the signal given by the light-emitting control line EM, and/or input the driving power source low level to the ELVSS terminal and The second pole of the driving thin film transistor DTFT is turned on.
  • the driving thin film transistor DTFT is disconnected from the gate line GATE and the data line DATA.
  • the first capacitor C1 maintains the gate voltage of the driving thin film transistor DTFT, and therefore, the driving thin film transistor DTFT is turned on.
  • the signal of the illumination control line EM is valid, the current supplied from the driving power source can flow from the high level input terminal ELVDD to the low level input terminal ELVSS, thereby causing the light emitting diode OLED to emit light.
  • the high level input terminal ELVDD of the driving power source is disconnected from the low level input terminal ELVSS of the driving power source, and the light emitting diode OLED does not emit light. .
  • the light emission control unit 20 may include a first light emission control transistor T5 and a second light emission control transistor T4, and the gate of the first light emission control transistor T5 is connected to the light emission control line EM.
  • a first pole of the first light-emitting control transistor T5 (one of a source and a drain of the first light-emitting control transistor T5) is connected to a first pole of the driving thin film transistor DTFT, and a second pole of the first light-emitting control transistor T5 ( The other of the source and the drain of the first light-emitting control transistor T5 is connected to the high-level input terminal ELVDD of the driving power source, and the gate of the second light-emitting control transistor T4 is connected to the light-emission control line EM, and the second light-emitting control transistor
  • the first pole of T4 (one of the source and the drain of the second light-emission control transistor T4) is connected to the second pole of the driving thin film transistor DTFT, and the second pole of the second light-emitting control transistor T4 (the second light-emitting control transistor T4)
  • the other of the source and the drain is connected to the anode of the light emitting diode OLED, and the cathode
  • the light emitting diode OLED may also be connected in series between the first pole of the first light emitting control transistor T5 and the first pole of the driving thin film transistor DTFT.
  • the first illumination control transistor T5 and the second illumination control transistor T4 are both turned on, and the current can flow from the high level input terminal ELVDD of the driving power source to the low of the driving power source.
  • the level input terminal ELVSS allows the light emitting diode OLED to emit light.
  • the other light-emitting diode T5 is turned off at a stage other than the light-emitting diode OLED light-emitting stage (ie, the t3 stage shown in FIG. 3), and the high-level input of the driving power source is turned off.
  • the input ELVDD is disconnected from the first electrode of the driving thin film transistor DTFT, so that the high level of the high-level input terminal ELVDD of the driving power source can be prevented from affecting the potential of the first electrode of the driving thin film transistor DTFT.
  • the driving thin film transistor DTFT In the data writing phase (ie, the t2 phase shown in FIG. 3), since the gate of the driving thin film diode DTFT is turned on with the second electrode of the driving thin film transistor, the driving thin film transistor DTFT at this time actually forms a critical conduction. The diode of the state, the second light-emitting diode T4 is turned off, so that the leakage current of the driving thin film transistor DTFT can be prevented from flowing to the light-emitting diode OLED.
  • the driving thin film transistor DTFT, the first driving control transistor T1, the second driving control transistor ⁇ 2, the third driving control transistor ⁇ 6, the initialization transistor ⁇ 3, the first illuminating control transistor ⁇ 5, and the second illuminating control transistor ⁇ 4 Types are not specified.
  • the types of the first driving control transistor T1, the second driving control transistor T2, and the third driving control transistor T6 should be the same (both ⁇ -type or ⁇ -type), the first illuminating control transistor ⁇ 5 and the second illuminating control transistor
  • the type of ⁇ 4 should be the same (both ⁇ type or ⁇ type).
  • the driving thin film transistor DTFT, the first driving control transistor T1, the second driving control transistor ⁇ 2, the third driving control transistor ⁇ 6, the initializing transistor ⁇ 3, the first illuminating control transistor ⁇ 5, and The second light emission control transistors ⁇ 4 are all ⁇ -type transistors.
  • the low level signals of the gate line GATE, the data line DATA, and the illumination control line EM are valid signals.
  • Fig. 4 is an equivalent circuit diagram when the pixel circuit of Fig. 2 is in the initialization phase (i.e., the tl phase shown in Fig. 3), the solid line portion represents the energized portion, and the broken line portion represents the portion that is not energized.
  • the reset signal input terminal RESET provides a valid signal to the initialization transistor T3, so that the initialization transistor T3 is turned on, and the residual power in the first capacitor C1 and the second capacitor C2 flows to the low-level input terminal REF, at this time, driving
  • the gate voltage of the thin film transistor DTFT is the voltage V rcf supplied from the low level input terminal REF
  • the voltage of the first terminal of the second capacitor C2 is the voltage V ref of the low level input terminal REF.
  • Figure 5 is an equivalent circuit diagram when the pixel circuit of Figure 2 is in the data writing phase (i.e., the t2 phase shown in Figure 3).
  • the solid line portion represents the energized portion, and the dotted portion Represents the part that is not powered.
  • the signal input to the reset signal input terminal RESET transitions to a high level
  • the initialization transistor T3 is turned off
  • the first capacitor C1 remains at the low level input terminal.
  • the voltage of REF is V ref .
  • the gate line GATE signal is valid
  • the first driving control transistor T1 is turned on
  • the data line DATA writes the display data signal into the pixel circuit.
  • the voltage at the first terminal N1 node of the second capacitor C2 is the voltage V of the data line DATA.
  • the sum of data and the voltage V ref of the low level input REF ie, V data +V ref ).
  • the second driving control transistor T2 is turned on, at this time, the gate of the driving thin film transistor DTFT is connected to the second electrode of the driving thin film transistor DTFT, and the driving thin film transistor DTFT at this time actually forms a
  • the diode in the critical conduction state drives the threshold voltage Vth of the thin film transistor DTFT, and the DTFT is recorded and held by the first capacitor C1.
  • the gate voltage of the driving thin film transistor is (V data + V ref - V th , DTFT ), and is stored by the first capacitor C1.
  • the light emission control line EM is at a high level, and the second light emission control diode T4 is turned off, and the operation of writing data to the pixel does not cause the light emitting state of the light emitting diode OLED. It has an effect and avoids the flicker of the display.
  • the illuminating control line EM is at a high level to ensure that the first illuminating control diode T5 is turned off, ensuring that the driving thin film transistor DTFT is disconnected from the high level input terminal ELVDD of the driving power source, thereby avoiding driving due to leakage of the driving thin film transistor DTFT.
  • the gate voltage of the thin film transistor DTFT causes an adverse effect.
  • the gate line GATE signal is valid, the third driving control transistor T6 is turned on, the first pole of the driving thin film transistor DTFT is prevented from being suspended, and the third driving control transistor T6 can drive the gate voltage of the driving thin film transistor DTFT to the driving.
  • the first pole of the thin film transistor DTFT does not affect the gate voltage of the driving thin film transistor DTFT even if the driving thin film transistor DTFT has a leakage phenomenon.
  • Figure 6 is an equivalent circuit diagram when the pixel circuit of Figure 2 is in the light-emitting diode OLED lighting stage (i.e., stage t3 shown in Figure 3). As in Figures 4 and 5, the solid line portion represents the energized portion. The dotted line represents the part that is not energized.
  • the gate line GATE signal jumps to a high level, and the first driving control transistor T1, the second driving control transistor ⁇ 2, and the third driving control transistor ⁇ 3 are turned off, driving the gate voltage of the thin film transistor (Vdata+Vref ⁇ V th , DT F T) held by the first capacitor CI, the driving voltage to ensure that the thin film transistor operates in a saturation region at this time, the driving thin film transistor DTFT output current I d is:
  • the second light-emitting control transistor T4 is turned on, and the current I d flows into the light-emitting diode OLED through the second light-emitting control transistor T4 to illuminate the display.
  • the low level of the initialization unit 30 can be grounded. If the high-level input ELVDD of the drive power supply has a voltage drop due to wire resistance or parasitic resistance, the low level of the initialization unit 30 can be adjusted to cancel the voltage drop caused by the wire resistance or the parasitic resistance. In this case, the pixel circuit can also compensate for fluctuations in the wire resistance or parasitic resistance of the driving power source.
  • an organic light emitting display wherein the organic light emitting display comprises the above pixel circuit provided by the present invention. Since the pixel circuit can output a uniform current to make the luminance of the light emitting diode in the pixel circuit uniform, the organic light emitting display including the pixel circuit can have uniform display brightness.
  • An exemplary embodiment however, the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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Abstract

一种像素电路及一种有机发光显示器。该像素电路包括驱动薄膜晶体管和发光二极管，该发光二极管串联在驱动电源的低电平输入端和高电平输入端之间，像素电路还包括第一电容和驱动控制单元，第一电容的第一端通过驱动控制单元与驱动薄膜晶体管的第一极电连接，第一电容的第二端与驱动薄膜晶体管的栅极连接，驱动薄膜晶体管的第二极和驱动薄膜晶体管的栅极通过驱动控制单元电连接，驱动控制单元与栅线和数据线连接。该像素电路可以输出均匀的电流，从而使像素电路中的发光二极管亮度均匀，进而使得包括像素电路的有机发光显示器的显示亮度均匀。

Description

像素电路和有机发光显示器 技术领域
本发明涉及有机发光显示领域， 具体地， 涉及一种像素电路和一种包括 该像素电路的有机发光显示器。 背景技术
AMOLED(有源发光二极管， Active Matrix/Organic Light Emitting Diode ) 显示背板的发光亮度和提供给 OLED (有机发光二极管， Organic Light-Emitting Diode )的驱动电流大小成正比。 为了实现最佳的显示效果， 需 要较大的驱动电流。 低温多晶硅技术由于可以提供较高的迁移率而成为 AMOLED显示背板的最佳选择。但是低温多晶硅技术固有的薄膜晶体管阈值 电压 Vth漂移的问题造成像素电路输出的电流不均匀， 从而也使得显示亮度 不均匀。
因此，如何使像素电路输出均匀的电流成为本领域亟待解决的技术问题。 发明内容
本发明的目的在于提供一种像素电路和一种包括该像素电路的有机发光 显示器。 所述像素电路可以输出均匀的电流， 从而使像素电路中的发光二极 管亮度均匀，进而使得包括所述像素电路的有机发光显示器的显示亮度均匀。
作为本发明的一个方面， 提供一种像素电路， 所述像素电路包括驱动薄 膜晶体管和发光二极管， 所述发光二极管串联在驱动电源的低电平输入端和 高电平输入端之间， 其中， 所述像素电路还包括第一电容和驱动控制单元， 所述第一电容的第一端通过所述驱动控制单元与所述驱动薄膜晶体管的第一 极电连接， 所述第一电容的第二端与所述驱动薄膜晶体管的栅极连接， 所述 驱动薄膜晶体管的第二极和所述驱动薄膜晶体管的栅极通过所述驱动控制单 元电连接， 所述驱动控制单元与栅线和数据线连接， 所述驱动控制单元在数 据写入阶段控制导通所述第一电容的第一端与所述驱动薄膜晶体管的第一极 之间的连接、 导通所述驱动薄膜晶体管的栅极与所述驱动薄膜晶体管的第二 极导通之间的连接， 所述驱动薄膜晶体管导通。
优选地， 所述像素电路还包括第二电容， 该第二电容的第一端与所述第 一电容的第二端连接， 所述第二电容的第二端通过所述驱动控制单元与所述 数据线电连接。
优选地， 所述驱动控制单元还包括第一驱动控制晶体管， 所述第一驱动 控制晶体管的栅极与所述栅线连接， 所述第一驱动控制晶体管的第一极与数 据线连接，所述第一驱动控制晶体管的第二极与所述第二电容的第二端连接。
优选地， 所述像素电路还包括提供低电平的初始化单元， 所述初始化单 元电连接到所述第一电容的第二端和所述第二电容的第一端。
优选地， 所述初始化单元包括初始化晶体管， 所述初始化晶体管的第一 极连接到所述第一电容的第二端和所述第二电容的第一端， 所述初始化晶体 管的第二极与低电平输入端连接， 所述初始化晶体管的栅极与复位信号输入 端相连。
优选地， 所述驱动控制单元包括第二驱动控制晶体管和第三驱动控制晶 体管， 所述第二驱动控制晶体管的栅极与所述栅线连接， 所述第二驱动控制 晶体管的第一极与所述驱动薄膜晶体管的第二极连接， 所述第二驱动控制晶 体管的第二极与所述驱动薄膜晶体管的栅极连接， 所述第三驱动控制晶体管 的栅极与栅线连接， 所述第三驱动控制晶体管的第一极与所述第一电容的第 一端连接， 所述第三驱动控制晶体管的第二极与所述驱动薄膜晶体管的第一 极连接。
优选地， 所述像素电路还包括发光控制单元， 所述发光控制单元与发光 控制线连接， 所述发光控制单元能够根据所述发光控制线给出的信号导通驱 动电源的高电平输入端与所述驱动薄膜晶体管的第一极之间的连接， 和 /或导 通所述驱动电源低电平输入端与所述驱动薄膜晶体管的第二极之间的连接。
优选地， 所述发光控制单元包括第一发光控制晶体管和第二发光控制晶 体管， 所述第一发光控制晶体管的栅极与所述发光控制线连接， 所述第一发 光控制晶体管的第一极与所述驱动薄膜晶体管的第一极连接， 所述第一发光 控制晶体管的第二极与所述驱动电源的高电平输入端连接， 所述第二发光控 制晶体管的栅极与所述发光控制线连接， 所述第二发光控制晶体管的第一极 与所述驱动薄膜晶体管的第二极连接， 所述第二发光控制晶体管的第二极与 所述发光二极管的阳极连接， 所述发光二极管的阴极与所述驱动电源的低电 平输入端连接。
优选地， 所述驱动薄膜晶体管、 所述第一驱动控制晶体管、 所述第二驱 动控制晶体管、 所述第三驱动控制晶体管、 所述初始化晶体管、 所述第一发 光控制晶体管和所述第二发光控制晶体管均为 p型晶体管。
作为本发明的另一个方面， 还提供一种有机发光显示器， 其中， 所述有 机发光显示器包括本发明所提供的上述像素电路。
在本发明提供的像素电路中， 在像素电路的数据写入阶段， 驱动控制单 元控制导通第一电容的第一端与所述驱动薄膜晶体管的第一极之间的连接， 导通所述驱动薄膜晶体管的栅极与所述驱动薄膜晶体管的第二极之间的连 接， 此时的驱动薄膜晶体管实际上形成了一个处于临界导通状态的二极管， 驱动薄膜晶体管的栅极电压 vg即为第一电容的第二端的电压 vN1减去所述驱 动薄膜晶体管的阈值电压 Vth,DTFT, (即， Vg=VN1-Vth,DTFT )。在该数据写入阶段， 第一电容将驱动薄膜晶体管的栅极电压记录下来并保持至像素电路的发光二 极管发光阶段。 在像素电路的发光二极管 OLED发光阶段， 驱动薄膜晶体管 处于饱和状态， 该驱动薄膜晶体管的栅极电压为第一电容所保持的电压 VN1-Vth,DTFT,所述驱动薄膜晶体管的栅极与第一极之间的电压 Vgs为该驱动薄 膜晶体管的第一极输入的电压 Vdd与该薄膜晶体管的栅极电压之差， 即， Vgs=Vdd- ( VN1-Vth,DTFT )。 而计算驱动薄膜晶体管的漏极电流的公式如下：
Figure imgf000005_0001
= -μ0οχ{ ΐφΜ - (VNl -Vt DTFT)-Vt DTFT f
Figure imgf000005_0002
通过上述公式可知， 在发光二极管的发光阶段， 驱动薄膜晶体管的漏极 电流与驱动薄膜晶体管的阈值电压无关 （换言之， 驱动薄膜晶体管的阈值电 压得到了补偿）进而解决了 AMOLED面板亮度不均匀和亮度衰减的问题。 附图说明
附图是用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与 下面的具体实施方式一起用于解释本发明， 但并不构成对本发明的限制。 在 附图中：
图 1是本发明所提供的像素电路的第一种实施方式的电路图；
图 2是本发明所提供的像素电路的第二种实施方式的电路图；
图 3是本发明所提供的像素电路的控制信号时序图； 图 4是图 2中所示的像素电路在 tl阶段的等效电路图；
图 5是图 2中所示的像素电路在 t2阶段的等效电路图；
图 6是图 2中所示的像素电路在 t3阶段的等效电路图。 附图标记说明
10: 驱动控制单元 20: 发光控制单元
30: 初始化单元 EM: 发光控制线
C1 : 第一电容 C2: 第二电容
T1 : 第一驱动控制晶体管 T2: 第二驱动控制晶体管
T3: 初始化晶体管 T4: 第二发光控制晶体管
T5: 第一发光控制晶体管 T6: 第三驱动控制晶体管
DTFT: 驱动薄膜晶体管 OLED: 发光二极管
GATE: 栅线 DATA: 数据线
ELVDD: 驱动电源的高电平输入端
ELVSS: 驱动电源的低电平输入端
RESET: 复位信号输入端 具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。 应当理解的是， 此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
本发明实施例提供一种像素电路， 如图 1所示， 该像素电路包括驱动薄 膜晶体管 DTFT和发光二极管 OLED, 发光二极管 OLED串联在驱动电源的 低电平输入端 ELVSS和高电平输入端 ELVDD之间。
其中， 所述像素电路还包括第一电容 C1和驱动控制单元 10, 第一电容 C1的第一端通过驱动控制单元 10与驱动薄膜晶体管 DTFT的第一极（驱动 薄膜晶体管 DTFT的源极和漏极中的一个）电连接，第一电容 C1的第二端与 驱动薄膜晶体管 DTFT的栅极连接， 驱动薄膜晶体管 DTFT的第二极（驱动 薄膜晶体管 DTFT的源极和漏极中的另一个）和驱动薄膜晶体管 DTFT的栅 极通过驱动控制单元 10电连接，驱动控制单元 10与栅线 GATE、数据线 DATA 连接， 驱动控制单元 10在数据写入阶段（即， 图 3中的 t2阶段）控制导通 第一电容 C1的第一端与驱动薄膜晶体管 DTFT的第一极之间的连接，并且控 制导通驱动薄膜晶体管 DTFT的栅极与驱动薄膜晶体管 DTFT的第二极之间 的连接， 此外还可以控制驱动薄膜晶体管 DTFT导通。
本领域技术人员应当理解的是， 驱动薄膜晶体管 DTFT的第一极和第二 极串联在驱动电源的低电平输入端 ELVSS和高电平输入端 ELVDD之间。 在 除数据写入阶段之外的其他阶段， 驱动薄膜晶体管 DTFT的栅极与该驱动薄 膜晶体管 DTFT第一极之间的连接， 以及驱动薄膜晶体管 DTFT的栅极与驱 动薄膜晶体管 DTFT的第二极之间的连接都是断开的。
在数据写入阶段， 栅线 GATE和数据线 DATA输入的信号有效（如图 3 所示）， 驱动控制单元 10使得导通第一电容 C1 的第一端与驱动薄膜晶体管 DTFT的第一极之间的连接， 导通驱动薄膜晶体管 DTFT的栅极与驱动薄膜 晶体管的第二极之间的连接， 此时的驱动薄膜晶体管 DTFT实际上形成了一 个处于临界导通状态的二极管， 此时驱动薄膜晶体管 DTFT 的阈值电压
Vth,DTFT被记录下来， 且由第一电容 C1存储。
由于此时驱动薄膜晶体管 DTFT的栅极电压为（ VN1-Vth,DTFT ),此处， VN1 指的是，第一电容 C1的第二端与数据线 DATA相连的节点 N1处的电压， VN1 与驱动薄膜晶体管 DTFT的阈值电压 Vth,DTFT无关。在发光二极管 OLED发光 阶段（即，图 3中的 t3阶段 ),驱动薄膜晶体管 DTFT的栅极电压（ VN1-Vth,DTFT ) 被第一电容 C1保持， 因此， 在发光二极管 OLED发光阶段， 驱动薄膜晶体 管 DTFT的第一极与驱动薄膜晶体管 DTFT的第二极之间经过的电流 Id (即， 驱动薄膜晶体管的源极与漏极之间经过的电流） 为： Vt DTFTf
Figure imgf000007_0001
其中， μ为驱动薄膜晶体管 DTFT的场效应迁移率；
C。x为驱动薄膜晶体管 DTFT的栅绝缘层单位面积电容；
W为驱动薄膜晶体管 DTFT的沟道宽度；
L为驱动薄膜晶体管 DTFT的沟道长度；
Vdd为驱动电源的高电平输入端输入的电压。
从上文中的描述可知， 驱动薄膜晶体管 DTFT的第一极与驱动薄膜晶体 管 DTFT的第二极之间经过的电流 Id与驱动薄膜二极管的阈值电压 ^^！^无 关。 因此， 驱动薄膜晶体管 DTFT的阈值电压 Vth,DTF1^々漂移不会对驱动薄膜 晶体管 DTFT输出的电流（即， 该驱动薄膜晶体管 DTFT的漏极电流）产生 影响， 发光二极管 OLED的亮度不会受到影响。
优选地， 所述像素电路还可以包括第二电容 C2, 该第二电容 C2的第一 端与第一电容 C1的第二端连接，第二电容 C2的第二端通过驱动控制单元 10 与数据线 DATA电连接。
在数据写入阶段（即图 3所示 t2阶段）， 数据线 DATA通过驱动控制单 元 10向第二电容 C2充电。 在发光二极管 OLED发光阶段 (即图 3所示 t3 阶段 ), 第二电容 C2将驱动薄膜晶体管 DTFT的栅极与数据线 DATA隔断， 从而可以防止漏电。
为了进一步防止在发光二极管 OLED发光阶段 ( 13阶段 )驱动薄膜晶体 管 DTFT的栅极漏电， 优选地， 如图 1所示， 驱动控制单元 10还可以包括第 一驱动控制晶体管 Tl。
第一驱动控制晶体管 T1 的栅极与栅线 GATE连接， 第一驱动控制晶体 管 T1的第一极（第一驱动控制晶体管 T1的源极和漏极中的一个 )与数据线 DATA连接， 所述第一驱动控制晶体管 T1 的第二极（第一驱动控制晶体管 T1的源极和漏极中的另一个）与所述第二电容 C2的第二端连接。
在数据写入阶段（即图 3所示 t2阶段）,栅线 GATE的信号和数据线 DATA 的信号有效， 第一驱动控制晶体管 T1导通（第一驱动控制晶体管 T1的第一 极和第二极导通 ),数据线 DATA通过第一驱动控制晶体管 T1向第二电容 C2 充电。 在发光二极管 OLED发光阶段（即图 3所示 t3阶段）， 第一驱动控制 晶体管 T1截止（即， 第一驱动控制晶体管 T1 的源极和漏极断开）， 从而可 以防止驱动薄膜晶体管 DTFT的栅极向数据线 DATA漏电。
为了消除第一电容 C1 和第二电容 C2 的残留电量对驱动薄膜晶体管 DTFT 的影响， 优选地， 所述像素电路还可以包括提供低电平的初始化单元 30。
初始化单元 30电连接在第一电容 C1和第二电容 C2的公共端一侧， 第 一电容 C1的第二端和第二电容 C2的第一端为公共端。 在进行数据写入阶段 (即图 3所示 t2阶段）之前， 可以先进行初始化阶段（即图 3中的 tl阶段）， 通过初始化单元 30对第一电容 C1和第二电容 C2进行放电， 完成所述像素 电路的初始化。 具体地， 如图 2所示， 初始化单元 30可以包括初始化晶体管 T3 , 该初 始化晶体管 T3的第一极（初始化晶体管 T3的源极与漏极中的一个）连接在 第一电容 C1的第二端和第二电容 C2的第一端之间， 初始化晶体管 T3的第 二极（初始化晶体管 T3的源极与漏极中的另一个）与低电平输入端 REF (该 低电平输入端 REF可以提供所述低电平）连接， 初始化晶体管 T3的栅极与 复位信号输入端 RESET相连。 在初始化阶段（tl 阶段）， 复位信号输入端 RESET输入的复位信号有效，初始化晶体管 T3导通，从而对第一电容 C1和 第二电容 C2进行放电， 完成像素状态的初始化。
作为本发明的一种实施方式， 优选地， 如图 2 所示， 驱动控制单元 10 还可以包括第二驱动控制晶体管 T2和第三驱动控制晶体管 T6。
第二驱动控制晶体管 Τ2的栅极与栅线 GATE连接， 第二驱动控制晶体 管 T2的第一极（第二驱动控制晶体管 T2的源极和漏极中的一个 )与驱动薄 膜晶体管 DTFT的第二极连接， 第二驱动控制晶体管 T2的第二极（第二驱动 控制晶体管 T2的源极和漏极中的另一个）与驱动薄膜晶体管 DTFT的栅极电 连接，第三驱动控制晶体管 T6的栅极与栅线 GATE连接， 第三驱动控制晶体 管 T6的第一极（第三驱动控制晶体管 T6的源极和漏极中的一个 )与第一电 容 C1的第一端连接， 第三驱动控制晶体管 T6的第二极（第三驱动控制晶体 管 T6的源极和漏极中的另一个 )与驱动薄膜晶体管 DTFT的第一极连接。
在数据写入阶段（即图 3所示 t2阶段）， 栅线 GATE和数据线 DATA的 信号有效， 第二驱动控制晶体管 T2和第三驱动控制晶体管 T6开启， 使驱动 薄膜晶体管 DTFT形成二极管连接。 在初始化阶段（即图 3所示 t2阶段 )和 发光二极管 OLED发光阶段 ( 13 )阶段， 第二驱动控制晶体管 T2和第三驱动 控制晶体管 T6截止。
如上所述， 发光二极管 OLED 串联在驱动电源的低电平输入端 ELVSS 和高电平输入端 ELVDD之间， 并且驱动薄膜晶体管 DTFT的第一极和第二 极也串联在驱动电源的低电平输入端 ELVSS和高电平输入端 ELVDD之间， 在驱动薄膜晶体管 DTFT 导通时， 电流可以从驱动电源的高电平输入端 ELVDD流向驱动电源的低电平输入端 ELVSS, 从而流经发光二极管 OLED, 使发光二极管 OLED发光。
为了便于控制发光二极管 OLED, 通常， 如图 2所示， 所述像素电路还 包括发光控制单元 20, 该发光控制单元 20与发光控制线 EM连接， 发光控 制单元 20可以根据发光控制线 EM给出的信号将驱动电源的高电平输入端 ELVDD与驱动薄膜晶体管 DTFT的第一极导通， 和 /或将所述驱动电源低电 平输入 ELVSS端与所述驱动薄膜晶体管 DTFT的第二极导通。
在发光二极管 OLED发光阶段 (即图 3所示 t3阶段）， 只有发光控制线 EM的信号有效，此时，驱动薄膜晶体管 DTFT与栅线 GATE和数据线 DATA 都是断开的。而第一电容 C1保持了驱动薄膜晶体管 DTFT的栅极电压，因此， 驱动薄膜晶体管 DTFT是导通状态。 并且， 由于发光控制线 EM的信号有效， 因此， 驱动电源提供的电流可以从高电平输入端 ELVDD 流向低电平输入端 ELVSS, 从而使发光二极管 OLED发光。
在发光二极管 OLED发光阶段（即图 3所示 t3阶段 )之外的其他阶段， 驱动电源的高电平输入端 ELVDD与驱动电源的低电平输入端 ELVSS是断开 的， 发光二极管 OLED不发光。
作为本发明的一种实施方式，如图 2所示，发光控制单元 20可以包括第 一发光控制晶体管 T5和第二发光控制晶体管 T4,第一发光控制晶体管 T5的 栅极与发光控制线 EM连接， 第一发光控制晶体管 T5的第一极（第一发光控 制晶体管 T5的源极和漏极中的一个）与驱动薄膜晶体管 DTFT的第一极连接， 第一发光控制晶体管 T5的第二极（第一发光控制晶体管 T5的源极和漏极中 的另一个） 与驱动电源的高电平输入端 ELVDD连接， 第二发光控制晶体管 T4的栅极与发光控制线 EM连接， 第二发光控制晶体管 T4的第一极（第二 发光控制晶体管 T4的源极和漏极中的一个）与驱动薄膜晶体管 DTFT的第二 极连接， 第二发光控制晶体管 T4的第二极（第二发光控制晶体管 T4的源极 和漏极中的另一个）与发光二极管 OLED的阳极连接， 发光二极管 OLED的 阴极与驱动电源的低电平输入端 ELVSS连接。
在本发明另一实施例中， 发光二极管 OLED还可以串联在第一发光控制 晶体管 T5的第一极与驱动薄膜晶体管 DTFT的第一极之间。
在发光控制线 EM的信号有效的情况下， 第一发光控制晶体管 T5和第 二发光控制晶体管 T4 均导通， 电流可以从所述驱动电源的高电平输入端 ELVDD 流向所述驱动电源的低电平输入端 ELVSS, 从而可以使发光二极管 OLED发光。
在发光二极管 OLED发光阶段（即图 3所示 t3阶段）之外的其他阶段（即 图 3所示 tl阶段、 12阶段）第一发光二极管 T5截止， 驱动电源的高电平输 入端 ELVDD与驱动薄膜晶体管 DTFT的第一极断开， 从而可以避免驱动电 源的高电平输入端 ELVDD的高电平对驱动薄膜晶体管 DTFT的第一极的电 位造成影响。
在数据写入阶段（即图 3所示 t2阶段）， 由于驱动薄膜二极管 DTFT的 栅极与驱动薄膜晶体管的第二极导通， 此时的驱动薄膜晶体管 DTFT实际上 形成了一个处于临界导通状态的二极管， 第二发光二极管 T4截止，从而可以 避免驱动薄膜晶体管 DTFT的漏电流流向发光二极管 OLED。
在本发明中， 对驱动薄膜晶体管 DTFT、 第一驱动控制晶体管 Tl、 第二 驱动控制晶体管 Τ2、 第三驱动控制晶体管 Τ6、 初始化晶体管 Τ3、 第一发光 控制晶体管 Τ5和第二发光控制晶体管 Τ4的类型不作具体要求。 但是， 第一 驱动控制晶体管 Tl、第二驱动控制晶体管 Τ2和第三驱动控制晶体管 Τ6的类 型应当相同 （均为 Ρ型或均为 Ν型）， 第一发光控制晶体管 Τ5和第二发光控 制晶体管 Τ4的类型应当相同 （均为 Ρ型或均为 Ν型）。
在本发明的图 2所示的实施方式中， 驱动薄膜晶体管 DTFT、 第一驱动 控制晶体管 Tl、 第二驱动控制晶体管 Τ2、 第三驱动控制晶体管 Τ6、 初始化 晶体管 Τ3、第一发光控制晶体管 Τ5和第二发光控制晶体管 Τ4均为 Ρ型晶体 管。 栅线 GATE、 数据线 DATA以及发光控制线 EM的低电平信号为有效信 号。
下面结合图 2、 图 4至图 6介绍本发明的一种实施方式的工作原理。 图 4所示的是当图 2中的像素电路处于初始化阶段（即图 3所示 tl阶段） 时的等效电路图， 实线部分代表通电的部分， 虚线的部分代表不通电的部分。
在初始化阶段， 复位信号输入端 RESET向初始化晶体管 T3提供有效信 号， 使初始化晶体管 T3导通， 使第一电容 C1和第二电容 C2中残余的电量 流向低电平输入端 REF, 此时， 驱动薄膜晶体管 DTFT的栅极电压为低电平 输入端 REF提供的电压 Vrcf, 第二电容 C2的第一端的电压为低电平输入端 REF的电压 Vref。
图 5所示的是当图 2中的像素电路处于数据写入阶段（即图 3所示 t2阶 段） 时的等效电路图， 与图 4中一样， 实线部分代表通电的部分， 虚线的部 分代表不通电的部分。
在数据写入阶段（即图 3所示 t2阶段 ), 复位信号输入端 RESET输入的 信号跳变为高电平， 初始化晶体管 T3截止， 第一电容 C1保持低电平输入端 REF的电压 Vref。 同时栅线 GATE信号有效， 第一驱动控制晶体管 T1开启， 数据线 DATA将显示数据信号写入所述像素电路， 此时， 第二电容 C2第一 端 N1节点处电压为数据线 DATA的电压 Vdata与低电平输入端 REF的电压 Vref之和（即， Vdata+Vref )。 同时， 由于栅线 GATE信号有效， 第二驱动控制 晶体管 T2导通， 此时驱动薄膜晶体管 DTFT的栅极和驱动薄膜晶体管 DTFT 的第二极连接， 此时的驱动薄膜晶体管 DTFT实际上形成了一个处于临界导 通状态的二极管， 驱动薄膜晶体管 DTFT的阈值电压 Vth,DTFT被第一电容 C1 记录并保持。 此时， 驱动薄膜晶体管的栅极电压为 （ Vdata+Vref -Vth,DTFT ), 且 由第一电容 C1存储。
在数据写入阶段（即图 3所示 t2阶段 ), 发光控制线 EM为高电平， 第 二发光控制二极管 T4截止， 将数据写入像素这一动作并不会对发光二极管 OLED的发光状态产生影响， 避免了显示的闪烁。 同时发光控制线 EM为高 电平保证了第一发光控制二极管 T5截止，确保此时驱动薄膜晶体管 DTFT与 驱动电源的高电平输入端 ELVDD 断开， 避免了由于驱动薄膜晶体管 DTFT 的漏电对驱动薄膜晶体管 DTFT的栅极电压造成不良影响。 另一方面， 栅线 GATE信号有效，第三驱动控制晶体管 T6开启，避免了驱动薄膜晶体管 DTFT 的第一极悬空，并且第三驱动控制晶体管 T6可以将驱动薄膜晶体管 DTFT的 栅极电压引至驱动薄膜晶体管 DTFT的第一极， 即使驱动薄膜晶体管 DTFT 存在漏电现象， 也不会对驱动薄膜晶体管 DTFT的栅极电压造成影响。
图 6所示的是当图 2中的像素电路处于发光二极管 OLED发光阶段 (即 图 3所示 t3阶段 ) 时的等效电路图， 与图 4和图 5中一样， 实线部分代表通 电的部分， 虚线的部分代表不通电的部分。
栅线 GATE信号跳变为高电平， 第一驱动控制晶体管 Tl、 第二驱动控制 晶体管 Τ2 和第三驱动控制晶体管 Τ3 截止， 驱动薄膜晶体管的栅极电压 ( Vdata+Vref -Vth,DTFT ) 由第一电容 CI保持， 该电压确保驱动薄膜晶体管工作 在饱和区， 则此时， 驱动薄膜晶体管 DTFT的输出电流 Id为：
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Figure imgf000012_0001
由此可知， 驱动薄膜晶体管 DTFT的第一极与驱动薄膜晶体管 DTFT的 第二极之间的电流 Id与驱动薄膜二极管的阈值电压 Vth,DTFT无关。 因此， 驱动 薄膜晶体管 DTFT的阈值电压 Vth,DTFT的漂移不会对驱动薄膜晶体管 DTFT输 出的电流（即， 该驱动薄膜晶体管 DTFT的漏极电流）产生影响， 发光二极 管 OLED的亮度不会受到影响。
同时， 在发光二极管 OLED发光阶段， 第二发光控制晶体管 T4导通， 电流 Id经第二发光控制晶体管 T4流入发光二极管 OLED, 点亮显示。
另夕卜，初始化单元 30的低电平可以接地。如果驱动电源的高电平输入端 ELVDD有导线电阻或寄生电阻引起的电压降， 则可以对初始化单元 30的低 电平进行调整， 使其可以与导线电阻或寄生电阻引起的电压降相互抵消。 在 这种情况下， 所述像素电路还可以补偿驱动电源的导线电阻或寄生电阻引起 波动。
作为本发明的另一个方面， 还提供一种有机发光显示器， 其中， 该有机 发光显示器包括本发明所提供的上述像素电路。 由于所述像素电路可以输出 均匀的电流， 使像素电路中的发光二极管亮度均匀， 所以包括所述像素电路 的有机发光显示器可以具有均匀的显示亮度。 例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技术人员而 言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这 些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1、一种像素电路， 所述像素电路包括驱动薄膜晶体管和发光二极管， 所 述发光二极管串联在驱动电源的低电平输入端和高电平输入端之间， 其特征 在于， 所述像素电路还包括第一电容和驱动控制单元， 所述第一电容的第一 端通过所述驱动控制单元与所述驱动薄膜晶体管的第一极电连接， 所述第一 电容的第二端与所述驱动薄膜晶体管的栅极连接， 所述驱动薄膜晶体管的第 二极和所述驱动薄膜晶体管的栅极通过所述驱动控制单元电连接， 所述驱动 控制单元与栅线和数据线连接， 所述驱动控制单元在数据写入阶段控制导通 所述第一电容的第一端与所述驱动薄膜晶体管的第一极之间的连接、 导通所 述驱动薄膜晶体管的栅极与所述驱动薄膜晶体管的第二极之间的连接， 所述 驱动薄膜晶体管导通。
2、根据权利要求 1所述的像素电路， 其特征在于， 所述像素电路还包括 第二电容， 该第二电容的第一端与所述第一电容的第二端连接， 所述第二电 容的第二端通过所述驱动控制单元与所述数据线电连接。
3、根据权利要求 2所述的像素电路， 其特征在于， 所述驱动控制单元还 包括第一驱动控制晶体管，所述第一驱动控制晶体管的栅极与所述栅线连接， 所述第一驱动控制晶体管的第一极与数据线连接， 所述第一驱动控制晶体管 的第二极与所述第二电容的第二端连接。
4、根据权利要求 3所述的像素电路， 其特征在于， 所述像素电路还包括 提供低电平的初始化单元， 所述初始化单元电连接到所述第一电容的第二端 和所述第二电容的第一端。
5、根据权利要求 4所述的像素电路， 其特征在于， 所述初始化单元包括 初始化晶体管， 所述初始化晶体管的第一极连接到所述第一电容的第二端和 所述第二电容的第一端， 所述初始化晶体管的第二极与低电平输入端连接， 所述初始化晶体管的栅极与复位信号输入端相连。
6、根据权利要求 1至 5中任意一项所述的像素电路， 其特征在于， 所述 驱动控制单元包括第二驱动控制晶体管和第三驱动控制晶体管， 所述第二驱 动控制晶体管的栅极与所述栅线连接， 所述第二驱动控制晶体管的第一极与 所述驱动薄膜晶体管的第二极连接， 所述第二驱动控制晶体管的第二极与所 述驱动薄膜晶体管的栅极连接， 所述第三驱动控制晶体管的栅极与所述栅线 连接， 所述第三驱动控制晶体管的第一极与所述第一电容的第一端连接， 所 述第三驱动控制晶体管的第二极与所述驱动薄膜晶体管的第一极连接。
7、根据权利要求 6所述的像素电路， 其特征在于， 所述像素电路还包括 发光控制单元， 所述发光控制单元与发光控制线连接， 所述发光控制单元能 够根据所述发光控制线给出的信号导通驱动电源的高电平输入端与所述驱动 薄膜晶体管的第一极之间的连接， 和 /或导通所述驱动电源低电平输入端与所 述驱动薄膜晶体管的第二极之间的连接。
8、根据权利要求 7所述的像素电路， 其特征在于， 所述发光控制单元包 括第一发光控制晶体管和第二发光控制晶体管， 所述第一发光控制晶体管的 栅极与所述发光控制线连接， 所述第一发光控制晶体管的第一极与所述驱动 薄膜晶体管的第一极连接， 所述第一发光控制晶体管的第二极与所述驱动电 源的高电平输入端连接， 所述第二发光控制晶体管的栅极与所述发光控制线 连接， 所述第二发光控制晶体管的第一极与所述驱动薄膜晶体管的第二极连 接， 所述第二发光控制晶体管的第二极与所述发光二极管的阳极连接， 所述 发光二极管的阴极与所述驱动电源的低电平输入端连接。
9、根据权利要求 8所述的像素电路，其特征在于，所述驱动薄膜晶体管、 所述第一驱动控制晶体管、 所述第二驱动控制晶体管、 所述第三驱动控制晶 体管、 所述初始化晶体管、 所述第一发光控制晶体管和所述第二发光控制晶 体管均为 P型晶体管。
10、 一种有机发光显示器， 其特征在于， 所述有机发光显示器包括权利 要求 1至 9中任意一项所述的像素电路。
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