WO2016058475A1 - 像素电路及其驱动方法和有机发光显示器 - Google Patents

像素电路及其驱动方法和有机发光显示器 Download PDF

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Publication number
WO2016058475A1
WO2016058475A1 PCT/CN2015/090664 CN2015090664W WO2016058475A1 WO 2016058475 A1 WO2016058475 A1 WO 2016058475A1 CN 2015090664 W CN2015090664 W CN 2015090664W WO 2016058475 A1 WO2016058475 A1 WO 2016058475A1
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Prior art keywords
film transistor
thin film
scan line
organic light
light emitting
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PCT/CN2015/090664
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English (en)
French (fr)
Inventor
胡思明
朱晖
杨楠
张婷婷
刘周英
黄秀颀
Original Assignee
昆山工研院新型平板显示技术中心有限公司
昆山国显光电有限公司
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Application filed by 昆山工研院新型平板显示技术中心有限公司, 昆山国显光电有限公司 filed Critical 昆山工研院新型平板显示技术中心有限公司
Priority to JP2017519844A priority Critical patent/JP6437644B2/ja
Priority to EP15850228.6A priority patent/EP3208793B1/en
Priority to US15/518,141 priority patent/US10217409B2/en
Priority to KR1020177013106A priority patent/KR101935563B1/ko
Publication of WO2016058475A1 publication Critical patent/WO2016058475A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present invention relates to the field of flat panel display technologies, and in particular, to a pixel circuit, a driving method thereof, and an organic light emitting display.
  • Organic Light Emitting Display is self-illuminating, unlike thin film transistor liquid crystal display (TFT-LCD), which requires a backlight system to light up. Therefore, the visibility and brightness are both higher and thinner.
  • organic light-emitting displays are known as a new generation of displays that can replace thin film transistor liquid crystal displays.
  • each pixel of the organic light emitting display includes a pixel circuit 10 and an organic light emitting diode OLED, and the pixel circuit 10 is connected to the data line Dm and the scan line Sn, and controls the light emission of the organic light emitting diode OLED, wherein
  • the pixel circuit 10 includes a switching thin film transistor M1, a driving thin film transistor M2, and a storage capacitor Cst.
  • the gate of the switching thin film transistor M1 is connected to the scan line Sn, and the source of the switching thin film transistor M1 is connected to the data line Dm.
  • the gate of the driving thin film transistor M2 is connected to the drain of the switching thin film transistor M1, and the source of the driving thin film transistor M2 is connected to the first power source ELVDD through a first power supply line (not shown).
  • the drain of the driving thin film transistor M2 is connected to the anode of the organic light emitting diode OLED, and the cathode of the organic light emitting diode OLED is connected to the second power source ELVSS through a second power supply line (not shown).
  • the organic light emitting diode OLED emits light according to a current supplied from the pixel circuit 10, and the storage capacitor Cst is connected to a gate and a source of the driving thin film transistor M2.
  • the manufacturing process can cause differences in the threshold voltage of the thin film transistors.
  • the deviation of the threshold voltage causes the organic light emitting diode OLED to emit light of different brightness for the data signal of the same brightness, causing uneven brightness and affecting the display effect.
  • the power supply trace since there is a certain impedance of the power supply trace connecting the first power source ELVDD and the pixel circuit 10, when a current flows, the power supply trace affects the power supply positive voltage VDD actually reaching the pixel circuit 10, resulting in each pixel.
  • the positive voltage VDD received by the circuit 10 is inconsistent, thereby increasing the brightness unevenness.
  • the OLED device is aged due to the long-term illumination of the OLED, and the illuminating efficiency of the OLED may also cause uneven brightness.
  • An object of the present invention is to provide a pixel circuit, a driving method thereof and an organic light emitting display, which solve the problem of uneven brightness of the conventional organic light emitting display.
  • the present invention provides a pixel circuit, the pixel circuit including: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a thin film transistor, a storage capacitor, and an organic light emitting diode; a source of the sixth thin film transistor is connected to a first power source, a drain of the sixth thin film transistor and a drain of the first thin film transistor and the first a source of the second thin film transistor is connected, a drain of the second thin film transistor is connected to an anode of the organic light emitting diode, a cathode of the organic light emitting diode is connected to a second power source, and a gate of the sixth thin film transistor is a source of the third thin film transistor is connected to one end of the storage capacitor, and another end of the storage capacitor is respectively connected to a drain of the fourth thin film transistor and a source of the fifth thin film transistor, a source of the
  • the first power source and the second power source are used to supply a power voltage to the organic light emitting diode
  • the reference power source is used to be a gate of the sixth thin film transistor and The drain and the anode of the organic light emitting diode provide an initialization voltage.
  • the gates of the second thin film transistor and the fifth thin film transistor are both connected to a first scan line, and the first scan line is used to control initialization and stable capacitance,
  • the gates of the first thin film transistor, the third thin film transistor, and the fourth thin film transistor are each connected to a second scan line for respectively controlling writing of a data voltage and threshold voltage of the sixth thin film transistor
  • the gate of the seventh thin film transistor is connected to a third scan line for controlling the writing of the initialization voltage.
  • the scan period of driving the pixel circuit includes a first stage to a fourth stage;
  • the gate of the sixth thin film transistor, the drain of the sixth thin film transistor, and the anode of the organic light emitting diode are initialized in the first stage, and the anode of the organic light emitting diode is initialized in the second stage,
  • the gate and the drain of the sixth thin film transistor are initialized at the third stage, the threshold voltage of the sixth thin film transistor is sampled in the third stage, and the sixth thin film transistor is guided in the fourth stage A current is supplied to the organic light emitting diode.
  • the current supplied by the sixth thin film transistor to the organic light emitting diode is determined by a data voltage provided by the data line and an initialization voltage provided by a reference power source, and the A power source and a power source voltage supplied from the second power source and a threshold voltage of the sixth thin film transistor are independent.
  • the pixel circuit further includes a boost capacitor disposed on the second scan line and the gate of the sixth thin film transistor and the third thin film transistor. Between the poles and the connection point of one end of the storage capacitor.
  • the present invention also provides a driving method of a pixel circuit, and the driving method of the pixel circuit includes:
  • the scanning cycle is divided into a first phase, a second phase, a third phase, and a fourth phase, wherein
  • the scan signal provided by the first scan line is kept at a low level, and the scan signals provided by the second scan line and the third scan line are both changed from a high level to a low level, the first thin film transistor, the first The three thin film transistors, the fourth thin film transistor, and the seventh thin film transistor are all turned on from off, while the second thin film transistor and the fifth thin film transistor are both in an on state, and the initialization voltage provided by the reference power source is respectively opposite.
  • the scan signal provided by the first scan line is changed from a low level to a high level, and the scan signals provided by the second scan line and the third scan line are kept at a low level, the second thin film transistor and The fifth thin film transistor is turned off by conduction, and the initialization of the anode of the organic light emitting diode is stopped;
  • the scan signal provided by the first scan line is kept at a high level
  • the scan signal provided by the second scan line is kept at a low level
  • the scan signal provided by the third scan line is changed from a low level to a high level.
  • the seventh thin film transistor is turned off by conduction, the second thin film transistor is kept turned on, the initialization of the gate and the drain of the sixth thin film transistor is stopped, and the sixth thin film transistor is simultaneously turned on.
  • the threshold voltage is sampled;
  • the scan signals provided by the first scan line and the third scan line are both kept at a high level, and the scan signal provided by the second scan line is changed from a low level to a high level, the first thin film transistor, the first The three thin film transistors and the fourth thin film transistor are both turned off by on, the writing of the data voltage is stopped, and the sampling of the threshold voltage of the sixth thin film transistor is completed; after the sampling is completed, the The scan signals provided by the first scan line are changed from a high level to a low level, the second thin film transistor and the fifth thin film transistor are both turned off by conduction, and the sixth thin film transistor is passed through the second film.
  • the transistor outputs a current to drive the organic light emitting diode to emit light.
  • the gate of the sixth thin film transistor is initialized by the reference power source
  • the drain of the sixth thin film transistor is initialized by the reference power source
  • an anode of the organic light emitting diode is initialized by the reference power source.
  • the boosting capacitor is opposite to a gate of the sixth thin film transistor in response to a scan signal provided by the second scan line
  • the voltage at the connection point of the source of the three thin film transistor and one end of the storage capacitor is boosted, so that the gate voltage of the sixth thin film transistor is raised.
  • the present invention also provides an organic light emitting display comprising the pixel circuit as described above.
  • the pixel circuit initializes an anode of the organic light emitting diode through the first thin film transistor, the second thin film transistor, and the seventh thin film transistor, and Initializing a gate and a drain of a sixth thin film transistor as a driving element by the first thin film transistor, the third thin film transistor, and the seventh thin film transistor, thereby slowing down aging of the organic light emitting diode and the sixth thin film transistor, Increasing the lifetime of the organic light emitting diode and the sixth thin film transistor, and the current output by the sixth thin film transistor as the driving element is independent of the threshold voltage of the sixth thin film transistor and the impedance of the power supply trace, thereby being able to avoid the thin film
  • the brightness unevenness caused by the difference between the threshold voltage deviation of the transistor and the impedance of the power supply line thereby employing the pixel circuit and the driving method thereof
  • the organic light-emitting display not only increases the service life, but also improves
  • FIG. 1 is a circuit diagram of a pixel of a related art organic light emitting display
  • FIG. 2 is a circuit diagram of a pixel circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a timing chart showing a driving method of a pixel circuit according to Embodiment 1 of the present invention.
  • FIG. 4 is a circuit diagram of a pixel circuit according to a second embodiment of the present invention.
  • the present invention provides a pixel circuit, a driving method thereof and an organic light emitting display, which are further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.
  • the pixel circuit 20 includes: a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, and a sixth thin film transistor M6, a thin film transistor M7, a storage capacitor C1, and an organic light emitting diode OLED; a source of the sixth thin film transistor M6 is connected to the first power source ELVDD, and a drain of the sixth thin film transistor M6 is respectively connected to the first thin film transistor M1 a drain is connected to a source of the second thin film transistor M2, a drain of the second thin film transistor M2 is connected to an anode of the organic light emitting diode OLED, a cathode of the organic light emitting diode OLED and a second power source ELVSS Connecting, the gate of the sixth thin film transistor M6 is connected to
  • the fourth thin The source of the membrane transistor M4 is connected to the data line DATA, and the drains of the fifth thin film transistor M5 and the seventh thin film transistor M7 are both connected to the reference power source VREF, and the sources of the seventh thin film transistor M7 are respectively associated with the first
  • a source of a thin film transistor M1 is connected to a drain of the third thin film transistor M3.
  • the pixel circuit 20 receives the first power source ELVDD, the second power source ELVSS, and the reference power source VREF supplied from the outside (for example, from the power source) through power supply lines (not shown).
  • the first power source ELVDD and the second power source ELVSS are used as a driving power source of the organic light emitting diode OLED, and the organic light emitting diode OLED is supplied with a power supply voltage, and the reference power source VREF is used to provide an initialization voltage Vref.
  • the first power supply voltage VDD provided by the first power supply ELVDD is generally a high level
  • the second power supply voltage VSS provided by the second power supply ELVSS is generally a low voltage
  • the initialization voltage Vref provided by the reference power supply VREF is A direct current (DC) voltage having a fixed voltage value, typically a negative voltage or a low voltage close to 0V.
  • the source of the sixth thin film transistor M6 is connected to the first power source ELVDD, and the drain of the sixth thin film transistor M6 is connected to the anode of the organic light emitting diode OLED through the second thin film transistor M2.
  • the cathode of the organic light emitting diode OLED is connected to the second power source ELVSS.
  • the sixth thin film transistor M6 serves as a driving transistor to supply current to the organic light emitting diode OLED, and the organic light emitting diode OLED emits light in response to a current.
  • the drains of the fifth thin film transistor M5 and the drain of the seventh thin film transistor M7 are both connected to the reference power source VREF, and the source of the fifth thin film transistor M5 is connected to the first The node N1, the gate of the fifth thin film transistor M5 is connected to the first scan line S1, and the fifth thin film transistor M5 is supplied from the reference power source VREF in response to the scan signal provided by the first scan line S1.
  • the initialization voltage Vref is supplied to the first node N1, the source of the seventh thin film transistor M7 is connected to the third node N3, and the gate of the seventh thin film transistor M7 is connected to the third scan line S3, the The seven thin film transistor M7 is responsive to the scan signal supplied from the third scan line S3, and the initialization voltage supplied from the reference power source VREF Vref is supplied to the third node N3, the source of the third thin film transistor M3 is connected to the second node N2, and the gate of the third thin film transistor M3 is connected to the second scan line S2, the third film The transistor M3 supplies the voltage at the third node N3 to the second node N2 in response to the scan signal provided by the second scan line S2, and the gate of the first thin film transistor M1 is connected to the second scan line S2.
  • the gate of the second thin film transistor M2 is connected to the first scan line S1, and the first thin film transistor M1 and the second thin film transistor M2 are respectively provided in response to the second scan line S2 and the first scan line S1.
  • the scan signal supplies a voltage at the third node N3 to the anode of the organic light emitting diode OLED.
  • the initialization voltage Vref supplied from the reference power source VREF is applied to the first node N1 when the fifth thin film transistor M5 is turned on, and the reference power source VREF when the seventh thin film transistor M7 is turned on.
  • the supplied initialization voltage Vref is applied to the third node N3, and the reference power supply VREF supplies the initialization voltage to the third node N3 when the seventh thin film transistor M7, the third thin film transistor M3, and the first thin film transistor M1 are simultaneously turned on.
  • Vref is applied to the drains of the second node N2 and the sixth thin film transistor M6, whereby the gate and drain of the driving transistor M6 are initialized.
  • An initialization voltage Vref provided by the reference power source VREF is applied to an anode of the organic light emitting diode OLED when the seventh thin film transistor M7, the first thin film transistor M1, and the second thin film transistor M2 are simultaneously turned on, thereby the organic
  • the anode of the light emitting diode OLED is initialized.
  • the source of the fourth thin film transistor M4 is connected to the data line DATA, and the data voltage Vdata outputted by the driving chip (not shown) is transmitted through the data line DATA.
  • the drains of the four thin film transistors M4 are respectively connected to one end of the storage capacitor C1 and the source of the fifth thin film transistor M5, and the gate of the fourth thin film transistor M4 is connected to the second scan line S2, the first The fourth thin film transistor M4 supplies the data voltage Vdata transmitted via the data line DATA to the first node N1 in response to the scan signal supplied from the second scan line S2.
  • the fourth thin film transistor M4 is turned on or off according to the scan signal provided by the second scan line S2.
  • the data line DATA and the first node N1 are electrically connected to each other. Thereby, the data voltage Vdata from the data line DATA is supplied to the first node N1.
  • the storage capacitor C1 is connected between the first node N1 and the second node N2 for controlling the voltage at the first node N1 to correspond to the amount of change of the voltage at the second node N2. That is, the difference voltage between the second node N2 and the first node N1 will be charged to the storage capacitor C1, and the storage capacitor C1 thus maintains the voltage signal after the end of charging.
  • the pixel circuit 20 is a 7T1C type circuit structure including 7 thin film transistors and 1 capacitor.
  • the pixel circuits 20 are respectively connected to three scanning lines.
  • the gates of the second thin film transistor M2 and the fifth thin film transistor M5 are both connected to the first scan line S1, and the first scan line S1 is used to control initialization and stable capacitance.
  • the gates of a thin film transistor M1, a third thin film transistor M3, and a fourth thin film transistor M4 are both connected to a second scan line S2 for controlling the writing of the data voltage Vdata and the driving transistor, respectively.
  • the sampling of the threshold voltage, the gate of the seventh thin film transistor M7 is connected to the third scan line S3, and the third scan line S3 is used to control the writing of the initialization voltage Vref.
  • the initialization voltage Vref supplied from the reference power source VREF is applied to the gate of the sixth thin film transistor M6 via the seventh thin film transistor M7 and the third thin film transistor M3, and the gate of the sixth thin film transistor M6 can be Initialization, the initialization voltage Vref supplied from the reference power source VREF is applied to the drain of the sixth thin film transistor M6 via the seventh thin film transistor M7 and the first thin film transistor M1, and is capable of leaking the sixth thin film transistor M6.
  • the initialization voltage Vref provided by the reference power source VREF is applied to the anode of the organic light emitting diode OLED via the seventh thin film transistor M7, the first thin film transistor M1 and the second thin film transistor M2, and the organic The anode of the light emitting diode OLED is performed Initialization, thereby increasing the service life of the organic light emitting diode OLED and the driving thin film transistor M6.
  • the current supplied to the organic light emitting diode OLED by the sixth thin film transistor M6 is determined by the data voltage Vdata provided by the data line DATA and the initialization voltage Vref provided by the reference power source VERF, and the first power source ELVDD and The power supply voltage supplied from the second power source ELVSS and the threshold voltage of the sixth thin film transistor M6 are independent. Therefore, the pixel circuit 20 can avoid uneven brightness caused by the difference in threshold voltage of the thin film transistor and the impedance of the power supply line, thereby improving the display quality of the display.
  • the present invention also provides a driving method of a pixel circuit.
  • the driving method of the pixel circuit includes:
  • the scanning period is divided into a first stage T1, a second stage T2, a third stage T3, and a fourth stage T4, wherein
  • the scan signal provided by the first scan line S1 is kept at a low level, and the scan signals provided by the second scan line S2 and the third scan line S3 are both changed from a high level to a low level, the first The thin film transistor M1, the third thin film transistor M3, the fourth thin film transistor M4, and the seventh thin film transistor M7 are all turned on by the turn-off, while the second thin film transistor M2 and the fifth thin film transistor M5 are both turned on.
  • the initialization voltage Vref provided by the reference power source VREF initializes the gate and the drain of the sixth thin film transistor M6 and the anode of the organic light emitting diode OLED, respectively, and the data voltage Vdata provided by the data line DATA passes through the
  • the fourth thin film transistor M4 is written to the drain of the fourth thin film transistor M4 and the source of the fifth thin film transistor M5, the connection point N1 of the other end of the storage capacitor C1;
  • the scan signal provided by the first scan line S1 changes from a low level to a high level, and the scan signals provided by the second scan line S2 and the third scan line S3 remain at a low level, the first The two thin film transistors M2 and the fifth thin film transistor M5 are turned off by conduction, and the initialization of the anode of the organic light emitting diode OLED is stopped;
  • the scan signal provided by the first scan line S1 is kept at a high level
  • the scan signal provided by the second scan line S2 is kept at a low level
  • the scan signal provided by the third scan line S3 is changed from a low level.
  • the seventh thin film transistor M7 is turned off
  • the second thin film transistor M2 and the fifth thin film transistor M5 are in an off state
  • the gate and drain of the sixth thin film transistor M6 are stopped. Initializing the pole while sampling the threshold voltage of the sixth thin film transistor M6;
  • the scan signals provided by the first scan line S1 and the third scan line S3 are both kept at a high level, and the scan signal provided by the second scan line S2 is changed from a low level to a high level, the first The thin film transistor M1, the third thin film transistor M3, and the fourth thin film transistor M4 are all turned off by on, and the writing of the data voltage Vdata is stopped, and the threshold voltage of the sixth thin film transistor M6 is sampled; after the sampling is completed, The scan signal provided by the first scan line S1 is changed from a high level to a low level, and the second thin film transistor M2 and the fifth thin film transistor M5 are both turned on and turned on, and the sixth thin film transistor M6 is turned on.
  • the second thin film transistor M2 outputs a current to drive the organic light emitting diode OLED to emit light.
  • the first thin film transistor M1 and the third thin film transistor M3 since the scan signals provided by the second scan line S2 and the third scan line S3 are both changed from a high level to a low level, the first thin film transistor M1 and the third thin film transistor M3, The fourth thin film transistor M4 and the seventh thin film transistor M7 are both turned on by the turn-off, and the second thin film transistor M2 and the fifth thin film transistor M5 are both turned on because the scan signal provided by the first scan line S1 is kept at a low level.
  • the initialization voltage Vref supplied from the reference power supply VREF is supplied to the connection point between the drain of the fourth thin film transistor M4 and the source of the fifth thin film transistor M5 and the other end of the storage capacitor C1 via the fifth thin film transistor M5.
  • One node N1 One node N1).
  • the initialization voltage Vref provided by the reference power supply VREF is supplied to the connection point of the source of the first thin film transistor M1 and the drain of the third thin film transistor M3 via the seventh thin film transistor M7 (third node) N3), and supplied to the gate of the sixth thin film transistor M6 via the third thin film transistor M3, and into the gate of the sixth thin film transistor M6 Row initialization, providing a drain to the sixth thin film transistor M6 via the first thin film transistor M1, and initializing a drain of the sixth thin film transistor M6 via the first thin film transistor M1 and the second
  • a thin film transistor M2 is provided to an anode of the organic light emitting diode OLED, and an anode of the organic light emitting diode OLED is initialized.
  • the fourth thin film transistor M4 since the fourth thin film transistor M4 is turned on, the data voltage Vdata supplied from the data line DATA is written into the first node N1 via the fourth thin film transistor M4. As apparent from the above, the total voltage Vdata+Vref of the data voltage Vdata and the initialization voltage Vref is supplied to the first node N1.
  • the reference The power source VREF cannot supply the initialization voltage Vref to the anode of the organic light emitting diode OLED through the second thin film transistor M2, thereby stopping the initialization of the anode of the organic light emitting diode OLED.
  • the reference power source VREF stops the initialization of the first node N1, and since the fourth thin film transistor M4 is turned on, only the data voltage Vdata is transmitted to the first node N1 via the data line DATA.
  • the seventh thin film transistor M7 is turned off by the turn-on, thereby stopping the initialization voltage supplied from the reference power source VREF.
  • Vref is supplied to the third node N3 between the source of the first thin film transistor M1 and the drain of the third thin film transistor M3, such that the reference power supply VREF cannot pass through the first thin film transistor M1 and the third thin film transistor M3 and seventh thin film transistor M7 supply an initialization voltage Vref to the gate and drain of the sixth thin film transistor M6, thereby stopping initialization of the gate and drain of the sixth thin film transistor M6.
  • the scan signal provided by S2 is kept low, the first power voltage VDD provided by the first power source ELVDD is transmitted to the source of the sixth thin film transistor M6, and the threshold voltage of the sixth thin film crystal M6 is sampled and stored.
  • the capacitor C1 is charged until the voltage at the second node N2, that is, the gate voltage Vg6 of the sixth thin film transistor M6 reaches VDD-Vth.
  • Vth is the absolute value of the threshold voltage of the sixth thin film transistor M6.
  • the first thin film transistor M1, the third thin film transistor M3, and the fourth thin film transistor M4 are all turned on.
  • the writing of the data voltage Vdata is stopped, and the storage capacitor C1 stops charging, thereby completing the sampling of the threshold voltage of the sixth thin film transistor M6.
  • the fourth thin film transistor M4 since the fourth thin film transistor M4 is turned off, the data voltage Vdata provided by the data line DATA stops writing to the first node N1, and the voltage at the first node N1 is the data voltage Vdata.
  • the data voltage Vdata provided by the data line DATA changes from a high level to a low level, and the driving chip starts to output a data signal of the next row of pixels.
  • the scan signal provided by the first scan line S1 also changes from a high level to a low level
  • the second thin film transistor M2 and the fifth thin film transistor M5 are both turned off by conduction, and the reference power supply VREF is provided.
  • the initialization voltage Vref is supplied to the first node N1 via the fifth thin film transistor M5, and the sixth thin film transistor M6 is turned on and outputs a current via the second thin film transistor M2. Since the voltage of the storage capacitor C1 does not abruptly change, the voltage at the second node N2 (ie, the gate voltage Vg6 of the sixth thin film transistor M6) will change following the voltage change at the first node N1.
  • the gate voltage Vg6 of the sixth thin film transistor M6 is determined by the following formula Line calculation:
  • Vg6 VDD-Vth-(Vdata-Vref) Equation 1;
  • Vth is an absolute value of a threshold voltage of the sixth thin film transistor M6,
  • VDD is a first power supply voltage supplied by the first power supply ELVDD,
  • Vdata is a data voltage supplied by the data line DATA, and
  • Vref is a reference power supply VREF. The initialization voltage provided.
  • the gate-source voltage Vsg6 of the sixth thin film transistor M6, that is, the sixth thin film transistor M6 The voltage difference between the gate and source can be calculated by the following formula:
  • Vsg6 VDD-(VDD-Vth-(Vdata-Vref)) Equation 2;
  • Vsg6-Vth Vdata-Vref Equation 3;
  • the organic light emitting diode OLED emits light proportional to the supplied current, and the current Ion flowing through the organic light emitting diode OLED is calculated as:
  • K is the product of the electron mobility, the aspect ratio, and the capacitance per unit area of the thin film transistor.
  • the current flowing through the organic light emitting diode OLED has nothing to do with the power supply voltage and the threshold voltage of the sixth thin film transistor M6, and is only related to the data voltage Vdata, the initialization voltage Vref, and the constant K. Even if there is a deviation in the threshold voltage of the sixth thin film transistor M6, the power supply trace impedance affects the power supply voltage actually reaching the pixel circuit and does not affect the current Ion flowing through the organic light emitting diode OLED. Therefore, the pixel circuit 20 and the driving method thereof can completely avoid the threshold voltage deviation and the power supply line resistance. Uneven brightness caused by resistance. At the same time, the lifetime of the organic light emitting diode OLED and the sixth thin film transistor M6 as a driving transistor is increased.
  • the pixel circuit 30 includes: a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, and a sixth thin film transistor M6, a thin film transistor M7, a storage capacitor C1, and an organic light emitting diode OLED; a source of the sixth thin film transistor M6 is connected to the first power source ELVDD, and a drain of the sixth thin film transistor M6 is respectively connected to the first thin film transistor M1 a drain is connected to a source of the second thin film transistor M2, a drain of the second thin film transistor M2 is connected to an anode of the organic light emitting diode OLED, a cathode of the organic light emitting diode OLED and a second power source ELVSS Connecting, the gate of the sixth thin film transistor M6 is connected to the source
  • the drain is connected to the source of the fifth thin film transistor M5, the source of the fourth thin film transistor M4 is connected to the data line DATA, and the fifth thin film transistor M5 and the seventh thin film transistor M7
  • the drains are all connected to the reference power source VREF, and the sources of the seventh thin film transistor M7 are respectively connected to the source of the first thin film transistor M1 and the drain of the third thin film transistor M3.
  • the pixel circuit 30 includes all the features of the pixel circuit 20 in the first embodiment.
  • the difference between this embodiment and the first embodiment is that the second node N2 and the second scan line S2 are provided with a rise.
  • the voltage capacitor C2 can boost the second node N2 through the boost capacitor C2.
  • the boost capacitor C2 is according to the second scan line S2.
  • the timing requirements of the scan signals provided by the first scan line S1, the second scan line S2, and the third scan line S3 in this embodiment are the same as the first scan line S1, the second scan line S2, and the third scan in the first embodiment.
  • the timing requirements of the scanning signals provided by the line S3 are the same, and will not be further described herein. For details, refer to the first stage T1 to the fourth stage T4 of the driving method of the pixel circuit in the first embodiment.
  • the present invention also provides an organic light emitting display comprising the pixel circuit as described above.
  • the pixel circuit performs the anode of the organic light emitting diode through the first thin film transistor, the second thin film transistor, and the seventh thin film transistor.
  • the aging increases the lifetime of the organic light emitting diode and the sixth thin film transistor, and the current output by the sixth thin film transistor as the driving element is independent of the threshold voltage of the sixth thin film transistor and the impedance of the power supply trace.
  • the pixel circuit boosts a gate voltage of the sixth thin film transistor by the boosting capacitor, thereby reducing a leakage current of the sixth thin film transistor, thereby improving display contrast.

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Abstract

一种像素电路（20）及其驱动方法和有机发光显示器。像素电路（20）通过第一薄膜晶体管（M1）、第二薄膜晶体管（M2）和第七薄膜晶体管（M7）对有机发光二极管（OLED）的阳极进行初始化，并通过第一薄膜晶体管（M1）、第三薄膜晶体管（M3）和第七薄膜晶体管（M7）对作为驱动元件的第六薄膜晶体管（M6）的栅极和漏极进行初始化，从而增加了有机发光二极管(OLED)和第六薄膜晶体管（M6）的使用寿命。而且，作为驱动元件的第六薄膜晶体管（M6）所输出的电流与第六薄膜晶体管（M6）的阈值电压和电源走线的阻抗无关，因此能够避免由薄膜晶体管阈值电压的偏差和电源走线的阻抗不同所造成的亮度不均。因此，采用像素电路（20）及其驱动方法的有机发光显示器不但增加了使用寿命，而且提高了显示质量。

Description

像素电路及其驱动方法和有机发光显示器 技术领域
本发明涉及平板显示技术领域，特别涉及一种像素电路及其驱动方法和有机发光显示器。
背景技术
有机发光显示器(英文全称Organic Lighting Emitting Display， 简称OLED)能够自行发光，不像薄膜晶体管液晶显示器(英文全称Thin Film Transistor liquid crystal display，简称TFT-LCD)需要背光系统(backlight system)才能点亮，因此可视度和亮度均更高，而且更轻薄。目前，有机发光显示器被誉为可以取代薄膜晶体管液晶显示器的新一代显示器。
请参考图1，其为现有技术的有机发光显示器的像素的电路图。如图1所示，有机发光显示器的每个像素包括像素电路10和有机发光二极管OLED，所述像素电路10与数据线Dm和扫描线Sn连接，并控制所述有机发光二极管OLED的发光，其中，所述像素电路10包括开关薄膜晶体管M1、驱动薄膜晶体管M2和存储电容Cst，所述开关薄膜晶体管M1的栅极与扫描线Sn连接，所述开关薄膜晶体管M1的源极与数据线Dm连接，所述驱动薄膜晶体管M2的栅极与所述开关薄膜晶体管M1的漏极连接，所述驱动薄膜晶体管M2的源极通过第一电源走线(图中未示出)与第一电源ELVDD连接，所述驱动薄膜晶体管M2的漏极与所述有机发光二极管OLED的阳极连接，所述有机发光二极管OLED的阴极通过第二电源走线(图中未示出)与第二电源ELVSS连接，所述有机发光二极管OLED根据所述像素电路10提供的电流而发光，所述存储电容Cst连接在所述驱动薄膜晶体管M2的栅极和源极之间，用于在预定时间期间维持提供到所述开关薄膜晶 体管M1的栅极的数据信号和所述驱动薄膜晶体管M2的阈值电压。
然而，制造工艺的偏差会导致薄膜晶体管的阈值电压出现差异。而作为驱动元件的薄膜晶体管，其阈值电压的偏差会导致所述有机发光二极管OLED对于相同亮度的数据信号仍发射出不同亮度的光，造成亮度不均，影响显示效果。
而且，由于连接所述第一电源ELVDD和像素电路10的电源走线存在一定的阻抗，当有电流流过时，电源走线会影响实际到达所述像素电路10的电源正压VDD，导致各个像素电路10接收到的电源正压VDD不一致，进而加重亮度不均现象。同时，由于所述有机发光二极管OLED长时间发光，导致所述有机发光二极管OLED器件老化，所述有机发光二极管OLED的发光效率下降也会造成亮度不均问题。
发明内容
本发明的目的在于提供一种像素电路及其驱动方法和有机发光显示器，以解决现有的有机发光显示器亮度不均的问题。
为解决上述问题，本发明提供一种像素电路，所述像素电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、存储电容和有机发光二极管；所述第六薄膜晶体管的源极与第一电源连接，所述第六薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极与第二电源连接，所述第六薄膜晶体管的栅极与所述第三薄膜晶体管的源极和所述存储电容的一端连接，所述存储电容的另一端分别与所述第四薄膜晶体管的漏极和所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的源极与数据线连接，所述第五薄膜晶体管和第 七薄膜晶体管的漏极均与参考电源连接，所述第七薄膜晶体管的源极分别与所述第一薄膜晶体管的源极和所述第三薄膜晶体管的漏极连接。
可选的，在所述的像素电路中，所述第一电源和第二电源用于为所述有机发光二极管提供电源电压，所述参考电源用于为所述第六薄膜晶体管的栅极和漏极以及所述有机发光二极管的阳极提供初始化电压。
可选的，在所述的像素电路中，所述第二薄膜晶体管和第五薄膜晶体管的栅极均与第一扫描线连接，所述第一扫描线用于控制初始化和稳定电容，所述第一薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管的栅极均与第二扫描线连接，所述第二扫描线用于分别控制数据电压的写入和所述第六薄膜晶体管的阈值电压的采样，所述第七薄膜晶体管的栅极与第三扫描线连接，所述第三扫描线用于控制初始化电压的写入。
可选的，在所述的像素电路中，驱动所述像素电路的扫描周期包括第一阶段至第四阶段；
所述第六薄膜晶体管的栅极、第六薄膜晶体管的漏极以及有机发光二极管的阳极在所述第一阶段开始初始化，所述有机发光二极管的阳极在所述第二阶段结束初始化，所述第六薄膜晶体管的栅极和漏极在所述第三阶段结束初始化，所述第六薄膜晶体管的阈值电压在所述第三阶段进行采样，所述第六薄膜晶体管在所述第四阶段导通并提供电流至所述有机发光二极管。
可选的，在所述的像素电路中，所述第六薄膜晶体管提供至所述有机发光二极管的电流由所述数据线提供的数据电压和参考电源提供的初始化电压决定，而与所述第一电源和第二电源提供的电源电压以及所述第六薄膜晶体管的阈值电压无关。
可选的，在所述的像素电路中，还包括一升压电容，所述升压电容设置于所述第二扫描线与所述第六薄膜晶体管的栅极与第三薄膜晶体管的源 极、存储电容的一端的连接点之间。
相应的，本发明还提供了一种像素电路的驱动方法，所述像素电路的驱动方法包括：
扫描周期分为第一阶段、第二阶段、第三阶段和第四阶段，其中，
在第一阶段，第一扫描线提供的扫描信号保持低电平，第二扫描线和第三扫描线提供的扫描信号均由高电平变为低电平，所述第一薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管和第七薄膜晶体管均由截止变为导通，同时所述第二薄膜晶体管和第五薄膜晶体管均处于导通状态，所述参考电源提供的初始化电压分别对所述第六薄膜晶体管的栅极、第六薄膜晶体管的漏极以及有机发光二极管的阳极进行初始化，所述数据线提供的数据电压经由第四薄膜晶体管写入所述第四薄膜晶体管的漏极与第五薄膜晶体管的源极、存储电容的另一端的连接点；
在第二阶段，第一扫描线提供的扫描信号由低电平变为高电平，所述第二扫描线和第三扫描线提供的扫描信号保持低电平，所述第二薄膜晶体管和第五薄膜晶体管均由导通变为截止，停止对所述有机发光二极管的阳极的初始化；
在第三阶段，第一扫描线提供的扫描信号保持高电平，所述第二扫描线提供的扫描信号保持低电平，第三扫描线提供的扫描信号由低电平变为高电平，所述第七薄膜晶体管由导通变为截止，所述第二薄膜晶体管保持导通截止，停止对所述第六薄膜晶体管的栅极和漏极的初始化，同时对所述第六薄膜晶体管的阈值电压进行采样；
在第四阶段，第一扫描线和第三扫描线提供的扫描信号均保持高电平，第二扫描线提供的扫描信号由低电平变为高电平，所述第一薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管均由导通变为截止，停止写入数据电压，同时完成对所述第六薄膜晶体管的阈值电压的采样；采样完成之后，所述 第一扫描线提供的扫描信号均由高电平变为低电平，所述第二薄膜晶体管和第五薄膜晶体管均由截止变为导通，所述第六薄膜晶体管经由所述第二薄膜晶体管输出电流以驱动所述有机发光二极管发光。
可选的，在所述的像素电路的驱动方法中，当所述第七薄膜晶体管和第三薄膜晶体管共同导通时，由所述参考电源对所述第六薄膜晶体管的栅极进行初始化；
当所述第一薄膜晶体管和第七薄膜晶体管共同导通时，由所述参考电源对所述第六薄膜晶体管的漏极进行初始化；
当所述第一薄膜晶体管、第二薄膜晶体管和第七薄膜晶体管共同导通时，由所述参考电源对所述有机发光二极管的阳极进行初始化。
可选的，在所述的像素电路的驱动方法中，在第四阶段，所述升压电容响应于所述第二扫描线提供的扫描信号而对所述第六薄膜晶体管的栅极与第三薄膜晶体管的源极、存储电容的一端的连接点处的电压进行升压，使得所述第六薄膜晶体管的栅极电压升高。
相应的，本发明还提供了一种有机发光显示器，所述有机发光显示器包括如上所述的像素电路。
在本发明提供的像素电路及其驱动方法和有机发光显示器中，所述像素电路通过所述第一薄膜晶体管、第二薄膜晶体管和第七薄膜晶体管对所述有机发光二极管的阳极进行初始化，并通过所述第一薄膜晶体管、第三薄膜晶体管和第七薄膜晶体管对作为驱动元件的第六薄膜晶体管的栅极和漏极进行初始化，从而减缓所述有机发光二极管和第六薄膜晶体管的老化，增加所述有机发光二极管和第六薄膜晶体管的使用寿命，而且，作为驱动元件的第六薄膜晶体管所输出的电流与第六薄膜晶体管的阈值电压和电源走线的阻抗无关，因此能够避免由薄膜晶体管的阈值电压偏差和电源走线的阻抗不同所造成的亮度不均，由此，采用所述像素电路及其驱动方法的 有机发光显示器不但增加了使用寿命，而且提高了显示质量。
附图说明
图1是现有技术的有机发光显示器的像素的电路图；
图2是本发明实施例一的像素电路的电路图；
图3是本发明实施例一的像素电路的驱动方法的时序图；
图4是本发明实施例二的像素电路的电路图。
具体实施方式
以下结合附图和具体实施例对本发明提出一种像素电路及其驱动方法和有机发光显示器作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
【实施例一】
请参考图2，其为本发明实施例一的像素电路的结构示意图。如图2所示，所述像素电路20包括：第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、存储电容C1和有机发光二极管OLED；所述第六薄膜晶体管M6的源极与第一电源ELVDD连接，所述第六薄膜晶体管M6的漏极分别与所述第一薄膜晶体管M1的漏极和所述第二薄膜晶体管M2的源极连接，所述第二薄膜晶体管M2的漏极与所述有机发光二极管OLED的阳极连接，所述有机发光二极管OLED的阴极与第二电源ELVSS连接，所述第六薄膜晶体管M6的栅极与所述第三薄膜晶体管M3的源极和所述存储电容C1的一端连接，所述存储电容C1的另一端分别与所述第四薄膜晶体管M4的漏极和所述第五薄膜晶体管M5的源极连接，所述第四薄 膜晶体管M4的源极与数据线DATA连接，所述第五薄膜晶体管M5和第七薄膜晶体管M7的漏极均与参考电源VREF连接，所述第七薄膜晶体管M7的源极分别与所述第一薄膜晶体管M1的源极和所述第三薄膜晶体管M3的漏极连接。
具体的，所述像素电路20通过电源走线(图中未示出)分别接收由外部(例如，从电源)提供的第一电源ELVDD，第二电源ELVSS和参考电源VREF。其中，所述第一电源ELVDD和第二电源ELVSS用作有机发光二极管OLED的驱动电源，为所述有机发光二极管OLED提供电源电压，所述参考电源VREF用于提供初始化电压Vref。其中，所述第一电源ELVDD提供的第一电源电压VDD一般为高电平，所述第二电源ELVSS提供的第二电源电压VSS一般为低电压，所述参考电源VREF提供的初始化电压Vref是具有固定电压值的直流(DC)电压，一般为负压或者接近0V的低电压。
如图2所示，所述第六薄膜晶体管M6的源极连接第一电源ELVDD，所述第六薄膜晶体管M6的漏极通过所述第二薄膜晶体管M2与所述有机发光二极管OLED的阳极连接，所述有机发光二极管OLED的阴极连接第二电源ELVSS。其中，所述第六薄膜晶体管M6作为驱动晶体管为所述有机发光二极管OLED提供电流，所述有机发光二极管OLED响应电流而发光。
请继续参考图2，所述第五薄膜晶体管M5的漏极和所述第七薄膜晶体管M7的漏极均与所述参考电源VREF连接，所述第五薄膜晶体管M5的源极连接至第一节点N1，所述第五薄膜晶体管M5的栅极与第一扫描线S1连接，所述第五薄膜晶体管M5响应于所述第一扫描线S1所提供的扫描信号，将来自参考电源VREF提供的初始化电压Vref提供给所述第一节点N1，所述第七薄膜晶体管M7的源极连接至第三节点N3，所述第七薄膜晶体管M7的栅极与第三扫描线S3连接，所述第七薄膜晶体管M7响应于所述第三扫描线S3所提供的扫描信号，将来自参考电源VREF提供的初始化电压 Vref提供至所述第三节点N3，所述第三薄膜晶体管M3的源极连接至第二节点N2，所述第三薄膜晶体管M3的栅极与第二扫描线S2连接，所述第三薄膜晶体管M3响应于所述第二扫描线S2所提供的扫描信号，将第三节点N3处的电压提供至第二节点N2，所述第一薄膜晶体管M1的栅极与第二扫描线S2连接，所述第二薄膜晶体管M2的栅极与第一扫描线S1连接，所述第一薄膜晶体管M1和第二薄膜晶体管M2分别响应于所述第二扫描线S2和第一扫描线S1所提供的扫描信号，将第三节点N3处的电压提供至所述有机发光二极管OLED的阳极。
如图2所示，当所述第五薄膜晶体管M5导通时所述参考电源VREF提供的初始化电压Vref施加到第一节点N1，当所述第七薄膜晶体管M7导通时所述参考电源VREF提供的初始化电压Vref施加到第三节点N3，当所述第七薄膜晶体管M7、第三薄膜晶体管M3和第一薄膜晶体管M1同时导通时所述参考电源VREF提供到第三节点N3的初始化电压Vref施加到第二节点N2和第六薄膜晶体管M6的漏极，由此驱动晶体管M6的栅极和漏极得以实现初始化。当所述第七薄膜晶体管M7、第一薄膜晶体管M1和第二薄膜晶体管M2同时导通时所述参考电源VREF提供的初始化电压Vref施加到所述有机发光二极管OLED的阳极，由此所述有机发光二极管OLED的阳极得以实现初始化。
请继续参考图2，所述第四薄膜晶体管M4的源极与所述数据线DATA连接，驱动芯片(图中未示出)输出的数据电压Vdata通过所述数据线DATA进行传输，所述第四薄膜晶体管M4的漏极分别与所述存储电容C1的一端和所述第五薄膜晶体管M5的源极连接，所述第四薄膜晶体管M4的栅极与第二扫描线S2连接，所述第四薄膜晶体管M4响应于所述第二扫描线S2所提供的扫描信号，将经由数据线DATA传输的数据电压Vdata提供给所述第一节点N1。
所述第四薄膜晶体管M4根据所述第二扫描线S2所提供的扫描信号导通或截止，当所述第四薄膜晶体管M4导通时，所述数据线DATA和第一节点N1彼此电连接，从而将来自所述数据线DATA的数据电压Vdata提供到第一节点N1。
所述存储电容C1连接在所述第一节点N1和第二节点N2之间，用于控制所述第一节点N1处的电压，以对应于所述第二节点N2处的电压的变化量，即所述第二节点N2与所述第一节点N1的差电压将会充至所述存储电容C1，充电结束后所述存储电容C1由此保持电压信号。
本实施例中，所述像素电路20为一种7T1C型电路结构，包括7个薄膜晶体管和1个电容。所述像素电路20分别与三条扫描线连接。其中，本实施例中，所述第二薄膜晶体管M2和第五薄膜晶体管M5的栅极均与第一扫描线S1连接，所述第一扫描线S1用于控制初始化和稳定电容，所述第一薄膜晶体管M1、第三薄膜晶体管M3和第四薄膜晶体管M4的栅极均与第二扫描线S2连接，所述第二扫描线S2分别用于控制数据电压Vdata的写入和所述驱动晶体管的阈值电压的采样，所述第七薄膜晶体管M7的栅极与第三扫描线S3连接，所述第三扫描线S3用于控制初始化电压Vref的写入。
所述参考电源VREF提供的初始化电压Vref经由所述第七薄膜晶体管M7和第三薄膜晶体管M3施加到所述第六薄膜晶体管M6的栅极，能够对所述第六薄膜晶体管M6的栅极进行初始化，所述参考电源VREF提供的初始化电压Vref经由所述第七薄膜晶体管M7和第一薄膜晶体管M1施加到所述第六薄膜晶体管M6的漏极，能够对所述第六薄膜晶体管M6的漏极进行初始化，所述参考电源VREF提供的初始化电压Vref经由所述第七薄膜晶体管M7、第一薄膜晶体管M1和第二薄膜晶体管M2施加到所述有机发光二极管OLED的阳极，能够对所述有机发光二极管OLED的阳极进行 初始化，从而增加所述有机发光二极管OLED和驱动薄膜晶体管M6的使用寿命。
而且，所述第六薄膜晶体管M6提供至所述有机发光二极管OLED的电流由所述数据线DATA提供的数据电压Vdata和参考电源VERF提供的初始化电压Vref决定，而与所述第一电源ELVDD和第二电源ELVSS提供的电源电压以及所述第六薄膜晶体管M6的阈值电压无关。因此，采用所述像素电路20能够避免由薄膜晶体管的阈值电压偏差和电源走线的阻抗不同所造成的亮度不均，进而提高显示器的显示质量。
相应的，本发明还提供了一种像素电路的驱动方法。请结合参考图2和图3，所述像素电路的驱动方法包括：
扫描周期分为第一阶段T1、第二阶段T2、第三阶段T3和第四阶段T4，其中，
在第一阶段T1，第一扫描线S1提供的扫描信号保持低电平，第二扫描线S2和第三扫描线S3提供的扫描信号均由高电平变为低电平，所述第一薄膜晶体管M1、第三薄膜晶体管M3、第四薄膜晶体管M4和第七薄膜晶体管M7均由截止变为导通，同时所述第二薄膜晶体管M2和第五薄膜晶体管M5均处于导通状态，所述参考电源VREF提供的初始化电压Vref分别对所述第六薄膜晶体管M6的栅极和漏极以及所述有机发光二极管OLED的阳极进行初始化，所述数据线DATA提供的数据电压Vdata经由所述第四薄膜晶体管M4写入所述第四薄膜晶体管M4的漏极与第五薄膜晶体管M5的源极、存储电容C1的另一端的连接点N1；
在第二阶段T2，第一扫描线S1提供的扫描信号由低电平变为高电平，所述第二扫描线S2和第三扫描线S3提供的扫描信号保持低电平，所述第二薄膜晶体管M2和第五薄膜晶体管M5均由导通变为截止，停止对所述有机发光二极管OLED的阳极的初始化；
在第三阶段T3，第一扫描线S1提供的扫描信号保持高电平，所述第二扫描线S2提供的扫描信号保持低电平，第三扫描线S3提供的扫描信号由低电平变为高电平，所述第七薄膜晶体管M7由导通变为截止，所述第二薄膜晶体管M2和第五薄膜晶体管M5处于截止状态，停止对所述第六薄膜晶体管M6的栅极和漏极的初始化，同时对所述第六薄膜晶体管M6的阈值电压进行采样；
在第四阶段T4，第一扫描线S1和第三扫描线S3提供的扫描信号均保持高电平，第二扫描线S2提供的扫描信号由低电平变为高电平，所述第一薄膜晶体管M1、第三薄膜晶体管M3和第四薄膜晶体管M4均由导通变为截止，停止写入数据电压Vdata，同时完成对所述第六薄膜晶体管M6的阈值电压的采样；采样完成之后，所述第一扫描线S1提供的扫描信号由高电平变为低电平，所述第二薄膜晶体管M2和第五薄膜晶体管M5均由截止变为导通，所述第六薄膜晶体管M6经由所述第二薄膜晶体管M2输出电流以驱动所述有机发光二极管OLED发光。
具体的，在第一阶段T1，由于第二扫描线S2和第三扫描线S3提供的扫描信号均由高电平变为低电平，所述第一薄膜晶体管M1、第三薄膜晶体管M3、第四薄膜晶体管M4和第七薄膜晶体管M7均由截止变为导通，由于第一扫描线S1提供的扫描信号保持低电平，第二薄膜晶体管M2和第五薄膜晶体管M5均处于导通状态，所述参考电源VREF提供的初始化电压Vref经由第五薄膜晶体管M5提供至所述第四薄膜晶体管M4的漏极与第五薄膜晶体管M5的源极、存储电容C1的另一端的连接点(第一节点N1)。
同时，所述参考电源VREF提供的初始化电压Vref经由所述第七薄膜晶体管M7提供至所述第一薄膜晶体管M1的源极与所述第三薄膜晶体管M3的漏极的连接点(第三节点N3)，并经由所述第三薄膜晶体管M3提供至所述第六薄膜晶体管M6的栅极，并对所述第六薄膜晶体管M6的栅极进 行初始化，经由所述第一薄膜晶体管M1提供至所述第六薄膜晶体管M6的漏极，并对所述第六薄膜晶体管M6的漏极进行初始化，经由所述第一薄膜晶体管M1和第二薄膜晶体管M2提供至所述有机发光二极管OLED的阳极，并对所述有机发光二极管OLED的阳极进行初始化。由此，减缓了所述有机发光二极管OLED器件和驱动薄膜晶体管M6的老化，增加了所述有机发光二极管OLED和驱动薄膜晶体管M6的使用寿命。
在此过程中，由于所述第四薄膜晶体管M4导通，所述数据线DATA提供的数据电压Vdata经由所述第四薄膜晶体管M4写入第一节点N1。由上述可知，所以数据电压Vdata和初始化电压Vref的总电压Vdata+Vref被提供至第一节点N1。
在第二阶段T2，由于第一扫描线S1提供的扫描信号由低电平变为高电平，所述第二薄膜晶体管M2和第五薄膜晶体管M5均由导通变为截止，所述参考电源VREF无法通过所述第二薄膜晶体管M2将初始化电压Vref提供至所述有机发光二极管OLED的阳极，从而停止对有机发光二极管OLED的阳极的初始化。
在此过程中，所述参考电源VREF停止对第一节点N1的初始化，同时由于所述第四薄膜晶体管M4导通，因此仅有数据电压Vdata经由数据线DATA传输到第一节点N1。
在第三阶段T3，由于第三扫描线S3提供的扫描信号由低电平变为高电平，所述第七薄膜晶体管M7由导通变为截止，从而停止将参考电源VREF提供的初始化电压Vref提供至所述第一薄膜晶体管M1的源极与所述第三薄膜晶体管M3的漏极之间的第三节点N3，使得所述参考电源VREF无法通过第一薄膜晶体管M1、第三薄膜晶体管M3和第七薄膜晶体管M7将初始化电压Vref提供至所述第六薄膜晶体管M6的栅极和漏极，从而停止对所述第六薄膜晶体管M6的栅极和漏极的初始化。同时，由于第二扫描线 S2提供的扫描信号保持低电平，第一电源ELVDD提供的第一电源电压VDD传输至所述第六薄膜晶体管M6的源极，同时对所述第六薄膜晶体M6的阈值电压进行采样，存储电容C1进行充电，直至第二节点N2处的电压即所述第六薄膜晶体管M6的栅极电压Vg6达到VDD-Vth。其中，Vth是所述第六薄膜晶体管M6的阈值电压的绝对值。
在此过程中，由于所述第二薄膜晶体管M2处于截止状态，作为驱动晶体管的第六薄膜晶体管M6和有机发光二极管OLED之间的电连接阻断，因此所述有机发光二极管OLED处于非发射状态。
在第四阶段T4，由于第二扫描线S2提供的扫描信号由低电平变为高电平，所述第一薄膜晶体管M1、第三薄膜晶体管M3和第四薄膜晶体管M4均由导通变为截止，停止写入数据电压Vdata，同时存储电容C1停止充电，从而完成对第六薄膜晶体管M6的阈值电压的采样。
在此过程中，由于所述第四薄膜晶体管M4截止，所述数据线DATA提供的数据电压Vdata停止写入第一节点N1，所述第一节点N1处的电压为数据电压Vdata。
之后，所述数据线DATA提供的数据电压Vdata由高电平变为低电平，驱动芯片开始输出下一行像素的数据信号。同时，由于第一扫描线S1提供的扫描信号也由高电平变为低电平，所述第二薄膜晶体管M2和第五薄膜晶体管M5均由截止变为导通，所述参考电源VREF提供的初始化电压Vref经由第五薄膜晶体管M5提供至第一节点N1,所述第六薄膜晶体管M6导通并经由所述第二薄膜晶体管M2输出电流。由于所述存储电容C1的电压不会突变，所以第二节点N2处的电压(即第六薄膜晶体管M6的栅极电压Vg6)将会跟随所述第一节点N1处的电压变化而变化。
由上述可知，所述第一节点N1处的电压由Vdata变为Vref，变化量为Vdata-Vref。因此，所述第六薄膜晶体管M6的栅极电压Vg6由以下公式进 行计算：
Vg6＝VDD-Vth-(Vdata-Vref)  式1；
其中，Vth为所述第六薄膜晶体管M6的阈值电压的绝对值，VDD为所述第一电源ELVDD提供的第一电源电压，Vdata为所述数据线DATA提供的数据电压，Vref为参考电源VREF提供的初始化电压。
由于所述第六薄膜晶体管M6的源极电压等于所述第一电源ELVDD提供的第一电源电压VDD，因此所述第六薄膜晶体管M6的栅源电压Vsg6，即所述第六薄膜晶体管M6的栅极和源极之间的电压差可由以下公式进行计算：
Vsg6＝VDD-(VDD-Vth-(Vdata-Vref))  式2；
由公式1和公式2可得：
Vsg6-Vth＝Vdata-Vref  式3；
所述有机发光二极管OLED发出与提供的电流成比例的光，此时流过所述有机发光二极管OLED的电流Ion的计算公式为：
Ion＝K×(Vsg6-Vth)2  式4；
其中，K为薄膜晶体管的电子迁移率、宽长比、单位面积电容三者之积。
由公式3和公式4可得：
Ion＝K×(Vdata-Vref)2
基于上述公式的表达式可知，流过所述有机发光二极管OLED的电流与所述电源电压和第六薄膜晶体管M6的阈值电压都没有关系，只与数据电压Vdata、初始化电压Vref以及常数K有关。即使第六薄膜晶体管M6的阈值电压存在偏差，电源走线阻抗影响了实际到达像素电路的电源电压也不会对流过所述有机发光二极管OLED的电流Ion造成影响。因此，采用所述像素电路20及其驱动方法能够完全避免因阈值电压偏差和电源走线阻 抗而造成的亮度不均现象。同时，增加所述有机发光二极管OLED和作为驱动晶体管的第六薄膜晶体管M6的使用寿命。
【实施例二】
请参考图4，其为本发明实施例二的像素电路的电路图。如图4所示，所述像素电路30包括：第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、存储电容C1和有机发光二极管OLED；所述第六薄膜晶体管M6的源极与第一电源ELVDD连接，所述第六薄膜晶体管M6的漏极分别与所述第一薄膜晶体管M1的漏极和所述第二薄膜晶体管M2的源极连接，所述第二薄膜晶体管M2的漏极与所述有机发光二极管OLED的阳极连接，所述有机发光二极管OLED的阴极与第二电源ELVSS连接，所述第六薄膜晶体管M6的栅极与所述第三薄膜晶体管M3的源极和所述存储电容C1的一端连接，所述存储电容C1的另一端分别与所述第四薄膜晶体管M4的漏极和所述第五薄膜晶体管M5的源极连接，所述第四薄膜晶体管M4的源极与数据线DATA连接，所述第五薄膜晶体管M5和第七薄膜晶体管M7的漏极均与参考电源VREF连接，所述第七薄膜晶体管M7的源极分别与所述第一薄膜晶体管M1的源极和所述第三薄膜晶体管M3的漏极连接。
具体的，所述像素电路30包含实施例一中所述像素电路20的所有特征，本实施例与实施例一的区别在于，所述第二节点N2和第二扫描线S2之间设置有升压电容C2，通过所述升压电容C2能够对所述第二节点N2进行升压。
请结合参考图3和图4，当所述第二扫描线S2提供的扫描信号在第四阶段T4从低电平跳到高电平时，所述升压电容C2根据所述第二扫描线S2提供的扫描信号的变化量和所述存储电容C1与升压电容C2的结合比 {C2/(C1+C2)}来对所述第二节点N2进行升压，使得所述第二节点N2的电压即所述第六薄膜晶体管M6的栅极电压Vg6升高，从而减少了第六薄膜晶体管M6的漏电流，进而提高了显示对比度。
本实施例中的第一扫描线S1、第二扫描线S2和第三扫描线S3提供的扫描信号的时序要求与实施例一中的第一扫描线S1、第二扫描线S2和第三扫描线S3提供的扫描信号的时序要求相同，在此不再一一赘述，具体内容请参见实施例一中像素电路的驱动方法的第一阶段T1至第四阶段T4。
需要说明的是，本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的像素电路而言，由于与实施例公开的像素电路的驱动方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
相应的，本发明还提供了一种有机发光显示器，所述有机发光显示器包括如上所述的像素电路。
综上，在本发明提供的像素电路及其驱动方法和有机发光显示器中，所述像素电路通过所述第一薄膜晶体管、第二薄膜晶体管和第七薄膜晶体管对所述有机发光二极管的阳极进行初始化，并通过所述第一薄膜晶体管、第三薄膜晶体管和第七薄膜晶体管对作为驱动元件的第六薄膜晶体管的栅极和漏极进行初始化，从而减缓所述有机发光二极管和第六薄膜晶体管的老化，增加所述有机发光二极管和第六薄膜晶体管的使用寿命，而且，作为驱动元件的第六薄膜晶体管所输出的电流与所述第六薄膜晶体管的阈值电压和电源走线的阻抗无关，因此能够避免由薄膜晶体管的阈值电压偏差和电源走线的阻抗不同所造成的亮度不均。进一步的，所述像素电路通过所述升压电容对所述第六薄膜晶体管的栅极电压进行升压，从而减少第六薄膜晶体管的漏电流，进而提高显示对比度。由此，采用所述像素电路及 其驱动方法的有机发光显示器不但增加了使用寿命，而且提高了显示质量。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (10)

  1. 一种像素电路，其特征在于，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、存储电容和有机发光二极管；所述第六薄膜晶体管的源极与第一电源连接，所述第六薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的源极连接，所述第二薄膜晶体管的漏极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极与第二电源连接，所述第六薄膜晶体管的栅极与所述第三薄膜晶体管的源极和所述存储电容的一端连接，所述存储电容的另一端分别与所述第四薄膜晶体管的漏极和所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的源极与数据线连接，所述第五薄膜晶体管和第七薄膜晶体管的漏极均与参考电源连接，所述第七薄膜晶体管的源极分别与所述第一薄膜晶体管的源极和所述第三薄膜晶体管的漏极连接。
  2. 如权利要求1所述的像素电路，其特征在于，所述第一电源和第二电源用于为所述有机发光二极管提供电源电压，所述参考电源用于为所述第六薄膜晶体管的栅极和漏极以及所述有机发光二极管的阳极提供初始化电压。
  3. 如权利要求1所述的像素电路，其特征在于，所述第二薄膜晶体管和第五薄膜晶体管的栅极均与第一扫描线连接，所述第一扫描线用于控制初始化和稳定电容，所述第一薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管的栅极均与第二扫描线连接，所述第二扫描线用于分别控制数据电压的写入和所述第六薄膜晶体管的阈值电压的采样，所述第七薄膜晶体管的栅极与第三扫描线连接，所述第三扫描线用于控制初始化电压的写入。
  4. 如权利要求1所述的像素电路，其特征在于，驱动所述像素电路的 扫描周期包括第一阶段至第四阶段；
    所述第六薄膜晶体管的栅极、第六薄膜晶体管的漏极以及有机发光二极管的阳极在所述第一阶段开始初始化，所述有机发光二极管的阳极在所述第二阶段结束初始化，所述第六薄膜晶体管的栅极和漏极在所述第三阶段结束初始化，所述第六薄膜晶体管的阈值电压在所述第三阶段进行采样，所述第六薄膜晶体管在所述第四阶段导通并提供电流至所述有机发光二极管。
  5. 如权利要求1所述的像素电路，其特征在于，所述第六薄膜晶体管提供至所述有机发光二极管的电流由所述数据线提供的数据电压和参考电源提供的初始化电压决定，而与所述第一电源和第二电源提供的电源电压以及所述第六薄膜晶体管的阈值电压无关。
  6. 如权利要求3所述的像素电路，其特征在于，还包括一升压电容，所述升压电容设置于所述第二扫描线与所述第六薄膜晶体管的栅极、第三薄膜晶体管的源极、存储电容的一端的连接点之间。
  7. 一种如权利要求1至6中任一项所述的像素电路的驱动方法，其特征在于，包括：
    扫描周期分为第一阶段、第二阶段、第三阶段和第四阶段，其中，
    在第一阶段，与所述第二薄膜晶体管和第五薄膜晶体管的栅极连接的第一扫描线提供的扫描信号保持低电平，与所述第一薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管的栅极连接的第二扫描线和与所述第七薄膜晶体管的栅极连接的第三扫描线提供的扫描信号均由高电平变为低电平，所述第一薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管和第七薄膜晶体管均由截止变为导通，所述参考电源提供的初始化电压分别对所述第六薄膜晶体管的栅极、第六薄膜晶体管的漏极以及有机发光二极管的阳极进行初始化，所述数据线提供的数据电压经由所述第四薄膜晶体管写入所述第四 薄膜晶体管的漏极与第五薄膜晶体管的源极、存储电容的另一端的连接点；
    在第二阶段，第一扫描线提供的扫描信号由低电平变为高电平，所述第二扫描线和第三扫描线提供的扫描信号保持低电平，所述第二薄膜晶体管和第五薄膜晶体管均由导通变为截止，停止对所述有机发光二极管的阳极的初始化；
    在第三阶段，第一扫描线提供的扫描信号保持高电平，所述第二扫描线提供的扫描信号保持低电平，第三扫描线提供的扫描信号由低电平变为高电平，所述第七薄膜晶体管由导通变为截止，所述第二薄膜晶体管和第五薄膜晶体管处于截止状态，停止对所述第六薄膜晶体管的栅极和漏极的初始化，同时对第六薄膜晶体管的阈值电压进行采样；
    在第四阶段，第一扫描线和第三扫描线提供的扫描信号均保持高电平，第二扫描线提供的扫描信号由低电平变为高电平，所述第一薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管均由导通变为截止，停止写入数据电压，同时完成对所述第六薄膜晶体管的阈值电压的采样；采样完成之后，所述第一扫描线提供的扫描信号由高电平变为低电平，所述第二薄膜晶体管和第五薄膜晶体管均由截止变为导通，所述第六薄膜晶体管经由所述第二薄膜晶体管输出电流以驱动所述有机发光二极管发光。
  8. 如权利要求7所述的像素电路的驱动方法，其特征在于，当所述第七薄膜晶体管和第三薄膜晶体管共同导通时，由所述参考电源对所述第六薄膜晶体管的栅极进行初始化；
    当所述第一薄膜晶体管和第七薄膜晶体管共同导通时，由所述参考电源对所述第六薄膜晶体管的漏极进行初始化；
    当所述第一薄膜晶体管、第二薄膜晶体管和第七薄膜晶体管共同导通时，由所述参考电源对所述有机发光二极管的阳极进行初始化。
  9. 如权利要求7所述的像素电路的驱动方法，其特征在于，在第四阶 段，设置于所述第二扫描线与所述第六薄膜晶体管的栅极之间的升压电容响应于所述第二扫描线提供的扫描信号而对所述第六薄膜晶体管的栅极、第三薄膜晶体管的源极、存储电容的一端的连接点处的电压进行升压，使得所述第六薄膜晶体管的栅极电压升高。
  10. 一种有机发光显示器，其特征在于，包括：如权利要求1至6中任一项所述的像素电路。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102527226B1 (ko) * 2015-11-23 2023-05-02 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106057128B (zh) * 2016-08-24 2018-07-06 中国科学院上海高等研究院 一种电压编程型amoled像素电路及其驱动方法
CN107886898B (zh) * 2016-09-30 2019-12-03 昆山国显光电有限公司 一种oled像素补偿电路及其控制方法
CN106652912B (zh) 2016-12-13 2020-05-19 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
TWI595468B (zh) * 2017-02-20 2017-08-11 友達光電股份有限公司 有機發光二極體面板及其相關的電源驅動系統
US10311794B2 (en) * 2017-08-23 2019-06-04 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Pixel driver circuit and driving method thereof
CN207474026U (zh) * 2017-10-31 2018-06-08 昆山国显光电有限公司 一种像素电路和显示装置
CN108053792B (zh) * 2018-01-19 2019-09-20 昆山国显光电有限公司 一种像素电路及其驱动方法、显示装置
KR102485163B1 (ko) 2018-02-12 2023-01-09 삼성디스플레이 주식회사 표시장치
CN111837173B (zh) * 2018-03-19 2022-07-22 夏普株式会社 显示装置以及其驱动方法
KR102604731B1 (ko) * 2018-05-30 2023-11-22 엘지디스플레이 주식회사 표시 장치
CN108806596A (zh) * 2018-06-26 2018-11-13 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
CN109711391B (zh) * 2019-01-18 2021-08-06 上海思立微电子科技有限公司 一种图像采集电路、采集方法及终端设备
CN109785797B (zh) * 2019-03-14 2020-11-17 电子科技大学 一种amoled像素电路
CN110232889B (zh) * 2019-05-09 2021-07-06 深圳市华星光电半导体显示技术有限公司 像素驱动电路以及显示面板
US20220335880A1 (en) * 2019-12-19 2022-10-20 Chongqing Konka Photoelectric Technology Research Institute Co., Ltd. Electroluminescence Display, Pixel Compensating Circuit and Voltage Compensating Method Based on Pixel Compensating Circuit
CN111540303A (zh) * 2020-01-17 2020-08-14 重庆康佳光电技术研究院有限公司 一种驱动电路及显示装置
US11074864B1 (en) * 2020-03-26 2021-07-27 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with global compensation
CN111445856B (zh) 2020-05-13 2021-04-09 京东方科技集团股份有限公司 驱动电路、驱动方法、显示面板及显示装置
KR20210149267A (ko) 2020-06-01 2021-12-09 삼성디스플레이 주식회사 표시장치
CN111564141A (zh) * 2020-06-15 2020-08-21 京东方科技集团股份有限公司 补偿电路及其补偿方法、像素电路以及显示装置
KR20220001034A (ko) * 2020-06-26 2022-01-05 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
KR102412729B1 (ko) * 2021-01-18 2022-06-23 연세대학교 산학협력단 신축성 디스플레이 장치
CN114038409B (zh) * 2021-11-24 2023-03-17 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN117012152B (zh) * 2023-08-31 2024-05-17 惠科股份有限公司 像素驱动电路及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100047694A (ko) * 2008-10-29 2010-05-10 엘지디스플레이 주식회사 유기발광다이오드 표시장치
US20110157126A1 (en) * 2009-12-31 2011-06-30 Bo-Yong Chung Pixel circuit and organic light emitting diode display device using the same
CN102222465A (zh) * 2011-03-17 2011-10-19 友达光电股份有限公司 具临界电压补偿机制的有机发光显示装置及其驱动方法
CN103578410A (zh) * 2012-08-01 2014-02-12 乐金显示有限公司 有机发光二极管显示装置及其驱动方法
CN104050917A (zh) * 2014-06-09 2014-09-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005202070A (ja) * 2004-01-14 2005-07-28 Sony Corp 表示装置、および画素回路
GB2411758A (en) 2004-03-04 2005-09-07 Seiko Epson Corp Pixel circuit
TWI340370B (en) 2006-08-24 2011-04-11 Chimei Innolux Corp System for displaying image
KR101022106B1 (ko) 2008-08-06 2011-03-17 삼성모바일디스플레이주식회사 유기전계발광표시장치
KR101064425B1 (ko) * 2009-01-12 2011-09-14 삼성모바일디스플레이주식회사 유기전계발광 표시장치
KR101749944B1 (ko) * 2009-12-28 2017-06-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액정 표시 장치 및 전자 기기
KR101329964B1 (ko) 2009-12-31 2013-11-13 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치
KR101152466B1 (ko) 2010-06-30 2012-06-01 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101162864B1 (ko) 2010-07-19 2012-07-04 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기 전계발광 표시장치
KR101682690B1 (ko) * 2010-07-20 2016-12-07 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101779076B1 (ko) * 2010-09-14 2017-09-19 삼성디스플레이 주식회사 화소를 포함하는 유기전계발광 표시장치
KR101911489B1 (ko) 2012-05-29 2018-10-26 삼성디스플레이 주식회사 화소를 갖는 유기전계발광 표시장치와 그의 구동방법
CN103077677B (zh) 2012-12-04 2015-02-25 彩虹（佛山）平板显示有限公司 用于显示器的驱动系统
KR20140081262A (ko) 2012-12-21 2014-07-01 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR102098143B1 (ko) 2013-01-17 2020-05-27 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR20140132504A (ko) 2013-05-08 2014-11-18 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR20150006145A (ko) 2013-07-08 2015-01-16 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100047694A (ko) * 2008-10-29 2010-05-10 엘지디스플레이 주식회사 유기발광다이오드 표시장치
US20110157126A1 (en) * 2009-12-31 2011-06-30 Bo-Yong Chung Pixel circuit and organic light emitting diode display device using the same
CN102222465A (zh) * 2011-03-17 2011-10-19 友达光电股份有限公司 具临界电压补偿机制的有机发光显示装置及其驱动方法
CN103578410A (zh) * 2012-08-01 2014-02-12 乐金显示有限公司 有机发光二极管显示装置及其驱动方法
CN104050917A (zh) * 2014-06-09 2014-09-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3208793A4 *

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