WO2015000249A1 - 像素电路、显示面板及显示装置 - Google Patents

像素电路、显示面板及显示装置 Download PDF

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Publication number
WO2015000249A1
WO2015000249A1 PCT/CN2013/087592 CN2013087592W WO2015000249A1 WO 2015000249 A1 WO2015000249 A1 WO 2015000249A1 CN 2013087592 W CN2013087592 W CN 2013087592W WO 2015000249 A1 WO2015000249 A1 WO 2015000249A1
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Prior art keywords
switching transistor
source
capacitor
signal source
gate
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PCT/CN2013/087592
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English (en)
French (fr)
Inventor
祁小敬
谭文
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/370,189 priority Critical patent/US9262966B2/en
Publication of WO2015000249A1 publication Critical patent/WO2015000249A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of organic light emitting display technologies, and in particular, to a pixel circuit, a display panel, and a display device. Background technique
  • Organic light-emitting display devices have attracted much attention due to their low power consumption, high brightness, low cost, wide viewing angle, and fast response speed, and have been widely used in the field of organic light-emitting technology.
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • AMOLED active matrix OLED
  • FIG. 1 a schematic diagram of a pixel circuit structure for illuminating a conventional driving light-emitting device, taking an n-type driving transistor as an example, the pixel circuit includes: a driving transistor T1, a capacitor Cl, and a switching transistor T2;
  • the first end of the capacitor C1 is connected to the gate of the driving transistor T1, the second end is connected to the low-level reference voltage source V ss ;
  • the drain of the switching transistor T2 is connected to the gate of the driving transistor T1, the gate and the gate signal source V Scan is connected, the source is connected to the data signal source V Data ;
  • the source of the driving transistor T1 is connected to the high-level reference voltage source V DD , the drain is connected to the anode of the light-emitting device D1, and the negative electrode and the low level of the light-emitting device D1
  • the reference voltage source V ss is connected.
  • the gate signal source output voltage signal VScan turns on the switching transistor T2, the data signal source and the branch of the capacitor C1 are turned on, and the data signal source output data signal V Data is loaded to The second end of the capacitor C1 charges the capacitor C1; when the light emitting device D1 is driven to emit light, the capacitor C1 is discharged to drive the light emitting device D1 to emit light.
  • the pixel circuit shown in FIG. 1 can only drive one light-emitting device to emit light, and each light-emitting device corresponds to a light-emitting area of one pixel unit, and each time an image is scanned, a signal is written into the pixel circuit, and each frame of image is scanned.
  • the light-emitting areas corresponding to the pixel units are all to be illuminated.
  • the AMOLED display drives the OLED illumination to be a DC drive.
  • the electric field corresponding to the DC drive voltage for a long time causes the internal OLED to leave.
  • the sub-polarization causes the OLED to form a built-in electric field, thereby increasing the threshold voltage of the OLED, greatly reducing the luminous efficiency of the OLED, and shortening the lifetime of the OLED.
  • the lifetime is an important factor that restricts the wide application of organic light-emitting display devices, especially large-sized, high-brightness organic light-emitting display devices. Summary of the invention
  • a pixel circuit, a display panel and a display device are provided for improving the life of a light emitting device in a display device.
  • a pixel circuit provided by an embodiment of the present invention includes: a charging sub-circuit, a first driving sub-circuit, and a second driving sub-circuit, a first capacitor and a second capacitor;
  • the first end of the first capacitor is connected to the first ends of the first driving sub-circuit and the second driving sub-circuit, and the second end of the first capacitor and the first end of the charging sub-circuit and the second capacitor Connected
  • the second end of the first driving sub-circuit is connected to the first light-emitting device, and the second end of the second driving sub-circuit is connected to the second light-emitting device, wherein the first driving sub-circuit flows into the driving of the first light-emitting device
  • the current and the driving current of the second driving sub-circuit flowing into the second light emitting device are opposite in direction;
  • the charging sub-circuit is configured to charge the first capacitor, the second capacitor is used to maintain a voltage of the second end of the first capacitor; and the first capacitor discharges to cause the first driving sub-circuit to drive the first illuminating The device emits light, or causes the second driver circuit to drive the second light emitting device to emit light.
  • the first driving subcircuit includes an N-type driving transistor
  • the second driving sub-circuit includes a P-type driving transistor
  • the gate of the N-type driving transistor is connected to the first end of the first capacitor, the source is connected to a first reference voltage source capable of providing an AC signal, and the drain is connected to a cathode of the first light emitting device, a positive electrode of a light emitting device is connected to a second reference voltage source capable of providing an alternating current signal; a second end of the second capacitor is connected to the first reference voltage source;
  • a gate of the P-type driving transistor is connected to a first end of the first capacitor; a source is connected to the first reference voltage source, a drain is connected to a positive electrode of the second light emitting device, and a cathode of the second light emitting device Connected to the second reference voltage source.
  • the charging subcircuit includes:
  • a data signal source a data signal source, a first gate signal source, and a first switching transistor coupled to the data signal source and the first gate signal source;
  • a drain of the first switching transistor is connected to the data signal source, a source is connected to the second end of the first capacitor, and a gate is connected to the first gate signal source;
  • the first gate signal source is configured to control the first switching transistor to be turned on, such that the data signal source is turned on with a branch of the first capacitor, and the data signal source is charged to the first capacitor.
  • the method further includes a reset sub-circuit, the reset sub-circuit comprising: a second gate signal source, a second open transistor, and a third reference voltage source to be reset to a reference reset voltage; a source of the second switching transistor and the first The second end of the capacitor is connected, the drain is connected to a third reference voltage source to be reset to a reference reset voltage, and the gate is connected to the second gate signal source.
  • the reset sub-circuit comprising: a second gate signal source, a second open transistor, and a third reference voltage source to be reset to a reference reset voltage; a source of the second switching transistor and the first The second end of the capacitor is connected, the drain is connected to a third reference voltage source to be reset to a reference reset voltage, and the gate is connected to the second gate signal source.
  • the reset sub-circuit is configured to reset a signal stored in the first capacitor to a reference reset voltage before the charging sub-circuit charges the first capacitor.
  • the first compensation subcircuit includes a third switching transistor
  • the second compensation subcircuit includes a fourth switching transistor
  • the source of the third switching transistor is connected to the gate of the N-type driving transistor, the drain is connected to the drain of the N-type driving transistor, and the gate is connected to the signal source of the third gate;
  • the source of the fourth switching transistor is connected to the gate of the P-type driving transistor, the drain is connected to the drain of the P-type driving transistor, and the gate is connected to the third gate signal source.
  • a fifth switching transistor that controls conduction between the first light emitting device and the second light emitting device and the second reference voltage source
  • the gate of the fifth switching transistor being connected to a charge control signal source a source connected to the anode of the first light emitting device and a cathode of the second light emitting device, the drain being connected to the second reference voltage source, wherein the charge control signal source is used to control the opening of the fifth switching transistor With off.
  • the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are N-type transistors, or
  • the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are P-type transistors
  • the second gate signal source and the third gate signal source are the same gate signal source.
  • a display panel comprising a plurality of pixel units arranged in a matrix surrounded by a gate line and a data line, each pixel unit including a pixel circuit and a light connection connected to the pixel circuit Device
  • the pixel circuit is the pixel circuit
  • the charging sub-circuits in the pixel circuits of the same row are connected to the same gate line and are located in the same column.
  • the charging sub-circuit in the pixel circuit is connected to the same data line; in a frame image display stage, the first driving sub-circuit and the second driving sub-circuit respectively drive the first light-emitting device to emit light and the second light-emitting device to emit light respectively
  • the charging subcircuit charges the first capacitor through a data line and a gate line.
  • the pixel circuit is the above pixel circuit
  • a drain of the first switching transistor is connected to the data signal source through a data line, and a gate is connected to the first gate signal source through the gate line;
  • the gate signal source and the data signal source charge the first capacitor through a gate line and a data line, respectively.
  • a display device comprising the above display panel.
  • the invention provides two first light-emitting devices and a second light-emitting device connected in parallel in each pixel region, and the working currents of the first light-emitting device and the second light-emitting device are opposite in direction, and are respectively driven by an N-type driving transistor and a p-type driving The transistor drives the illumination.
  • the first light-emitting device and the second light-emitting device alternately emit light, which can increase the life of each light-emitting device.
  • FIG. 1 is a schematic structural view of a conventional pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is a third schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 5 is a fourth schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a fifth schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 7 is a sixth schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • Figure 8 is a timing chart showing the operation of the pixel circuit shown in Figure 6;
  • FIG. 9 is a schematic structural diagram of a pixel circuit having a reset function corresponding to a first driving sub-circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a pixel circuit having a charging function corresponding to a first driving sub-circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a pixel circuit having a function of driving a light emitting device corresponding to a first driving sub-circuit according to an embodiment of the present invention
  • FIG. 12 is a schematic structural diagram of a pixel circuit having a reset function corresponding to a second driving sub-circuit according to an embodiment of the present invention.
  • FIG. 13 is a diagram showing a pixel having a charging function corresponding to a second driving sub-circuit according to an embodiment of the present invention.
  • Road structure diagram is a diagram showing a pixel having a charging function corresponding to a second driving sub-circuit according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a pixel circuit having a function of driving a light emitting device to emit light corresponding to a second driving sub-circuit according to an embodiment of the present invention
  • FIG. 15 is a schematic structural diagram of an organic light emitting display panel according to an embodiment of the present invention. detailed description
  • a pixel circuit, a display panel and a display device are provided for improving the lifetime of the light emitting device in the display device and improving the uneven display of the light emitting device.
  • the source of the transistor mentioned in the embodiment of the present invention may be the drain of the transistor, and the drain of the transistor may also be Is the source of the transistor.
  • each pixel unit includes a pixel circuit.
  • the first driving and the second lighting devices are alternately illuminated by providing two first driving sub-circuits and a second driving sub-circuit connected in parallel in each pixel unit.
  • the first driving sub-circuit drives the first light-emitting device to emit light in the first (1/2) t time
  • the second driving sub-circuit drives the second light in the second (1/2) t time. The device emits light.
  • the lifetime of the light-emitting device according to the embodiment of the present invention is at least doubled compared to the pixel circuit in which one light-emitting device is disposed in one pixel unit.
  • the writing phase and the lighting phase of the number Before the first driving sub-circuit and the second driving sub-circuit respectively drive the first light-emitting device and the second light-emitting device to emit light, the charging sub-circuit is used to charge the capacitor in the driving sub-circuit, and the capacitor is charged and discharged in the light-emitting phase, and the driving is performed.
  • a light emitting device in a driving sub circuit or a second driving sub circuit emits light.
  • a pixel circuit according to an embodiment of the present invention includes:
  • a charging sub-circuit 1 a first capacitor Cl, a second capacitor C2, a first driving sub-circuit 2 and a second driving sub-circuit 3;
  • the first end of the first capacitor C1 is connected to the first ends of the first driving sub-circuit 2 and the second driving sub-circuit 3, and the second end of the first capacitor C1 and the first end of the charging sub-circuit 1 and the second capacitor C2 Connected
  • the second end of the first driving sub-circuit 2 is connected to the first light-emitting device D1
  • the second end of the second driving sub-circuit 3 is connected to the second light-emitting device D2, wherein the first driving sub-circuit 2 flows into the first light-emitting device D1.
  • the driving current is opposite to the driving current of the second driving sub-circuit 3 flowing into the second light emitting device D2; the line segment with an arrow in Fig. 2 indicates the direction of the driving current.
  • the charging sub-circuit 1 is for charging the first capacitor C1, and the second capacitor C2 is for maintaining the voltage of the second end of the first capacitor C1; when the first capacitor C1 is discharged, causing the first driving sub-circuit 2 to drive the first light-emitting device D1 to emit light, Or causing the second driving sub-circuit 3 to drive the second light emitting device D2 to emit light.
  • the illuminating device (such as the first illuminating device and the second illuminating device) used in the embodiments of the present invention may be an OLED or other organic electroluminescent device, and the like, which is not specifically limited.
  • first driving sub-circuit and the second driving sub-circuit as shown in FIG. 2 share the first capacitor Cl.
  • the first driving sub-circuit and the second driving sub-circuit of the embodiment of the present invention may also be respectively connected to one capacitor, and the two capacitors are connected in parallel.
  • the pixel circuit provided in Fig. 2 will be more specifically described below by way of example.
  • a pixel circuit according to an embodiment of the present invention includes:
  • a charging sub-circuit 1 a first capacitor C1, a second capacitor C2, a first driving sub-circuit 2 and a second driving sub-circuit 3;
  • the first driving sub-circuit 2 is connected to the first light-emitting device D1;
  • the second driving sub-circuit 3 is The second light emitting device D2 is connected;
  • the first driving sub-circuit 2 includes: an n-type driving transistor Tn;
  • the gate of the ⁇ -type driving transistor Tn is connected to the first end (A end) of the first capacitor C1, and the source is connected to the output end of the first reference voltage source 11 that can provide an AC voltage signal;
  • the negative terminal of the light emitting device D1 is connected;
  • the second end (B end) of the first capacitor C1 is connected to the first end (C end) of the second capacitor C2, and the second end (D end) of the second capacitor C2 is connected to the first reference
  • the output terminals of the voltage source 11 are connected (ie, the first capacitor C1 and the second capacitor C2 are connected in series);
  • the anode of the first light emitting device D1 is connected to the output end of the second reference voltage source 12 that can provide an alternating voltage signal;
  • the second driving sub-circuit 3 includes: a P-type driving transistor Tp;
  • a gate of the ⁇ -type driving transistor ⁇ is connected to a first end ( ⁇ terminal) of the first capacitor C1, a source is connected to an output end of the first reference voltage source 11; a drain is connected to an anode of the second light emitting device D2; a second end (terminal) of the capacitor C1 is connected to the first end (C end) of the second capacitor C2, and a second end (D end) of the second capacitor C2 is connected to the output end of the first reference voltage source 11; a cathode of the second light emitting device D2 is connected to an output end of the second reference voltage source 12;
  • the charging sub-circuit 1 is connected to the second end ( ⁇ end) of the first capacitor C1;
  • the charging sub-circuit 1 is for inputting a data signal to the first capacitor C1 before driving the first light emitting device D1 or the second light emitting device D2 to emit light, and the second capacitor C2 is for maintaining the potential of the second end (B terminal) of the first capacitor C1 .
  • the first driving sub-circuit 2 and the second driving sub-circuit 3 are for driving the first light-emitting device D1 and the second light-emitting device D2 to emit light, respectively, under the control of the timing signal.
  • the first light-emitting device and the second light-emitting device alternately emit light, and their respective lifetimes are at least doubled.
  • the first driving sub-circuit and the second driving sub-circuit share the first capacitor and the second capacitor, and share the first reference voltage source and the second reference voltage source;
  • the circuit and the second driver sub-circuit operate at different time periods, and the first capacitor, the second capacitor, the first reference voltage source, and the second reference voltage source operate in a time-sharing manner, and the structure of the circuit can be collapsed.
  • the pixel circuit according to the embodiment of the present invention only needs to switch between the high and low states of the output voltages of the first reference voltage source and the second reference voltage source, so that the first driver subcircuit and the second driver subcircuit are alternated. jobs. Specifically, when the first reference voltage source and the second reference voltage source respectively output high level and low level voltages, the second driving sub circuit drives the second light emitting device to emit light; when the first reference voltage source and the second reference voltage source When the low level and the high level voltage are respectively output, the first driving sub circuit drives the first light emitting device to emit light.
  • the light emitting device connected to the first driving sub-circuit is not limited to one, and the light emitting device connected to the second driving sub-circuit is not limited to one.
  • the first driving sub-circuit and the second driving sub-circuit may respectively be connected to a plurality of light-emitting devices connected in series, which are not specifically limited herein.
  • the high voltage of the voltage V SD outputted by the first reference voltage source is V DD
  • the low level voltage is V ss
  • the high level voltage of the reference voltage V DS output by the second reference voltage source is V DD
  • low power The flat voltage is Vsso V DD is a positive value greater than zero, and the value of V ss can be zero or a negative value less than zero.
  • the charging sub-circuit 1 shown in FIG. 3 may include:
  • a data signal source 13 a first gate signal source 14, and a first switching transistor T1 connected to the data signal source 13 and the first gate signal source 14;
  • the drain of the first switching transistor T1 is connected to the output end of the data signal source 13, the source is connected to the second end (B end) of the first capacitor C1, and the output of the gate and the first gate signal source 14 Connected; the first gate signal source 14 is used to control the opening and closing of the first switching transistor T1 under the control of the timing signal
  • the data source 13 is used to write a data signal to the first capacitor C1 when the first switching transistor T1 is turned on.
  • the first switching transistor T1 functions as a switch, which may be an N-type transistor or a P-type transistor.
  • the first switching transistor T1 shown in Fig. 4 is a P-type transistor.
  • the pixel circuit according to the embodiment of the present invention further includes a reset sub-circuit 4 for using the first capacitor C1 before charging the sub-circuit 1
  • the voltage at the two terminals (B terminal) is reset to the reference reset voltage V INI .
  • the reset sub-circuit 4 includes:
  • a second gate signal source 41 a second open transistor T2, and a third reference voltage source 42 that provides a reference reset voltage VJM;
  • the second switching transistor T2 has a source connected to the second terminal B of the first capacitor C1, a drain connected to the third reference voltage source 42 for providing a reference reset voltage, and a gate connected to the output terminal of the second gate signal source 41;
  • the voltage output by the third reference voltage source 42 may be a constant voltage having a certain value, and the output voltage may be a ground voltage GND.
  • the embodiment of the present invention avoids the problem of uneven illumination of each pixel caused by the difference in threshold voltages of different driving transistors.
  • the pixel circuit further includes a compensation sub-circuit that solves the above problem.
  • a pixel circuit further includes: a first compensation sub-circuit 5 connected to the first driving sub-circuit 2, and a second compensation sub-circuit 6 connected to the second driving sub-circuit 3;
  • the compensation sub-circuit 5 includes a third switching transistor T3; the source of the third switching transistor T3 is connected to the gate of the N-type driving transistor Tn, the drain is connected to the drain of the n-type driving transistor Tn, and the gate and the third gate signal are connected.
  • the output of source 15 is connected;
  • the second compensation sub-circuit 6 includes a fourth switching transistor T4; the source of the fourth switching transistor T4 is connected to the gate of the P-type driving transistor Tp, and the drain is connected to the drain of the ⁇ -type driving transistor ⁇ , the gate and the third The outputs of the gate signal source 15 are connected.
  • the first illuminating device and the second illuminating device according to the embodiment of the present invention may be an OLED or other organic electroluminescent device, etc., which is not specifically limited in the present invention.
  • the pixel circuit further includes: a fifth switching transistor ⁇ 5;
  • the gate of the fifth switching transistor T5 is connected to the output terminal of the charging control signal source 16, and the source is simultaneously connected to the anode of the first light emitting device D1 and the cathode of the second light emitting device D2, and the drain and the second reference voltage source 12 The outputs are connected.
  • the charge control signal source 16 controls the fifth switching transistor T5 to be turned on or off under the control of the timing.
  • the types of the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor may be identical or partially identical.
  • the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are all N-type transistors or both are N-type transistors.
  • the second gate signal source and the third gate signal source are the same gate signal source (ie, The common gate signal source), so that the purpose of the tubular circuit structure can be achieved.
  • the first gate source, the second gate source, and the third gate source are connected to the corresponding switching transistors through the gate lines.
  • the data signal source is coupled to the first switching transistor through a data line.
  • the first gate signal source is connected to the first switching transistor T1 through the gate line G_n, and the first gate signal source supplies the gate voltage to the first switching transistor T1 (the first gate signal source is not shown in FIG. 7).
  • the second gate signal source is connected to the second switching transistor T2 through the gate line G_(n-1), and the third gate signal source passes through the gate line 0_(11-1) and the third switching transistor T3 and the fourth switching transistor T4, respectively. Connected (the second gate source and the third gate source are not shown in Figure 7).
  • the second driver circuit that controls the pixel circuit drives the second light emitting device to emit light in the last 1/2 second.
  • the process of controlling the first driving sub-circuit to drive the first light emitting device to emit light specifically includes: a reset phase, the second gate signal source controls the second switching transistor to be turned on, and the third gate signal source controls the third switching transistor and the fourth The switching transistor is turned on; the charging control signal source controls the fifth switching transistor to be turned on; the first gate signal source controls the first switching transistor to be turned off; the first reference voltage source outputs a low level, and the second reference voltage source outputs a high level, so that the N type
  • the driving transistor, the first capacitor and the second capacitor are turned on, the voltage VJM outputted by the third reference voltage source is applied to the second end of the first capacitor, and the second end of the second capacitor is reset to V INI .
  • the first gate signal source controls the first switching transistor to be turned on
  • the second gate signal source controls the second switching transistor to be turned off
  • the third gate signal source controls the third switching transistor and the fourth switching transistor Turning off
  • the charging control signal source controls the fifth switching transistor to be turned off
  • the first reference voltage source outputs a low level
  • the second reference voltage source outputs a high level, so that the N-type driving transistor, the first capacitor, the second capacitor, and the data signal source
  • the branch is turned on, and the voltage output from the data signal source is loaded to the second end of the first capacitor, and the first capacitor stores the data signal.
  • the first gate signal source controls the first switching transistor to be turned off
  • the second gate signal source controls the second switching transistor to be turned off
  • the third gate signal source controls the third switching transistor and the fourth switching transistor to be turned off
  • the charging control signal source Controlling that the fifth switching transistor is turned on
  • the first reference voltage source outputs a low level
  • the second reference voltage source outputs a high level, so that the N-type driving transistor, the first capacitor, the second capacitor, and the first light-emitting device make a branch path
  • the first capacitor is discharged, and the first driving sub-circuit drives the first light emitting device to emit light.
  • the process of controlling the second driving sub-circuit to drive the second light emitting device to emit light specifically includes: a reset phase, the second gate signal source controls the second switching transistor to be turned on, and the third gate signal source controls the third switching transistor and the fourth The switching transistor is turned on; the charging control signal source controls the fifth switching transistor to be turned on; the first gate signal source controls the first switching transistor to be turned off; the first reference voltage source outputs a high level, and the second reference voltage source outputs a low level, so that the N type The driving transistor, the first capacitor and the second capacitor are turned on, the voltage VJM outputted by the third reference voltage source is applied to the second end of the first capacitor, and the second end of the second capacitor is reset to V INI .
  • the first gate signal source controls the first switching transistor to be turned on
  • the second gate signal source controls the second switching transistor to be turned off
  • the third gate signal source controls the third switching transistor and the fourth switching transistor to be turned off
  • the source control fifth switching transistor is turned off;
  • the first reference voltage source outputs a high level, and the second reference voltage source outputs a low level, so that the branches of the N-type driving transistor, the first capacitor, the second capacitor, and the data signal source are turned on
  • the voltage output from the data signal source is loaded to the second end of the first capacitor, and the first capacitor stores the data signal.
  • the first gate signal source controls the first switching transistor to be turned off
  • the second gate signal source controls the second switching transistor to be turned off
  • the third gate signal source controls the third switching transistor and the fourth switching transistor to be turned off
  • the charging control signal source Controlling the fifth switching transistor to be turned on
  • the first reference voltage source outputs a high level
  • the second reference voltage source outputs a low level, so that the N-type driving transistor, the first capacitor, the second capacitor, and the first light-emitting device make a branch path
  • the first capacitor is discharged, and the first driving sub-circuit drives the first light emitting device to emit light.
  • the working principle of the pixel circuit provided by the embodiment of the present invention will be specifically described below in conjunction with the pixel circuit shown in FIG. 6 and the timing chart of the pixel circuit shown in FIG. 6 ;
  • the first gate signal source 14 output voltage signal is V Scanl
  • the second gate signal source 41 output voltage signal is V Scan2
  • the third gate signal source 15 output voltage signal is V Scan3 ;
  • the second gate signal source 41 and the third gate signal source 15 have the same timing diagram; exemplarily, the second gate signal source 41 and the third gate signal source 15 are the same gate signal source; and the charging control signal source 16 outputs the voltage.
  • the signal is V EM .
  • V DD be a positive value above GND and V ss be a negative value below GND.
  • the first switching transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3, the fourth switching transistor ⁇ 4, and the fifth switching transistor ⁇ 5 are exemplified as ⁇ -type transistors.
  • the ⁇ -type transistor is turned on when the gate inputs a high-level voltage, and is turned off when a low-level voltage is input.
  • the ⁇ -type transistor is turned on when the gate inputs a low-level voltage, and is turned off when a high-level voltage is input.
  • driving the first light emitting device D1 to emit light corresponds to the reset phase (a phase), the writing phase (b phase), and the light emitting phase (c phase) in FIG. 8; driving the second light emitting device D2 to emit light corresponds to FIG.
  • Phase a The reset phase.
  • the first gate signal source 14 in FIG. 6 outputs a voltage VScan1 at a high level, and the first switching transistor T1 connected to the first gate signal source 14 is turned off;
  • the second gate signal source 41 and the third gate signal source 15 output voltages V Scan2 and V Scan3 are at a low level, and are respectively connected to the second gate signal source 41 and the third gate signal source 15 by a second switching transistor T2, a third The switching transistor ⁇ 3 and the fourth switching transistor ⁇ 4 are turned on; the third switching transistor ⁇ 3 is turned on, and the source and the drain of the ⁇ -type driving transistor ⁇ connected to the third switching transistor ⁇ 3 are turned on, and at this time, the ⁇ -type driving transistor ⁇ is equivalent It is the connection method of the diode.
  • the voltage V EM outputted by the charging control signal source 16 is at a low level, and the fifth switching transistor T5 connected to the charging control signal source 16 is turned on;
  • the first reference voltage source 11 outputs a low level voltage V ss
  • the second reference voltage source 12 outputs a high level voltage V DD .
  • the P-type driving transistor Tp is turned off, and the branch of the ⁇ -type driving transistor is broken.
  • the ⁇ -type driving transistor ⁇ is turned on, and the branch of the ⁇ -type driving transistor ⁇ is turned on.
  • the third reference voltage source 42 outputs a reference reset voltage V leg.
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit configuration shown in Fig. 9.
  • the branch circuit of the ⁇ -type driving transistor ⁇ , the first capacitor Cl, the third reference voltage source 42, the first reference voltage source 11 and the second reference voltage source 12 are turned on.
  • V A is the defect voltage
  • V B is the voltage at point B
  • V c is the voltage at point C.
  • Stage b Write phase.
  • the first gate signal source 14 in FIG. 6 outputs a voltage VScan1 at a low level, and the first switching transistor T1 connected to the first gate signal source 14 is turned on;
  • the second gate signal source 41 and the third gate signal source 15 output voltages V Scan2 and V Scan3 are at a high level, and are respectively connected to the second gate signal source 41 and the third gate signal source 15 by a second switching transistor T2, a third The switching transistor ⁇ 3 and the fourth switching transistor ⁇ 4 are turned off;
  • the voltage V EM outputted by the charging control signal source 16 is at a high level, and the fifth switching transistor T5 connected to the charging control signal source 16 is turned off;
  • the first reference voltage source 11 outputs a low level voltage V ss , and an output high level voltage V DD of the second reference voltage source 12.
  • the P-type driving transistor Tp is turned off, and the branch of the ⁇ -type driving transistor is broken.
  • the ⁇ -type driving transistor Tn is turned on, and the branch of the N-type driving transistor Tn is turned on.
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit structure shown in Fig. 10.
  • the first capacitor Cl, the second capacitor C2, the data signal source 13, the N-type driving transistor Tn, and the branch of the first reference voltage source 11 are turned on;
  • the data signal source 13 outputs a data signal V Data , and the data signal V Data is loaded to the second end (B terminal) of the first capacitor C1.
  • the first end (A terminal) of the first capacitor C1 is also loaded with the voltage V.
  • Stage c Illumination stage.
  • the output voltage V Scan1 of the first gate signal source 14 shown in FIG. 6 is at a high level, and the first switching transistor T1 connected to the first gate signal source 14 is turned off;
  • the second gate signal source 41 outputs a voltage V Scan2 at a high level, and the second switching transistor T2 connected to the second gate signal source 42 is turned off;
  • the third gate signal source 15 outputs a voltage V Scan3 at a high level, and is connected to the third gate signal source 15
  • the three-switch transistor T3 and the fourth switching transistor ⁇ 4 are turned off, and the connection mode of the ⁇ -type driving transistor ⁇ is a connection mode of the triode.
  • the voltage V EM outputted by the charging control signal source 16 is at a low level, and the fifth switching transistor T5 connected to the charging control signal source 16 is turned on;
  • the output voltage V SD of the first reference voltage source 11 is a low level voltage V ss
  • the output voltage V DS of the second reference voltage source 12 is a high level voltage V DD .
  • the branch of the first capacitor C1, the second capacitor C2, the N-type driving transistor, the first reference voltage source 11, the second reference voltage source 12, and the first light-emitting device D1 are turned on.
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit configuration shown in Fig. 11.
  • VfVData+VtM-VjN The first capacitor C1 is discharged, and the gate voltage of the type II driving transistor Til is VfVData+VtM-VjN.
  • VData+VtM-V leg-V SS is brought into the formula -V leg -V SS) 2 .
  • the optical device D1 is illuminated by the driving of the leakage current i dn .
  • the timing of each signal source in the pixel circuit is the same as the timing of driving the first light emitting device to emit light, except that the output voltage V SD of the first reference voltage source 11 is from the low level voltage V. Ss is switched to a high level voltage V DD , and the output voltage V DS of the second reference voltage source 12 is switched from a high level voltage V DD to a level voltage V ss .
  • Stage d Reset phase.
  • the first gate signal source 14 in FIG. 6 outputs a voltage VScan1 at a high level, and the first switching transistor T1 connected to the first gate signal source 14 is turned off;
  • the second gate signal source 41 and the third The gate signal source 15 outputs a voltage V Scan2 at a low level, and the second switching transistor T2, the third switching transistor ⁇ 3, and the fourth switching transistor ⁇ 4 respectively connected to the second gate signal source 41 and the third gate signal source 15 are turned on;
  • the voltage V EM outputted by the control signal source 16 is at a low level, and the fifth switching transistor T5 connected to the charging control signal source 16 is turned on;
  • the ⁇ -type driving transistor ⁇ is turned off, and the branch of the ⁇ -type driving transistor ⁇ is broken.
  • the third reference voltage source 42 outputs a reference reset voltage ⁇ !
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit configuration shown in Fig. 12.
  • the branch of the ⁇ -type driving transistor ⁇ , the first capacitor C1, the third reference voltage source 42, the first reference voltage source 11, and the second reference voltage source 12 are turned on.
  • the reference reset voltage V leg outputted by the third reference voltage source 42 and the high level voltage V DD outputted by the first reference voltage source are applied to both ends of the second capacitor C2, and the voltage V C of the second capacitor C is V INI .
  • the connection mode of the P-type driving transistor Tp is a diode connection mode.
  • the gate of the P-type driving transistor Tp is discharged to ⁇ ⁇ 2 , and ⁇ ⁇ 2 is the threshold voltage of the P-type driving transistor Tp. At this time, the voltage across the first capacitor C1 is
  • Stage e Write phase.
  • the first gate signal source 14 in FIG. 6 outputs a voltage VScan1 at a low level, and the first switching transistor T1 connected to the first gate signal source 14 is turned on;
  • the second gate signal source 41 and the third gate signal source 15 output voltage V Scan2 are at a high level, and the second switching transistor T2 and the third switching transistor ⁇ 3 are respectively connected to the second gate signal source 41 and the third gate signal source 15.
  • the fourth switching transistor ⁇ 4 is turned off;
  • the voltage V EM outputted by the charging control signal source 16 is at a high level, and the fifth switching transistor T5 connected to the charging control signal source 16 is turned off;
  • the output of the first reference voltage source 11 is a high level voltage V DD
  • the output of the second reference voltage source 12 is a low level voltage V ss .
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit configuration shown in Fig. 13.
  • Stage f Illumination stage.
  • the output voltage V Scan1 of the first gate signal source 14 shown in FIG. 6 is at a high level, and the first switching transistor T1 connected to the first gate signal source 14 is turned off;
  • the second gate signal source 41 outputs a voltage V Scan2 at a high level, and the second switching transistor T2 connected to the second gate signal source 41 is turned off;
  • the third gate signal source 15 outputs the voltage V Scan2 to a high level, and the third switching transistor T3 and the fourth switching transistor T4 connected to the third gate signal source 15 are turned off, since the fourth switching transistor T4 is turned off, at this time, the P type
  • the driving transistor Tp is a connection mode of a triode.
  • the voltage V EM outputted by the charging control signal source 16 is at a low level, and the fourth switching transistor T4 connected to the charging control signal source 16 is turned on;
  • the output voltage V SD of the first reference voltage source 11 is a high level voltage V DD
  • the output voltage V DS of the second reference voltage source 12 is a low level voltage V ss .
  • the branch of the first capacitor C1, the second capacitor C2, the P-type driving transistor Tp, the first reference voltage source 11, the second reference voltage source 12, and the second light-emitting device D2 is turned on.
  • the pixel circuit shown in Fig. 6 is equivalent to the circuit configuration shown in Fig. 14.
  • the second light emitting device D2 emits light under the driving of the drain current i dp .
  • the leakage current i dp flowing through the P-type driving transistor Tp is only provided with the data signal source 13
  • the voltage signal is related to the threshold voltage ⁇ ⁇ 2 of the P-type driving transistor Tp. That is, the pixel circuit has a function of compensating ⁇ ⁇ 2 .
  • the leakage current i dp drives the second light-emitting device D2 to emit light, and the current flowing through D2 is different from the current caused by the unevenness of the threshold voltage ⁇ ⁇ 2 of the p-type driving transistor Tp due to the manufacturing process of the backplane.
  • a display panel is further provided.
  • the display panel includes: a plurality of gate lines distributed along a row direction, as shown in FIG. 15; Gl, G2Gn;
  • Each pixel unit includes a pixel circuit 20 according to an embodiment of the present invention and a first light emitting device D1 and a second light emitting device D2 connected to the pixel circuit 20;
  • the pixel circuits 20 located in the same row are connected to the same gate line, and the pixel circuits 20 in the same column are connected to the same data line;
  • a plurality of pixel circuits are coupled to the same first reference voltage source (not shown in Figure 15) and a second reference voltage source.
  • a drain of the first switching transistor in the charging sub-circuit is connected to the data signal source through a data line, and a gate is connected to the first gate signal source through the gate line; the gate signal source and the data signal The source charges the first capacitor through the gate line and the data line, respectively.
  • a display device comprising the above display panel.
  • the display device may be a display device such as an organic electroluminescence display OLED panel, an OLED display, an OLED television, or an electronic paper.
  • the first reference voltage source and the second reference voltage source, the first gate signal source, the data signal source, and the charging control signal source of the embodiment of the present invention are alternating current signals, which vary according to changes in timing.
  • the present invention provides a first light emitting device and a second light emitting device in each pixel region, the operating currents of the first light emitting device and the second light emitting device are opposite in direction, and are respectively driven by an N-type driving transistor and a P-type driving.
  • the transistor drives the illumination.
  • the first light-emitting device and the second light-emitting device alternately emit light, and the life of the light-emitting device is at least doubled.

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Abstract

一种像素电路、显示面板及显示装置，用以提高显示装置中发光器件的寿命。所述像素电路包括：充电子电路（1）、第一驱动子电路（2）和第二驱动子电路（3），第一电容（C1）和第二电容（C2）；所述第一电容（C1）的第一端（A）与第一驱动子电路（2）和第二驱动子电路（3）的第一端相连，所述第一电容（C1）的第二端（B）与所述充电子电路（1）和第二电容（C2）的第一端（C）相连；所述第一驱动子电路（2）的第二端与第一发光器件（D1）相连，所述第二驱动子电路（3）的第二端与第二发光器件（D2）相连，其中，第一驱动子电路（2）流入第一发光器件（D1）的驱动电流和第二驱动子电路（3）流入第二发光器件（D2）的驱动电流方向相反。

Description

像素电路、 显示面板及显示装置
技术领域
本发明涉及有机发光显示技术领域， 尤其涉及一种像素电路、 显示面板及 显示装置。 背景技术
有机发光显示器件因其具有低功耗、 高亮度、 低成本、 广视角， 以及响应 速度快等优点备受关注， 在有机发光技术领域已经得到广泛应用。
有机电致发光二极管 （Organic Light Emitting Diode, OLED )是目前有机 发光领域应用较多的一种发光器件。 目前， OLED按照驱动方式可以分为无源 驱动和有源驱动两大类， 即直接寻址和薄膜晶体管（ Thin Film Transistor, TFT ) 矩阵寻址两类。 其中， 有源驱动 OLED也称为有源矩阵 OLED ( AMOLED ), 每一个子像素单元中的发光器件通过像素电路和加载直流电源电压信号 （VDD 或 Vss ) 的电源线对其进行驱动发光。
参见图 1 , 为现有驱动发光器件发光的像素电路结构示意图， 以 n型驱动 晶体管为例， 像素电路包括： 驱动晶体管 Tl、 电容 Cl、 开关晶体管 T2;
电容 C1的第一端与驱动晶体管 T1的栅极相连，第二端与低电平参考电压 源 Vss相连； 开关晶体管 T2的漏极与驱动晶体管 T1的栅极相连， 栅极与门信 号源 VScan相连， 源极与数据信号源 VData相连； 驱动晶体管 T1的源极与高电 平参考电压源 VDD相连， 漏极与发光器件 D1的正极相连， 发光器件 D1的负 极与低电平参考电压源 Vss相连。
在一帧图像显示阶段， 驱动发光器件 D1发光之前， 门信号源输出电压信 号 VScan使开关晶体管 T2开启， 数据信号源与电容 C1所在支路导通， 数据信 号源输出数据信号 VData加载到电容 C1的第二端， 为电容 C1充电； 驱动发光 器件 D1发光阶段， 电容 C1放电， 驱动发光器件 D1发光。
图 1所示的像素电路， 仅能驱动一个发光器件发光， 每一发光器件对应一 个像素单元的发光区域， 在每帧图像扫描时， 信号均要写入该像素电路， 每帧 图像扫描时， 像素单元对应的发光区域均要发光显示。 AMOLED显示器驱动 OLED发光属于直流驱动，长时间直流驱动电压对应的电场造成 OLED内部离 子极性化， 使得 OLED形成内建电场， 从而使 OLED阈值电压增大， 大大降 低了 OLED的发光效率， 缩短了 OLED寿命。 寿命是制约有机发光显示装置， 尤其是大尺寸， 高亮度的有机发光显示装置广泛应用的重要因素。 发明内容
本发明实施例提供的一种像素电路、 显示面板及显示装置， 用以提高显示 装置中发光器件的寿命。
本发明实施例提供的一种像素电路包括： 充电子电路、 第一驱动子电路和 第二驱动子电路， 第一电容和第二电容；
所述第一电容的第一端与第一驱动子电路和第二驱动子电路的第一端相 连， 所述第一电容的第二端与所述充电子电路和第二电容的第一端相连；
所述第一驱动子电路的第二端与第一发光器件相连， 所述第二驱动子电路 的第二端与第二发光器件相连， 其中， 第一驱动子电路流入第一发光器件的驱 动电流和第二驱动子电路流入第二发光器件的驱动电流方向相反；
所述充电子电路用于为所述第一电容充电， 所述第二电容用于维持所述第 一电容第二端的电压； 所述第一电容放电时使得第一驱动子电路驱动第一发光 器件发光， 或使得第二驱动子电路驱动第二发光器件发光。
示例性地， 所述第一驱动子电路包括 N型驱动晶体管， 所述第二驱动子电 路包括 P型驱动晶体管；
其中，所述 N型驱动晶体管的栅极与所述第一电容的第一端相连， 源极与 可提供交流信号的第一参考电压源相连， 漏极与第一发光器件的负极相连， 第 一发光器件的正极与可提供交流信号的第二参考电压源相连； 所述第二电容的 第二端与所述第一参考电压源相连；
所述 P型驱动晶体管的栅极与所述第一电容的第一端相连； 源极与所述第 一参考电压源相连， 漏极与第二发光器件的正极相连， 第二发光器件的负极与 所述第二参考电压源相连。
示例性地， 所述充电子电路包括：
数据信号源、 第一门信号源， 以及与数据信号源和第一门信号源相连的第 一开关晶体管；
第一开关晶体管的漏极与数据信号源相连， 源极与第一电容的第二端相 连， 栅极与第一门信号源相连； 所述第一门信号源用于控制所述第一开关晶体管开启，使得所述数据信号 源与所述第一电容所在支路导通， 数据信号源向所述第一电容充电。
示例性地， 还包括复位子电路， 复位子电路包括： 第二门信号源、 第二开 管晶体管和待复位到参考复位电压的第三参考电压源； 第二开关晶体管的源极 与第一电容的第二端相连， 漏极与待复位到参考复位电压的第三参考电压源相 连， 栅极与第二门信号源相连。
所述复位子电路用于在充电子电路为第一电容充电之前， 将第一电容中存 储的信号复位至参考复位电压。
示例性地， 还包括与所述第一驱动子电路相连的第一补偿子电路， 和与所 述第二驱动子电路相连的第二补偿子电路；
所述第一补偿子电路包括第三开关晶体管；
所述第二补偿子电路包括第四开关晶体管；
其中， 所述第三开关晶体管的源极与所述 N型驱动晶体管的栅极相连， 漏 极与 N型驱动晶体管的漏极相连， 栅极与第三门信号源相连；
所述第四开关晶体管的源极与 P型驱动晶体管的栅极相连，漏极与 P型驱 动晶体管的漏极相连， 栅极与所述第三门信号源相连。
示例性地，还包括控制所述第一发光器件和第二发光器件与第二参考电压 源之间的导通的第五开关晶体管， 所述第五开关晶体管的栅极与充电控制信号 源相连， 源极与所述第一发光器件的正极以及第二发光器件的负极相连， 漏极 与所述第二参考电压源相连， 所述充电控制信号源用于控制所述第五开关晶体 管的开启与关闭。
示例性地， 所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第 四开关晶体管和第五开关晶体管为 N型晶体管， 或者
所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第四开关晶体 管和第五开关晶体管为 P型晶体管；
所述第二门信号源和第三门信号源为同一门信号源。
按照本发明实施例， 提供一种显示面板， 包括由栅线和数据线围设而成的 多个呈矩阵排列的像素单元，每一像素单元中包括一个像素电路和与该像素电 路相连的发光器件；
其中， 所述像素电路为上述像素电路；
位于同一行的像素电路中的充电子电路与同一条栅线相连，位于同一列的 像素电路中的充电子电路与同一条数据线相连； 在一帧图像显示阶段， 所述第 一驱动子电路和第二驱动子电路先后分别驱动第一发光器件发光和第二发光 器件发光之前， 所述充电子电路通过数据线和栅线为所述第一电容充电。
示例性地， 所述像素电路为上述像素电路；
所述第一开关晶体管的漏极通过数据线与所述数据信号源相连，栅极通过 所述栅线与所述第一门信号源相连；
所述门信号源和数据信号源分别通过栅线和数据线为所述第一电容充电。 按照本发明实施例，提供一种显示装置， 包括上述显示面板。
本发明通过在每一个像素区域设置两个相并联的第一发光器件和第二发 光器件， 第一发光器件和第二发光器件的工作电流方向相反，且分别通过 N型 驱动晶体管和 p型驱动晶体管驱动发光。第一发光器件和第二发光器件交替轮 流发光， 可以提高每一发光器件的寿命。 附图说明
图 1为现有像素电路结构示意图；
图 2为本发明实施例的像素电路结构示意图之一；
图 3为本发明实施例的像素电路结构示意图之二；
图 4为本发明实施例的像素电路结构示意图之三；
图 5为本发明实施例的像素电路结构示意图之四；
图 6为本发明实施例的像素电路结构示意图之五；
图 7为本发明实施例的像素电路结构示意图之六；
图 8为图 6所示的像素电路工作的时序图；
图 9为本发明实施例的与第一驱动子电路对应的具有复位功能的像素电路 结构示意图；
图 10为本发明实施例的与第一驱动子电路对应的具有充电功能的像素电 路结构示意图；
图 11 为本发明实施例的与第一驱动子电路对应的具有驱动发光器件发光 功能的像素电路结构示意图；
图 12为本发明实施例的与第二驱动子电路对应的具有复位功能的像素电 路结构示意图；
图 13为本发明实施例的与第二驱动子电路对应的具有充电功能的像素电 路结构示意图；
图 14为本发明实施例的与第二驱动子电路对应的具有驱动发光器件发光 功能的像素电路结构示意图；
图 15为本发明实施例的有机发光显示面板结构示意图。 具体实施方式
在本发明实施例中提供一种像素电路、 显示面板及显示装置， 用以提高显 示装置中发光器件的寿命， 以及改善发光器件发光显示不均匀的问题。
需要说明的是，对于显示领域的晶体管来说，漏极和源极没有明确的区别， 因此本发明实施例中所提到的晶体管的源极可以为晶体管的漏极， 晶体管的漏 极也可以为晶体管的源极。
在 AMOLED显示面板中， 包括由栅线和数据线围设而成的多个呈矩阵分 布的像素单元， 每一个像素单元包括一个像素电路。 本发明实施例通过在每一 个像素单元设置两个并联连接的第一驱动子电路和第二驱动子电路， 第一驱动 和第二发光器件轮流发光。 例如， 在一帧图像显示时间 t内， 前（1/2 ) t时间 内第一驱动子电路驱动第一发光器件发光， 后 （1/2 ) t时间内第二驱动子电路 驱动第二发光器件发光。 相比较在一个像素单元设置一个发光器件的像素电 路， 按照本发明实施例的发光器件的寿命至少提高一倍。 号的写入阶段和发光阶段。在第一驱动子电路和第二驱动子电路分别驱动第一 发光器件和第二发光器件发光之前， 充电子电路用于为驱动子电路中的电容充 电， 电容充电后在发光阶段放电， 驱动第一驱动子电路或第二驱动子电路中的 发光器件发光。
以下将结合附图具体说明按照本发明实施例的像素电路、显示面板及显示 装置。
参见图 2, 本发明实施例的像素电路， 包括：
充电子电路 1、 第一电容 Cl、 第二电容 C2、 第一驱动子电路 2和第二驱 动子电路 3;
第一电容 C1的第一端与第一驱动子电路 2和第二驱动子电路 3的第一端 相连， 第一电容 C1的第二端与充电子电路 1和第二电容 C2的第一端相连； 第一驱动子电路 2的第二端与第一发光器件 D1相连， 第二驱动子电路 3 的第二端与第二发光器件 D2相连， 其中， 第一驱动子电路 2流入第一发光器 件 D1的驱动电流和第二驱动子电路 3流入第二发光器件 D2的驱动电流方向 相反； 图 2中带箭头的线段表示驱动电流的方向。
充电子电路 1用于为第一电容 C1充电， 第二电容 C2用于维持第一电容 C1第二端的电压；第一电容 C1放电时使得第一驱动子电路 2驱动第一发光器 件 D1发光， 或使得第二驱动子电路 3驱动第二发光器件 D2发光。
示例性地， 本发明实施例中采用的发光器件（如所述第一发光器件和第二 发光器件）可以为 OLED或其他有机电致发光元件等， 本发明不作具体限定。
需要说明的是，如图 2所示的第一驱动子电路和第二驱动子电路共用第一 电容 Cl。 本发明实施例的第一驱动子电路和第二驱动子电路也可以分别连接 一个电容， 两个电容并联连接。
以下通过举例更具体地说明图 2提供的像素电路。
参见图 3, 本发明实施例的像素电路， 包括：
充电子电路 1、 第一电容 Cl、 第二电容 C2, 第一驱动子电路 2和第二驱 动子电路 3; 第一驱动子电路 2与第一发光器件 D1相连； 第二驱动子电路 3 与第二发光器件 D2相连；
第一驱动子电路 2包括： n型驱动晶体管 Tn;
其中， Ν型驱动晶体管 Tn的栅极与第一电容 C1的第一端 （A端）相连， 源极与可提供交流电压信号的第一参考电压源 11 的输出端相连； 漏极与第一 发光器件 D1的负极相连； 第一电容 C1的第二端（B端）与第二电容 C2的第 一端（C端）相连， 第二电容 C2的第二端（D端）与第一参考电压源 11的输 出端相连 (即第一电容 C1和第二电容 C2串联连接)； 第一发光器件 D1的正极 与可提供交流电压信号的第二参考电压源 12的输出端相连；
第二驱动子电路 3包括： P型驱动晶体管 Tp;
Ρ型驱动晶体管 Τρ的栅极与第一电容 C1的第一端（Α端）相连， 源极与 第一参考电压源 11的输出端相连； 漏极与第二发光器件 D2的正极相连； 第一 电容 C1的第二端 （Β端）与第二电容 C2的第一端 （C端）相连， 第二电容 C2的第二端 （D端）与第一参考电压源 11的输出端相连； 第二发光器件 D2 的负极与第二参考电压源 12的输出端相连；
充电子电路 1与第一电容 C1的第二端 （Β端）相连； 充电子电路 1用于在驱动第一发光器件 D1或第二发光器件 D2发光之前 向第一电容 C1输入数据信号， 第二电容 C2用于维持第一电容 C1第二端 （B 端） 的电位。
第一驱动子电路 2和第二驱动子电路 3用于在时序信号的控制下分别驱动 第一发光器件 D1和第二发光器件 D2发光。
按照本发明实施例的像素电路， 第一发光器件和第二发光器件交替发光， 各自的寿命至少提高一倍。
此外， 按照本发明实施例的像素电路， 第一驱动子电路和第二驱动子电路 共用第一电容和第二电容， 且共用第一参考电压源和第二参考电压源； 由于第 一驱动子电路和第二驱动子电路在不同时间段工作， 第一电容、 第二电容、 第 一参考电压源和第二参考电压源分时间工作， 可以筒化电路的结构。
在具体实施时，按照本发明实施例的像素电路只需要切换第一参考电压源 和第二参考电压源输出电压的高低电平状态， 即可实现第一驱动子电路和第二 驱动子电路交替工作。 具体地， 当第一参考电压源和第二参考电压源分别输出 高电平和低电平电压时， 第二驱动子电路驱动第二发光器件发光； 当第一参考 电压源和第二参考电压源分别输出低电平和高电平电压时， 第一驱动子电路驱 动第一发光器件发光。
需要说明的是， 按照本发明实施例的像素电路， 与第一驱动子电路相连的 发光器件不限于为一个， 与第二驱动子电路相连的发光器件也不限于为一个。 第一驱动子电路和第二驱动子电路分别可以与多个相互串联的发光器件相连， 这里不作具体限定。
设第一参考电压源输出的电压 VSD的高电平电压为 VDD, 低电平电压为 Vss,第二参考电压源输出的参考电压 VDS的高电平电压为 VDD,低电平电压为 Vsso VDD为大于零的正值， Vss的值可以为零或者为小于零的负值。
以下将举例说明图 3所示的像素电路结构。
参见图 4, 图 3所示的充电子电路 1可包括：
数据信号源 13、 第一门信号源 14, 以及与数据信号源 13和第一门信号源 14相连的第一开关晶体管 T1;
具体地， 第一开关晶体管 T1的漏极与数据信号源 13的输出端相连， 源极 与第一电容 C1的第二端（B端）相连，栅极与第一门信号源 14的输出端相连； 第一门信号源 14用于在时序信号的控制下控制第一开关晶体管 T1的开启与关 闭， 数据信号源 13用于在第一开关晶体管 T1开启时向第一电容 C1写入数据 信号。
需要说明的是， 第一开关晶体管 T1起开关作用， 其可以为 N型晶体管或 P型晶体管。 图 4中所示的第一开关晶体管 T1为 P型晶体管。
参见图 5, 为了保证上一帧信号对下一帧信号的影响程度最小， 按照本发 明实施例的像素电路还包括复位子电路 4, 用于在充电子电路 1充电之前将第 一电容 C1第二端 （B端） 的电压复位至参考复位电压 VINI。
复位子电路 4包括：
第二门信号源 41、 第二开管晶体管 T2和提供参考复位电压 VJM的第三参 考电压源 42;
第二开关晶体管 T2的源极与第一电容 C1的第二端 B相连， 漏极与提供 参考复位电压的第三参考电压源 42相连，栅极与第二门信号源 41的输出端相 连；
所述第三参考电压源 42输出的电压可以为具有一定值的恒定电压， 输出 的电压为 也可以为接地电压 GND。
本发明实施例为了实现所述驱动电流与 N型驱动晶体管 Tn 的阈值电压 νω或 Ρ型驱动晶体管 Τρ的阈值电压 νώ2无关， 避免不同驱动晶体管阈值电 压差异导致的各像素发光不均匀的问题， 该像素电路还包括解决上述问题的补 偿子电路。
参见图 6, 按照本发明实施例的像素电路还包括： 与第一驱动子电路 2相 连的第一补偿子电路 5, 以及与第二驱动子电路 3相连的第二补偿子电路 6; 第一补偿子电路 5包括第三开关晶体管 T3; 第三开关晶体管 T3的源极与 N型驱动晶体管 Tn的栅极相连， 漏极与 n型驱动晶体管 Tn的漏极相连，栅极 与第三门信号源 15的输出端相连；
第二补偿子电路 6包括第四开关晶体管 T4; 第四开关晶体管 T4的源极与 P型驱动晶体管 Tp的栅极相连， 漏极与 Ρ型驱动晶体管 Τρ的漏极相连， 栅极 与第三门信号源 15的输出端相连。
示例性地， 按照本发明实施例的第一发光器件和第二发光器件可以为 OLED或其他有机电致发光元件等， 本发明对此不作具体限定。
参见图 7,为了避免在写入阶段像素电路第二参考电压源 12对充电子电路 1的影响， 像素电路还包括： 第五开关晶体管 Τ5; 第五开关晶体管 T5的栅极与充电控制信号源 16的输出端相连，源极同时 与第一发光器件 D1的正极以及第二发光器件 D2的负极相连， 漏极与第二参 考电压源 12的输出端相连。 充电控制信号源 16在时序的控制下控制第五开关 晶体管 T5开启或关闭。
示例性地， 所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第 四开关晶体管和第五开关晶体管的类型可以完全相同或者部分相同。 例如， 所 述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第四开关晶体管和第 五开关晶体管均为 N型晶体管或者均为 N型晶体管。
当第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第四开关晶体管 和第五开关晶体管的类型相同时， 所述第二门信号源和第三门信号源为同一门 信号源 （即共用门信号源）， 这样可以达到筒化电路结构的目的。
在具体实施过程中， 第一门信号源、 第二门信号源、 第三门信号源通过栅 线与相应的开关晶体管相连。 数据信号源通过数据线与第一开关晶体管相连。
如图 7所示， 第一门信号源通过栅线 G_n与第一开关晶体管 T1相连， 第 一门信号源为第一开关晶体管 T1提供栅极电压 (图 7中未体现第一门信号源)； 第二门信号源通过栅线 G_(n-1)与第二开关晶体管 T2相连，第三门信号源 通过栅线0_(11-1)分别与第三开关晶体管 T3和第四开关晶体管 T4相连 (图 7中 未体现第二门信号源和第三门信号源 )。
以下将举例说明本发明实施例的像素电路的工作原理：
在一帧图像显示的前 1/2时间内控制所述第一驱动子电路驱动第一发光器 件发光；
在后 1/2时间内控制像素电路的第二驱动子电路驱动第二发光器件发光。 所述控制第一驱动子电路驱动第一发光器件发光的过程 , 具体包括： 复位阶段， 所述第二门信号源控制第二开关晶体管开启， 第三门信号源控 制第三开关晶体管和第四开关晶体管开启； 充电控制信号源控制第五开关晶体 管开启；第一门信号源控制第一开关晶体管关闭；第一参考电压源输出低电平、 第二参考电压源输出高电平，使得 N型驱动晶体管、第一电容和第二电容所在 支路导通， 第三参考电压源输出的电压 VJM加载到第一电容的第二端， 第二电 容的第二端复位至 VINI。
写入阶段， 第一门信号源控制第一开关晶体管开启， 所述第二门信号源控 制第二开关晶体管关闭， 第三门信号源控制第三开关晶体管和第四开关晶体管 关闭；充电控制信号源控制第五开关晶体管关闭；第一参考电压源输出低电平、 第二参考电压源输出高电平， 使得 N型驱动晶体管、 第一电容、 第二电容和数 据信号源所在支路导通， 数据信号源输出的电压加载到第一电容的第二端， 第 一电容存储数据信号。
发光阶段， 第一门信号源控制第一开关晶体管关闭， 所述第二门信号源控 制第二开关晶体管关闭， 第三门信号源控制第三开关晶体管和第四开关晶体管 关闭；充电控制信号源控制第五开关晶体管开启；第一参考电压源输出低电平、 第二参考电压源输出高电平， 使得 N型驱动晶体管、 第一电容、 第二电容和第 一发光器件所造支路导通， 第一电容放电， 第一驱动子电路驱动第一发光器件 发光。
所述控制第二驱动子电路驱动第二发光器件发光的过程 , 具体包括： 复位阶段， 所述第二门信号源控制第二开关晶体管开启， 第三门信号源控 制第三开关晶体管和第四开关晶体管开启； 充电控制信号源控制第五开关晶体 管开启；第一门信号源控制第一开关晶体管关闭；第一参考电压源输出高电平、 第二参考电压源输出低电平，使得 N型驱动晶体管、第一电容和第二电容所在 支路导通， 第三参考电压源输出的电压 VJM加载到第一电容的第二端， 第二电 容的第二端复位至 VINI。
写入阶段， 第一门信号源控制第一开关晶体管开启， 所述第二门信号源控 制第二开关晶体管关闭， 第三门信号源控制第三开关晶体管和第四开关晶体管 关闭；充电控制信号源控制第五开关晶体管关闭；第一参考电压源输出高电平、 第二参考电压源输出低电平， 使得 N型驱动晶体管、 第一电容、 第二电容和数 据信号源所在支路导通， 数据信号源输出的电压加载到第一电容的第二端， 第 一电容存储数据信号。
发光阶段， 第一门信号源控制第一开关晶体管关闭， 所述第二门信号源控 制第二开关晶体管关闭， 第三门信号源控制第三开关晶体管和第四开关晶体管 关闭；充电控制信号源控制第五开关晶体管开启；第一参考电压源输出高电平、 第二参考电压源输出低电平， 使得 N型驱动晶体管、 第一电容、 第二电容和第 一发光器件所造支路导通， 第一电容放电， 第一驱动子电路驱动第一发光器件 发光。
以下将结合图 6所示的像素电路和图 8所示的像素电路工作过程的时序 图， 具体说明本发明实施例提供的像素电路工作原理。 设第一门信号源 14输出电压信号为 VScanl, 设第二门信号源 41输出电压 信号为 VScan2, 第三门信号源 15输出电压信号为 VScan3;
第二门信号源 41和第三门信号源 15对应的时序图相同； 示例性地， 第二 门信号源 41和第三门信号源 15为同一门信号源； 设充电控制信号源 16输出 电压信号为 VEM。 设 VDD为高于 GND的正值， Vss为低于 GND的负值。
以第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3、 第四开 关晶体管 Τ4和第五开关晶体管 Τ5为 Ρ型晶体管为例说明。
Ν型晶体管在栅极输入高电平电压时开启， 输入低电平电压时关闭； Ρ型 晶体管在栅极输入低电平电压时开启， 输入高电平电压时关闭。
图 6中， 驱动第一发光器件 D1发光对应图 8中的复位阶段（ a阶段）、 写 入阶段（ b阶段 ), 以及发光阶段（ c阶段 ); 驱动第二发光器件 D2发光对应图 8中的复位阶段 ( d阶段）、 写入阶段 ( e阶段）， 以及发光阶段 ( f阶段）。
a阶段： 复位阶段。
如图 8所示， 图 6中的第一门信号源 14输出电压 VScanl为高电平， 与第一 门信号源 14相连的第一开关晶体管 T1关闭；
第二门信号源 41和第三门信号源 15输出电压 VScan2和 VScan3为低电平， 分别与第二门信号源 41和第三门信号源 15相连的第二开关晶体管 T2、 第三 开关晶体管 Τ3和第四开关晶体管 Τ4开启； 第三开关晶体管 Τ3开启， 与第三 开关晶体管 Τ3相连的 Ν型驱动晶体管 Τη的源极和漏极接通， 此时， Ν型驱 动晶体管 Τη等效为二极管的连接方式。
充电控制信号源 16输出的电压 VEM为低电平，与充电控制信号源 16相连 的第五开关晶体管 T5开启；
第一参考电压源 11输出低电平电压 Vss, 第二参考电压源 12输出高电平 电压 VDD。 P型驱动晶体管 Tp截止， Ρ型驱动晶体管所在支路断路。 Ν型驱动 晶体管 Τη导通， Ν型驱动晶体管 Τη所在支路导通。
第三参考电压源 42输出参考复位电压 V腿。
此时， 图 6所示的像素电路等效为图 9所示的电路结构。
Ν型驱动晶体管 Τη、 第一电容 Cl、 第三参考电压源 42、 第一参考电压源 11和第二参考电压源 12所在支路导通。
第三参考电压源 42输出的参考复位电压 VJM加载到第一电容 C1的第二端 ( B端）和第二电容 C2的第一端 （ C端），VB=VC=V腿。 N型驱动晶体管 Tn的栅极被放电至 νω, 栅极电压 Vg= νω, νω为 Ν型 驱动晶体管 Τη的阈值电压， Ν型驱动晶体管 Tn的栅极与第一电容 C1的第一 端 A端相连， 因此， 第一电容 C1的第一端 A端电压 VA等于 n型驱动晶体管 Tn的栅极电压， 即 VA= Vg。
此时， 第一电容 ci两端的电压为 vA-vB=vg- νΒ= νω-ν腿。
其中， VA为 Α点电压， VB为 B点电压， Vc为 C点电压。
b阶段： 写入阶段。
如图 8所示， 图 6中的第一门信号源 14输出电压 VScanl为低电平， 与第一 门信号源 14相连的第一开关晶体管 T1开启；
第二门信号源 41和第三门信号源 15输出电压 VScan2和 VScan3为高电平， 分别与第二门信号源 41和第三门信号源 15相连的第二开关晶体管 T2、 第三 开关晶体管 Τ3和第四开关晶体管 Τ4关闭；
充电控制信号源 16输出的电压 VEM为高电平，与充电控制信号源 16相连 的第五开关晶体管 T5关闭；
第一参考电压源 11输出低电平电压 Vss, 第二参考电压源 12的输出高电 平电压 VDD。 P型驱动晶体管 Tp截止， Ρ型驱动晶体管所在支路断路。 Ν型驱 动晶体管 Tn导通， N型驱动晶体管 Tn所在支路导通。
此时， 图 6所示的像素电路等效为图 10所示的电路结构。
第一电容 Cl、 第二电容 C2、 数据信号源 13、 N型驱动晶体管 Tn和第一 参考电压源 11所在支路导通；
数据信号源 13输出数据信号 VData, 数据信号 VData加载到第一电容 C1的 第二端（B端）， 根据电荷守恒原理， 第一电容 C1的第一端（ A端）也加载电 压 VData, 第一电容 C1的第一端 （A端） 的电压为存储电压 VtM-VjM与数据信 号 VData之和， 即 VA=VData+Vthl-V腿。
此时， 数据信号写入第一电容 C1中。
c阶段： 发光阶段。
如图 8所示， 图 6所示的第一门信号源 14输出电压 VScanl为高电平， 与第 一门信号源 14相连的第一开关晶体管 T1关闭；
第二门信号源 41输出电压 VScan2为高电平， 与第二门信号源 42相连的第 二开关晶体管 T2关闭；
第三门信号源 15输出电压 VScan3为高电平， 与第三门信号源 15相连的第 三开关晶体管 T3、 第四开关晶体管 Τ4关闭， Ν型驱动晶体管 Τη的连接方式 为三极管的连接方式。
充电控制信号源 16输出的电压 VEM为低电平，与充电控制信号源 16相连 的第五开关晶体管 T5开启；
第一参考电压源 11 的输出电压 VSD为低电平电压 Vss, 第二参考电压源 12的输出电压 VDS为高电平电压 VDD。 第一电容 Cl、 第二电容 C2、 N型驱动 晶体管、 第一参考电压源 11、 第二参考电压源 12和第一发光器件 D1所在支 路导通。
此时， 图 6所示的像素电路等效为图 11所示的电路结构。
如图 11 所示， 第一电容 C1 的第一端 （ A 端） 的电压为 VA=
VfVData+VtM-VjN 第一电容 C1 放电， II 型驱动晶体管 Til 的栅极电压 VfVData+VtM-VjN N型驱动晶体管 Til的源极连接至 VSS , 源极电压 VS=VSS。 因此， N 型驱动晶体管 Tn 的栅极和源极之间的电压 Vgs=Vg-Vs
- ss- oata+ thl-Vi I-Vss。
由于 N型驱动晶体管 Tn工作于饱和状态， 根据饱和状态电流特性可知 N 型驱动晶体管 Tn的漏电流满足如下公式： ί<!η=^(ν^ν )2，其中 ^为 Ν型驱动 晶体管 Tn 的漏电流， 为结构参数， 相同结构中此数值相对稳定， 将 Vgs=
VData+VtM-V腿 -VSS带入公式 -V腿 -VSS) 2。第一发
Figure imgf000015_0001
光器件 D1在漏电流 idn的驱动下发光显示。
由此可知， 流经 N型驱动晶体管 Tn的漏电流 ^仅与数据信号源 13提供 的电压信号有关与阈值电压 νω无关。 即该像素电路具有补偿阈值电压 νω的 功能。 该漏电流 idn驱动第一发光器件 D1发光， 流经 D1的电流不因背板制造 工艺原因而造成的 N型驱动晶体管 Tn的阈值电压 νω不均匀所导致的电流不 同。
以下将举例说明像素电路驱动第二发光器件发光的工作原理。
驱动第二发光器件发光时，像素电路中的各信号源的时序与驱动第一发光 器件发光的时序相同， 不同之处在于， 第一参考电压源 11 的输出电压 VSD由 低电平电压 Vss切换为高电平电压 VDD, 第二参考电压源 12的输出电压 VDS 由高电平电压 VDD切换为氏电平电压 Vss。
d阶段： 复位阶段。 如图 8所示， 图 6中的第一门信号源 14输出电压 VScanl为高电平， 与第一 门信号源 14相连的第一开关晶体管 T1关闭； 第二门信号源 41和第三门信号 源 15输出电压 VScan2为低电平， 分别与第二门信号源 41和第三门信号源 15 相连的第二开关晶体管 T2、 第三开关晶体管 Τ3和第四开关晶体管 Τ4开启； 充电控制信号源 16输出的电压 VEM为低电平，与充电控制信号源 16相连 的第五开关晶体管 T5开启；
第一参考电压源 11的输出高电平电压 VDD, 第二参考电压源 12的输出低 电平电压 Vss, P型驱动晶体管 Tp导通， Ρ型驱动晶体管所在支路导通。 Ν型 驱动晶体管 Τη截止， Ν型驱动晶体管 Τη所在支路断路。
第三参考电压源 42输出参考复位电压 ν!Μ。
此时， 图 6所示的像素电路等效为图 12所示的电路结构。
Ρ型驱动晶体管 Τρ、 第一电容 Cl、 第三参考电压源 42、 第一参考电压源 11和第二参考电压源 12所在支路导通。第三参考电压源 42输出的参考复位电 压 V腿和第一参考电压源输出的高电平电压 VDD加载到第二电容 C2的两端， 第二电容 C端的电压 VC=VINI。 第一电容 C1的第二端（B端）， 即第二电容 C2 的第一端 （C端）， 第一电容 C1的 B端电压
Figure imgf000016_0001
由于第四开关晶体管 T4开启， P型驱动晶体管 Tp的连接方式为二极管的 连接方式。 P型驱动晶体管 Tp的栅极被放电至 νώ2, νώ2为 P型驱动晶体管 Tp的阈值电压。 此时， 第一电容 C1两端的电压为
Figure imgf000016_0002
e阶段： 写入阶段。
如图 8所示， 图 6中的第一门信号源 14输出电压 VScanl为低电平， 与第一 门信号源 14相连的第一开关晶体管 T1开启；
第二门信号源 41和第三门信号源 15输出电压 VScan2为高电平， 分别与第 二门信号源 41和第三门信号源 15相连的第二开关晶体管 T2、 第三开关晶体 管 Τ3、 第四开关晶体管 Τ4关闭；
充电控制信号源 16输出的电压 VEM为高电平，与充电控制信号源 16相连 的第五开关晶体管 T5关闭；
第一参考电压源 11的输出高电平电压 VDD, 第二参考电压源 12的输出低 电平电压 Vss。
此时， 图 6所示的像素电路等效为图 13所示的电路结构。
第一电容 Cl、 第二电容 C2、 数据信号源 13、 P型驱动晶体管 Tp和第一 参考电压源 11所在支路导通；
数据信号源 13输出数据信号 VData, 数据信号 VData加载到第一电容 C1的 第二端（B端）， 根据电荷守恒原理， 第一电容 C1的第一端（ A端）的电压为 VA= VData+ νώ2 -VjMo 此时， 数据信号写入第一电容 CI中。
f阶段： 发光阶段。
如图 8所示， 图 6所示的第一门信号源 14输出电压 VScanl为高电平， 与第 一门信号源 14相连的第一开关晶体管 T1关闭；
第二门信号源 41输出电压 VScan2为高电平， 与第二门信号源 41相连的第 二开关晶体管 T2关闭；
第三门信号源 15输出电压 VScan2为高电平， 与第三门信号源 15相连的第 三开关晶体管 T3和第四开关晶体管 T4关闭， 由于第四开关晶体管 T4关闭， 此时， P型驱动晶体管 Tp为三极管的连接方式。
充电控制信号源 16输出的电压 VEM为低电平，与充电控制信号源 16相连 的第四开关晶体管 T4开启；
第一参考电压源 11 的输出电压 VSD为高电平电压 VDD, 第二参考电压源 12的输出电压 VDS为低电平电压 Vss。 第一电容 Cl、 第二电容 C2、 P型驱动 晶体管 Tp、 第一参考电压源 11、 第二参考电压源 12和第二发光器件 D2所在 支路导通。
此时， 图 6所示的像素电路等效为图 14所示的电路结构。
如图 14 所示， 第一电容 C1 的第一端 （Α 端） 的电压为 VA= VData+ Vth2+VDD-V腿，第一电容 CI放电， P型驱动晶体管 Tp的栅极电压 Vg= vData+ νώ2 -VJN P型驱动晶体管 Tp为三极管的连接方式， P型驱动晶体管 Tp的源极与 第一参考电压源 11相连，源极电压 VS=VDD。栅极和源极之间的电压 Vgs= Vg-Vs=
Voata+ th2 - iNI - VQD。
由于 P型驱动晶体管 Tp工作于饱和状态， 根据饱和状态电流特性可知 P 型驱动晶体管 Tp的漏电流满足如下公式： idf^^Vgs-v^2， 其中 idp为 P型驱动 晶体管 Tp的漏电流， 为结构参数,相同结构中此数值相对稳定，将 Vgs= VData+ νώ2 -V丽 - vDD带入公式 idp= (vgs-vth2)2得到 idp= (VData -V腿 -VDD)2。
第二发光器件 D2在漏电流 idp的驱动下发光显示。
由此可知， 流经 P型驱动晶体管 Tp的漏电流 idp仅与数据信号源 13提供 的电压信号有关， 与 P型驱动晶体管 Tp的阈值电压 νώ2无关。 即该像素电路 具有补偿 νώ2的功能。 该漏电流 idp驱动第二发光器件 D2发光， 流经 D2的电 流不因背板制造工艺原因而造成的 p型驱动晶体管 Tp的阈值电压 νώ2不均匀 所导致的电流不同。
按照本发明实施例， 还提供一种显示面板， 参见图 15, 该显示面板包括： 多条沿行方向分布的栅线， 如图 15中所示的 Gl、 G2 Gn;
多条沿列方向分布的数据线， 如图 15中所示的 Dl、 D2 Dm; 相邻的两条栅线和数据线围设成的多个像素单元；
每一像素单元包括一个按照本发明实施例的像素电路 20和与该像素电路 20相连的第一发光器件 D1和第二发光器件 D2;
位于同一行的像素电路 20与同一条栅线相连， 位于同一列的像素电路 20 与同一条数据线相连；
多个像素电路连接至同一个第一参考电压源（图 15 中未示出)和第二参考 电压源。所述充电子电路中的第一开关晶体管的漏极通过数据线与所述数据信 号源相连， 栅极通过所述栅线与所述第一门信号源相连； 所述门信号源和数据 信号源分别通过栅线和数据线为第一电容充电。
按照本发明实施例， 还提供一种显示装置， 包括上述显示面板。 该显示装 置可以为有机电致发光显示 OLED面板、 OLED显示器、 OLED电视或电子纸 等显示装置。
本发明实施例的第一参考电压源和第二参考电压源、 第一门信号源、 数据 信号源， 以及充电控制信号源为交流信号， 按照时序的变化而变化。
综上所述， 本发明通过在每一个像素区域设置第一发光器件和第二发光器 件， 第一发光器件和第二发光器件的工作电流方向相反，且分别通过 N型驱动 晶体管和 P型驱动晶体管驱动发光。第一发光器件和第二发光器件交替轮流发 光、 发光器件的寿命至少提高一倍。 明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要求及 其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、 一种像素电路， 包括： 充电子电路、 第一驱动子电路和第二驱动子电 路， 第一电容和第二电容；
所述第一电容的第一端与第一驱动子电路和第二驱动子电路的第一端相 连， 所述第一电容的第二端与所述充电子电路和第二电容的第一端相连； 所述第一驱动子电路的第二端与第一发光器件相连， 所述第二驱动子电路 的第二端与第二发光器件相连， 其中， 第一驱动子电路流入第一发光器件的驱 动电流和第二驱动子电路流入第二发光器件的驱动电流方向相反；
所述充电子电路用于为所述第一电容充电， 所述第二电容用于维持所述第 一电容第二端的电压； 所述第一电容放电时使得第一驱动子电路驱动第一发光 器件发光， 或使得第二驱动子电路驱动第二发光器件发光。
2、 根据权利要求 1所述的像素电路， 其中， 所述第一驱动子电路包括 N 型驱动晶体管， 所述第二驱动子电路包括 P型驱动晶体管；
其中，所述 N型驱动晶体管的栅极与所述第一电容的第一端相连， 源极与 可提供交流信号的第一参考电压源相连， 漏极与第一发光器件的负极相连， 第 一发光器件的正极与可提供交流信号的第二参考电压源相连； 所述第二电容的 第二端与所述第一参考电压源相连；
所述 P型驱动晶体管的栅极与所述第一电容的第一端相连； 源极与所述第 一参考电压源相连， 漏极与第二发光器件的正极相连， 第二发光器件的负极与 所述第二参考电压源相连。
3、 根据权利要求 2所述的像素电路， 其中， 所述充电子电路包括： 数据信号源、 第一门信号源， 以及与数据信号源和第一门信号源相连的第 一开关晶体管；
第一开关晶体管的漏极与数据信号源相连， 源极与第一电容的第二端相 连， 栅极与第一门信号源相连；
所述第一门信号源用于控制所述第一开关晶体管开启，使得所述数据信号 源与所述第一电容所在支路导通， 数据信号源向所述第一电容充电。
4、 根据权利要求 3所述的像素电路， 其中， 还包括复位子电路， 复位子 电路包括： 第二门信号源、 第二开管晶体管和待复位到参考复位电压的第三参 考电压源； 第二开关晶体管的源极与第一电容的第二端相连， 漏极与待复位到 参考复位电压的第三参考电压源相连， 栅极与第二门信号源相连；
所述复位子电路用于在充电子电路为第一电容充电之前， 将第一电容中存 储的信号复位至参考复位电压。
5、 根据权利要求 4所述的像素电路， 其中， 还包括与所述第一驱动子电 路相连的第一补偿子电路， 和与所述第二驱动子电路相连的第二补偿子电路； 所述第一补偿子电路包括第三开关晶体管；
所述第二补偿子电路包括第四开关晶体管；
其中， 所述第三开关晶体管的源极与所述 N型驱动晶体管的栅极相连， 漏 极与 N型驱动晶体管的漏极相连， 栅极与第三门信号源相连；
所述第四开关晶体管的源极与 P型驱动晶体管的栅极相连，漏极与 P型驱 动晶体管的漏极相连， 栅极与所述第三门信号源相连。
6、 根据权利要求 5所述的像素电路， 其中， 还包括控制所述第一发光器 件和第二发光器件与第二参考电压源之间的导通的第五开关晶体管， 所述第五 开关晶体管的栅极与充电控制信号源相连， 源极与所述第一发光器件的正极以 及第二发光器件的负极相连， 漏极与所述第二参考电压源相连， 所述充电控制 信号源用于控制所述第五开关晶体管的开启与关闭。
7、 根据权利要求 6所述的像素电路， 其中， 所述第一开关晶体管、 第二 开关晶体管、第三开关晶体管、第四开关晶体管和第五开关晶体管为 N型晶体 管， 或者
所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第四开关晶体 管和第五开关晶体管为 P型晶体管；
所述第二门信号源和第三门信号源为同一门信号源。
8、 一种显示面板， 包括由栅线和数据线围设而成的多个呈矩阵排列的像 素单元， 每一像素单元中包括一个像素电路和与该像素电路相连的发光器件； 其中， 所述像素电路为权利要求 1所述的像素电路；
位于同一行的像素电路中的充电子电路与同一条栅线相连，位于同一列的 像素电路中的充电子电路与同一条数据线相连； 在一帧图像显示阶段， 所述第 一驱动子电路和第二驱动子电路先后分别驱动第一发光器件发光和第二发光 器件发光之前， 所述充电子电路通过数据线和栅线为所述第一电容充电。
9、 根据权利要求 8所述的显示面板， 其中， 所述第一开关晶体管的漏极通过数据线与所述数据信号源相连，栅极通过 所述栅线与所述第一门信号源相连；
所述门信号源和数据信号源分别通过栅线和数据线为所述第一电容充电。
10、 根据权利要求 9所述的显示面板， 其中， 所述第一驱动子电路包括 N 型驱动晶体管， 所述第二驱动子电路包括 P型驱动晶体管；
其中， 所述 N型驱动晶体管的栅极与所述第一电容的第一端相连， 源极与 可提供交流信号的第一参考电压源相连， 漏极与第一发光器件的负极相连， 第 一发光器件的正极与可提供交流信号的第二参考电压源相连； 所述第二电容的 第二端与所述第一参考电压源相连；
所述 P型驱动晶体管的栅极与所述第一电容的第一端相连； 源极与所述第 一参考电压源相连， 漏极与第二发光器件的正极相连， 第二发光器件的负极与 所述第二参考电压源相连。
11、 根据权利要求 10所述的显示面板， 其中， 所述充电子电路包括： 数据信号源、 第一门信号源， 以及与数据信号源和第一门信号源相连的第 一开关晶体管；
第一开关晶体管的漏极与数据信号源相连， 源极与第一电容的第二端相 连， 栅极与第一门信号源相连；
所述第一门信号源用于控制所述第一开关晶体管开启，使得所述数据信号 源与所述第一电容所在支路导通， 数据信号源向所述第一电容充电。
12、 根据权利要求 11 所述的显示面板， 其中， 还包括复位子电路， 复位 子电路包括： 第二门信号源、 第二开管晶体管和待复位到参考复位电压的第三 参考电压源； 第二开关晶体管的源极与第一电容的第二端相连， 漏极与待复位 到参考复位电压的第三参考电压源相连， 栅极与第二门信号源相连；
所述复位子电路用于在充电子电路为第一电容充电之前， 将第一电容中存 储的信号复位至参考复位电压。
13、 根据权利要求 12所述的显示面板， 其中， 还包括与所述第一驱动子 电路相连的第一补偿子电路， 和与所述第二驱动子电路相连的第二补偿子电 路；
所述第一补偿子电路包括第三开关晶体管；
所述第二补偿子电路包括第四开关晶体管；
其中， 所述第三开关晶体管的源极与所述 N型驱动晶体管的栅极相连， 漏 极与 N型驱动晶体管的漏极相连， 栅极与第三门信号源相连；
所述第四开关晶体管的源极与 P型驱动晶体管的栅极相连，漏极与 P型驱 动晶体管的漏极相连， 栅极与所述第三门信号源相连。
14、 根据权利要求 13所述的显示面板， 其中， 还包括控制所述第一发光 器件和第二发光器件与第二参考电压源之间的导通的第五开关晶体管， 所述第 五开关晶体管的栅极与充电控制信号源相连， 源极与所述第一发光器件的正极 以及第二发光器件的负极相连， 漏极与所述第二参考电压源相连， 所述充电控 制信号源用于控制所述第五开关晶体管的开启与关闭。
15、 根据权利要求 14所述的显示面板， 其中， 所述第一开关晶体管、 第 二开关晶体管、第三开关晶体管、第四开关晶体管和第五开关晶体管为 N型晶 体管， 或者
所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管、 第四开关晶体 管和第五开关晶体管为 P型晶体管；
所述第二门信号源和第三门信号源为同一门信号源。
16、 一种显示装置， 其中， 包括权利要求 8或 9所述的显示面板。
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CN103000131A (zh) * 2012-12-05 2013-03-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
CN103383834A (zh) * 2013-07-02 2013-11-06 京东方科技集团股份有限公司 一种像素电路、显示面板及显示装置

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CN109658866A (zh) * 2019-03-04 2019-04-19 上海大学 一种高密度像素驱动电路及其驱动方法

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