WO2015062318A1 - 交流驱动的像素电路、驱动方法及显示装置 - Google Patents

交流驱动的像素电路、驱动方法及显示装置 Download PDF

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Publication number
WO2015062318A1
WO2015062318A1 PCT/CN2014/083194 CN2014083194W WO2015062318A1 WO 2015062318 A1 WO2015062318 A1 WO 2015062318A1 CN 2014083194 W CN2014083194 W CN 2014083194W WO 2015062318 A1 WO2015062318 A1 WO 2015062318A1
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Prior art keywords
terminal
voltage
voltage input
switching transistor
light
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PCT/CN2014/083194
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English (en)
French (fr)
Inventor
青海刚
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/429,464 priority Critical patent/US9881544B2/en
Publication of WO2015062318A1 publication Critical patent/WO2015062318A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the invention relates to an AC driven pixel circuit, a driving method and a display device. Background technique
  • the AMOLED Active Matrix Organic Light Emitting Diode
  • a driving TFT Thin Film Transistor
  • the threshold voltage of the different driving TFTs ie, the threshold voltage
  • OLED organic light-emitting diodes have aging problems, which is a common problem that all OLED light-emitting displays must face. Since most of the prior art uses direct current driving, the transport direction of holes and electrons is fixed, and they are injected from the positive and negative electrodes to the light-emitting layer, respectively, and excitons are formed in the light-emitting layer to emit light. The excess holes (or electrons) which are not involved in the recombination, or accumulate at the interface of the hole transport layer/light emitting layer (or the light emitting layer/electron transport layer), or flow into the electrode across the barrier.
  • an embodiment of the present invention provides an AC driven pixel circuit, a driving method, and a display device, which can effectively eliminate the rapid aging of the organic light emitting diode and eliminate the line.
  • an AC driven pixel circuit including: a first capacitor, a second capacitor, a first voltage input unit, a second voltage input unit, a data signal input unit, a first lighting unit, and a second Light unit.
  • the first lighting unit is configured to emit light under the control of the driving control end, the first voltage input end, and the second voltage input end; the second lighting unit is configured to be at the driving control end, the first voltage The input end and the second voltage input end emit light under control; wherein the first light emitting unit emits light in a preset first time period and the second light emitting unit emits light in a preset second time period.
  • the first voltage input unit is configured to provide a first input voltage of the first voltage terminal to the first light emitting unit and the second light emitting unit under control of the first scanning end;
  • the second voltage input unit is configured Providing a second input voltage of the second voltage terminal to the first light emitting unit and the second light emitting unit under the control of the second scanning end.
  • the data signal input unit is configured to input a data line signal of the data line to the drive control end under the control of the first scan end.
  • a first pole of the first capacitor is connected to the first voltage end, a second pole of the capacitor is connected to the first voltage input end, and a first pole of the second capacitor is connected to the first voltage input end
  • the second pole of the first capacitor is connected to the driving control end.
  • the first voltage input unit includes a first switching transistor, a gate of the first switching transistor is connected to the first scanning end, and a source of the first switching transistor is connected to the first voltage end The drain of the first switching transistor is connected to the first voltage input terminal.
  • the data signal input unit includes a second switching transistor, a gate of the second switching transistor is connected to the first scanning end, and a source of the second switching transistor is connected to the data line, A drain of the second switching transistor is coupled to the drive control terminal.
  • the second voltage input unit includes a third switching transistor, a gate of the third switching transistor is connected to the second scanning end, and a source of the third switching transistor is connected to the second voltage end The drain of the third switching transistor is connected to the second voltage input terminal.
  • the first light emitting unit includes: a first driving transistor and a first light emitting diode; a gate of the first driving transistor is connected to the driving control end, and a source of the first driving transistor is connected to the a first voltage input end; a first pole of the first light emitting diode is connected to the first drive The drain of the transistor, the second pole of the first LED is connected to the second voltage input.
  • the second light emitting unit includes: a second driving transistor and a second light emitting diode; a gate of the second driving transistor is connected to the driving control end, and a source of the second driving transistor is connected to the first voltage input a second pole of the second LED is connected to a drain of the second driving transistor, and a first pole of the second LED is connected to the second voltage input end.
  • the types of the first driving transistor and the second driving transistor are different.
  • the first lighting unit emits a preset high-level period illumination or a preset low-level period illumination between the first voltage end and the second voltage end, and the second illumination unit Illuminating in the period.
  • a display device comprising the pixel circuit of any of the above.
  • a driving method of a pixel circuit as described above including:
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a first reference voltage to the driving control end, and the second scanning end controls the second voltage input unit to be turned on,
  • the two voltage input terminals and the second voltage terminal are turned on, and the first capacitor and the second capacitor are charged to reset the voltage of the first voltage input terminal;
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a data voltage to the driving control terminal, and the second scanning end controls the second voltage input unit to be turned off, the second capacitor Combining the voltage at the first voltage input;
  • the first scanning end controls the first voltage input unit to be turned on, the control data signal input unit is turned off, the second scanning end controls the second voltage input unit to be turned on, the driving control terminal, the first voltage input terminal, and the second voltage input.
  • Driving the first light emitting unit to emit light
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a second reference voltage to the driving control end, and the second scanning end controls the second voltage input unit to be turned on,
  • the two voltage input terminals and the second voltage terminal are turned on, and the first capacitor and the second capacitor are charged to reset the voltage of the first voltage input terminal;
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a data voltage to the driving control terminal, and the second scanning end controls the second voltage input unit to be turned off, the second capacitor Combining the voltage at the first voltage input;
  • the first scanning end controls the first voltage input unit to be turned on, the control data signal input unit is turned off, the second scanning end controls the second voltage input unit to be turned on, the driving control end, the first voltage input end, and the second voltage input.
  • the terminal drives the second light emitting unit to emit light.
  • the first switching transistor and the second driving transistor are turned off, the second switching transistor, the third switching transistor, and the first driving transistor are turned on; in the second stage, the first switching transistor and the third switch The transistor is turned off, the second switching transistor is turned on, the first driving transistor and the second driving transistor are turned off; in the third stage, the first switching transistor, the third switching transistor, the first driving transistor are turned on, the second switching transistor and the second The driving transistor is turned off; in the fourth stage, the first switching transistor, the first driving transistor are turned off, the second switching transistor, the third switching transistor and the second driving transistor are turned on; in the fifth stage, the first switching transistor and the third switch The transistor is turned off, the second switching transistor is turned on, and the first driving transistor and the second driving transistor are turned off; in the sixth stage, the first switching transistor, the third switching transistor, and the second driving transistor are turned on, the second switching transistor, the first The drive transistor is turned off.
  • the AC-driven pixel circuit, the driving method and the display device provided by the embodiment of the invention provide a compensation capacitor and two light-emitting units respectively operating in different time periods in each pixel circuit to realize AC driving of the pixel circuit. While effectively avoiding the rapid aging of the organic light emitting diode, the influence of the internal resistance of the line on the luminous current and the influence of the threshold voltage of the driving transistor on the display unevenness of the panel are eliminated.
  • FIG. 1 is a schematic structural diagram of an AC-driven pixel circuit according to an embodiment of the present invention
  • FIG. 2 is another schematic structural diagram of an AC-driven pixel circuit according to an embodiment of the present invention
  • FIG. 4 is an equivalent circuit diagram of an AC-driven pixel circuit in a first stage according to an embodiment of the present invention
  • 5 is an equivalent circuit diagram of an AC-driven pixel circuit in a second stage according to an embodiment of the present invention
  • 6 is an equivalent circuit diagram of an AC-driven pixel circuit in a third stage according to an embodiment of the present invention
  • FIG. 7 is an equivalent circuit diagram of an AC-driven pixel circuit in a fourth stage according to an embodiment of the present invention.
  • FIG. 8 is an equivalent circuit diagram of an AC-driven pixel circuit in a fifth stage according to an embodiment of the present invention.
  • FIG. 9 is an equivalent circuit diagram of a sixth stage of an AC-driven pixel circuit according to an embodiment of the present invention. detailed description
  • the switching transistor and the driving transistor used in all the embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in the embodiments of the present invention include P-type transistors and N-type transistors.
  • the P-type transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level
  • the N-type transistor is turned on when the gate is at a high level, and is turned off when the gate is at a high level, and is also replaced by a turn-off in the technical field.
  • Corresponding functions may be indicated in the embodiments of the present application.
  • an AC-driven pixel circuit includes: a first capacitor C1, a second capacitor C2, a first voltage input unit 11, a second voltage input unit 12, and a data signal input unit 13.
  • the first lighting unit 14 is connected to the first voltage input terminal a, the second voltage input terminal 1), the driving control terminal g, and is configured to be at the driving control terminal g, the first voltage input terminal a, and the second voltage input terminal b. Under the control, it emits light in the Nth frame.
  • the second lighting unit 15 is connected to the first voltage input terminal a, the second voltage input terminal 1), the driving control terminal g, and is configured to be at the driving control terminal g, the first voltage input terminal a, and the second voltage input terminal b. Under control, the N+1th frame adjacent to the Nth frame emits light.
  • the first voltage input unit 11 is connected to the first voltage terminal POWER1 ( n ), the first voltage input terminal a and the first scan terminal G ( n ); and is configured to be under the control of the first scanning terminal G ( n )
  • a light emitting unit 14 and a second light emitting unit 15 provide a first input power of the first voltage terminal POWER1 ( n ) Pressure.
  • the second voltage input unit 12 is connected to the second voltage terminal POWER2 ( n ), the second voltage input terminal b and the second scan terminal EM (n); and is configured to be under the control of the second scanning terminal EM (n)
  • a light emitting unit 14 and a second light emitting unit 15 provide a second input voltage of the second voltage terminal POWER2 (n).
  • the data signal input unit 13 is connected to the data line DATA, the first scan terminal G(n), and the drive control terminal g, and is configured to input the data line DATA data to the drive control terminal g under the control of the first scan terminal G(n). Line signal.
  • the first pole of the first capacitor C1 is connected to the first voltage terminal POWER1 (n), and the second pole of the first capacitor C1 is connected to the first voltage input terminal a.
  • the first pole of the second capacitor C2 is connected to the first voltage input terminal a, and the second pole of the second capacitor C2 is connected to the drive control terminal g.
  • the first time period and the second time period may be two adjacent data frames, but are not limited thereto; the first time period and the second time period may be set as needed.
  • a data frame (referred to as a frame) is the time of "one display period", which is about several milliseconds to tens of milliseconds.
  • a compensation capacitor and two light-emitting units respectively operating in different time periods are implemented to realize AC driving of the pixel circuit, which can effectively avoid rapid aging of the organic light-emitting diode.
  • the influence of the internal resistance of the line on the illuminating current and the influence of the threshold voltage of the driving transistor on the display unevenness of the panel are eliminated.
  • the first voltage input unit 11 may include a first switching transistor T1, the gate of the first switching transistor T1 is connected to the first scanning terminal G(n), and the first switching transistor T1 The source is connected to the first voltage terminal POWER1 (n), and the drain of the first switching transistor T1 is connected to the first voltage input terminal a.
  • the data signal input unit 13 may include a second switching transistor T2, the gate of the second switching transistor T2 is connected to the first scanning terminal G(n), and the source of the second switching transistor T2 is connected to the data line. DATA, the drain of the second switching transistor T2 is connected to the driving control terminal g.
  • the second voltage input unit 12 may include a third switching transistor T3, the gate of the third switching transistor T3 is connected to the second scanning terminal EM(n), and the source of the third switching transistor T3 is connected to the first The second voltage terminal POWER2 (n), the drain of the third switching transistor T3 is connected to the second voltage input terminal b.
  • the first light emitting unit 14 may include: a first driving transistor DTFT1 and a first light emitting diode Tube OLED1.
  • the gate of the first driving transistor DTFT1 is connected to the driving control terminal g, and the source of the first driving transistor DTFT1 is connected to the first voltage input terminal a.
  • a first pole of the first LED OLED1 is connected to a drain of the first driving transistor DTFT1, and a second pole of the first LED OLED1 is connected to the second voltage input terminal b.
  • the second light emitting unit 15 may include: a second driving transistor DTFT2 and a second light emitting diode OLED2.
  • the gate of the second driving transistor DTFT2 is connected to the driving control terminal g, and the source of the second driving transistor DTFT2 is connected to the first voltage input terminal a.
  • the second electrode of the second LED OLED2 is connected to the drain of the second driving transistor DTFT2, and the first electrode of the second LED OLED1 is connected to the second voltage input terminal b.
  • the second light emitting diode OLED2 in the second light emitting unit 15 is reverse biased and is in a recovery phase
  • the second time period eg, Within N+1 frame
  • the first light emitting diode OLED1 in the first light emitting unit 14 is reverse biased and is in a recovery phase.
  • the types of the first driving transistor DTFT1 and the second driving transistor DTFT2 are different.
  • the first driving transistor DTFT1 is a P-type transistor
  • the second driving transistor DTFT2 is an N-type transistor.
  • the first light emitting unit 14 emits a preset high level period light or a preset low level period between the first voltage end and the second voltage end, and the second light emitting unit 15 is in the The first period of luminescence.
  • the first light emitting unit 14 emits light in a positive half cycle or a negative half cycle of the alternating current provided between the first voltage end and the second voltage end
  • the second light emitting unit 15 a negative half cycle or positive half cycle illumination of the alternating current provided between the first voltage terminal and the second voltage terminal, that is, when the first light emitting unit emits light in the positive half cycle of the alternating current, the second light emitting unit emits light in the negative half cycle of the alternating current
  • the first light emitting unit emits light in the negative half cycle of the alternating current.
  • the alternating current can be provided in the following manner: When the current pixel circuit performs the output of the current frame and the output of the next frame, the voltages of the first voltage terminal POWER1 ( n ) and the second voltage terminal POWE 2 ( n ) are reversely jumped. change.
  • Embodiments of the present invention also provide a display device including the above pixel circuit.
  • the display device provided by the embodiment of the invention provides a compensation capacitor and two light-emitting units respectively operating in different time periods in each pixel circuit to realize AC driving of the pixel circuit. It is enough to effectively avoid the rapid aging of the organic light emitting diode, and eliminate the influence of the internal resistance of the line on the luminous current and the influence of the threshold voltage of the driving transistor on the display unevenness of the panel.
  • Embodiments of the present invention also provide a driving method of a pixel circuit, which includes the following six stages.
  • the first scanning end controls the first voltage input unit to be turned off
  • the control data signal input unit is turned on
  • the data line inputs a first reference voltage to the driving control end
  • the second scanning end controls the second voltage input unit to be turned on
  • the two voltage input terminals and the second voltage terminal are turned on, and the first capacitor and the second capacitor are charged to reset the voltage of the first voltage input terminal.
  • the first capacitor and the second capacitor can be charged in the first direction during the first phase.
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a data voltage to the driving control terminal, and the second scanning end controls the second voltage input unit to be turned off, the second capacitor The voltage jumps at the first voltage input.
  • the first scanning end controls the first voltage input unit to be turned on, the control data signal input unit is turned off, the second scanning end controls the second voltage input unit to be turned on, the driving control terminal, the first voltage input terminal, and the second voltage input.
  • the terminal drives the first light emitting unit to emit light.
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a second reference voltage to the driving control end, and the second scanning end controls the second voltage input unit to be turned on,
  • the two voltage input terminals and the second voltage terminal are turned on, and the first capacitor and the second capacitor are charged to reset the voltage of the first voltage input terminal.
  • the first capacitor and the second capacitor can be charged in a second direction opposite the first direction.
  • the first scanning end controls the first voltage input unit to be turned off, the control data signal input unit is turned on, the data line inputs a data voltage to the driving control terminal, and the second scanning end controls the second voltage input unit to be turned off, the second capacitor The voltage jumps at the first voltage input.
  • the first scanning end controls the first voltage input unit to be turned on
  • the control data signal input unit is turned off
  • the second scanning end controls the second voltage input unit to be turned on
  • the driving control end the first voltage input end
  • the second voltage input The terminal drives the second light emitting unit to emit light.
  • the first switching transistor and the second driving transistor are turned off, and the second switching transistor, the third switching transistor, and the first driving transistor are turned on; in the second stage, the first The switching transistor and the third switching transistor are turned off, the second switching transistor is turned on, and the first driving transistor and the second driving transistor are turned off; in the third stage, the first switching transistor, the third switching transistor, and the first driving transistor are turned on, The second switching transistor and the second driving transistor are turned off; in the fourth stage, the first switching transistor, the first driving transistor are turned off, the second switching transistor, The third switching transistor and the second driving transistor are turned on; in the fifth stage, the first switching transistor and the third switching transistor are turned off, the second switching transistor is turned on, and the first driving transistor and the second driving transistor are turned off; In the stage, the first switching transistor, the third switching transistor and the second driving transistor are turned on, and the second switching transistor and the first driving transistor are turned off.
  • the driving method of the AC-driven pixel circuit provided by the embodiment of the invention provides a compensation capacitor and two light-emitting units respectively operating in different time periods in each pixel circuit to realize AC driving of the pixel circuit, which can effectively avoid At the same time of rapid aging of the organic light emitting diode, the influence of the internal resistance of the line on the luminous current and the influence of the threshold voltage of the driving transistor on the display unevenness of the panel are eliminated.
  • the first scanning end and the second scanning end may be powered by separate power supply, or may be powered by scanning lines, or any combination of the two.
  • the following specific embodiments are described in the form of scanning lines, that is, The first scan line serves as a first scan end, and the second scan line serves as a second scan end to provide an input control signal to the circuit of the present invention.
  • the pixel circuit shown in FIG. 2 takes the first two data frames (N and N+1) as the first time period and the second time period as an example.
  • the pixel driving method provided by the invention is specifically described as follows.
  • FIG. 2 is a schematic diagram of a pixel driving circuit of the present invention.
  • the whole circuit is composed of three switching transistors (T1-T3), two driving transistors DTFT1, DTFT2, two capacitors C1 and C2, and two light emitting diodes OLED1, OLED2.
  • DTFT1 is P-type
  • DTFT2 is N-type
  • Tl and T3 are P-type as switching transistors
  • T2 is N-type as switching transistors.
  • the light emitting diode comprises a cathode and an anode, so that the first pole and the second pole of the above light emitting diode are respectively an anode and a cathode of the light emitting diode, and are connected to the drain of the driving transistor according to specific requirements, and the light emitting diode in this embodiment
  • the first is the very anode and the second is the cathode.
  • Each row of pixel circuits shares a first scan signal line G(n) and a second scan signal line EM(n) for illumination control, and the power signal is respectively composed of a first voltage terminal POWER1 (n) and a second voltage terminal POWER2 ( n) Provide, a data line DATA.
  • each row of pixel circuits requires a separate power signal control, and each time a frame of time, each row of pixel circuit power signals (the first voltage terminal POWER1, the second voltage terminal POWE 2) need to be flipped.
  • the power supply of the current pixel circuit is provided by the first voltage terminal POWER1 (n) and the second voltage terminal POWER2 (n), and the power of the next-stage pixel circuit is powered by the first voltage terminal POWER1. (n+1), the second voltage terminal POWER2 (n+1) is provided.
  • FIG. 3 Also shown in FIG. 3 is a first scan line G ( n ) signal, a second scan line EM ( n ) signal of the current pixel circuit, a first scan line G ( n+1 ) signal of the next-stage pixel circuit, Two scan line EM (n+1) signals.
  • the operation of each row of pixel circuits in each frame is divided into three stages, as shown in FIG. 3, the operation of each row of pixel circuits in the current frame includes three stages t1-t3 and the operation of each row of pixel circuits in the next frame. Includes 3 stages t4-t6. Since the illuminating drive of two adjacent frames is alternated by the symmetrical part of the pixel circuit, the circuit operation of each stage of the adjacent two frames will be described here - a total of 6 stages, but the circuit operation itself only needs 3 Stages.
  • the N-type switching transistor is turned on at a high level VGH and the off level is at a low level VGL.
  • the P-type switching transistor turns on at a low level VGL and the off level is at a high level VGH.
  • the power supply has a high level of VDD and a low level of VSS. Therefore, with respect to the P-type switching transistor, when replacing the N-type switching transistor, it is only necessary to change the timing of the signal of the gate.
  • the switching transistor can realize the switching action in the method claims.
  • the specific circuit operation timing diagram is shown in Figure 3.
  • the operation of the three phases of the Nth frame is as follows.
  • the first stage tl The equivalent circuit is shown in Figure 4.
  • G(n) is high and EM(n) is low.
  • the signal on the data line DATA is the first reference voltage Vref1.
  • Vrefl corresponds to the lowest gray scale data signal voltage, that is, for the P-type driving transistor DTFT1
  • Vdata(max) can be taken as Vrefl, that is, the maximum value of the data line signal, so Vrefl satisfies the following conditions:
  • and Vrefl > Vdata
  • Vthdl is the threshold voltage of DTFT1
  • Vdata(max) is the maximum value of the voltage in the data line signal.
  • Vref1 causes DTFT1 to be turned on
  • the first capacitor C1 and the second capacitor C2 are charged through the DTFT1 in the direction from POWER1(n) to POWER2(n), and a current flows through the OLED1, and the potential at the point is continuously decreased until a point.
  • the potential is Vrefl +
  • the second stage t2 The equivalent circuit is shown in Figure 5. G(n) is high and EM(n) is turned high. Flat, so Tl, ⁇ 3 cut off, ⁇ 2 turn on. Point a is in a floating state, and the voltage on the data line jumps from Vrefl to Vdata. Due to the combination of C2, the potential jump of point a becomes:
  • Va Vrefl+
  • the third stage t3 the equivalent circuit is shown in Figure 6.
  • G(n) jumps to low level
  • EM(n) jumps to low level
  • Tl low level
  • ⁇ 3 turns on
  • ⁇ 2 turns off.
  • OLED1 is forward biased and enters the active phase during the positive half cycle of the AC drive, while OLED2 is reverse biased, with no current flowing through the negative half cycle of the AC drive into the recovery period. Therefore, the DTFT 2 is in a source open state. Since T1 is turned on, in the third phase, the first capacitor C 1 is short-circuited, and the potential at point a is maintained at VDD of POWER1 (n).
  • the driving current through the DTFT1, that is, the illuminating current of the OLED1 is:
  • Kdl is a constant related to the size design of the process and drive transistor DTFT1;
  • Vthdl is the threshold voltage of DTFT1.
  • the driving current is only affected by the data voltage Vdata and the first reference voltage Vref1, and has no relationship with the threshold voltage of the driving transistor DTFT1.
  • OLED 2 is switched from the positive half cycle of the AC drive to the negative half cycle and will be in the negative half cycle for one frame time.
  • the excess holes and electrons on the interface of the OLED layer change the direction of motion and move in the opposite direction, relatively consuming these excess electrons and holes, thereby weakening the positive half cycle.
  • the built-in electric field formed by the extra carriers inside the OLED further enhances the carrier injection and recombination of the next positive half cycle, which ultimately improves the recombination efficiency.
  • a negative half-cycle reverse bias process can "burn out" some of the locally-conducted micro-channel "Filaments", which are actually "pinholes".
  • the elimination of pinholes is very important to extend the life of the device, where the pinhole is a semiconductor Fine pores formed by uneven deposition during deposition. Therefore, in other words, OLED 2 is in a recovery period during this frame time.
  • the N+1 frame is entered, and the operation of the three stages of the frame circuit is under the mouth.
  • the fourth stage t4 The equivalent circuit is shown in Figure 7. G(n) is high and EM(n) is low.
  • T1 is turned off, T2 and ⁇ 3 are turned on, and POWER1(n) jumps from VDD to VSS, and POWE 2(n) changes from VSS to VDD.
  • the signal on the data line is the second reference voltage Vref2.
  • the second reference voltage Vref2 corresponds to the lowest gray level data signal voltage, that is, for the N-type driving transistor DTFT2, Vdata(min) can be taken as Vref2, so Vref2 satisfies the following conditions:
  • Vref2-VSS>Vthd2 and Vref2 ⁇ Vdata;
  • Vthd2 is the threshold voltage of DTFT2
  • Vdata(min) is the minimum voltage of the data line signal.
  • the fifth stage t5 The equivalent circuit is shown in Fig. 8. G(n) is high level and EM(n) jumps to high level, so Tl and ⁇ 3 are turned off, and ⁇ 2 is turned on. When the defect is floating, the voltage on the data line changes from Vref2 to Vdata. Due to the combination of C2, the potential jump at point a becomes:
  • Va Vref2-Vthd2+(Vdata-Vref2)*C2/(Cl+C2);
  • the sixth stage t6 The equivalent circuit is shown in Figure 9. G(n) jumps to low level and EM(n) jumps to Low level, Tl, ⁇ 3 turn on, ⁇ 2 cutoff. OLED2 is forward biased and enters the active phase during the positive half cycle of AC drive, while OLED1 is reverse biased and flows in the negative half cycle of AC drive into the recovery period without current flowing. Therefore, the DTFT 1 is in a source open state. Since T1 is turned on, in the sixth stage, the first capacitor C1 is short-circuited, and the potential at point a is maintained at VSS of POWER1(n).
  • the driving current through DTFT2 that is, the illuminating current of OLED2 is:
  • Kd2 is a constant related to the size design of the process and drive transistor DTFT2;
  • Vthd2 is the threshold voltage of DTFT2.
  • the drive current is only affected by the data voltage Vdata and the second reference voltage Vref2, and has no relationship with the threshold voltage of the drive transistor DTFT2.
  • OLED1 is switched from the positive half cycle of the AC drive to the negative half cycle, and will be in the negative half cycle for one frame time.
  • the excess holes and electrons on the interface of the OLED layer change the direction of motion and move in the opposite direction, relatively consuming these excess electrons and holes, thereby weakening the positive half cycle.
  • the built-in electric field formed by the extra carriers inside the OLED further enhances the carrier injection and recombination of the next positive half cycle, which ultimately improves the recombination efficiency.
  • a negative half-cycle reverse bias process can "burn out" some of the locally-conducted micro-channel "Filaments", which are actually "pinholes". As a result, the elimination of pinholes is important to extend the life of the device. Therefore, in other words, OLED1 is in a recovery period during this frame time.
  • the driving circuit in the adjacent two frame time of the present invention is the operation of the driving circuit in the adjacent two frame time of the present invention.
  • the driving current is expressed differently. Therefore, the data lines are required to provide different data line voltages for different driving transistors.
  • Vrefl is provided in the first stage data line
  • the data signal data is provided in the second stage data line.
  • the data signal input unit is turned off, the signal provided by the data line does not afford the line pixel circuit.
  • the fourth stage of data The line provides Vref2, and the data signal data is provided in the fifth stage data line.
  • the switching transistor of the pixel circuit is suitable for a thin film transistor of amorphous silicon, polysilicon, oxide, etc., and the circuit can be easily modified into other NMOS, PMOS or CMOS circuits by simplification, substitution and combination, and only needs to adjust the input signal correspondingly.
  • the timing relationship can be realized, and therefore it is within the scope of the invention as long as it does not deviate from the essence of the invention.

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Abstract

一种交流驱动的像素电路、驱动方法及显示装置，涉及显示器制造领域，能够在有效避免有机发光二极管的快速老化的同时，消除线路内阻对发光电流的影响和驱动晶体管阈值电压对面板显示不均匀性的影响。该像素电路包括：第一电容（C1）、第二电容（C2）、第一电压输入单元（11）、第二电压输入单元（12）、数据信号输入单元（13）、第一发光单元（14）和第二发光单元（15）。

Description

交流驱动的像素电路、 驱动方法及显示装置 技术领域
本发明涉及一种交流驱动的像素电路、 驱动方法及显示装置。 背景技术
AMOLED ( Active Matrix Organic Light Emitting Diode， 有源矩阵有机发 光二极管面板） 由驱动 TFT ( Thin Film Transistor ， 薄膜场效应晶体管)在饱 和状态下产生的驱动电流驱动发光。 在输入相同的灰阶电压时， 不同的驱动 TFT的临界电压（即阔值电压）会产生不同的驱动电流， 从而造成 AMOLED 中各驱动 TFT 的驱动电流的不一致性。 由于 LTPS ( Low Temperature Poly-silicon, 低温多晶硅）制程上 Vth (晶体管阔值电压） 的均匀性非常差， 同时由于 Vth还存在漂移，因此釆用传统的 2T1C电路的 AMOLED的亮度均 匀性一直很差。 此外， 影响 AMOLED 的亮度均匀性的另一个原因在于： 由 于给 OLED (发光二极管）供电的线路存在内阻， 而 OLED是电流驱动的发 光器件， 一旦有电流通过， 在给 OLED供电的线路的内阻上必然产生压降， 因此会直接导致不同位置处的 OLED的电源电压达不到要求的电压。
此外， OLED有机发光二极管存在老化问题， 这是所有 OLED发光显示 都必须面对的共性问题。 由于现有技术大多使用直流驱动， 空穴和电子的传 输方向是固定不变的， 它们分别从正负极注入到发光层， 在发光层中形成激 子， 辐射发光。 其中未参与复合的多余空穴 (或电子)， 或者积累在空穴传输层 /发光层 (或发光层 /电子传输层)界面， 或者越过势垒流入电极。 随着 OLED使 用时间的延长， 在发光层的内部界面积累的很多未复合的载流子使得 OLED 内部形成内建电场， 导致 OLED的阔值电压不断升高， 其发光亮度也会不断 降低， 能量利用效率也逐步降低。现有技术提出了一种 OLED交流驱动电路， 该电路虽然实现了 OLED的交流驱动， 解决了 OLED的老化问题， 然而无法 改善内阻和驱动晶体管阔值对面板显示不均勾性的影响。 发明内容
针对上述问题， 本发明实施例提供了一种交流驱动的像素电路、 驱动方 法及显示装置， 能够在有效避免有机发光二极管的快速老化的同时， 消除线 路内阻对发光电流的影响和驱动晶体管阔值电压对面板显示不均勾' I"生的影 响。
根据本发明实施例， 提供了一种交流驱动的像素电路， 包括： 第一电容、 第二电容、 第一电压输入单元、 第二电压输入单元、 数据信号输入单元、 第 一发光单元和第二发光单元。
所述第一发光单元被配置为在所述驱动控制端、 第一电压输入端、 第二 电压输入端的控制下发光； 所述第二发光单元被配置为在所述驱动控制端、 第一电压输入端、 第二电压输入端的控制下发光； 其中所述第一发光单元在 预设的第一时间周期内发光和所述第二发光单元在预设的第二时间周期内发 光。
所述第一电压输入单元被配置为在第一扫描端的控制下向所述第一发光 单元和所述第二发光单元提供第一电压端的第一输入电压； 所述第二电压输 入单元被配置为在所述第二扫描端的控制下向所述第一发光单元和第二发光 单元提供第二电压端的第二输入电压。
所述数据信号输入单元用于在所述第一扫描端的控制下向所述驱动控制 端输入数据线的数据线信号。
所述第一电容的第一极连接所述第一电压端， 所述电容的第二极连接所 述第一电压输入端； 所述第二电容的第一极连接所述第一电压输入端， 所述 第一电容的第二极连接所述驱动控制端。
可选的， 所述第一电压输入单元包括第一开关晶体管， 所述第一开关晶 体管的栅极连接所述第一扫描端， 所述第一开关晶体管的源极连接所述第一 电压端， 所述第一开关晶体管的漏极连接所述第一电压输入端。
可选的， 所述数据信号输入单元包括第二开关晶体管， 所述第二开关晶 体管的栅极连接所述第一扫描端， 所述第二开关晶体管的源极连接所述数据 线， 所述第二开关晶体管的漏极连接所述驱动控制端。
可选的， 所述第二电压输入单元包括第三开关晶体管， 所述第三开关晶 体管的栅极连接所述第二扫描端， 所述第三开关晶体管的源极连接所述第二 电压端， 所述第三开关晶体管的漏极连接所述第二电压输入端。
可选的， 所述第一发光单元包括： 第一驱动晶体管和第一发光二极管； 所述第一驱动晶体管的栅极连接所述驱动控制端， 所述第一驱动晶体管的源 极连接所述第一电压输入端； 所述第一发光二极管的第一极连接所述第一驱 动晶体管的漏极， 所述第一发光二极管的第二极连接所述第二电压输入端。 所述第二发光单元包括： 第二驱动晶体管和第二发光二极管； 所述第二 驱动晶体管的栅极连接所述驱动控制端， 所述第二驱动晶体管的源极连接所 述第一电压输入端； 所述第二发光二极管的第二极连接所述第二驱动晶体管 的漏极， 所述第二发光二极管的第一极连接所述第二电压输入端。
所述第一驱动晶体管和第二驱动晶体管的类型不同。
可选的， 所述第一发光单元在所述第一电压端和第二电压端之间提供的 预设的高电平周期发光或预设的低电平周期发光， 所述第二发光单元在所述 周期发光。
根据本发明实施例， 还提供了一种显示装置， 包括上述任一项所述的像 素电路。
根据本发明实施例， 还提供了一种如上所述的像素电路的驱动方法， 包 括：
在第一阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第一参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压；
在第二阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变；
在第三阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第一发光单元发光；
在第四阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第二参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压；
在第五阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变； 在第六阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第二发光单元发光。
可选的， 在第一阶段， 第一开关晶体管、 第二驱动晶体管截止， 第二开 关晶体管、 第三开关晶体管及第一驱动晶体管导通； 在第二阶段， 第一开关 晶体管及第三开关晶体管截止， 第二开关晶体管导通， 第一驱动晶体管及第 二驱动晶体管断路； 在第三阶段， 第一开关晶体管、 第三开关晶体管、 第一 驱动晶体管导通、 第二开关晶体管及第二驱动晶体管截止； 在第四阶段， 第 一开关晶体管、 第一驱动晶体管截止， 第二开关晶体管、 第三开关晶体管及 第二驱动晶体管导通； 在第五阶段， 第一开关晶体管、 第三开关晶体管管截 止， 第二开关晶体管导通， 第一驱动晶体及第二驱动晶体管断路； 在第六阶 段， 第一开关晶体管、 第三开关晶体管及第二驱动晶体管开启， 第二开关晶 体管、 第一驱动晶体管截止。
本发明实施例提供的交流驱动的像素电路、 驱动方法及显示装置， 在每 个像素电路中设置补偿电容以及两个分别工作在不同的时间周期内的发光单 元以实现像素电路的交流驱动， 能够在有效避免有机发光二极管的快速老化 的同时， 消除线路内阻对发光电流的影响和驱动晶体管阔值电压对面板显示 不均匀性的影响。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例。
图 1为本发明实施例提供的一种交流驱动的像素电路的结构示意图； 图 2为本发明实施例提供的交流驱动的像素电路的另一结构示意图； 图 3为本发明实施例提供的交流驱动的像素电路的输入信号时序状态示 意图；
图 4为本发明实施例提供的交流驱动的像素电路在第一阶段的等效电路 图；
图 5为本发明实施例提供的交流驱动的像素电路在第二阶段的等效电路 图； 图 6为本发明实施例提供的交流驱动的像素电路在第三阶段的等效电路 图；
图 7为本发明实施例提供的交流驱动的像素电路在第四阶段的等效电路 图；
图 8为本发明实施例提供的交流驱动的像素电路在第五阶段的等效电路 图；
图 9为本发明实施例提供的交流驱动的像素电路在第六阶段的等效电路 图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。
本发明所有实施例中釆用的开关晶体管和驱动晶体管均可以为薄膜晶体 管或场效应管或其他特性相同的器件， 此外本发明实施例所釆用的晶体管包 括 P型晶体管和 N型晶体管两种， 其中， P型晶体管在栅极为低电平时导通， 在栅极为高电平时截止， N型晶体管为在栅极为高电平时导通， 在栅极为低 在本技术领域内也用关闭替代， 在本申请的实施例中可以表示对应的功能。
参照图 1所示， 本发明实施例提供的一种交流驱动的像素电路包括： 第 一电容 Cl、 第二电容 C2、 第一电压输入单元 11、 第二电压输入单元 12、 数 据信号输入单元 13、 第一发光单元 14和第二发光单元 15。
第一发光单元 14连接第一电压输入端 a、 第二电压输入端1)、 驱动控制 端 g， 并且被配置为在驱动控制端 g、 第一电压输入端 a、 第二电压输入端 b 的控制下在第 N帧发光。
第二发光单元 15连接第一电压输入端 a、 第二电压输入端1)、 驱动控制 端 g， 并且被配置为在驱动控制端 g、 第一电压输入端 a、 第二电压输入端 b 的控制下在与第 N帧相邻的第 N+1帧发光。
第一电压输入单元 11连接第一电压端 POWER1 ( n )、 第一电压输入端 a 和第一扫描端 G ( n ); 并且被配置为在第一扫描端 G ( n )的控制下向第一发 光单元 14和第二发光单元 15提供第一电压端 POWER1 ( n ) 的第一输入电 压。
第二电压输入单元 12连接第二电压端 POWER2 ( n )、第二电压输入端 b 和第二扫描端 EM (n); 并且被配置为在第二扫描端 EM (n) 的控制下向第 一发光单元 14和第二发光单元 15提供第二电压端 POWER2 (n) 的第二输 入电压。
数据信号输入单元 13连接数据线 DATA、 第一扫描端 G (n)和驱动控 制端 g， 并且被配置为在第一扫描端 G (n) 的控制下向驱动控制端 g输入数 据线 DATA数据线信号。
第一电容 C1 的第一极连接第一电压端 POWER1 (n)， 第一电容 C1 的 第二极连接第一电压输入端 a。
第二电容 C2的第一极连接第一电压输入端 a， 所述第二电容 C2的第二 极连接所述驱动控制端 g。
第一时间周期和第二时间周期可以为相邻的两个数据帧， 但不以此为限 定； 第一时间周期和第二时间周期可以根据需要进行设定。 通常， "一个数据 帧 （简称为一帧） "即为"一个显示周期 "的时间， 约在数毫秒至数十毫秒。
在本发明实施例提供的交流驱动的像素电路中设置补偿电容以及两个分 别工作在不同的时间周期内的发光单元以实现像素电路的交流驱动， 能够在 有效避免有机发光二极管的快速老化的同时， 消除线路内阻对发光电流的影 响和驱动晶体管阔值电压对面板显示不均匀性的影响。
根据本发明实施例，第一电压输入单元 11可以包括第一开关晶体管 Tl， 所述第一开关晶体管 T1的栅极连接所述第一扫描端 G(n)， 所述第一开关晶 体管 T1的源极连接所述第一电压端 POWER1 (n)， 所述第一开关晶体管 T1 的漏极连接所述第一电压输入端 a。
数据信号输入单元 13可以包括第二开关晶体管 T2， 所述第二开关晶体 管 Τ2的栅极连接所述第一扫描端 G ( η )， 所述第二开关晶体管 Τ2的源极连 接所述数据线 DATA, 所述第二开关晶体管 T2的漏极连接驱动控制端 g。
第二电压输入单元 12可以包括第三开关晶体管 T3， 所述第三开关晶体 管 Τ3的栅极连接所述第二扫描端 EM (η)， 所述第三开关晶体管 Τ3的源极 连接所述第二电压端 POWER2 (η)， 所述第三开关晶体管 Τ3的漏极连接所 述第二电压输入端 b。
所述第一发光单元 14可以包括： 第一驱动晶体管 DTFT1和第一发光二 极管 OLEDl。所述第一驱动晶体管 DTFT1的栅极连接所述驱动控制端 g，所 述第一驱动晶体管 DTFT1的源极连接所述第一电压输入端 a。 所述第一发光 二极管 OLED1的第一极连接所述第一驱动晶体管 DTFT1的漏极， 所述第一 发光二极管 0LED1的第二极连接所述第二电压输入端 b。
所述第二发光单元 15可以包括： 第二驱动晶体管 DTFT2和第二发光二 极管 OLED2。所述第二驱动晶体管 DTFT2的栅极连接所述驱动控制端 g，所 述第二驱动晶体管 DTFT2的源极连接所述第一电压输入端 a。 所述第二发光 二极管 OLED2的第二极连接所述第二驱动晶体管 DTFT2的漏极， 所述第二 发光二极管 OLED1的第一极连接所述第二电压输入端 b。
在所述第一时间周期 （例如第 N帧） 内， 所述第二发光单元 15中的第 二发光二极管 OLED2被反向偏置并且处于恢复阶段，而在所述第二时间周期 (例如第 N+1帧）内， 所述第一发光单元 14中的第一发光二极管 OLED1被 反向偏置并且处于恢复阶段。
所述第一驱动晶体管 DTFT1和第二驱动晶体管 DTFT2的类型不同。 例 如， 第一驱动晶体管 DTFT1为 P型晶体管， 第二驱动晶体管 DTFT2为 N型 晶体管。
所述第一发光单元 14 在所述第一电压端和第二电压端之间提供的预设 的高电平周期发光或预设的低电平周期发光，所述第二发光单元 15在所述第 期发光。
可选的，在釆用交流电时，所述第一发光单元 14在所述第一电压端和第 二电压端之间提供的交流电的正半周发光或负半周发光， 所述第二发光单元 15在所述第一电压端和第二电压端之间提供的交流电的负半周发光或正半周 发光， 即第一发光单元在交流电的正半周发光时， 第二发光单元在交流电的 负半周发光； 第二发光单元在交流电的正半周发光时， 第一发光单元在交流 电的负半周发光。 可以釆用以下方式提供交流电： 当前像素电路在进行当前 帧的输出和下一帧的输出时， 第一电压端 POWER1 ( n ) 和第二电压端 POWE 2 ( n ) 的电压要发生反向跳变。
本发明实施例还提供一种显示装置， 其包括上述的像素电路。
本发明实施例提供的显示装置， 在每个像素电路中设置补偿电容以及两 个分别工作在不同的时间周期内的发光单元以实现像素电路的交流驱动， 能 够在有效避免有机发光二极管的快速老化的同时， 消除线路内阻对发光电流 的影响和驱动晶体管阔值电压对面板显示不均匀性的影响。
本发明实施例还提供一种像素电路的驱动方法， 其包括以下六个阶段。 在第一阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第一参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压。 例如， 在第一阶段中第一电容和第 二电容可以沿第一方向充电。
在第二阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变。
在第三阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第一发光单元发光。
在第四阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第二参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压。 例如， 在第四阶段中第一电容和第 二电容可以沿与第一方向相反的第二方向充电。
在第五阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变。
在第六阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第二发光单元发光。
根据本发明实施例， 可选的， 在第一阶段， 第一开关晶体管及第二驱动 晶体管截止， 第二开关晶体管、 第三开关晶体管及第一驱动晶体管导通； 在 第二阶段， 第一开关晶体管及第三开关晶体管截止， 第二开关晶体管导通， 第一驱动晶体管及第二驱动晶体管断路； 在第三阶段， 第一开关晶体管、 第 三开关晶体管、 第一驱动晶体管导通、 第二开关晶体管及第二驱动晶体管截 止； 在第四阶段， 第一开关晶体管、 第一驱动晶体管截止， 第二开关晶体管、 第三开关晶体管及第二驱动晶体管导通； 在第五阶段， 第一开关晶体管、 第 三开关晶体管管截止， 第二开关晶体管导通， 第一驱动晶体及第二驱动晶体 管断路； 在第六阶段， 第一开关晶体管、 第三开关晶体管及第二驱动晶体管 开启， 第二开关晶体管、 第一驱动晶体管截止。
本发明实施例提供的交流驱动的像素电路的驱动方法， 在每个像素电路 中设置补偿电容以及两个分别工作在不同的时间周期内的发光单元以实现像 素电路的交流驱动， 能够在有效避免有机发光二极管的快速老化的同时， 消 除线路内阻对发光电流的影响和驱动晶体管阔值电压对面板显示不均匀性的 影响。
以上第一扫描端、 第二扫描端可以釆用单独供电的方式， 也可以釆用扫 描线的形式进行供电， 或者两者结合的任意组合， 以下具体实施例以扫描线 的形式进行说明， 即第一扫描线作为第一扫描端、 第二扫描线作为第二扫描 端分别为本发明的电路提供输入的控制信号。
具体的， 结合图 3所示的信号时序状态图， 图 2所示的像素电路， 以第 一时间周期和第二时间周期为相邻的两个数据帧 （N和 N+1 ) 为例对本发明 提供的像素驱动方法具体说明如下。
图 2为本发明的像素驱动电路原理图， 整个电路的构成包括 3个开关晶 体管 （T1-T3 ), 两个驱动晶体管 DTFT1、 DTFT2, 两个电容 C1和 C2， 以及 两个发光二极管 OLED1、 OLED2。 DTFT1为 P型， DTFT2为 N型， Tl、 T3 作为开关晶体管为 P型， T2作为开关晶体管为 N型。 可以理解的是， 发光二 极管包括阴极和阳极， 因此以上发光二极管的第一极和第二极分别为发光二 极管的阳极和阴极， 根据具体需求与驱动晶体管的漏极连接， 本实施例中发 光二极管的第一极为阳极， 第二极为阴极。 每一行像素电路公用一条第一扫 描信号线 G(n)、 一条第二扫描信号线 EM (n) 用于发光控制， 电源信号分别 由第一电压端 POWER1 ( n )、 第二电压端 POWER2 ( n )提供， 一条数据线 DATA。
需要说明的是： 每一行像素电路需要单独的电源信号控制， 且每过一帧 的时间后， 每行像素电路电源信号 （第一电压端 POWERl、 第二电压端 POWE 2 )需要翻转。
参照图 3所示， 当前像素电路的电源由第一电压端 POWER1 ( n )、 第二 电压端 POWER2 ( n )提供， 下一级像素电路的电源由第一电压端 POWER1 ( n+1 )、 第二电压端 POWER2 ( n+1 )提供。
图 3 中还示出了当前像素电路的第一扫描线 G ( n )信号、 第二扫描线 EM ( n )信号， 下一级像素电路的第一扫描线 G ( n+1 )信号、 第二扫描线 EM ( n+1 )信号。 在每个帧中每行像素电路的操作分 3个阶段， 如图 3中示 出， 当前帧中每行像素电路的操作包括 3个阶段 tl-t3以及下一帧中每行像素 电路的操作包括 3个阶段 t4-t6。 由于相邻两帧的发光驱动是由像素电路中对 称的部分交替进行， 因此这里会将相邻两帧的每个阶段的电路操作——说明， 共 6个阶段， 但电路操作本身只需 3个阶段。
N型开关晶体管开启电平为高电平 VGH， 关闭电平为低电平 VGL。 P 型开关晶体管开启电平为低电平 VGL， 关闭电平为高电平 VGH。 电源的高 电平为 VDD， 低电平为 VSS。 因此相对于 P型的开关晶体管， 当替换成 N 型的开关晶体管时， 只需要调换栅极的信号的时序即可， 当然本发明中以开 关晶体管能够实现方法权利要求中的开关作用即可。
具体电路操作时序图如图 3所示， 第 N帧的三个阶段的操作情况如下。 第一阶段 tl : 等效电路如图 4所示， G(n)为高电平、 EM(n)为低电平。
T1截止， T2、 Τ3导通， 同时 POWER2(n)从 VDD跳变为 VSS， POWE l(n) 从 VSS跳变为 VDD。 此时数据线 DATA上的信号为第一参考电压 Vrefl。 需 要说明的是该第一参考电压 Vrefl 对应于最低灰阶数据信号电压， 即对于 P 型驱动晶体管 DTFT1， 可以取 Vdata(max)为 Vrefl即数据线信号的最大值， 因此 Vrefl满足以下条件：
VDD- Vrefl >| Vthdl | 且 Vrefl >=Vdata;
Vthdl为 DTFTl的阔值电压， Vdata(max)为数据线信号中电压的最大值， 此时 DTFT2虽然开启， 但由于从两个 POWERl(n)和 POWER2(n)电压跳变开 始， OLED2 已经从交流驱动的正半周期进入交流驱动的负半周期， OLED2 处于反向偏置， 没有电流流过， 因此 DTFT2 处于源极开路的状态， OLED2 进入恢复时期。 由于 Vrefl使得 DTFT1开启， 因此第一电容 C1和第二电容 C2通过 DTFT1沿着从 POWERl(n)到 POWER2(n)的方向充电， 电流会流过 OLED1 , a点的电位不断下降， 直到 a点的电位为 Vrefl +| Vthdl |， 因此 a点 电位为：
Va= Vrefl+| Vthdl
第二阶段 t2: 等效电路如图 5所示， G(n)为高电平、 EM(n)跳变为高电 平， 因此 Tl、 Τ3截止， Τ2导通。 a点处于悬空状态，数据线上的电压从 Vrefl 跳变为 Vdata， 由于 C2的辆合， a点的电位跳变为：
Va= Vrefl+|Vthdl|+(Vdata-Vrefl)*C2/(Cl+C2);
因此对 C2来说， 两端的压差为：
Vc2=Va-Vg= Vrefl +| Vthdl | + ( Vdata- Vref 1 ) * C2/(C 1 +C2)- Vdata;
=(Vrefl-Vdata)*Cl/(Cl+C2)+ |Vthdl| 0
在该阶段中， OLED1和 OLED2都处于断路状态。
第三阶段 t3:等效电路如图 6所示，在该阶段， G(n)跳变为低电平、 EM(n) 跳变为低电平， Tl、 Τ3导通， Τ2截止。 OLED1 为正向偏置， 处于交流驱 动的正半周期进入工作状态， 而 OLED2为反向偏置，处于交流驱动的负半周 期进入恢复期无电流流过。 因此 DTFT2处于源极断路状态。 由于 T1导通， 在第三阶段中， 第一电容 C 1被短路， a点电位维持在 POWER1 (n)的 VDD。
对于 DTFT1来说， 由于 T2截止， 栅极处于悬空状态， 因此 a点电位的 变化对于电容 C2两端的电压没有影响， DTFT1的栅源电压仍然为上一阶段 C2两端的电压即：
Vsg=Vc2= (Vrefl -Vdata)*Cl/(Cl+C2)+ |Vthdl|;
通过 DTFT1的驱动电流即 OLED1的发光电流为：
Ioledl=kdl(Vsg-| Vthdl I )Λ2
=kdl[(Vrefl-Vdata)*Cl/(Cl+C2)+ | Vthdl |-| Vthdl | ]Λ2;
=kdl[(Vrefl-Vdata)*Cl/(Cl+C2)]A2。
Kdl 为与工艺和驱动晶体管 DTFT1 的尺寸设计有关的常数； Vthdl 为 DTFT1的阔值电压。 驱动电流只受数据电压 Vdata和第一参考电压 Vrefl的 影响， 与驱动晶体管 DTFT1的阔值电压没有关系。
在第一阶段处， OLED2从交流驱动的正半周期转向负半周期， 而且将在 一帧的时间内都处于负半周期。 当处于交流驱动的负半周时， OLED 的发光 层界面上多余空穴和电子改变运动方向， 朝着相反的方向运动， 相对地消耗 了这些多余的电子和空穴， 从而削弱了由正半周的多余载流子在 OLED内部 形成的内建电场， 进一步增强了下一个正半周的载流子注入及复合， 最终有 利提高复合效率。 另外， 负半周的反向偏压处理可以 "烧断 (Burn out)"某些局 部导通的微观小通道 "细丝 (Filaments)", 这种细丝实际上是由某种"针孔"引起 的， 针孔的消除对于延长器件的使用寿命是相当重要的， 其中针孔为半导体 沉积过程中沉积不均匀形成的细孔。 因此， 换句话说， OLED2在这一帧时间 中处于恢复期。
在过了一帧的时间后， 进入第 N+1帧， 该帧电路的 3个阶段的操作情况 ^口下。
第四阶段 t4: 等效电路如图 7所示， G(n)为高电平、 EM(n)为低电平。
T1截止， T2、 Τ3导通， 同时 POWERl(n)从 VDD跳变为 VSS， POWE 2(n) 从 VSS跳变为 VDD。
此时数据线上的信号为第二参考电压 Vref2。需要说明的是： 该第二参考 电压 Vref2对应于最低灰阶数据信号电压， 即对于 N型驱动晶体管 DTFT2， 可以取 Vdata(min)为 Vref2， 因此 Vref2满足以下条件：
Vref2-VSS>Vthd2 且 Vref2<=Vdata;
Vthd2为 DTFT2的阔值电压， Vdata(min)为数据线信号中电压的最小值， 此时 DTFT1虽然开启， 但由于从两个 POWERl(n)和 POWER2(n)电压跳变开 始， OLED1 已经从交流驱动的正半周期进入交流驱动的负半周期， OLED1 处于反向偏置， 没有电流流过， 因此 DTFT1 处于源极开路的状态， OLED1 进入恢复时期。 由于在第三阶段中第一电容 C1两端的电压为 0， 因此在进入 第四阶段时 a点的电位为 POWERl(n)的电位，即 VSS。由于 Vref2使得 DTFT2 开启，因此流过 OLED2的电流通过 DTFT2沿着从 POWER2(n)到 POWE l(n) 的方向对 C1和 C2充电， a点的电位不断上升，直到 a点的电位为 Vref2-Vthd2， 因此 a点电位为：
Va= Vref2-Vthd2。
第五阶段 t5: 等效电路如图 8所示， G(n)为高电平、 EM(n)跳变为高电 平， 因此 Tl、 Τ3截止， Τ2导通。 Α点处于悬空状态，数据线上的电压从 Vref2 跳变为 Vdata， 由于 C2的辆合， a点的电位跳变为：
Va= Vref2-Vthd2+(Vdata-Vref2)*C2/(Cl+C2);
因此， 对 C2来说， 两端的压差为：
Vc2=Vg-Va
=Vdata-[Vref2-Vthd2+(Vdata-Vref2)*C2/(Cl+C2)];
=(Vdata-Vref2)*Cl/(Cl+C2)+Vthd2。
在该阶段中， OLED1和 OLED2都处于断路状态。
第六阶段 t6: 等效电路如图 9所示， G(n)跳变为低电平、 EM(n)跳变为 低电平， Tl、 Τ3导通， Τ2截止。 OLED2为正向偏置， 处于交流驱动的正半 周期进入工作状态， 而 OLED1为反向偏置，处于交流驱动的负半周期进入恢 复期无电流流过。 因此 DTFT1处于源极断路状态。 由于 T1导通， 在第六阶 段中， 第一电容 C1被短路， a点电位维持在 POWERl(n)的 VSS。
对于 DTFT2来说， 由于 T2截止， 栅极处于悬空状态， 因此 a点电位的 变化对于电容 C1 两端的电压没有影响， DTFT2的栅源电压仍然为上一阶段 确定的 C1两端的电压即：
Vgs=Vc2
=( Vdata-Vref2)*Cl/(Cl+C2)+ Vthd2;
通过 DTFT2的驱动电流即 OLED2的发光电流为：
Ioled2=kd2(Vgs-Vthd2)A2
=kd2[( Vdata-Vref2)*Cl/(Cl+C2)+ Vthd2-Vthd2]A2;
= kd2[( Vdata-Vref2)*Cl/(Cl+C2)]A2
Kd2 为与工艺和驱动晶体管 DTFT2 的尺寸设计有关的常数； Vthd2 为 DTFT2的阔值电压。 驱动电流只受数据电压 Vdata和第二参考电压 Vref2的 影响， 与驱动晶体管 DTFT2的阔值电压没有关系。
在第四阶段处， OLED1从交流驱动的正半周期转向负半周期， 而且将在 一帧的时间内都处于负半周期。 当处于交流驱动的负半周时， OLED 的发光 层界面上多余空穴和电子改变运动方向， 朝着相反的方向运动， 相对地消耗 了这些多余的电子和空穴， 从而削弱了由正半周的多余载流子在 OLED内部 形成的内建电场， 进一步增强了下一个正半周的载流子注入及复合， 最终有 利提高复合效率。 另外， 负半周的反向偏压处理可以 "烧断 (Burn out)"某些局 部导通的微观小通道 "细丝 (Filaments)", 这种细丝实际上是由某种"针孔"引起 的， 针孔的消除对于延长器件的使用寿命是相当重要的。 因此， 换句话说， OLED1在这一帧时间中处于恢复期。
以上即是本发明相邻两帧时间里的驱动电路的操作。 需要说明的是由于 在相邻两帧时间里， 驱动晶体管不一样， 驱动电流的表达方式也不一样， 因 此需要数据线针对不同的驱动晶体管提供不同的数据线电压， 具体参照时序 电路图 3， 在第 N帧的范围内， 在第一阶段数据线提供 Vrefl， 在第二阶段数 据线提供数据信号 data, 在第三阶段由于数据信号输入单元关闭， 数据线提 供的信号对该行像素电路不起作用， 在第 N+1帧的范围内， 在第四阶段数据 线提供 Vref2， 在第五阶段数据线提供数据信号 data, 在第六阶段由于数据信 号输入单元关闭， 数据线提供的信号对该行像素电路不起作用。 当然该像素 电路的开关晶体管适用于非晶硅、 多晶硅、 氧化物等工艺的薄膜晶体管， 该 电路可以经过简化、替代、组合轻易改成其它 NMOS、 PMOS或 CMOS电路， 只需对应的调整输入信号的时序关系即可实现， 因此只要不违背本发明的实 质都属于本发明范畴。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。
本申请要求 2013年 10月 31 日提交的申请号为 201310530181.4且发明 名称为"一种交流驱动的像素电路、 驱动方法及显示装置 "的中国优先申请的 优先权， 通过引用将其全部内容并入于此。

Claims

权 利 要 求 书
1、 一种交流驱动的像素电路， 包括： 第一电容、 第二电容、 第一电压输 入单元、 第二电压输入单元、 数据信号输入单元、 第一发光单元和第二发光 单元； 其中，
所述第一发光单元被配置为在所述驱动控制端、 第一电压输入端、 第二 电压输入端的控制下发光；
所述第二发光单元被配置为在所述驱动控制端、 第一电压输入端、 第二 电压输入端的控制下发光； 其中所述第一发光单元在预设的第一时间周期内 发光和所述第二发光单元在预设的第二时间周期内发光；
其中， 所述第一电压输入单元被配置为在第一扫描端的控制下向所述第 一发光单元和所述第二发光单元提供第一电压端的第一输入电压；
所述第二电压输入单元被配置为在所述第二扫描端的控制下向所述第一 发光单元和第二发光单元提供第二电压端的第二输入电压；
所述数据信号输入单元被配置为在所述第一扫描端的控制下向所述驱动 控制端输入数据线的数据线信号；
所述第一电容的第一极连接所述第一电压端， 所述电容的第二极连接所 述第一电压输入端；
所述第二电容的第一极连接所述第一电压输入端， 所述第一电容的第二 极连接所述驱动控制端。
2、根据权利要求 1所述的像素电路， 其中， 所述第一电压输入单元包括 第一开关晶体管， 所述第一开关晶体管的栅极连接所述第一扫描端， 所述第 一开关晶体管的源极连接所述第一电压端， 所述第一开关晶体管的漏极连接 所述第一电压输入端。
3、根据权利要求 1所述的像素电路， 其中， 所述数据信号输入单元包括 第二开关晶体管， 所述第二开关晶体管的栅极连接所述第一扫描端， 所述第 二开关晶体管的源极连接所述数据线， 所述第二开关晶体管的漏极连接所述 驱动控制端。
4、根据权利要求 1所述的像素电路， 其中， 所述第二电压输入单元包括 第三开关晶体管， 所述第三开关晶体管的栅极连接所述第二扫描端， 所述第 三开关晶体管的源极连接所述第二电压端， 所述第三开关晶体管的漏极连接 所述第二电压输入端。
5、 根据权利要求 1所述的像素电路， 其中，
所述第一发光单元包括： 第一驱动晶体管和第一发光二极管； 所述第一 驱动晶体管的栅极连接所述驱动控制端， 所述第一驱动晶体管的源极连接所 述第一电压输入端； 所述第一发光二极管的第一极连接所述第一驱动晶体管 的漏极， 所述第一发光二极管的第二极连接所述第二电压输入端；
所述第二发光单元包括： 第二驱动晶体管和第二发光二极管； 所述第二 驱动晶体管的栅极连接所述驱动控制端， 所述第二驱动晶体管的源极连接所 述第一电压输入端； 所述第二发光二极管的第二极连接所述第二驱动晶体管 的漏极， 所述第二发光二极管的第一极连接所述第二电压输入端；
所述第一驱动晶体管和第二驱动晶体管的类型不同。
6、 根据权利要求 1-5任一项所述的像素电路， 其中， 所述第一发光单元 在所述第一电压端和第二电压端之间提供的预设的高电平周期发光或预设的 低电平周期发光， 所述第二发光单元在所述第一电压端和第二电压端之间提 供的预设的低电平周期发光或预设的高电平周期发光。
7、 一种显示装置， 包括权利要求 1-6任一项所述的像素电路。
8、 一种如权利要求 1所述的像素电路的驱动方法， 包括：
在第一阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第一参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压；
在第二阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变；
在第三阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第一发光单元发光；
在第四阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入第二参考电压， 第二扫描端控制第二 电压输入单元开启， 将第二电压输入端和第二电压端导通， 第一电容和第二 电容充电以重置第一电压输入端的电压； 在第五阶段， 第一扫描端控制第一电压输入单元关闭， 控制数据信号输 入单元开启， 数据线向驱动控制端输入数据电压， 第二扫描端控制第二电压 输入单元关闭， 第二电容辆合使得第一电压输入端的电压跳变；
在第六阶段， 第一扫描端控制第一电压输入单元开启， 控制数据信号输 入单元关闭， 第二扫描端控制第二电压输入单元开启， 驱动控制端、 第一电 压输入端、 第二电压输入端驱动第二发光单元发光。
9、 根据权利要求 8所述的驱动方法， 其特征在于，
在第一阶段， 第一开关晶体管、 第二驱动晶体管截止， 第二开关晶体管、 第三开关晶体管及第一驱动晶体管导通；
在第二阶段， 第一开关晶体管及第三开关晶体管截止， 第二开关晶体管 导通， 第一驱动晶体管及第二驱动晶体管断路；
在第三阶段， 第一开关晶体管、 第三开关晶体管、 第一驱动晶体管导通、 第二开关晶体管及第二驱动晶体管截止；
在第四阶段， 第一开关晶体管、 第一驱动晶体管截止， 第二开关晶体管、 第三开关晶体管及第二驱动晶体管导通；
在第五阶段， 第一开关晶体管、 第三开关晶体管管截止， 第二开关晶体 管导通， 第一驱动晶体及第二驱动晶体管断路；
在第六阶段，第一开关晶体管、第三开关晶体管及第二驱动晶体管开启， 第二开关晶体管、 第一驱动晶体管截止。
10、 根据权利要求 9所述的驱动方法， 其中，
在第一阶段到第三阶段中， 所述第一电压端的第一输入电压处于第一电 平， 所述第二电压端的第二输入电压处于第二电平； 以及
在第四阶段到第六阶段中， 所述第一电压段的第一输入电压处于第二电 平， 所述第二电压端的第二输入电压处于第一电平。
11、 根据权利要求 10所述的驱动方法， 其中，
在第一阶段中， 所述第一电容和第二电容沿第一方向充电以将第一电压 输入端的电压重置至第一值； 以及
在第四阶段中， 所述第一电容和第二电容沿与第一方向相反的方向充电 以将第一电压输入端的电压重置至第二值。
PCT/CN2014/083194 2013-10-31 2014-07-29 交流驱动的像素电路、驱动方法及显示装置 WO2015062318A1 (zh)

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