WO2015000245A1 - 像素电路及其驱动方法、显示面板及显示装置 - Google Patents

像素电路及其驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2015000245A1
WO2015000245A1 PCT/CN2013/086461 CN2013086461W WO2015000245A1 WO 2015000245 A1 WO2015000245 A1 WO 2015000245A1 CN 2013086461 W CN2013086461 W CN 2013086461W WO 2015000245 A1 WO2015000245 A1 WO 2015000245A1
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Prior art keywords
circuit
light
emitting device
sub
driving
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PCT/CN2013/086461
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English (en)
French (fr)
Inventor
祁小敬
谭文
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/366,184 priority Critical patent/US9496293B2/en
Publication of WO2015000245A1 publication Critical patent/WO2015000245A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of organic light emitting display technologies, and in particular, to a pixel circuit, a driving method thereof, a display panel, and a display device. Background technique
  • Organic light-emitting display devices have attracted much attention due to their low power consumption, high brightness, low cost, wide viewing angle, and fast response speed, and have been widely used in the field of organic light-emitting technology.
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • the active driving OLED is also called an active matrix OLED (AMOLED), and the light emitting device in each pixel unit is driven to emit light through a pixel circuit and a power line loaded with a DC power supply voltage signal (V dd or V ss ).
  • the pixel circuit includes: a driving transistor T1, a capacitor C1, a switching transistor T2; a first end of the capacitor C1 and a driving transistor T1 The gate is connected, the second end is connected to the low-level reference voltage source V ss ; the drain of the switching transistor T2 is connected to the gate of the driving transistor T1, and the gate is connected to the gate signal source V Scan , the source and the data signal source V Data is connected; the source of the driving transistor T1 is connected to the high-level reference voltage source V DD , the drain is connected to the anode of the light-emitting device D1 , and the cathode of the light-emitting device D1 is connected to the low-level reference voltage source V ss .
  • the gate voltage of the signal source output signal V Scan the switching transistor T2 is turned on, the data signal source V data where the branch is turned on and the capacitor C1, the output data signal source V Data Data
  • the signal is loaded to the first end of the capacitor C1 to charge the capacitor C1; the illumination device D1 is driven to emit light, the gate signal source VScan outputs a voltage signal to turn off the switching transistor T2, and the data signal source V Data and the capacitor C1 are disconnected, the capacitor The C1 discharges to drive the light-emitting device D1 to emit light.
  • the pixel circuit provided by the prior art only includes a driving transistor and a light emitting device connected to the driving transistor.
  • the driving transistor in the pixel circuit drives the light emitting device to emit light;
  • the AMOLED display drives the OLED light to be a DC driving , long time DC drive
  • the electric field corresponding to the voltage causes the internal ion of the OLED to be polarized, so that the OLED forms a built-in electric field, thereby increasing the threshold voltage of the OLED, greatly reducing the luminous efficiency of the OLED, and shortening the lifetime of the OLED. Lifetime is an important factor that restricts the widespread use of organic light-emitting display devices, especially large-sized, high-brightness organic light-emitting display devices. Summary of the invention
  • a pixel circuit, a driving method thereof, a display panel and a display device are provided for improving the life of a light emitting device in a display device.
  • a pixel circuit provided by an embodiment of the present invention includes: a charging sub-circuit, a capacitor, a first driving sub-circuit, and a second driving sub-circuit;
  • the first end of the capacitor is connected to the first end of the first driving sub-circuit and the second driving sub-circuit, and the second end of the capacitor is connected to the charging sub-circuit;
  • a second end of the first driving sub-circuit is connected to the first light-emitting device, and a second end of the second driving sub-circuit is connected to the second light-emitting device, wherein the first driving sub-circuit flows into the first light-emitting device
  • the driving current is opposite to a driving current flowing from the second driving sub-circuit into the second light emitting device;
  • the charging sub circuit is configured to charge the capacitor, and the capacitor discharges to cause the first driving sub circuit to drive the first light emitting device to emit light Or causing the second driver circuit to drive the second light emitting device to emit light.
  • the first driving subcircuit includes an n-type driving transistor
  • the second driving sub-circuit includes a p-type driving transistor
  • the gate of the n-type driving transistor is connected to the first end of the capacitor, the source is connected to a first reference voltage source capable of providing an alternating current signal, and the drain is connected to the cathode of the first light emitting device, the first light emitting
  • the anode of the device is coupled to a second reference voltage source that provides an alternating current signal;
  • a gate of the p-type driving transistor is connected to the first end of the capacitor; a source is connected to the first reference voltage source, a drain is connected to an anode of the second light emitting device, and a cathode and a second light emitting device are connected The second reference voltage source is connected;
  • a second end of the capacitor is coupled to the charging subcircuit and to the first reference voltage source.
  • the charging subcircuit comprises:
  • a first gate signal source a data signal source, and a first switching transistor
  • the drain of the first switching transistor is connected to the data signal source, the source is connected to the second end of the capacitor, and the gate is connected to the first gate signal source;
  • the first gate signal source is configured to control the first switching transistor to be turned on, such that the data signal source is connected to a branch where the capacitor is located, and the data signal source charges the capacitor.
  • the method further includes a first compensation sub-circuit connected to the first driving sub-circuit, and a second compensation sub-circuit connected to the second driving sub-circuit;
  • the first compensation subcircuit includes a second switching transistor
  • the second compensation subcircuit includes a third switching transistor
  • the source of the second switching transistor is connected to the gate of the n-type driving transistor, the drain is connected to the drain of the n-type driving transistor, and the gate is connected to the second gate signal source;
  • the third switching transistor has a source connected to the gate of the p-type driving transistor, a drain connected to the drain of the p-type driving transistor, and a gate connected to the second gate signal source.
  • the method further includes controlling a fourth switching transistor connected between the first light emitting device and the second light emitting device and the second reference voltage source, the gate of the fourth switching transistor being connected to the charging control signal source, the source a pole connected to the anode of the first light emitting device and a cathode of the second light emitting device, and a drain connected to the second reference voltage source, wherein the charge control signal source is used to control the conduction of the fourth switching transistor cutoff.
  • the method further includes: a fifth switching transistor that controls the capacitor to be connected to the first reference voltage source;
  • the gate of the fifth switching transistor is connected to the third gate signal source, the source is connected to the first reference voltage source, and the drain is connected to the second end of the capacitor;
  • the third gate signal source is configured to control the fifth switching transistor to be turned on and off.
  • the first switching transistor, the second switching transistor, and the third switching transistor are n-type transistors, and the fifth switching transistor is a p-type transistor; or
  • the first switching transistor, the second switching transistor, and the third switching transistor are p-type transistors, and the fifth switching transistor is an n-type transistor;
  • the first gate signal source, the second gate signal source, and the third gate signal source are the same gate signal source.
  • the embodiment of the invention further provides a display panel comprising a plurality of pixel units arranged in a matrix surrounded by a gate line and a data line, each pixel unit including a pixel circuit and a first connection with the pixel circuit a light emitting device and a second light emitting device;
  • the pixel circuit is the pixel circuit
  • the charging sub-circuits in the pixel circuits of the same row are connected to the same gate line, and the charging sub-circuits in the pixel circuits of the same column are connected to the same data line; in one frame of image display, in Before the first driving sub-circuit and the second driving sub-circuit respectively drive the first light-emitting device to emit light and the second light-emitting device to emit light, the charging sub-circuit charges the capacitor through the data line and the gate line.
  • the drain of the first switching transistor is connected to the data signal source through the data line, and the gate is connected to the first gate signal source through the gate line;
  • the gate signal source and the data signal source charge the capacitor through a gate line and a data line, respectively.
  • Embodiments of the present invention provide a display device including the display panel.
  • An embodiment of the present invention provides a method for driving the foregoing pixel circuit, including:
  • the first driving sub-circuit and the second driving sub-circuit respectively drive the first light-emitting device to emit light and the second light-emitting device to emit light respectively under the control of timing;
  • the charging sub-circuit charges the capacitor before the first driving sub-circuit drives the first light-emitting device to emit light, and the capacitor discharges to cause the first driving sub-circuit to drive the first light-emitting device to emit light, or to make the second driving The sub-circuit drives the second light emitting device to emit light.
  • the branch of the first driving sub-circuit is disconnected, and the second driving sub-circuit is located
  • the branch circuit is turned on, and the second driving sub circuit drives the second light emitting device to emit light
  • the first driving sub-circuit drives the first light emitting device to emit light.
  • the invention provides two first light-emitting devices and a second light-emitting device connected in parallel in each pixel region, the working currents of the first light-emitting device and the second light-emitting device are opposite in direction, and pass through the first driving sub-circuit and the second driving The sub-circuits respectively drive the first light emitting device and the second light emitting device to emit light.
  • the first light-emitting device and the second light-emitting device alternately emit light, which can increase the life of each light-emitting device.
  • FIG. 1 is a schematic structural view of a conventional pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is a third schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram of the operation of the pixel circuit shown in FIG. 5 according to an embodiment of the present invention
  • FIG. 7 is an image with a reset function corresponding to the first driving sub-circuit according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a pixel circuit having a charging function corresponding to a first driving sub-circuit according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a pixel circuit having a function of driving a light emitting device according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a pixel circuit having a reset function corresponding to a second driving sub-circuit according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a pixel circuit having a charging function corresponding to a second driving sub-circuit according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a pixel circuit having a function of driving a light emitting device corresponding to a second driving sub-circuit according to an embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of an organic light emitting display panel according to an embodiment of the present invention. detailed description
  • the source of the transistor mentioned in the embodiment of the present invention may be the drain of the transistor, and the drain of the transistor is also Can be the source of the transistor.
  • a pixel circuit, a driving method thereof, a display panel and a display device are provided for improving the life of a light emitting device in a display device and improving the uneven display of the light emitting device.
  • each pixel unit includes a pixel circuit.
  • the present invention provides two first driving sub-circuits and a second driving sub-circuit connected in parallel in each pixel circuit, and the two driving sub-circuits respectively drive the first light-emitting device and the second light-emitting device respectively connected to each other at different time periods
  • the device emits light in turn; for example, in a frame image display time t, the first light-emitting device is driven to emit light in the first (1/2) t time, and the second light-emitting device is driven to emit light in the second (1/2) t time.
  • the life of the light emitting device provided by the present invention is at least doubled.
  • the charging sub-circuit is configured to charge the capacitor before the first driving sub-circuit and the second driving sub-circuit respectively drive the first light emitting device and the second light emitting device to emit light, When the capacitor is discharged, one of the first driving sub-circuit and the second driving sub-circuit drives the light-emitting device connected thereto to emit light.
  • a pixel circuit includes: a charging sub-circuit 1, a capacitor Cst, a first driving sub-circuit 2, and a second driving sub-circuit 3.
  • a first end (A end) of the capacitor Cst is connected to the first end of the first driving sub-circuit 2 and the second driving sub-circuit 3, and a second end (B end) of the capacitor Cst is connected to the charging sub-circuit 1;
  • the second end of the sub-circuit 2 is connected to the first light-emitting device D1
  • the second end of the second driving sub-circuit 3 is connected to the second light-emitting device D2, wherein the driving of the first light-emitting device D1 through the first driving sub-circuit 2 L and opposing currents through the drive current of the second driving circuit into the second sub-light-emitting device 1 in the second direction D2; segment 2 with arrows showing the direction of the driving current of FIG.
  • the charging sub-circuit 1 is for charging the capacitor Cst, and the capacitor Cst is discharged such that the first driving sub-circuit 2 drives the first light-emitting device D1 to emit light, or causes the second driving sub-circuit 3 to drive the second light-emitting device D2 to emit light.
  • the illuminating device provided by the embodiment of the present invention may be an OLED or other organic electroluminescent device, and the like, which is not specifically limited.
  • the pixel circuit includes: a charging sub-circuit 1, a first driving sub-circuit 2 and a second driving sub-circuit 3 connected to the charging sub-circuit 1; the first driving sub-circuit 2 is connected to the first light-emitting device D1; The driving sub-circuit 3 is connected to the second light emitting device D2;
  • the first driving sub-circuit 2 includes: an n-type driving transistor Tn; the second driving sub-circuit 3 includes: a p-type driving transistor ⁇ ;
  • the gate of the n-type driving transistor Tn is connected to the first end (terminal) of the capacitor Cst, and the source is connected to the output end of the first reference voltage source 11 that can provide an alternating current signal;
  • the gate of the p-type driving transistor Tp is connected to the first end (A end) of the capacitor Cst, the source is connected to the output end of the first reference voltage source 11, the drain is connected to the anode of the second light emitting device D2, and the second light is emitted.
  • a cathode of device D2 is coupled to an output of a second reference voltage source 12;
  • the second end (B terminal) of the capacitor Cst is connected to the output end of the first reference voltage source 11;
  • the charging sub-circuit 1 is connected to the second end (B end) of the capacitor Cst;
  • the charging sub-circuit 1 is used to drive the first driving sub-circuit 2 and the second driving sub-circuit 3, respectively.
  • a light emitting device D1 and a second light emitting device D2 input a data signal to the capacitor Cst before the light is emitted;
  • the first driving sub circuit 2 and the second driving sub circuit 3 are configured to respectively drive the first light emitting device D1 and the second light after discharging the capacitor Cst Device D2 illuminates.
  • the first light emitting device D1 and the second light emitting device D2 alternately emit light, and the lifetimes of the first light emitting device D1 and the second light emitting device D2 are at least doubled.
  • the first driving sub-circuit 2 and the second driving sub-circuit 3 share the first reference voltage source 11 and the second reference voltage source 12; since the first driving sub-circuit 2 and the second driving sub-circuit 3 Working at different time periods, the first reference voltage source 11 and the second reference voltage source 12 operate over time, and the structure of the circuit can be collapsed. In a specific implementation, only the high and low states of the output voltages of the first reference voltage source 11 and the second reference voltage source 12 are switched, so that the first driving sub-circuit 2 and the second driving sub-circuit 3 are alternately operated.
  • the light emitting device respectively connected to the first driving sub circuit and the second driving sub circuit is not limited to one, and the first light emitting device and the second light emitting device may be connected in series with each other.
  • the light-emitting devices connected in parallel are connected, and are not specifically limited herein.
  • the first driving sub-circuit and the second driving sub-circuit share a capacitor Cst, and the structure of the circuit can be reduced.
  • the capacitance Cst is not limited to one, and is not specifically limited herein.
  • the high voltage of the voltage V DS output by the first reference voltage source 11 is V dd
  • the low level voltage is V ss
  • the high level voltage of the reference voltage V SD outputted by the second reference voltage source 12 is V dd
  • the low level voltage is V ss .
  • V dd is a positive value greater than zero, and the value of V ss can be zero or a negative value less than zero.
  • the branch of the second driving sub-circuit 3 when the first reference voltage source 11 outputs a high level voltage and the second reference voltage source 12 outputs a low level voltage, the branch of the second driving sub-circuit 3 is turned on, and the branch of the first driving sub-circuit 2 is open.
  • the branch of the second driving sub-circuit 3 is disconnected, and the branch of the first driving sub-circuit 2 is turned on.
  • the charging sub-circuit 1 shown in FIG. 2 or FIG. 3 includes: a data signal source 13, a first gate signal source 14, and a first switching transistor T1 connected to the data signal source 13 and the first gate signal source 14. .
  • the drain of the first switching transistor T1 is connected to the output end of the data signal source 13, the source is connected to the second end (B end) of the capacitor Cst, and the gate is connected to the output end of the first gate signal source 14;
  • the first gate signal source 14 is used to control the on and off of the first switching transistor T1 under the control of the timing, and the data signal source 13 is electrically connected to the first switching transistor T1 in the on state under the control of the timing.
  • the Cst writes the data signal.
  • the driving current of the present invention for driving the first light emitting device D1 and the driving light emitting device D2 is independent of the voltage V DS provided by the first reference voltage source 11 and the V SD provided by the second reference voltage source 12, avoiding V dd or V ss a change in current flowing through the light emitting device due to a voltage drop IR Drop caused by a load on the signal line; and a threshold voltage ⁇ ⁇ of the driving current and the n-type driving transistor Tn and a threshold value of the p-type driving transistor ⁇
  • the voltage ⁇ ⁇ 2 is independent, and the problem of uneven illumination of each pixel caused by the difference in threshold voltages of different driving transistors is avoided, and the pixel circuit further includes a compensation sub-circuit for solving the above problem.
  • the pixel circuit provided by the present invention further includes: a first compensation sub-circuit 4 connected to the first driving sub-circuit 2, and a second compensation sub-circuit 5 connected to the second driving sub-circuit 3.
  • the first compensating sub-circuit 4 includes a second switching transistor T2; the source of the second switching transistor T2 is connected to the gate of the n-type driving transistor Tn, and the drain is connected to the drain of the n-type driving transistor Tn, the gate and the second The outputs of the gate signal source 15 are connected.
  • the second compensating sub-circuit 5 includes a third switching transistor T3; the source of the third switching transistor T3 is connected to the gate of the p-type driving transistor Tp, and the drain is connected to the drain of the p-type driving transistor ⁇ , the gate and the second The outputs of the gate signal source 15 are connected.
  • the second switching transistor ⁇ 2 and the third switching transistor ⁇ 3 can be respectively connected to different gate signal sources (ie, respectively connected to mutually independent gate signal sources), and the second switching transistors ⁇ 2 and third are controlled by different gate signal sources.
  • the switching transistor ⁇ 3 is turned on or off, respectively.
  • first gate source 14 and the second gate source 15 may be the same gate source or different gate sources.
  • first gate signal source 14 and the second gate signal source 15 are the same gate signal source
  • the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor ⁇ 3 are the same type of transistors (for example, both are n-type or The p-type transistor);
  • the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 shown in FIG. 5 are all p-type transistors.
  • the pixel circuit further includes: a fourth switching transistor ⁇ 4 and a fifth switching transistor ⁇ 5 .
  • the gate of the fourth switching transistor T4 is connected to the output terminal of the charging control signal source 16, and the source is simultaneously connected to the anode of the first light emitting device D1 and the cathode of the second light emitting device D2, and the drain and the second reference voltage source 12 The outputs are connected.
  • the charge control signal source 16 controls the on and off of the fourth switching transistor T4 under the control of the timing.
  • the gate of the fifth switching transistor T5 is connected to the third gate signal source 17, the source is connected to the output terminal of the first reference voltage source 11, and the drain is connected to the second terminal (B terminal) of the capacitor Cst.
  • the third gate signal source 17 controls the on and off of the fifth switching transistor T5 under the control of the timing.
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 are the same gate signal source (ie, sharing a gate signal source);
  • the switching transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3 are n-type transistors, the fifth switching transistor ⁇ 5 is a p-type transistor; or the first switching transistor T1, the second switching transistor ⁇ 2, and the third switch
  • the transistor ⁇ 3 is a p-type transistor
  • the fifth switching transistor ⁇ 5 is an n-type transistor.
  • the charge control signal source 16 independently controls the on and off of the fourth switching transistor ⁇ 4.
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 are connected to the transistors through the gate lines.
  • the data signal source 13 is connected to the first switching transistor T1 through a data line.
  • the first driving sub-circuit 2 and the second driving sub-circuit 3 respectively drive the first light emitting device D1 to emit light and the second light emitting device D2 to emit light respectively under the control of timing;
  • the charging sub-circuit 1 charges the capacitor Cst, and when the capacitor Cst is discharged, causes the first driving sub-circuit 2 to drive the first light-emitting device D1 to emit light, or makes the second The driving sub circuit 3 drives the second light emitting device D2 to emit light.
  • first driving sub-circuit 2 and the second driving sub-circuit 3 respectively drive the first light emitting device D1 to emit light and the second light emitting device D2 to emit light respectively under the control of timing is described herein, the present invention is not limited thereto.
  • the second driving sub-circuit 3 and the first driving sub-circuit 2 respectively drive the second light-emitting device D2 to emit light and the first light-emitting device D1 to emit light respectively under the control of the timing, in the second driving sub-circuit 3, before driving the second light-emitting device D2 to emit light, the charging sub-circuit 1 charges the capacitor Cst, and when the capacitor Cst is discharged, causes the first driving sub-circuit 2 to drive the first light-emitting device D1 to emit light, or makes the second driver The circuit 3 drives the second light emitting device D2 to emit light.
  • the branch of the first driving sub-circuit 2 is disconnected, and the second driving The branch of the sub-circuit 3 is turned on, and the second driving sub-circuit 3 drives the second light-emitting device D2 to emit light;
  • the branch of the second driving sub-circuit 3 is disconnected, and the first driving sub-circuit 2 When the branch is turned on, the first driving sub-circuit 2 drives the first light emitting device D1 to emit light.
  • the controlling the first driving sub-circuit 2 to drive the first light emitting device D1 to emit light specifically includes: a reset phase, wherein the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switch The transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3 are turned on, the fifth switching transistor ⁇ 5 is turned off, the charging control signal source 16 controls the fourth switching transistor ⁇ 4 to be turned on; the first reference voltage source 11 outputs a low level, The two reference voltage sources 12 output a high level, so that the branches of the first light-emitting device D1, the n-type driving transistor Tn and the capacitor Cst are turned on, and the voltages output by the data signal source 13 and the second reference voltage source 12 are loaded to the capacitor Cst. At both ends, the voltage across the capacitor Cst is reset;
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor ⁇ 3 to be turned on, and fifth The switching transistor ⁇ 5 is turned off, and the charging control signal source 16 controls the fourth switching transistor ⁇ 4 to be turned off; the first reference voltage source 11 outputs a low level, and the second reference voltage source 12 outputs a high level, so that the n-type driving transistor Tn and the capacitor Cst are located When the branch is turned on, the voltage output from the data signal source 13 is loaded to one end of the capacitor Cst, and the capacitor Cst stores the data signal;
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switching transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3 to be turned off, and the fifth switching transistor ⁇ 5 is turned on
  • the charging control signal source 16 controls the fourth switching transistor ⁇ 4 to be turned on
  • the first reference voltage source 11 outputs a low level
  • the second reference voltage source 12 outputs a high level, so that the n-type driving transistor ⁇ , the capacitor Cst and The branch of the first light-emitting device D1 is turned on, the capacitor Cst is discharged, and the first driver circuit 2 drives the first light-emitting device D1 to emit light.
  • the controlling the second driving sub-circuit 3 to drive the second light emitting device D2 to emit light specifically includes: in a reset phase, the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switching transistor T1
  • the first reference voltage source 11 outputs a high level, the second reference The voltage source 12 outputs a low level, so that the branch of the second light emitting device D2, the p-type driving transistor Tp and the capacitor Cst are turned on, and the voltages output by the data signal source 13 and the first reference voltage source 11 are applied to both ends of the capacitor Cst. , the voltage across the capacitor Cst is reset;
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor ⁇ 3 to be turned on,
  • the five-switching transistor T5 is turned off, and the charging control signal source 16 controls the fourth switching transistor ⁇ 4 to be turned off;
  • the first reference voltage source 11 outputs a high level
  • the second reference voltage source 12 outputs a low level, so that the p-type driving transistor ⁇ and the capacitor Cst
  • the voltage output from the data signal source 13 is loaded to one end of the capacitor Cst, and the capacitor Cst stores the data signal;
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 respectively control the first switching transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3 to be turned off, and the fifth switching transistor ⁇ 5 leads
  • the charging control signal source 16 controls the fourth switching transistor ⁇ 4 to be turned on; the first reference voltage source 11 outputs a high level, and the second reference voltage source 12 outputs a low level, such that the p-type driving transistor ⁇ , the capacitor Cst, and the first The branch where the light-emitting device D1 is located is turned on, the capacitor Cst is discharged, and the second driver circuit 3 drives the second light-emitting device D2 to emit light.
  • the first gate signal source 14, the second gate signal source 15, and the third gate signal source 17 are the same gate signal source, and the output voltage signal is VScan .
  • the first switching transistor T1, the second switching transistor ⁇ 2, the third switching transistor ⁇ 3, and the fourth switching transistor ⁇ 4 are p-type transistors, and the fifth switching transistor ⁇ 5 is an n-type transistor as an example.
  • the n-type transistor turns on when the gate inputs a high-level voltage, and turns off when a low-level voltage is input.
  • the p-type transistor turns on when the gate inputs a low-level voltage, and turns off when a high-level voltage is input.
  • V dd be a positive value above GND and V ss be a negative value below GND.
  • FIG. 6 is a diagram showing a reset phase (a phase), a writing phase (b phase), and an illumination phase (c phase) corresponding to driving the first light emitting device D1 to emit light; and driving the second light emitting device D2 to emit light corresponding to Reset phase (d phase), write phase (e phase), and illuminating phase (f phase).
  • Phase a The reset phase.
  • the first gate signal source 14 in FIG. 5 outputs a voltage VScan at a low level
  • the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor are connected to the first gate signal source 14.
  • ⁇ 3 is turned on at a low level voltage
  • the fifth switching transistor ⁇ 5 connected to the third gate signal source 17 is turned off (ie, turned off).
  • the second switching transistor ⁇ 2 is turned on, and the n-type driving transistor connected to the second switching transistor ⁇ 2
  • the gate and drain of ⁇ n are turned on, and at this time, the n-type drive transistor ⁇ n is equivalent to one diode.
  • Third The switching transistor T3 is turned on, and the gate and the drain of the p-type driving transistor ⁇ connected to the third switching transistor ⁇ 3 are turned on. At this time, the p-type driving transistor ⁇ is equivalent to one diode.
  • the voltage V EM output from the charge control signal source 16 is at a low level, and the fourth switching transistor T4 connected to the charge control signal source 16 is turned on.
  • the first reference voltage source 11 outputs a low level voltage V ss
  • the second reference voltage source 12 outputs a high level voltage V dd .
  • the p-type driving transistor Tp is turned off, and the branch of the p-type driving transistor ⁇ is broken.
  • the n-type driving transistor ⁇ is turned on, and the branch of the n-type driving transistor ⁇ is turned on.
  • the data signal source 13 outputs a low level data voltage signal V Data .
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit structure shown in Fig. 7.
  • the branch of the first light emitting device D1, the n-type driving transistor Tn, and the capacitor Cst and the data signal source 13 are turned on.
  • the voltage V Data of the data signal source 13 and the voltage V DD of the second reference voltage source 12 are respectively applied to both ends of the capacitor Cst, and the voltage across the capacitor Cst is V DD -V Data .
  • Stage b Write phase.
  • the first gate signal source 14 in FIG. 5 outputs a voltage VScan at a low level
  • the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor are connected to the first gate signal source 14.
  • ⁇ 3 is turned on
  • the fifth switching transistor ⁇ 5 connected to the third gate signal source 17 is turned off.
  • the second switching transistor ⁇ 2 turns on the gate and drain of the n-type driving transistor Tn, and the n-type driving transistor Tn is equivalent to one diode.
  • the voltage V EM output from the charge control signal source 16 is at a high level, and the fourth switching transistor T4 connected to the charge control signal source 16 is turned off.
  • the output voltage V DS of the first reference voltage source 11 is a low level voltage V ss
  • the output voltage V SD of the second reference voltage source 12 is a high level voltage V dd .
  • the branch of the first reference voltage source ll, the n-type driving transistor Tn and the data signal source 13 is turned on.
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit structure shown in Fig. 8.
  • the threshold voltage between the pole and the source, the voltage across the capacitor Cst is V ss +V thl -V Data .
  • the threshold voltage ⁇ ⁇ of the data signal V Data and the n-type driving transistor Tn is written in the capacitor Cst.
  • Stage c Illumination stage.
  • the first gate signal source 14 shown in FIG. 5 outputs a voltage VScan at a high level, and the first switching transistor T1, the second switching transistor ⁇ 2, and the third switch are connected to the first gate signal source 14.
  • the transistor ⁇ 3 is turned off, and the fifth switching transistor ⁇ 5 connected to the third gate signal source 17 (the third gate signal source 17 and the first gate signal source 14 are the same signal source) is turned on.
  • Charging output voltage control signal V EM source 16 is low, the charge control signal 16 is connected to a source of the fourth switching transistor T4 is turned on.
  • the output voltage V DS of the first reference voltage source 11 is a low level voltage V ss
  • the output voltage V SD of the second reference voltage source 12 is a high level voltage V dd .
  • the capacitor Cst is disconnected from the branch where the data signal source 13 is located, and the branch of the capacitor Cst, the n-type driving transistor Tn and the first light-emitting device D1 is turned on.
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit structure shown in Fig. 9.
  • the second terminal of the capacitor Cst in FIG. 9 connected to the first reference voltage source 11 (output low voltage V ss), a first end connected to the n-type driving transistor Tn of the gate, the n-type driving transistor Tn Gate voltage
  • the source voltage V S V SS .
  • the drain-source current, V gs is the voltage between the gate and the source of the n-type driving transistor Tn, which is a structural parameter. This value is relatively stable in the same structure, and the ⁇ ⁇ ⁇ -type driving transistor (V gs -V thl ) 2 Get A TA ) 2 .
  • the drain-source current i dn flowing through the n-type driving transistor Tn is only related to the voltage signal v Data supplied from the data signal source 13 regardless of ⁇ ⁇ and v dd . That is, the pixel circuit has a function of compensating ⁇ ⁇ and V dd .
  • the drain-source current i dn drives the first light-emitting device D1 to emit light, and the current flowing through the D1 is not caused by the unevenness of the threshold voltage V thl of the n-type driving transistor Tn due to the manufacturing process of the backplane, and the current is not The current change caused by the IR Drop of V dd due to the load on the V dd signal line.
  • the timing chart of each signal source in the pixel circuit is the same as the timing chart for driving the first light emitting device D1 to emit light, except that the first reference voltage source 11
  • the output voltage V DS is switched from the low level voltage V ss to the high level voltage V dd
  • the output voltage V SD of the second reference voltage source 12 is switched from the high level voltage V dd to the low level voltage V ss .
  • Stage d Reset phase.
  • the first gate signal source 14 in FIG. 5 outputs a voltage VScan at a low level, and the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor are connected to the first gate signal source 14. ⁇ 3 is turned on, and the fifth switching transistor ⁇ 5 is turned off.
  • the third switching transistor ⁇ 3 is turned on, and the gate and the drain of the p-type driving transistor ⁇ connected to the third switching transistor ⁇ 3 are turned on. At this time, the p-type driving transistor ⁇ is equivalent to the diode.
  • the voltage V EM output from the charge control signal source 16 is at a low level, and the fourth switching transistor T4 connected to the charge control signal source 16 is turned on.
  • the data signal source 13 outputs a data voltage signal of V Data .
  • the first reference voltage source 11 outputs a high level voltage V dd
  • the second reference voltage source 12 outputs a low level voltage V ss .
  • the branch of the n-type driving transistor Tn is open.
  • the branch of the p-type driving transistor ⁇ , the second illuminating device D2, and the data signal source 13 is turned on.
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit configuration shown in Fig. 10.
  • the voltage V Data output from the data signal source 13 and the voltage V ss output from the second reference voltage source 12 are applied across the capacitor Cst, and the voltage across the capacitor Cst is V ss -V Data .
  • Stage e Write phase.
  • the first gate signal source 14 in FIG. 5 outputs a voltage VScan at a low level, and the first switching transistor T1, the second switching transistor ⁇ 2, and the third switching transistor are connected to the first gate signal source 14. ⁇ 3 is turned on, and the fifth switching transistor ⁇ 5 is turned off;
  • the third switching transistor ⁇ 3 turns on the gate and drain of the p-type driving transistor ⁇ , and the p-type driving transistor ⁇ is equivalent to a diode.
  • the voltage V EM output from the charge control signal source 16 is at a high level, and the fourth switching transistor T4 connected to the charge control signal source 16 is turned off.
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit configuration shown in Fig. 11.
  • the capacitor Cst is charged by the p-type driving transistor Tp until the p-type driving transistor ⁇ is turned off. At this time, the voltage between the gate and the source of the p-type driving transistor Tp is the threshold voltage ⁇ ⁇ 2 of the p-type driving transistor Tp, and the two ends of the capacitor Cst The voltage is V ss +Vth 2 -V Data . At this time, the data signal V Data and the threshold voltage V th2 of the p-type driving transistor Tp are written in the capacitance Cst.
  • Stage f Light stage. As shown in FIG. 6, the first gate signal source 14 shown in FIG. 5 outputs a voltage VScan at a high level, and the first switching transistor T1, the second switching transistor ⁇ 2, and the third switch are connected to the first gate signal source 14. The transistor ⁇ 3 is turned off, and the fifth switching transistor ⁇ 5 is an n-type transistor which is turned on at a high level voltage.
  • Charging output voltage control signal V EM source 16 is low, the charge control signal 16 is connected to a source of the fourth switching transistor T4 is turned on.
  • the output voltage V DS of the first reference voltage source 11 is a high level voltage V dd
  • the output voltage V SD of the second reference voltage source 12 is a low level voltage V ss .
  • the pixel circuit shown in Fig. 5 is equivalent to the circuit configuration shown in Fig. 12.
  • the second end of the capacitor Cst is connected to the first reference voltage source 11 (output high level signal), the first end is connected to the gate of the P-type driving transistor Tp, and the gate of the p-type driving transistor ⁇
  • the voltage V g V dd + V ss + Vth 2 - V Data
  • the source voltage V s V dd
  • ⁇ ⁇ 2 is the threshold voltage of the p-type driving transistor ⁇ ⁇
  • the drain-source current i dp flowing through the p-type driving transistor Tp is only related to the data signal source 13 H0 ⁇ J voltage signal Voata, and is independent of Vth2 and dd.
  • the leakage/idp drives the second light-emitting device D2 to emit light, and the current flowing through D2 is not caused by the unevenness of the threshold voltage ⁇ ⁇ 2 of the p-type driving transistor Tp due to the manufacturing process of the backplane, nor is it due to V The change in current caused by the IR Drop of V dd caused by the load on the dd signal line.
  • the embodiment of the present invention further provides a display panel.
  • the display panel includes: a plurality of gate lines distributed along the row direction, as shown in FIG. 13; Gl, G2 Gn;
  • Each pixel unit includes a pixel circuit 20 provided by an embodiment of the present invention and a first light emitting device D1 and a second light emitting device D2 connected to the pixel circuit 20;
  • the pixel circuits 20 located in the same row are connected to the same gate line, and the pixel circuits 20 located in the same column are connected to the same data line;
  • the charging sub-circuits in the pixel circuits of the same row are connected to the same gate line, and the charging sub-circuits in the pixel circuits of the same column are connected to the same data line; in one frame image display stage, the first driver The charging sub-circuit charges the capacitor through the data line and the gate line before the circuit and the second driving sub-circuit respectively drive the first light-emitting device to emit light and the second light-emitting device to emit light.
  • a drain of the first switching transistor in the charging sub-circuit is connected to the data signal source through a data line, and a gate is connected to the first gate signal source through the gate line; the gate signal source And the data signal source charges the capacitor through the gate line and the data line, respectively.
  • the embodiment of the invention further provides a display device comprising the above display panel.
  • the display device may be an organic electroluminescence display device such as an OLED panel, an OLED display, an OLED television or an electronic paper.
  • the first reference voltage source and the second reference voltage source, the first gate signal source, the data signal source, and the AC signal provided by the charge control signal source of the present invention vary in accordance with the timing.
  • the present invention provides a first light emitting device and a second light emitting device in each pixel region, the operating currents of the first light emitting device and the second light emitting device are opposite in direction, and are respectively driven by an n-type driving transistor and a p-type driving.
  • the transistor drives the illumination.
  • the first light emitting device and the second light emitting device alternately emit light in turn, so that the lifetime of the light emitting device is at least doubled.

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Abstract

一种像素电路及其驱动方法、显示面板及显示装置，用以提高像素电路的寿命。所述像素电路包括：充电子电路（1）、电容（CST）、第一驱动子电路（2）和第二驱动子电路（3）；所述电容（CST）的第一端与第一驱动子电路（2）和第二驱动子电路（3）的第一端相连，所述电容（CST）的第二端与所述充电子电路（1）相连；所述第一驱动子电路（2）的第二端与第一发光器件（D1）相连，所述第二驱动子电路（3）的第二端与第二发光器件（D2）相连，其中，第一驱动子电路（2）流入第一发光器件（D1）的驱动电流（I1）和第二驱动子电路（3）流入第二发光器件（D2）的驱动电流（I2）方向相反；所述充电子电路（1）用于为所述电容（CST）充电，所述电容（CST）放电时使得第一驱动子电路（2）驱动第一发光器件（D1）发光，或使得第二驱动子电路（3）驱动第二发光器件（D2）发光。

Description

像素电路及其驱动方法、 显示面板及显示装置 技术领域
本发明涉及有机发光显示技术领域， 尤其涉及一种像素电路及其驱动方 法、 显示面板及显示装置。 背景技术
有机发光显示器件因其具有低功耗、 高亮度、 低成本、 广视角， 以及响 应速度快等优点备受关注， 在有机发光技术领域已经得到广泛应用。
有机电致发光二极管 （ Organic Light Emitting Diode, OLED )是目前有 机发光领域应用较多的一种发光器件。 目前， OLED按照驱动方式可以分为 无源驱动和有源驱动两大类，即直接寻址和薄膜晶体管（ Thin Film Transistor, TFT ) 矩阵寻址两类。 其中， 有源驱动 OLED 也称为有源矩阵 OLED ( AMOLED ), 通过像素电路和加载直流电源电压信号 （Vdd或 Vss ) 的电源 线驱动每一个像素单元中的发光器件发光。
参见图 1 , 为现有驱动发光器件发光的像素电路结构示意图， 以 n型驱 动晶体管为例， 像素电路包括： 驱动晶体管 Tl、 电容 Cl、 开关晶体管 T2; 电容 C1的第一端与驱动晶体管 T1的栅极相连， 第二端与低电平参考电压源 Vss相连； 开关晶体管 T2的漏极与驱动晶体管 T1的栅极相连， 栅极与门信 号源 VScan相连， 源极与数据信号源 VData相连； 驱动晶体管 T1的源极与高电 平参考电压源 VDD相连， 漏极与发光器件 D1的阳极相连， 发光器件 D1的阴 极与低电平参考电压源 Vss相连。
在一帧图像显示阶段， 驱动发光器件 D1发光之前， 门信号源 VScan输出 电压信号使开关晶体管 T2导通， 数据信号源 Vdata与电容 C1所在支路接通， 数据信号源 VData输出数据信号加载到电容 C1的第一端，为电容 C1充电；驱 动发光器件 D1发光阶段， 门信号源 VScan输出电压信号使开关晶体管 T2截 止， 数据信号源 VData与电容 C1所在支路断路， 电容 C1放电， 驱动发光器件 D1发光。
现有技术提供的像素电路仅包含一个驱动晶体管和与该驱动晶体管相连 的发光器件， 在一帧图像显示阶段， 像素电路中的驱动晶体管驱动所述发光 器件发光； AMOLED显示器驱动 OLED发光属于直流驱动，长时间直流驱动 电压对应的电场造成 OLED内部离子极性化， 使得 OLED形成内建电场， 从 而使 OLED阈值电压增大， 大大降低了 OLED的发光效率， 缩短了 OLED寿 命。 寿命是制约有机发光显示装置， 尤其是大尺寸高亮度的有机发光显示装 置广泛应用的重要因素。 发明内容
本发明实施例提供的一种像素电路及其驱动方法、显示面板及显示装置， 用以提高显示装置中发光器件的寿命。
本发明实施例提供的一种像素电路包括： 充电子电路、 电容、 第一驱动 子电路和第二驱动子电路；
所述电容的第一端与第一驱动子电路和第二驱动子电路的第一端相连， 所述电容的第二端与所述充电子电路相连；
所述第一驱动子电路的第二端与第一发光器件相连， 所述第二驱动子电 路的第二端与第二发光器件相连， 其中， 从第一驱动子电路流入第一发光器 件的驱动电流和从第二驱动子电路流入第二发光器件的驱动电流方向相反； 所述充电子电路用于为所述电容充电， 所述电容放电时使得第一驱动子 电路驱动第一发光器件发光，或使得第二驱动子电路驱动第二发光器件发光。
较佳地， 所述第一驱动子电路包括 n型驱动晶体管， 所述第二驱动子电 路包括 p型驱动晶体管；
其中， 所述 n型驱动晶体管的栅极与所述电容的第一端相连， 源极与可 提供交流信号的第一参考电压源相连， 漏极与第一发光器件的阴极相连， 第 一发光器件的阳极与可提供交流信号的第二参考电压源相连；
所述 p型驱动晶体管的栅极与所述电容的第一端相连； 源极与所述第一 参考电压源相连， 漏极与第二发光器件的阳极相连， 第二发光器件的阴极与 所述第二参考电压源相连；
所述电容的第二端与所述充电子电路相连且与所述第一参考电压源相 连。
较佳地， 所述充电子电路包括：
第一门信号源、 数据信号源和第一开关晶体管；
所述第一开关晶体管的漏极与所述数据信号源相连， 源极与所述电容的 第二端相连， 栅极与所述第一门信号源相连； 所述第一门信号源用于控制所述第一开关晶体管导通， 使得所述数据信 号源与所述电容所在支路接通， 数据信号源向所述电容充电。
较佳地， 还包括与所述第一驱动子电路相连的第一补偿子电路， 和与所 述第二驱动子电路相连的第二补偿子电路；
所述第一补偿子电路包括第二开关晶体管；
所述第二补偿子电路包括第三开关晶体管；
其中， 所述第二开关晶体管的源极与所述 n型驱动晶体管的栅极相连， 漏极与 n型驱动晶体管的漏极相连， 栅极与第二门信号源相连；
所述第三开关晶体管的源极与 p型驱动晶体管的栅极相连， 漏极与 p型 驱动晶体管的漏极相连， 栅极与所述第二门信号源相连。
较佳地， 还包括控制所述第一发光器件和第二发光器件与第二参考电压 源之间接通的第四开关晶体管， 所述第四开关晶体管的栅极与充电控制信号 源相连， 源极与所述第一发光器件的阳极以及第二发光器件的阴极相连， 漏 极与所述第二参考电压源相连， 所述充电控制信号源用于控制所述第四开关 晶体管的导通与截止。
较佳地， 还包括： 控制所述电容与第一参考电压源接通的第五开关晶体 管；
所述第五开关晶体管的栅极与第三门信号源相连， 源极与所述第一参考 电压源相连， 漏极与所述电容的第二端相连；
所述第三门信号源用于控制所述第五开关晶体管导通与截止。
较佳地， 所述第一开关晶体管、 第二开关晶体管、 第三开关晶体管为 n 型晶体管， 所述第五开关晶体管为 p型晶体管； 或者
所述第一开关晶体管、第二开关晶体管、第三开关晶体管为 p型晶体管， 所述第五开关晶体管为 n型晶体管；
所述第一门信号源、 第二门信号源、 第三门信号源为同一门信号源。 本发明实施例还提供一种显示面板， 包括由栅线和数据线围设而成的多 个呈矩阵排列的像素单元， 每一像素单元中包括一个像素电路和与该像素电 路相连的第一发光器件和第二发光器件；
其中， 所述像素电路为上述像素电路；
位于同一行的像素电路中的充电子电路与同一条栅线相连， 位于同一列 的像素电路中的充电子电路与同一条数据线相连； 在一帧图像显示阶段， 在 所述第一驱动子电路和第二驱动子电路先后分别驱动第一发光器件发光和第 二发光器件发光之前， 所述充电子电路通过数据线和栅线为所述电容充电。
较佳地， 所述第一开关晶体管的漏极通过所述数据线与所述数据信号源 相连， 栅极通过所述栅线与所述第一门信号源相连；
所述门信号源和数据信号源分别通过栅线和数据线为所述电容充电。 本发明实施例提供一种显示装置， 包括所述显示面板。
本发明实施例提供一种驱动上述像素电路的方法， 包括：
在一帧图像显示阶段， 所述第一驱动子电路和第二驱动子电路在时序的 控制下先后分别驱动第一发光器件发光和第二发光器件发光；
在所述第一驱动子电路驱动第一发光器件发光之前， 所述充电子电路为 所述电容充电，所述电容放电时使得第一驱动子电路驱动第一发光器件发光， 或使得第二驱动子电路驱动第二发光器件发光。
较佳地， 当控制所述第一参考电压源输出高电平且所述第二参考电压源 为低电平时， 所述第一驱动子电路所在支路断路， 所述第二驱动子电路所在 支路接通， 第二驱动子电路驱动第二发光器件发光；
当控制所述第一参考电压源输出低电平且所述第二参考电压源为高电平 时， 所述第二驱动子电路所在支路断路， 所述第一驱动子电路所在支路接通， 第一驱动子电路驱动第一发光器件发光。
本发明通过在每一个像素区域设置两个相并联的第一发光器件和第二发 光器件， 第一发光器件和第二发光器件的工作电流方向相反， 且通过第一驱 动子电路和第二驱动子电路分别驱动第一发光器件和第二发光器件发光。 第 一发光器件和第二发光器件交替轮流发光， 可以提高每一发光器件的寿命。 附图说明
图 1为现有像素电路结构示意图；
图 2为本发明实施例提供的像素电路结构示意图之一；
图 3为本发明实施例提供的像素电路结构示意图之二；
图 4为本发明实施例提供的像素电路结构示意图之三；
图 5为本发明实施例提供的像素电路结构示意图之四；
图 6为本发明实施例提供的图 5所示的像素电路工作的时序图； 图 7为本发明实施例提供的与第一驱动子电路对应的具有复位功能的像 素电路结构示意图；
图 8为本发明实施例提供与第一驱动子电路对应的具有充电功能的像素 电路结构示意图；
图 9为本发明实施例提供的与第一驱动子电路对应的具有驱动发光器件 发光功能的像素电路结构示意图；
图 10 为本发明实施例提供的与第二驱动子电路对应的具有复位功能的 像素电路结构示意图；
图 11 为本发明实施例提供与第二驱动子电路对应的具有充电功能的像 素电路结构示意图；
图 12 为本发明实施例提供的与第二驱动子电路对应的具有驱动发光器 件发光功能的像素电路结构示意图；
图 13为本发明实施例提供的有机发光显示面板结构示意图。 具体实施方式
需要说明的是， 对于液晶显示领域的晶体管来说， 漏极和源极没有明确 的区别， 因此本发明实施例中所提到的晶体管的源极可以为晶体管的漏极， 晶体管的漏极也可以为晶体管的源极。
本发明实施例提供的一种像素电路及其驱动方法、显示面板及显示装置， 用以提高显示装置中发光器件的寿命， 以及改善发光器件发光显示不均匀的 问题。
在 AMOLED显示面板中， 包括由栅线和数据线围设而成的多个呈矩阵 分布的像素单元， 每一个像素单元包括一个像素电路。 本发明通过在每一个 像素电路中设置两个并联连接的第一驱动子电路和第二驱动子电路， 两个驱 动子电路分别在不同时间段驱动与各自相连的第一发光器件和第二发光器件 轮流发光； 例如， 在一帧图像显示时间 t内， 前（1/2 ) t时间内驱动第一发光 器件发光， 后 （1/2 ) t时间内驱动第二发光器件发光。
相比较在一个像素单元中设置一个发光器件的像素电路， 本发明提供的 发光器件的寿命至少提高一倍。 信号的写入阶段和发光阶段。 在第一驱动子电路和第二驱动子电路分别驱动 第一发光器件和第二发光器件发光之前， 充电子电路用于为所述电容充电， 当所述电容放电时， 所述第一驱动子电路和第二驱动子电路之一驱动与之相 连的发光器件发光。
以下将结合附图具体说明本发明提供的像素电路、显示面板及显示装置。 参见图 2, 本发明实施例提供的像素电路， 包括： 充电子电路 1、 电容 Cst、 第一驱动子电路 2和第二驱动子电路 3。
电容 Cst的第一端 (A端)与第一驱动子电路 2和第二驱动子电路 3的第一 端相连， 电容 Cst的第二端 (B端)与充电子电路 1相连； 第一驱动子电路 2的 第二端与第一发光器件 D1相连， 第二驱动子电路 3的第二端与第二发光器 件 D2相连， 其中， 经由第一驱动子电路 2流入第一发光器件 D1的驱动电流 L和经由第二驱动子电路流入第二发光器件 D2的驱动电流 12方向相反； 图 2 中带箭头的线段表示驱动电流的方向。 充电子电路 1用于为电容 Cst充电， 电容 Cst放电时使得第一驱动子电路 2驱动第一发光器件 D1发光，或使得第 二驱动子电路 3驱动第二发光器件 D2发光。
较佳地， 本发明实施例提供的发光器件可以为 OLED或其他有机电致发 光元件等， 本发明不作具体限定。
以下以发光器件为 OLED为例将具体说明图 2所示的像素电路结构。 参见图 3, 像素电路包括： 充电子电路 1、 与充电子电路 1相连的第一驱 动子电路 2和第二驱动子电路 3;第一驱动子电路 2与第一发光器件 D1相连； 第二驱动子电路 3与第二发光器件 D2相连；
第一驱动子电路 2包括： n型驱动晶体管 Tn; 第二驱动子电路 3包括： ρ型驱动晶体管 Τρ;
其中， η型驱动晶体管 Tn的栅极与电容 Cst的第一端 (Α端)相连， 源极 与可提供交流信号的第一参考电压源 11的输出端相连； 漏极与第一发光器件 D1的阴极相连， 第一发光器件 D1的阳极与可提供交流信号的第二参考电压 源 12的输出端相连；
p型驱动晶体管 Tp的栅极与电容 Cst的第一端 (A端)相连， 源极与第一 参考电压源 11的输出端相连； 漏极与第二发光器件 D2的阳极相连； 第二发 光器件 D2的阴极与第二参考电压源 12的输出端相连；
电容 Cst的第二端 (B端)与第一参考电压源 11的输出端相连；
充电子电路 1与电容 Cst的第二端 （B端）相连；
充电子电路 1用于在第一驱动子电路 2和第二驱动子电路 3分别驱动第 一发光器件 D1和第二发光器件 D2发光之前向电容 Cst输入数据信号； 第一驱动子电路 2和第二驱动子电路 3用于在电容 Cst放电后分别驱动 第一发光器件 D1和第二发光器件 D2发光。 第一发光器件 D1和第二发光器 件 D2交替发光，第一发光器件 D1和第二发光器件 D2的寿命至少提高一倍。
此外， 如图 3所示， 第一驱动子电路 2和第二驱动子电路 3共用第一参 考电压源 11和第二参考电压源 12; 由于第一驱动子电路 2和第二驱动子电 路 3在不同时间段工作， 第一参考电压源 11和第二参考电压源 12分时间工 作， 可以筒化电路的结构。 在具体实施时， 只需要切换第一参考电压源 11和 第二参考电压源 12输出电压的高低电平状态，即可实现第一驱动子电路 2和 第二驱动子电路 3交替工作。
需要说明的是， 本发明提供的像素电路， 与第一驱动子电路和第二驱动 子电路分别相连的发光器件不限于为一个， 第一发光器件和第二发光器件分 别可以与多个相互串联 /并联的发光器件相连， 这里不作具体限定。 第一驱动 子电路和第二驱动子电路共用一个电容 Cst, 可以筒化电路的结构， 其实电容 Cst不限于为一个， 在此不作具体限定。
参见图 3, 设第一参考电压源 11输出的电压 VDS的高电平电压为 Vdd, 低电平电压为 Vss。 设第二参考电压源 12输出的参考电压 VSD的高电平电压 为 Vdd, 低电平电压为 Vss。 Vdd为大于零的正值， Vss的值可以为零或者为小 于零的负值。
本发明当第一参考电压源 11输出高电平电压且第二参考电压源 12输出 低电平电压时， 第二驱动子电路 3所在支路接通， 第一驱动子电路 2所在支 路断路； 当第一参考电压源 11输出低电平电压且第二参考电压源 12输出高 电平电压时， 第二驱动子电路 3所在支路断路， 第一驱动子电路 2所在支路 接通。
参见图 4, 图 2或图 3所示的充电子电路 1包括： 数据信号源 13、 第一 门信号源 14, 以及与数据信号源 13和第一门信号源 14相连的第一开关晶体 管 Tl。
具体地， 第一开关晶体管 T1的漏极与数据信号源 13的输出端相连， 源 极与电容 Cst的第二端（B端）相连，栅极与第一门信号源 14的输出端相连； 第一门信号源 14用于在时序的控制下控制第一开关晶体管 T1的导通与截止， 数据信号源 13在时序的控制下通过处于导通状态的第一开关晶体管 T1向电 容 Cst写入数据信号。
本发明为了实现驱动第一发光器件 D1和驱动发光器件 D2的驱动电流均 与第一参考电压源 11提供的电压 VDS和第二参考电压源 12提供的 VSD无关， 避免 Vdd或 Vss信号线上由于负载原因所导致的电压降 IR Drop而引起的流过 发光器件的电流变化；且为了实现所述驱动电流与 n型驱动晶体管 Tn的阈值 电压 νω和 ρ型驱动晶体管 Τρ的阈值电压 νώ2无关，避免不同驱动晶体管阈 值电压差异导致的各像素发光不均匀的问题， 该像素电路还包括解决上述问 题的补偿子电路。
参见图 5, 本发明提供的像素电路还包括： 与第一驱动子电路 2相连的 第一补偿子电路 4, 以及与第二驱动子电路 3相连的第二补偿子电路 5。
第一补偿子电路 4包括第二开关晶体管 T2; 第二开关晶体管 T2的源极 与 n型驱动晶体管 Tn的栅极相连， 漏极与 n型驱动晶体管 Tn的漏极相连， 栅极与第二门信号源 15的输出端相连。
第二补偿子电路 5包括第三开关晶体管 T3; 第三开关晶体管 T3的源极 与 p型驱动晶体管 Tp的栅极相连， 漏极与 ρ型驱动晶体管 Τρ的漏极相连， 栅极与第二门信号源 15的输出端相连。
当然， 第二开关晶体管 Τ2和第三开关晶体管 Τ3可以分别与不同的门信 号源相连（即分别与相互独立的门信号源相连）， 通过不同的门信号源控制第 二开关晶体管 Τ2和第三开关晶体管 Τ3分别导通或截止。
同理， 第一门信号源 14和第二门信号源 15可以为同一门信号源也可以 是不同的门信号源。 当第一门信号源 14和第二门信号源 15为同一门信号源 时， 第一开关晶体管 Tl、第二开关晶体管 Τ2和第三开关晶体管 Τ3为同一类 型的晶体管（例如均为 η型或 ρ型晶体管）； 图 5所示的第一开关晶体管 Tl、 第二开关晶体管 Τ2和第三开关晶体管 Τ3均为 ρ型晶体管。
参见图 5, 为了避免像素电路在写入阶段中第一参考电压源 11和第二参 考电压源 12对充电子电路 1的影响， 像素电路还包括： 第四开关晶体管 Τ4 和第五开关晶体管 Τ5。
第四开关晶体管 Τ4的栅极与充电控制信号源 16的输出端相连， 源极同 时与第一发光器件 D1的阳极以及第二发光器件 D2的阴极相连，漏极与第二 参考电压源 12的输出端相连。 充电控制信号源 16在时序的控制下控制第四 开关晶体管 Τ4的导通与截止。 第五开关晶体管 T5的栅极与第三门信号源 17相连， 源极与第一参考电 压源 11的输出端相连， 漏极与电容 Cst的第二端 （B端）相连。 第三门信号 源 17在时序的控制下控制第五开关晶体管 T5的导通与截止。
较佳地， 为了筒化电路结构， 所述第一门信号源 14、 第二门信号源 15、 第三门信号源 17为同一门信号源 （即共用一个门信号源）； 所述第一开关晶 体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3为 η型晶体管， 所述第五 开关晶体管 Τ5为 ρ型晶体管； 或者所述第一开关晶体管 Tl、 第二开关晶体 管 Τ2、第三开关晶体管 Τ3为 ρ型晶体管， 所述第五开关晶体管 Τ5为 η型晶 体管。
充电控制信号源 16独立控制第四开关晶体管 Τ4的导通与截止。
在具体实施过程中， 第一门信号源 14、 第二门信号源 15、 第三门信号源 17通过栅线与各晶体管相连。 数据信号源 13通过数据线与第一开关晶体管 T1相连。
以下将具体说明本发明实施例提供的像素电路驱动方法：
在一帧图像显示阶段， 所述第一驱动子电路 2和第二驱动子电路 3在时 序的控制下先后分别驱动第一发光器件 D1发光和第二发光器件 D2发光； 在所述第一驱动子电路 2驱动第一发光器件 D1发光之前， 所述充电子 电路 1为所述电容 Cst充电，所述电容 Cst放电时使得第一驱动子电路 2驱动 第一发光器件 D1发光,或使得第二驱动子电路 3驱动第二发光器件 D2发光。
尽管在这里描述了所述第一驱动子电路 2和第二驱动子电路 3在时序的 控制下先后分别驱动第一发光器件 D1发光和第二发光器件 D2发光的情况， 然而本发明不限于此， 还可以是： 第二驱动子电路 3和所述第一驱动子电路 2在时序的控制下先后分别驱动第二发光器件 D2发光和第一发光器件 D1发 光， 在所述第二驱动子电路 3驱动第二发光器件 D2发光之前， 所述充电子 电路 1为所述电容 Cst充电，所述电容 Cst放电时使得第一驱动子电路 2驱动 第一发光器件 D1发光,或使得第二驱动子电路 3驱动第二发光器件 D2发光。
较佳地，当控制所述第一参考电压源 11输出高电平且所述第二参考电压 源 12输出低电平时， 所述第一驱动子电路 2所在支路断路， 所述第二驱动子 电路 3所在支路接通， 第二驱动子电路 3驱动第二发光器件 D2发光；
当控制所述第一参考电压源 11输出低电平且所述第二参考电压源 12输 出高电平时， 所述第二驱动子电路 3所在支路断路， 所述第一驱动子电路 2 所在支路接通 , 第一驱动子电路 2驱动第一发光器件 D1发光。
所述控制第一驱动子电路 2驱动第一发光器件 D1发光， 具体包括： 复位阶段， 所述第一门信号源 14、 第二门信号源 15和第三门信号源 17 分别控制第一开关晶体管 Tl、第二开关晶体管 Τ2、第三开关晶体管 Τ3导通， 第五开关晶体管 Τ5截止， 充电控制信号源 16控制第四开关晶体管 Τ4导通； 第一参考电压源 11输出低电平、 第二参考电压源 12输出高电平， 使得第一 发光器件 Dl、 n型驱动晶体管 Tn和电容 Cst所在支路接通， 数据信号源 13 和第二参考电压源 12输出的电压加载到电容 Cst的两端， 电容 Cst两端的电 压复位；
写入阶段， 所述第一门信号源 14、 第二门信号源 15和第三门信号源 17 分别控制第一开关晶体管 Tl、第二开关晶体管 Τ2、第三开关晶体管 Τ3导通， 第五开关晶体管 Τ5截止， 充电控制信号源 16控制第四开关晶体管 Τ4截止； 第一参考电压源 11输出低电平、 第二参考电压源 12输出高电平， 使得 η型 驱动晶体管 Tn和电容 Cst所在支路接通， 数据信号源 13输出的电压加载到 电容 Cst的一端， 电容 Cst存储数据信号；
发光阶段， 所述第一门信号源 14、 第二门信号源 15和第三门信号源 17 分别控制第一开关晶体管 Tl、第二开关晶体管 Τ2、第三开关晶体管 Τ3截止， 第五开关晶体管 Τ5导通， 充电控制信号源 16控制第四开关晶体管 Τ4导通； 第一参考电压源 11输出低电平、 第二参考电压源 12输出高电平， 使得 η型 驱动晶体管 Τη、 电容 Cst和第一发光器件 D1所在支路接通， 电容 Cst放电， 第一驱动子电路 2驱动第一发光器件 D1发光。
所述控制第二驱动子电路 3驱动第二发光器件 D2发光， 具体包括： 复位阶段， 第一门信号源 14、 第二门信号源 15、 第三门信号源 17分别 控制第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3导通， 第 五开关晶体管 Τ5截止， 充电控制信号源 16控制第四开关晶体管 Τ4导通； 第一参考电压源 11输出高电平、 第二参考电压源 12输出低电平， 使得第二 发光器件 D2、 p型驱动晶体管 Tp和电容 Cst所在支路接通， 数据信号源 13 和第一参考电压源 11输出的电压加载到电容 Cst的两端， 电容 Cst两端的电 压复位；
写入阶段， 第一门信号源 14、 第二门信号源 15、 第三门信号源 17分别 控制第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3导通， 第 五开关晶体管 T5截止， 充电控制信号源 16控制第四开关晶体管 Τ4截止； 第一参考电压源 11输出高电平、 第二参考电压源 12输出低电平， 使得 ρ型 驱动晶体管 Τρ和电容 Cst所在支路接通， 数据信号源 13输出的电压加载到 电容 Cst的一端， 电容 Cst存储数据信号；
发光阶段， 第一门信号源 14、 第二门信号源 15、 第三门信号源 17分别 控制第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3截止， 第 五开关晶体管 Τ5导通， 充电控制信号源 16控制第四开关晶体管 Τ4导通； 第一参考电压源 11输出高电平、 第二参考电压源 12输出低电平， 使得 ρ型 驱动晶体管 Τρ、 电容 Cst和第一发光器件 D1所在支路接通， 电容 Cst放电， 第二驱动子电路 3驱动第二发光器件 D2发光。
以下将结合图 5所示的像素电路和图 6所示的像素电路工作的时序图， 具体说明本发明实施例提供的像素电路工作原理。
设第一门信号源 14、 第二门信号源 15、 第三门信号源 17为同一门信号 源， 输出电压信号为 VScan。
设充电控制信号源 16输出电压信号为 VEM。
以第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶体管 Τ3和第四 开关晶体管 Τ4为 ρ型晶体管， 第五开关晶体管 Τ5为 η型晶体管为例说明。
η 型晶体管在栅极输入高电平电压时导通， 输入低电平电压时截止； ρ 型晶体管在栅极输入低电平电压时导通， 输入高电平电压时截止。
设 Vdd为高于 GND的正值， Vss为低于 GND的负值。
以下将介绍像素电路驱动第一发光器件发光的工作原理。
图 6中， 示出了驱动第一发光器件 D1发光所对应的复位阶段（a阶段）、 写入阶段 ( b阶段 ), 以及发光阶段（ c阶段）； 驱动第二发光器件 D2发光所 对应的复位阶段 ( d阶段）、 写入阶段 ( e阶段）， 以及发光阶段 ( f阶段）。
a阶段： 复位阶段。
如图 6所示， 图 5中的第一门信号源 14输出电压 VScan为低电平， 与第 一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶 体管 Τ3在低电平电压下导通， 与第三门信号源 17 (第三门信号源 17与第一 门信号源 14是同一信号源）相连的第五开关晶体管 Τ5截止（即截止）。
第二开关晶体管 Τ2导通， 与第二开关晶体管 Τ2相连的 η型驱动晶体管
Τη的栅极和漏极接通， 此时， η型驱动晶体管 Τη等效于一个二极管。 第三 开关晶体管 T3导通， 与第三开关晶体管 Τ3相连的 ρ型驱动晶体管 Τρ的栅 极和漏极接通， 此时， ρ型驱动晶体管 Τρ等效于一个二极管。
充电控制信号源 16输出的电压 VEM为低电平， 与充电控制信号源 16相 连的第四开关晶体管 T4导通。
第一参考电压源 11输出低电平电压 Vss,第二参考电压源 12输出高电平 电压 Vdd。 p型驱动晶体管 Tp截止， ρ型驱动晶体管 Τρ所在支路断路。 η型 驱动晶体管 Τη导通， η型驱动晶体管 Τη所在支路接通。
数据信号源 13输出低电平数据电压信号 VData。
此时， 图 5所示的像素电路等效为图 7所示的电路结构。
第一发光器件 Dl、 n型驱动晶体管 Tn以及电容 Cst和数据信号源 13所 在支路接通。数据信号源 13的电压 VData和第二参考电压源 12的电压 VDD分 别加载到电容 Cst的两端， 电容 Cst两端的电压为 VDD-VData。
b阶段： 写入阶段。
如图 6所示， 图 5中的第一门信号源 14输出电压 VScan为低电平， 与第 一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶 体管 Τ3导通， 与第三门信号源 17 (第三门信号源 17与第一门信号源 14是 同一信号源 )相连的第五开关晶体管 Τ5截止。
第二开关晶体管 Τ2将 η型驱动晶体管 Tn的栅极和漏极接通， n型驱动 晶体管 Tn等效于一个二极管。
充电控制信号源 16输出的电压 VEM为高电平， 与充电控制信号源 16相 连的第四开关晶体管 T4截止。
第一参考电压源 11的输出电压 VDS为低电平电压 Vss, 第二参考电压源 12的输出电压 VSD为高电平电压 Vdd。
第一参考电压源 ll、n型驱动晶体管 Tn和数据信号源 13所在支路接通。 此时， 图 5所示的像素电路等效为图 8所示的电路结构。
电容 Cst通过 n型驱动晶体管 Tn放电直到 n型驱动晶体管 Tn截止， 此 时 n型驱动晶体管 Tn的栅极和源极之间的电压 Vgs=Vthl, νώ1是 n型驱动晶 体管 Tn的栅极和源极之间的阈值电压，电容 Cst两端的电压为 Vss+Vthl-VData。 此时， 数据信号 VData和 n型驱动晶体管 Tn的阈值电压 νω, 写入电容 Cst 中。
c阶段： 发光阶段。 如图 6所示， 图 5所示的第一门信号源 14输出电压 VScan为高电平， 与 第一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关 晶体管 Τ3截止， 与第三门信号源 17 (第三门信号源 17与第一门信号源 14 是同一信号源）相连的第五开关晶体管 Τ5导通。
充电控制信号源 16输出的电压 VEM为低电平， 与充电控制信号源 16相 连的第四开关晶体管 T4导通。
第一参考电压源 11的输出电压 VDS为低电平电压 Vss, 第二参考电压源 12的输出电压 VSD为高电平电压 Vdd。 电容 Cst与数据信号源 13所在支路断 路， 电容 Cst、 n型驱动晶体管 Tn和第一发光器件 D1所在支路接通。
此时， 图 5所示的像素电路等效为图 9所示的电路结构。
如图 9所示， 电容 Cst的第二端连接至第一参考电压源 11 (输出低电平 电压 Vss ), 第一端连接至 n型驱动晶体管 Tn的栅极， n型驱动晶体管 Tn的 栅极电压
Figure imgf000015_0001
源极电压 VS=VSS。 n型驱动晶体管 Tn的栅极和 源极之间的电压 Vgs=Vg-Vs=
Figure imgf000015_0002
由于 n型驱动晶体管 Tn工作于饱和状态，根据饱和状态电流特性可知 n 型驱动晶体管 Tn的漏源电流满足如下公式： idn= (Vgs-Vthl)2 ， 其中 ^为 n 型驱动晶体管 Tn的漏源电流， Vgs为 n型驱动晶体管 Tn的栅极和源极之间的 电压， 为结构参数， 相同结构中此数值相对稳定， νω η型驱动晶体管 (Vgs-Vthl)2 得到 ATA)2。
Figure imgf000015_0003
由此可知， 流经 n型驱动晶体管 Tn的漏源电流 idn仅与数据信号源 13 提供的电压信号 vData有关， 与 νω和 vdd无关。 即该像素电路具有补偿 νω 和 Vdd的功能。 该漏源电流 idn驱动第一发光器件 D1发光， 流经 D1的电流不 因背板制造工艺原因而造成的 n型驱动晶体管 Tn的阈值电压 Vthl不均匀所导 致的电流不同， 也不会因为 Vdd信号线上因负载原因所导致的 Vdd的 IR Drop 而引起的电流变化。
以下将介绍像素电路驱动第二发光器件 D2发光的工作原理。
驱动第二发光器件 D2发光时， 像素电路中的各信号源的时序图与驱动 第一发光器件 D1发光的时序图相同， 不同之处在于， 第一参考电压源 11的 输出电压 VDS由低电平电压 Vss切换为高电平电压 Vdd, 第二参考电压源 12 的输出电压 VSD由高电平电压 Vdd切换为低电平电压 Vss。
d阶段： 复位阶段。
如图 6所示， 图 5中的第一门信号源 14输出电压 VScan为低电平， 与第 一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶 体管 Τ3导通， 第五开关晶体管 Τ5截止。
第三开关晶体管 Τ3导通， 与第三开关晶体管 Τ3相连的 ρ型驱动晶体管 Τρ的栅极和漏极接通， 此时， ρ型驱动晶体管 Τρ等效于二极管。
充电控制信号源 16输出的电压 VEM为低电平， 与充电控制信号源 16相 连的第四开关晶体管 T4导通。
数据信号源 13输出数据电压信号为 VData。
第一参考电压源 11输出高电平电压 Vdd, 第二参考电压源 12输出低电 平电压 Vss。 n型驱动晶体管 Tn所在支路断路。 ρ型驱动晶体管 Τρ、 第二发 光器件 D2和数据信号源 13所在支路接通。
此时， 图 5所示的像素电路等效为图 10所示的电路结构。
数据信号源 13输出的电压 VData和第二参考电压源 12输出的电压 Vss加 载到电容 Cst两端， 电容 Cst两端的电压为 Vss-VData。
e阶段： 写入阶段。
如图 6所示， 图 5中的第一门信号源 14输出电压 VScan为低电平， 与第 一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关晶 体管 Τ3导通， 第五开关晶体管 Τ5截止；
第三开关晶体管 Τ3将 ρ型驱动晶体管 Τρ的栅极和漏极接通， ρ型驱动 晶体管 Τρ等效为二极管。
充电控制信号源 16输出的电压 VEM为高电平， 与充电控制信号源 16相 连的第四开关晶体管 T4截止。
此时， 图 5所示的像素电路等效为图 11所示的电路结构。
电容 Cst通过 p型驱动晶体管 Tp充电直到 ρ型驱动晶体管 Τρ截止， 此 时 ρ型驱动晶体管 Tp的栅极和源极之间的电压为 p型驱动晶体管 Tp的阈值 电压 νώ2, 电容 Cst两端的电压为 Vss+Vth2 -VData。 此时， 数据信号 VData和 p 型驱动晶体管 Tp的阈值电压 Vth2写入电容 Cst中。
f阶阶段： 发光阶段。 如图 6所示， 图 5所示的第一门信号源 14输出电压 VScan为高电平， 与 第一门信号源 14相连的第一开关晶体管 Tl、 第二开关晶体管 Τ2、 第三开关 晶体管 Τ3截止， 第五开关晶体管 Τ5为 η型晶体管， 在高电平电压下导通。
充电控制信号源 16输出的电压 VEM为低电平， 与充电控制信号源 16相 连的第四开关晶体管 T4导通。
第一参考电压源 11的输出电压 VDS为高电平电压 Vdd, 第二参考电压源 12的输出电压 VSD为低电平电压 Vss。
此时， 图 5所示的像素电路等效为图 12所示的电路结构。
如图 12所示， 电容 Cst的第二端连接至第一参考电压源 11 (输出高电平 信号）， 第一端连接至 P型驱动晶体管 Tp的栅极， ρ型驱动晶体管 Τρ的栅极 电压 Vg=Vdd+ Vss+ Vth2-VData, 源极电压 Vs=Vdd。 p型驱动晶体管 Tp的栅极和 源极之间的电压 Vgs=Vg-Vs= Vdd+Vss+Vth2-VData - Vdd =Vss+Vth2-VData。
由于 p型驱动晶体管 Tp工作于饱和状态，根据饱和状态电流特性可知 p 型驱动晶体管 Tp的漏源电流满足如下公式： idp=^(Vgs-Vth2)2， 其中 idp为 p 型驱动晶体管 Tp的漏源电流， Vgs为 p型驱动晶体管 Tp的栅极和源极之间的 电压， 为结构参数， 相同结构中此数值相对稳定， νώ2为 ρ型驱动晶体管 τΡ 的阈值电压， 将 vgs= νώ2-νθ3ΐ3 带入公式 idp= (Vgs-Vth 2)2得到 -VData )2。
Figure imgf000017_0001
由此可知， 流经 p型驱动晶体管 Tp的漏源电流 idp仅与数据信号源 13 H0^J电压信号 Voata有关, 与 Vth2和 dd无关。 该漏 电 / idp驱动第二发光 器件 D2发光，流经 D2的电流不因背板制造工艺原因而造成的 p型驱动晶体 管 Tp的阈值电压 νώ2不均匀所导致的电流不同， 也不会因为 Vdd信号线上因 负载原因所导致的 Vdd的 IR Drop而引起的电流变化。
本发明实施例还提供一种显示面板， 参见图 13, 所述显示面板包括： 多条沿行方向分布的栅线， 如图 13中所示的 Gl、 G2 Gn;
多条沿列方向分布的数据线， 如图 13中所示的 Dl、 D2 Dm; 相邻的两条栅线和数据线围设成的多个像素单元；
每一像素单元包括一个本发明实施例提供的像素电路 20 和与该像素电 路 20相连的第一发光器件 D1和第二发光器件 D2; 位于同一行的像素电路 20 与同一条栅线相连， 位于同一列的像素电路 20与同一条数据线相连；
位于同一行的像素电路中的充电子电路与同一条栅线相连， 位于同一列 的像素电路中的充电子电路与同一条数据线相连； 在一帧图像显示阶段， 在 所述第一驱动子电路和第二驱动子电路先后分别驱动第一发光器件发光和第 二发光器件发光之前， 所述充电子电路通过数据线和栅线为所述电容充电。
具体地， 所述充电子电路中的第一开关晶体管的漏极通过数据线与所述 数据信号源相连， 栅极通过所述栅线与所述第一门信号源相连； 所述门信号 源和数据信号源分别通过栅线和数据线为所述电容充电。
本发明实施例还提供一种显示装置， 包括上述显示面板。 该显示装置可 以为有机电致发光显示 OLED面板、 OLED显示器、 OLED电视或电子纸等 显示装置。
本发明第一参考电压源和第二参考电压源、第一门信号源、数据信号源， 以及充电控制信号源提供的交流信号按照时序的变化而变化。
综上所述， 本发明通过在每一个像素区域设置第一发光器件和第二发光 器件， 第一发光器件和第二发光器件的工作电流方向相反， 且分别通过 n型 驱动晶体管和 p型驱动晶体管驱动发光。 第一发光器件和第二发光器件交替 轮流发光， 使得发光器件的寿命至少提高一倍。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、 一种像素电路， 其特征在于， 包括： 充电子电路、 电容、 第一驱动子 电路和第二驱动子电路；
所述电容的第一端与第一驱动子电路和第二驱动子电路的第一端相连， 所述电容的第二端与所述充电子电路相连；
所述第一驱动子电路的第二端与第一发光器件相连， 所述第二驱动子电 路的第二端与第二发光器件相连， 其中， 从第一驱动子电路流入第一发光器 件的驱动电流和从第二驱动子电路流入第二发光器件的驱动电流方向相反； 所述充电子电路用于为所述电容充电， 所述电容放电时使得第一驱动子 电路驱动第一发光器件发光，或使得第二驱动子电路驱动第二发光器件发光。
2、 根据权利要求 1所述的像素电路， 其中， 所述第一驱动子电路包括 n 型驱动晶体管， 所述第二驱动子电路包括 p型驱动晶体管；
其中， 所述 n型驱动晶体管的栅极与所述电容的第一端相连， 源极与可 提供交流信号的第一参考电压源相连， 漏极与第一发光器件的阴极相连， 第 一发光器件的阳极与可提供交流信号的第二参考电压源相连；
所述 p型驱动晶体管的栅极与所述电容的第一端相连； 源极与所述第一 参考电压源相连， 漏极与第二发光器件的阳极相连， 第二发光器件的阴极与 所述第二参考电压源相连；
所述电容的第二端与所述充电子电路相连且与所述第一参考电压源相 连。
3、 根据权利要求 2所述的像素电路， 其中， 所述充电子电路包括： 第一门信号源、 数据信号源和第一开关晶体管；
所述第一开关晶体管的漏极与所述数据信号源相连， 源极与所述电容的 第二端相连， 栅极与所述第一门信号源相连；
所述第一门信号源用于控制所述第一开关晶体管导通， 使得所述数据信 号源与所述电容所在支路接通， 数据信号源向所述电容充电。
4、根据权利要求 3所述的像素电路，还包括与所述第一驱动子电路相连 的第一补偿子电路， 和与所述第二驱动子电路相连的第二补偿子电路；
所述第一补偿子电路包括第二开关晶体管；
所述第二补偿子电路包括第三开关晶体管； 其中， 所述第二开关晶体管的源极与所述 n型驱动晶体管的栅极相连， 漏极与 n型驱动晶体管的漏极相连， 栅极与第二门信号源相连；
所述第三开关晶体管的源极与所述 p型驱动晶体管的栅极相连， 漏极与 p型驱动晶体管的漏极相连， 栅极与所述第二门信号源相连。
5、根据权利要求 4所述的像素电路，还包括控制所述第一发光器件和第 二发光器件与第二参考电压源之间接通的第四开关晶体管， 所述第四开关晶 体管的栅极与充电控制信号源相连， 源极与所述第一发光器件的阳极以及第 二发光器件的阴极相连， 漏极与所述第二参考电压源相连， 所述充电控制信 号源用于控制所述第四开关晶体管的导通与截止。
6、根据权利要求 5所述的像素电路， 还包括： 控制所述电容与第一参考 电压源接通的第五开关晶体管；
所述第五开关晶体管的栅极与第三门信号源相连， 源极与所述第一参考 电压源相连， 漏极与所述电容的第二端相连；
所述第三门信号源用于控制所述第五开关晶体管导通与截止。
7、 根据权利要求 6所述的像素电路， 其中， 所述第一开关晶体管、 第二 开关晶体管、 第三开关晶体管为 n型晶体管， 所述第五开关晶体管为 p型晶 体管； 或者
所述第一开关晶体管、第二开关晶体管、第三开关晶体管为 p型晶体管， 所述第五开关晶体管为 n型晶体管；
所述第一门信号源、 第二门信号源、 第三门信号源为同一门信号源。
8、一种显示面板， 包括由栅线和数据线围设而成的多个呈矩阵排列的像 素单元， 每一像素单元中包括一个像素电路和与该像素电路相连的第一发光 器件和第二发光器件；
其中， 所述像素电路为如权利要求 1所述的像素电路；
位于同一行的像素电路中的充电子电路与同一条栅线相连， 位于同一列 的像素电路中的充电子电路与同一条数据线相连； 在一帧图像显示阶段， 在 所述第一驱动子电路和第二驱动子电路先后分别驱动第一发光器件发光和第 二发光器件发光之前， 所述充电子电路通过数据线和栅线为所述电容充电。
9、根据权利要求 8所述的显示面板， 其中， 所述像素电路为如权利要求 2-7任一项所述的像素电路；
所述第一开关晶体管的漏极通过所述数据线与所述数据信号源相连， 栅 极通过所述栅线与所述第一门信号源相连；
所述门信号源和数据信号源分别通过栅线和数据线为所述电容充电。
10、 一种显示装置， 包括权利要求 8或 9所述的显示面板。
11、 一种如权利要求 1-7任一项所述的像素电路的驱动方法， 包括： 在一帧图像显示阶段， 所述第一驱动子电路和第二驱动子电路在时序的 控制下先后分别驱动第一发光器件发光和第二发光器件发光；
在所述第一驱动子电路驱动第一发光器件发光之前， 所述充电子电路为 所述电容充电，所述电容放电时使得第一驱动子电路驱动第一发光器件发光， 或使得第二驱动子电路驱动第二发光器件发光。
12、根据权利要求 11所述的像素电路的驱动方法， 其中， 当控制所述第 一参考电压源输出高电平且所述第二参考电压源输出低电平时， 所述第一驱 动子电路所在支路断路， 所述第二驱动子电路所在支路接通， 第二驱动子电 路驱动第二发光器件发光；
当控制所述第一参考电压源输出低电平且所述第二参考电压源输出高电 平时， 所述第二驱动子电路所在支路断路， 所述第一驱动子电路所在支路接 通， 第一驱动子电路驱动第一发光器件发光。
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