WO2014172963A1 - 低温多晶硅薄膜、薄膜晶体管、其制备方法及显示面板 - Google Patents

低温多晶硅薄膜、薄膜晶体管、其制备方法及显示面板 Download PDF

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WO2014172963A1
WO2014172963A1 PCT/CN2013/076957 CN2013076957W WO2014172963A1 WO 2014172963 A1 WO2014172963 A1 WO 2014172963A1 CN 2013076957 W CN2013076957 W CN 2013076957W WO 2014172963 A1 WO2014172963 A1 WO 2014172963A1
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nano
silicon film
film
silicon
low
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刘震
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H10P14/3816—Pulsed laser beam

Definitions

  • Embodiments of the present invention relate to a low temperature polysilicon film, a method of fabricating the same, a thin film transistor, a method of fabricating the same, and a display panel. Background technique
  • Low temperature polysilicon thin film transistors have superior electrical properties compared to amorphous silicon (a-Si) thin film transistors.
  • the size of the LTPS-TFT can be made smaller than that of the a-Si TFT, thereby increasing the transmittance of light, thereby reducing the load on the backlight module of the liquid crystal display panel and prolonging the life of the liquid crystal display panel.
  • the low temperature polysilicon film (LTPS) can directly form a high-speed CMOS (Complementary Metal Oxide Semiconductor) driving circuit system on the substrate, the external printed circuit board has fewer pins, and the wiring is connected. The fewer points reduce the probability of defects in the liquid crystal display panel and increase the durability.
  • CMOS Complementary Metal Oxide Semiconductor
  • a polysilicon film is used as an active layer.
  • an amorphous amorphous silicon film is first deposited as a precursor film, and then the precursor film is crystallized into a polysilicon film by, for example, excimer laser annealing.
  • the pulse laser generated by the excimer laser has a short pulse width and a melting time of only several tens of nanoseconds, so the crystallization rate is fast, resulting in a small crystal grain size and easy generation of more crystals in the channel. This reduces carrier mobility and increases leakage current.
  • the melting point of amorphous silicon is still high, and the energy of laser crystallization is limited by a certain range.
  • the amorphous silicon which is completely melted is concentrated on the surface layer.
  • the temperature of the bottom layer is lower than the melting point of the crystalline silicon, it is in a semi-molten state, and the direction of crystallization will grow upward from the molten seed crystal, and the polycrystalline silicon is columnar, so this affects the mobility of the carrier more.
  • the energy density of the incident laser light is increased, the crystal grains are liable to be uneven, and there are significant protrusions which adversely affect the deposition of the subsequent film. Summary of the invention
  • Embodiments of the present invention provide a low temperature polysilicon film, a preparation method thereof, and a thin film transistor
  • the preparation method and the display panel can reduce grain boundaries and defects, and improve the quality of the thin film transistor.
  • One aspect of the present invention provides a method of preparing a low temperature polysilicon film formed by crystallizing a nano silicon film as a precursor.
  • the method includes the steps of: depositing a nano-silicon film; performing a dehydrogenation treatment on the deposited nano-silicon film; and crystallizing the dehydrogenated nano-silicon film to form a low-temperature polycrystalline silicon film.
  • the deposited nano-silicon film contains crystalline nano-silicon grains having a volume of 50-60% of the volume of the deposited nano-silicon film.
  • the step of depositing a nano-silicon film comprises: depositing a nano-silicon film by plasma enhanced chemical vapor deposition.
  • the reaction gas is a mixed gas of 99.999% silane and 99.999% hydrogen, wherein the mass percentage of silane in the mixed gas 0.1-10%, the flow rate of the mixed gas is
  • the RF frequency is 13.56 MHz, and the RF power is 30-500 W.
  • the deposition time is 20 seconds to 30 minutes.
  • the deposited nano-silicon film has a thickness of 30-100 nm.
  • the nano-silicon in the deposited nano-silicon film has a particle size of l-40 nm, and the average particle size is
  • the step of crystallizing the nano-silicon film to form a low-temperature polysilicon film comprises: crystallizing the nano-silicon film to form low-temperature polysilicon by excimer laser annealing, solid phase crystallization or metal induced lateral crystallization. film.
  • the step of crystallizing the nano-silicon film to form a low-temperature polysilicon film comprises: crystallization of the nano-silicon film by an excimer laser pulse annealing method to form a low-temperature polysilicon film, wherein the laser pulse frequency is 200-400HZ, laser energy density is 240-250 mJ / cm 2
  • Another aspect of the invention provides a method for preparing a thin film transistor, comprising preparing the low-temperature polysilicon film prepared by the embodiment of the invention as A low temperature polysilicon film of the source layer.
  • a low temperature polysilicon film is prepared, which is prepared by the method provided by the embodiment of the present invention.
  • Still another aspect of the present invention provides a thin film transistor including the low temperature polysilicon film provided by the embodiment of the present invention.
  • a display panel comprising the thin film transistor according to the embodiment of the present invention is provided.
  • FIG. 1 is a flow chart of a method for preparing a low-temperature polysilicon film according to an embodiment of the present invention
  • FIG. 2 is a schematic view showing a method for preparing a low-temperature polysilicon film of FIG.
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • Source 7 Drain 8: Laser generated by an excimer laser 9: Direction of movement of the laser 10: Nano-silicon film layer
  • Embodiments of the present invention provide a method for preparing a low-temperature polysilicon film formed by crystallizing a nano-silicon film as a precursor, that is, a nano-silicon film is used as a precursor film of a polysilicon film.
  • Low temperature polysilicon film is a branch of polysilicon film, in addition to high temperature polysilicon film (HTPS).
  • the high temperature polysilicon film requires a high temperature annealing technique of 1000 ° C or higher in the preparation process to convert the amorphous silicon structure into a polysilicon structure.
  • the preparation process of the low-temperature polysilicon film is usually completed below 600 ° C, which greatly reduces the energy consumption compared to the high-temperature polysilicon film.
  • the nano-silicon film is a low-fiber material composed of a large number of nano-sized silicon micro-grains and contains a certain amount of crystalline components.
  • crystalline components i.e., crystalline nano-silicon grains
  • the ratio is merely illustrative, and those skilled in the art can select a nano-silicon film having other crystalline components in accordance with the principles disclosed in the present specification.
  • the nano-silicon film can be deposited by a PECVD (plasma enhanced chemical vapor deposition) method.
  • PECVD plasma enhanced chemical vapor deposition
  • a sputtering method or the like For example, a sputtering method or the like.
  • the nano-silicon film After forming a nano-silicon film having a certain amount of crystalline components, the nano-silicon film can be crystallized by an ELA (Excimer Laser Annealing) method to form a low-temperature polycrystalline silicon film. It can be understood that a person skilled in the art can also crystallize a polycrystalline silicon film by other methods, for example, by SPC (Solid Phase Crystallization) method or MILC (Metal Induced Lateral Crystallization) method. .
  • ELA Excimer Laser Annealing
  • the polysilicon film can be grown as a seed nanocrystalline crystal grain as a seed. Therefore, the grain size in the polycrystalline silicon film formed by crystallization is large, the grain boundary generated in the channel is reduced, the carrier mobility is improved, the leakage current is reduced, and the quality of the polysilicon film is improved.
  • the nanocrystalline silicon film is used as a precursor for crystallization, which overcomes the problem of using an amorphous amorphous silicon film as a precursor film.
  • the strict range limitation of the laser crystallization energy makes it easier to control the reaction conditions during the production process.
  • Another embodiment of the present invention provides a method for preparing a low temperature polysilicon film. As shown in FIG. 1, the method includes the following steps 101-103:
  • the nano-silicon film is deposited by the PECVD method.
  • the nano-silicon film 10 contains only a very small amount of nano-sized silicon particles of amorphous silicon structure, that is, no crystalline component exists in the nano-silicon film 10 at this time.
  • the particle size grows, and highly crystallized nano-silicon grains with a small amount of crystal phase are gradually formed.
  • the PECVD method uses a mixed gas of silane (SiH 4 ) and hydrogen ( 3 ⁇ 4 ) as a reaction gas.
  • the H-based etches the weak Si-Si bond on the surface of the nano-silicon film, removing the weak Si-Si bond, leaving a strong Si-Si bond, so that the growth rate of the nano-silicon film 10 is not too fast.
  • the crystal lattice structure in which the bonding is good is preserved, and the disordered mesh composition is minimized to form nano silicon crystal grains.
  • the nano-silicon grains formed in this step account for 50-60% of the volume of the nano-silicon film.
  • a buffer layer 2 is first deposited on the glass substrate 1, and then a nano-silicon film 10 is deposited on the buffer layer 2.
  • the deposited nano-silicon film is treated by a dehydrogenation process for 50-120 minutes at a temperature of, for example, 350 to 550 °C. Preferably, it is annealed, for example, at a temperature of 450 ° C for 90 minutes.
  • the nano-silicon film is crystallized by the ELA method to form a low-temperature polysilicon film.
  • Fig. 2 there is shown a schematic diagram of laser light generated by an excimer laser moving from right to left over the nano-silicon film 10 in the direction indicated by the arrow to crystallize it.
  • the region 11 is a region of the nano-silicon film 10 which is being crystallized at this time, and on the right side thereof is a polysilicon film active layer 3 which has been crystallized.
  • the nano-silicon film is deposited by the PECVD method, and the deposited nano-silicon film contains 50-60% of the nano-silicon grains occupying the volume of the nano-silicon film. Then, the nano-silicon film is dehydrogenated, and finally the nano-silicon film is crystallized to form Low temperature polysilicon film. Since the polycrystalline silicon thin film can be grown by using these crystalline nano silicon crystal grains as a seed crystal during the crystallization of the nano silicon thin film into a low temperature polycrystalline silicon thin film, the crystal grain size in the polycrystalline silicon thin film formed by the crystallization is large and reduced.
  • the grain boundaries generated in the channel improve the carrier mobility and reduce the leakage current, thereby improving the quality of the polysilicon film.
  • the crystallization of the nano-silicon film as a precursor overcomes the strict range limitation of the laser crystallization energy when the amorphous silicon film is used as the precursor film, and the reaction conditions can be easily controlled in the production process.
  • a suitable deposition process parameter to control the growth rate of the nano-silicon film within a suitable range.
  • a nano silicon film can be deposited by using the following process parameters.
  • the reaction gas was a mixed gas of 99.999% silane and 99.999% hydrogen.
  • the mass percentage of the silane in the mixed gas is 0.1 to 10%
  • the flow rate of the mixed gas is 100 to 1500 sppm
  • the working gas pressure is 10 - 2 to 10 3 Pa.
  • the mass percentage of silane in the mixed gas is 10%.
  • the working gas pressure is 10 2 Pa.
  • the nano-silicon film may be deposited by the following process parameters.
  • the RF frequency is 13.56MHz and the RF power is 30-500W.
  • the radio frequency power is 100W.
  • the nano-silicon film may be deposited by the following process parameters.
  • the deposition time is 20 seconds -30 minutes.
  • the nano-silicon film may be deposited by the following process parameters.
  • the deposited nano-silicon film has a thickness of, for example, 30 to 100 nm. Further preferably, the thickness of the nano-silicon film is, for example, 50 nm.
  • the nano-silicon film may be deposited by the following process parameters.
  • the nano-silicon in the deposited nano-silicon film has a particle size of, for example, 1 to 40 nm, and an average particle size of, for example, 1 to 20 nm. Further preferably, for example, the nano-silicon has a particle size of 20 nm.
  • the nano-silicon includes nano-silicon particles (grains) which form a crystalline structure and amorphous silicon particles which do not form a crystal-phase structure.
  • the nano silicon film may be crystallized to form a low temperature polycrystal according to the following process parameters.
  • Silicon film is crystallized by excimer laser annealing to form a low-temperature polysilicon film, for example, a laser pulse frequency of 200-400 Hz and a laser energy density of 240-250 mJ/cm 2 .
  • the method of the present invention further provides a method for preparing a thin film transistor, which comprises the method for preparing a low temperature polycrystalline silicon film provided by the embodiment of the present invention.
  • a low-temperature polysilicon film as an active layer in a thin film transistor is crystallized by a nano-silicon film, so that a crystal grain size in the polycrystalline silicon film formed by crystallization is large, and there is a decrease in The grain boundaries generated in the channel of the source layer improve carrier mobility and reduce leakage current, thereby improving the quality of the polysilicon film.
  • the crystallization of the nano-silicon film as a precursor overcomes the strict range limitation of the laser crystallization energy when the amorphous silicon film is used as the precursor film, and the reaction conditions can be easily controlled in the production process.
  • the embodiment of the present invention further provides a low-temperature polysilicon film prepared by the above-mentioned various low-temperature polycrystalline silicon film preparation methods provided by the embodiments of the present invention.
  • the layer 3 is a polycrystalline silicon film as an active layer prepared by the low-temperature polysilicon film production method in the above embodiment.
  • the low-temperature polysilicon film provided by the embodiment of the invention is crystallized by the nano-silicon film, so that the grain size in the polycrystalline silicon film formed by crystallization is larger, the grain boundary generated in the channel is reduced, and the carrier is improved.
  • the mobility which reduces the leakage current, improves the quality of the polysilicon film.
  • the crystallization of the nano-silicon film as a precursor overcomes the strict range limitation of the laser crystallization energy when the amorphous silicon film is used as the precursor film, and the reaction conditions can be easily controlled in the production process.
  • the embodiment of the invention further provides a thin film transistor comprising the above-mentioned low-temperature polysilicon film provided by the embodiment of the invention.
  • a low temperature polysilicon film provided by an embodiment of the present invention is used as a thin film transistor of an active layer.
  • the thin film transistor comprises a glass substrate 1, a buffer layer 2, a polysilicon thin film active layer 3, a gate electrode 4, a gate insulating layer 5, a highly doped source region 3a on the left side of the polysilicon film active layer, and a polysilicon film active layer right
  • the drain region 3b on the side, the source 6 and the drain 7.
  • FIG. 3 is only a schematic illustration of a thin film transistor provided by an embodiment of the present invention, and the skilled person may also be known in the art. Common forms or common techniques are used to obtain other forms of transistors including the low temperature polysilicon film of the present invention.
  • the glass substrate can be replaced with, for example, a plastic substrate or the like.
  • the thin film transistor provided by the embodiment of the invention adopts a low temperature polysilicon film crystallized by a nano silicon film as an active layer, so that the crystal grain size in the polycrystalline silicon film formed by crystallization is large, and the crystal generated in the channel is reduced.
  • the boundary thereby increasing the mobility of carriers and reducing the leakage current, thereby improving the quality of the thin film transistor.
  • the crystallization of the nano-silicon film as a precursor overcomes the strict range limitation of the laser crystallization energy when the amorphous silicon film is used as the precursor film, and the reaction conditions can be easily controlled in the production process.
  • the embodiment of the invention further provides a display panel, which comprises the thin film transistor provided by the embodiment of the invention.
  • the low-temperature polysilicon film in the thin film transistor is crystallized by the nano-silicon film, so that the grain size in the polycrystalline silicon film formed by crystallization is larger, and the grain boundary generated in the channel is reduced, thereby The carrier mobility is improved, and the leakage current is reduced, thereby improving the quality of the polysilicon film.
  • the crystallization of the nano-silicon film as a precursor overcomes the strict range limitation of the laser crystallization energy when the amorphous silicon film is used as the precursor film, and the reaction conditions can be easily controlled in the production process.
  • PECVD process are deposited on a glass substrate and 80nm 8 ⁇ lOOnm and 802, Si0 2 and SiN x is formed a double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixed gas of 99.999% silane (SiH 4 ) and 99.999% hydrogen ( 3 ⁇ 4 ), the silane content is lwt%; the mixed gas flow rate is 300sppm; the radio frequency is 13.56MHz; the radio frequency power is 100W
  • the working pressure is 100 Pa; the temperature of the glass substrate is 180 ° C; the deposition time is 10 minutes.
  • the nano-silicon film layer is deposited under the above process parameters; the thickness of the obtained nano-silicon film is 40 nm, the average particle size of the nano-silicon is 15 nm, and the crystalline nano-silicon grains account for 52% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a dehydrogenation process at 450 ° C for 90 minutes, and then the nano-silicon film layer was treated by a XeCl excimer laser annealing process.
  • the process parameters are as follows: the glass substrate temperature is 350 ° C, the ambient atmosphere is 20 Pa nitrogen atmosphere, the laser pulse frequency is 300 Hz, and the laser energy density is 250mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.
  • SiN x and SiO 2 of 80 nm and 100 nm were separately deposited on the glass substrate by a PECVD process to form a SiN x and SiO 2 double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixed gas of 99.999% silane (SiH 4 ) and 99.999% hydrogen ( 3 ⁇ 4 ), the silane content is 0.8 wt%; the mixed gas flow rate is 250 sppm; the radio frequency is 13.56 MHz; the RF power is 150 W; working pressure is 150 Pa; glass substrate temperature is 200 ° C; deposition time is 12 minutes.
  • the nano-silicon film layer is deposited under the above process parameters; after testing, the obtained nano-silicon film has a thickness of 50 nm, the average particle size of the nano-silicon is 18 nm, and the crystalline nano-silicon grains account for 57% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a dehydrogenation process at 450 ° C for 90 minutes, and then the nano-silicon film layer was treated by a XeCl excimer laser annealing process.
  • the process parameters are as follows: the temperature of the glass substrate is 350 ° C, the ambient atmosphere is a nitrogen atmosphere of lOPa, the laser pulse frequency is 300 Hz, and the laser energy density is 240 mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.
  • PECVD process are deposited on a glass substrate and 80nm 8 ⁇ lOOnm and 802, Si0 2 and SiN x is formed a double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixture of 99.999% silane (SiH 4 ) and 99.999% hydrogen (H 2 ), the silane content is lwt%; the mixed gas flow rate is 1300sppm; the radio frequency is 13.56MHz; the RF power is 200W; working pressure is lOOPa; glass substrate temperature is 180 ° C; deposition time is 10 minutes.
  • a nano-silicon film layer is deposited under the above process parameters; after testing, the obtained nano-silicon film has a thickness of 70 nm, the average particle size of the nano-silicon is 5 nm, and the crystalline nano-silicon grains account for 55% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a 480 ° C dehydrogenation process for 85 minutes, and then the nano-silicon film layer was treated by a XeCl excimer laser annealing process.
  • the process parameters are as follows: the glass substrate temperature is 350 ° C, the ambient atmosphere is 20 Pa nitrogen atmosphere, the laser pulse frequency is 220 Hz, and the laser energy density is 250 mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.
  • Example 4 SiN x and SiO 2 of 80 nm and 100 nm were separately deposited on the glass substrate by a PECVD process to form a SiN x and SiO 2 double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixed gas of 99.999% silane (SiH 4 ) and 99.999% hydrogen ( 3 ⁇ 4 ), the silane content is lwt%; the mixed gas flow rate is 200sppm; the radio frequency is 13.56MHz; the radio frequency power is 400W
  • the working pressure is 100 Pa; the temperature of the glass substrate is 180 ° C; the deposition time is 10 minutes.
  • the nano-silicon film layer is deposited under the above process parameters; after testing, the thickness of the obtained nano-silicon film is 100 nm, the average particle size of the nano-silicon is 12 nm, and the crystalline nano-silicon grains account for 54% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a 320 ° C dehydrogenation process for 110 minutes, and then the nano-silicon film layer was processed by a XeCl excimer laser annealing process.
  • the process parameters are as follows: The glass substrate temperature is 350 ° C, the ambient atmosphere is 20 Pa nitrogen atmosphere, the laser pulse frequency is 350 Hz, and the laser energy density is 250 mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.
  • PECVD process are deposited on a glass substrate and 80nm 8 ⁇ lOOnm and 802, Si0 2 and SiN x is formed a double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixed gas of 99.999% silane (SiH 4 ) and 99.999% hydrogen (H 2 ), the silane content is lwt%; the mixed gas flow rate is lOOsppm; the radio frequency frequency is 13.56 MHz; the radio frequency power is 30W; working pressure of 10- 2 Pa; temperature of the glass substrate is 180 ° C; deposition time was 20 seconds.
  • the nano-silicon film layer is deposited under the above process parameters; after testing, the obtained nano-silicon film has a thickness of 30 nm, the average particle size of the nano-silicon is 1 nm, and the crystalline nano-silicon grains account for 50% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a 320 ° C dehydrogenation process for 110 minutes, and then the nano-silicon film layer was processed by a XeCl excimer laser annealing process.
  • the process parameters are as follows: The glass substrate temperature is 350 ° C, the ambient atmosphere is 20 Pa nitrogen atmosphere, the laser pulse frequency is 200 Hz, and the laser energy density is 245 mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.
  • Example 6 SiN x and SiO 2 of 80 nm and 100 nm were separately deposited on the glass substrate by a PECVD process to form a SiN x and SiO 2 double buffer layer.
  • a nano-silicon film layer is deposited on the double buffer layer using a PECVD process.
  • the process parameters are as follows:
  • the reaction gas is a mixed gas of 99.999% silane (SiH 4 ) and 99.999% hydrogen ( 3 ⁇ 4 ), the silane content is 1wt%; the mixed gas flow rate is 1500sppm; the RF frequency is 13.56MHz; the RF power is 500W.
  • the working pressure is lOOOPa; the temperature of the glass substrate is 180 ° C; the deposition time is 30 minutes.
  • a nano-silicon film layer is deposited under the above process parameters; after testing, the obtained nano-silicon film has a thickness of 90 nm, the average particle size of the nano-silicon is 40 nm, and the crystalline nano-silicon grains account for 60% of the volume of the nano-silicon film.
  • the nano-silicon film layer was treated by a 320 ° C dehydrogenation process for 110 minutes, and then the nano-silicon film layer was processed by a XeCl excimer laser annealing process.
  • the process parameters are as follows: The glass substrate temperature is 350 ° C, the ambient atmosphere is 20 Pa nitrogen atmosphere, the laser pulse frequency is 400 Hz, and the laser energy density is 248 mJ/cm 2 . Under the above process parameters, the nano-silicon film layer is crystallized into a polysilicon film layer.

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Abstract

一种低温多晶硅薄膜及其制备方法、薄膜晶体管及其制备方法、显示面板。所述低温多晶硅薄膜的制备方法包括：所述低温多晶硅薄膜由纳米硅薄膜晶化形成。

Description

低温多晶硅薄膜、 薄膜晶体管、 其制备方法及显示面板 技术领域
本发明的实施例涉及一种低温多晶硅薄膜及其制备方法、 薄膜晶体管及 其制备方法和显示面板。 背景技术
低温多晶硅薄膜晶体管 （LTPS-TFT )相较于非晶硅（a-Si )薄膜晶体管 具有更加优异的电学性能。 LTPS-TFT的尺寸可较 a-Si TFT更小， 因而可使 光的穿透率提高， 进而可减小液晶显示面板的背光模块的负荷， 延长液晶显 示面板的寿命。 此外， 由于低温多晶硅薄膜（LTPS )能够直接在基板上制成 高速 CMOS ( Complementary Metal Oxide Semiconductor, 互补金属氧化物半 导体）驱动电路系统， 这样外部的印制电路板接脚亦较少， 接线的连接点较 少， 使液晶显示面板产生缺陷的几率减小， 增加了耐用度。
低温多晶硅薄膜晶体管中以多晶硅薄膜作为有源层。 现有技术在形成多 晶硅薄膜有源层的工艺过程中， 首先沉积无定型非晶硅薄膜作为前驱薄膜， 然后通过例如准分子激光退火法将前驱薄膜晶化为多晶硅薄膜。 但是， 在该 方法中， 准分子激光器产生的脉沖激光脉宽短、 熔融时间仅数十纳秒， 因此 晶化速率很快， 导致生成的晶粒尺寸小， 容易在沟道中产生较多的晶界， 这 降低了载流子迁移率， 增加漏电流。 另外由于使用无定型非晶硅薄膜为前驱 薄膜， 非晶硅熔点仍然较高， 而激光晶化的能量是受一定的范围限制的， 能 量过低时所能完全熔融的非晶硅集中在表层， 底层温度低于晶化硅的熔点， 则呈现半熔融状态， 晶化的方向将由为熔融的籽晶向上生长， 多晶硅呈柱状 的， 所以这更影响了载流子迁移率的提高。 但是， 如果提高入射激光的能量 密度， 则容易造成结晶颗粒不均匀， 有明显的凸起， 对后续薄膜的沉积产生 不利的影响。 发明内容
本发明的实施例提供了一种低温多晶硅薄膜及其制备方法、 薄膜晶体管 及其制备方法和显示面板， 能够减少晶界及缺陷， 提高薄膜晶体管质量。 本发明的一个方面提供了一种低温多晶硅薄膜的制备方法， 所述低温多 晶硅薄膜通过以纳米硅薄膜作为前驱体进行晶化而形成。
例如， 所述方法包括下述步骤： 沉积纳米硅薄膜； 对所述沉积的纳米硅 薄膜进行退氢处理； 以及将所述退氢处理后的纳米硅薄膜晶化形成低温多晶 硅薄膜。
例如， 所述沉积的纳米硅薄膜包含的晶态的纳米硅晶粒的体积占所述沉 积的纳米硅薄膜的体积的 50-60%
例如， 所述沉积纳米硅薄膜的步骤包括： 采用等离子增强化学气相沉积 法沉积纳米硅薄膜。
例如，在所述采用等离子增强化学气相沉积法沉积纳米硅薄膜的过程中， 反应气体为 99.999%的硅烷及 99.999%的氢气的混合气体， 其中， 硅烷在所 述混合气体中的质量百分含量为 0.1-10% , 所述混合气体的流量为
100-1500sppm, 工作气压为 10—2-103Pa
例如，在所述采用等离子增强化学气相沉积法沉积纳米硅薄膜的过程中， 射频频率为 13.56MHz, 射频功率为 30-500W
例如，在所述采用等离子增强化学气相沉积法沉积纳米硅薄膜的过程中， 沉积时间为 20秒 -30分钟。
例如， 所述沉积的纳米硅薄膜的厚度为 30-100nm
例如， 所述沉积的纳米硅薄膜中的纳米硅的粒度为 l-40nm, 平均粒度为
1-20
例如， 所述将所述纳米硅薄膜晶化形成低温多晶硅薄膜的步骤包括： 采 用准分子激光退火法、 固相晶化法或金属诱导横向晶化法将所述纳米硅薄膜 晶化形成低温多晶硅薄膜。
例如， 在所述将所述纳米硅薄膜晶化形成低温多晶硅薄膜的步骤为包括 采用准分子激光脉沖退火法将所述纳米硅薄膜晶化形成低温多晶硅薄膜的情 况下， 其中， 激光脉沖频率为 200-400HZ, 激光能量密度为 240-250mJ/cm2 本发明的另一个方面提供了一种薄膜晶体管的制备方法， 包括采用本发 明实施例提供的所述的低温多晶硅薄膜的制备方法制备作为有源层的低温多 晶硅薄膜。 本发明的再一个方面提供了一种低温多晶硅薄膜， 所述低温多晶硅薄膜 为通过本发明实施例提供的方法制备而成的。
本发明的再一个方面提供了一种薄膜晶体管， 所述薄膜晶体管包括本发 明实施例提供的低温多晶硅薄膜。
本发明的再一个方面提供了一种显示面板， 所述显示面板包括本发明实 施例提供的所述的薄膜晶体管。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的一种低温多晶硅薄膜的制备方法的流程图； 图 2为图 1中的低温多晶硅薄膜的制备方法示意图；
图 3为本发明实施例提供的一种薄膜晶体管的结构示意图。
附图标记
1: 玻璃基板； 2: 緩沖层 3: 多晶硅薄膜有源层
4: 栅极； 5: 栅极绝缘层 3a:多晶硅薄膜有源层左侧的高 掺杂源区； 3b: 多晶硅薄膜有源层右侧的漏区
6: 源极 7: 漏极 8: 准分子激光器产生的激光 9: 激光的移动方向 10: 纳米硅薄膜层
11 : 激光与纳米硅薄膜相作用发生晶化的区域 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 "一个" 、 "一" 或者 "该" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在其前面的元件或者物件涵盖出现在其后面列举 的元件或者物件及其等同， 而不排除其他元件或者物件。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变 后， 则该相对位置关系也可能相应地改变。
本发明实施例提供了一种低温多晶硅薄膜的制备方法， 所述低温多晶硅 薄膜通过以纳米硅薄膜作为前驱体进行晶化而形成， 也即采用了纳米硅薄膜 为多晶硅薄膜的前驱薄膜。
低温多晶硅薄膜（ LTPS )是多晶硅薄膜的一个分支， 除此之外还有高温 多晶硅薄膜（HTPS ) 。 高温多晶硅薄膜在制备工艺中需要 1000°C以上的高 温退火技术方能将非晶硅结构特性转化为多晶硅结构。 而低温多晶硅薄膜的 制备工艺通常是在 600°C以下完成的， 相比于高温多晶硅薄膜而言大大降低 了能耗。
纳米硅薄膜是由大量纳米尺寸的硅微晶粒构成的一种低纤维材料， 并含 有一定量的晶态成分。 例如， 晶态成分（也即晶态的纳米硅晶粒） 占纳米硅 薄膜中体积 40-70%。 当然该比例仅为举例说明，本领域技术人员可根据本说 明书公开的原理选择具有其他含量晶态成分的纳米硅薄膜。
纳米硅薄膜可通过 PECVD (等离子增强化学气相沉积）方法沉积而成。 例如溅射（sputter )方法等。
在形成了具有一定量晶态成分的纳米硅薄膜后，可以采用 ELA ( Excimer Laser Annealing, 准分子激光退火）方法将该纳米硅薄膜晶化形成低温多晶 硅薄膜。 可以理解的是， 本领域技术人员还可通过其他方法晶化形成多晶硅 薄膜， 例如通过 SPC ( Solid Phase Crystallization, 固相晶化 )方法或者 MILC ( Metal Induced Lateral Crystallization, 金属诱导横向晶化）方法等。
在采用上述方法将纳米硅薄膜晶化成低温多晶硅薄膜的过程中， 多晶硅 薄膜能够以晶态的纳米硅晶粒为籽晶 （seed )进行生长。 因此， 使得晶化形 成的多晶硅薄膜中的晶粒尺寸较大， 减少了沟道中产生的晶界， 从而提高了 载流子的迁移率， 降低了漏电流， 从而提高了多晶硅薄膜的质量。 此外， 以 纳米硅薄膜作为前驱体进行晶化， 克服了以非定型非晶硅薄膜为前驱薄膜时 对激光晶化能量的严格的范围限制，可在生产过程中较容易的控制反应条件。 本发明实施例提供了另一种低温多晶硅薄膜的制备方法， 如图 1所示， 所示方法包括如下步骤 101-103:
101、 沉积纳米硅薄膜。
在本步骤中， 优选的， 如图 2所示， 采用 PECVD方法沉积纳米硅薄膜
10。在纳米硅薄膜 10沉积的初期阶段， 纳米硅中并没有形成晶相结构。 纳米 硅薄膜 10中仅含有极少量的纳米级别小颗粒的非晶硅结构的纳米硅,也即此 时纳米硅薄膜 10 中没有晶态成分存在。 在沉积的过程中， 随着纳米硅薄膜 10的增厚，颗粒尺寸生长，逐步形成带有少量晶相的高度晶化的纳米硅晶粒。
此处 PECVD方法采用硅烷 ( SiH4 )和氢气（¾ ) 的混合气体为反应气 体。 H基对纳米硅薄膜表面的弱的 Si-Si键起到刻蚀作用， 去掉了弱的 Si-Si 键， 留下强的 Si-Si键， 使得纳米硅薄膜 10的生长速度不至于过快， 使其中 键合良好的晶格结构得以保存下来， 而无序网格成分降到最低， 从而形成纳 米硅晶粒。 本步骤中形成的纳米硅晶粒占纳米硅薄膜体积的 50-60%。
可以理解的是， 在本步骤之前还可以包括在玻璃基板上沉积緩沖层的步 骤， 本发明对此不作具体限定， 本领域技术人员可根据本领域公知常识或常 用技术手段沉积所述緩沖层。 如图 2所示， 首先在玻璃基板 1上沉积緩沖层 2, 然后在緩沖层 2上沉积纳米硅薄膜 10。
102、 对所述沉积的纳米硅薄膜进行退氢处理。
在本步骤中， 例如 350-550°C的温度下将沉积的纳米硅薄膜以退氢工艺 处理 50-120分钟。 优选的， 例如在 450°C的温度下退火 90分钟。
103、 将所述退氢处理后的纳米硅薄膜晶化形成低温多晶硅薄膜。
在本步骤中，采用 ELA方法将纳米硅薄膜晶化形成低温多晶硅薄膜。如 图 2所示， 图中示出了准分子激光器产生的激光沿箭头示出的方向在纳米硅 薄膜 10上方从右向左移动， 以对其进行晶化的示意图。 区域 11为此时正在 被晶化的纳米硅薄膜 10的区域，在其右侧为已经晶化成的多晶硅薄膜有源层 3。
本发明实施例提供的低温多晶硅薄膜的制备方法， 采用 PECVD方法沉 积纳米硅薄膜，沉积的纳米硅薄膜中含有占纳米硅薄膜体积的 50-60%的纳米 硅晶粒。 然后， 对纳米硅薄膜进行脱氢处理， 最后将纳米硅薄膜晶化即形成 低温多晶硅薄膜。 由于在纳米硅薄膜晶化成低温多晶硅薄膜的过程中， 多晶 硅薄膜能够以这些晶态的纳米硅晶粒为籽晶进行生长， 因此， 使得晶化形成 的多晶硅薄膜中的晶粒尺寸较大， 减少了沟道中产生的晶界， 从而提高了载 流子的迁移率， 降低了漏电流， 从而提高了多晶硅薄膜的质量。 此外， 以纳 米硅薄膜作为前驱体进行晶化， 克服了以非定型非晶硅薄膜为前驱薄膜时对 激光晶化能量的严格的范围限制， 可在生产过程中较容易的控制反应条件。
在形成纳米硅薄膜的过程中， 最好选择合适的沉积工艺参数控制纳米硅 薄膜的生长速率在适宜的范围内。
因此， 在本发明提供的又一实施例中， 步骤 101中可以采取如下工艺参 数沉积纳米硅薄膜。 反应气体为 99.999%的硅烷及 99.999%的氢气的混合气 体。 硅烷在所述混合气体中的质量百分含量为 0.1-10%, 所述混合气体的流 量为 100-1500sppm, 工作气压为 10—2-103Pa。 进一步优选的， 例如硅烷在所 述混合气体中的质量百分含量为 10%。进一步优选的，例如工作气压为 102Pa。
优选的， 为了进一步提高多晶硅薄膜的质量， 在本发明提供的又一实施 例中， 步骤 101中可以采取如下工艺参数沉积纳米硅薄膜。 例如， 射频频率 为 13.56MHz,射频功率为 30-500W。进一步优选的，例如射频功率为 100W。
优选的，为了进一步提高多晶硅薄膜的质量，在本发明的又一实施例中， 优选的， 步骤 101中可以采取如下工艺参数沉积纳米硅薄膜。 例如， 沉积时 间为 20秒 -30分钟。
优选的， 为了进一步提高多晶硅薄膜的质量， 在本发明提供的又一实施 例中， 步骤 101中可以采取如下工艺参数沉积纳米硅薄膜。 所述沉积的纳米 硅薄膜的厚度例如为 30-100nm。 进一步优选的， 纳米硅薄膜的厚度例如为 50nm。
优选的， 为了进一步提高多晶硅薄膜的质量， 在本发明提供的又一实施 例中， 步骤 101中可以采取如下工艺参数沉积纳米硅薄膜。 所述沉积的纳米 硅薄膜中的纳米硅的粒度例如为 l—40nm, 平均粒度例如为 l-20nm。 进一步 优选的， 例如纳米硅的粒度为 20nm。 所述纳米硅包括形成晶态结构的纳米 硅颗粒（晶粒）及未形成晶相结构的非晶硅颗粒。
优选的， 为了进一步提高多晶硅薄膜的质量， 在本发明提供的又一实施 例中， 步骤 103中可采取如下工艺参数将所述纳米硅薄膜晶化形成低温多晶 硅薄膜。采用准分子激光退火法将所述纳米硅薄膜晶化形成低温多晶硅薄膜， 例如激光脉沖频率为 200-400HZ, 激光能量密度为 240-250mJ/cm2。
可以理解的是， 可以将上述实施例中的沉积纳米硅薄膜的各个工艺参数 组合应用， 此处不再赘述。
与上述低温多晶硅薄膜的制备方法相对应的， 本发明实施例还提供了一 种薄膜晶体管的制备方法， 所述制备方法包括本发明实施例提供的低温多晶 硅薄膜的制备方法。 本发明实施例提供的薄膜晶体管的制备方法， 薄膜晶体 管中作为有源层的低温多晶硅薄膜由纳米硅薄膜晶化而成， 使得晶化形成的 多晶硅薄膜中的晶粒尺寸较大， 减少了有源层的沟道中产生的晶界， 从而提 高了载流子的迁移率， 降低了漏电流，从而提高了多晶硅薄膜的质量。 此外， 以纳米硅薄膜作为前驱体进行晶化， 克服了以非定型非晶硅薄膜为前驱薄膜 时对激光晶化能量的严格的范围限制， 可在生产过程中较容易的控制反应条 件。
与上述低温多晶硅薄膜制备方法相对应的， 本发明实施例还提供了一种 低温多晶硅薄膜， 该低温多晶硅薄膜由本发明实施例提供的上述各低温多晶 硅薄膜制备方法制备而成。 如图 2所示， 层 3即为通过上述实施例中的低温 多晶硅薄膜制备方法制备而成的作为有源层的多晶硅薄膜。
本发明实施例提供的低温多晶硅薄膜， 由纳米硅薄膜晶化而成， 使得晶 化形成的多晶硅薄膜中的晶粒尺寸较大， 减少了沟道中产生的晶界， 从而提 高了载流子的迁移率， 降低了漏电流，从而提高了多晶硅薄膜的质量。 此外， 以纳米硅薄膜作为前驱体进行晶化， 克服了以非定型非晶硅薄膜为前驱薄膜 时对激光晶化能量的严格的范围限制， 可在生产过程中较容易的控制反应条 件。
与上述低温多晶硅薄膜相对应的， 本发明实施例还提供了一种薄膜晶体 管， 该薄膜晶体管包括本发明实施例提供的上述各低温多晶硅薄膜。
如图 3所示， 为采用本发明实施例提供的低温多晶硅薄膜作为有源层的 薄膜晶体管。该薄膜晶体管包括玻璃基板 1、緩沖层 2、多晶硅薄膜有源层 3、 栅极 4、 栅极绝缘层 5、 多晶硅薄膜有源层左侧的高掺杂源区 3a、 多晶硅薄 膜有源层右侧的漏区 3b、 源极 6和漏极 7。 可以理解的是， 图 3仅为本发明 实施例提供的薄膜晶体管的示意说明， 本领技术人员还可根据本领域的公知 常识或常用技术手段获得其他形式的包括本发明低温多晶硅薄膜的晶体管。 玻璃基板例如可以使用塑料基板等代替。
本发明实施例提供的薄膜晶体管， 采用了由纳米硅薄膜晶化而成的低温 多晶硅薄膜作为有源层， 使得晶化形成的多晶硅薄膜中的晶粒尺寸较大， 减 少了沟道中产生的晶界， 从而提高了载流子的迁移率， 降低了漏电流， 从而 提高了薄膜晶体管的质量。 此外， 以纳米硅薄膜作为前驱体进行晶化， 克服 了以非定型非晶硅薄膜为前驱薄膜时对激光晶化能量的严格的范围限制， 可 在生产过程中较容易的控制反应条件。
与上述薄膜晶体管相对应的， 本发明实施例还提供了一种显示面板， 所 述显示面板包括本发明实施例提供的薄膜晶体管。 本发明实施例提供的显示 面板， 其薄膜晶体管中低温多晶硅薄膜由纳米硅薄膜晶化而成， 使得晶化形 成的多晶硅薄膜中的晶粒尺寸较大， 减少了沟道中产生的晶界， 从而提高了 载流子的迁移率， 降低了漏电流， 从而提高了多晶硅薄膜的质量。 此外， 以 纳米硅薄膜作为前驱体进行晶化， 克服了以非定型非晶硅薄膜为前驱薄膜时 对激光晶化能量的严格的范围限制，可在生产过程中较容易的控制反应条件。
为了更好的说明上述低温多晶硅薄膜及其制备方法， 下面以四个具体示 例进行详细说明。
示例 1
在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 8 ^及8 02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（¾ ) 的混合气体， 硅 烷的含量为 lwt%; 混合气体流量为 300sppm; 射频频率为 13.56MHz; 射频 功率为 100W; 工作气压为 lOOPa; 玻璃基板的温度为 180°C ; 沉积时间为 10 分钟。 在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳米硅 薄膜的厚度为 40nm, 纳米硅的平均粒度为 15nm, 晶态的纳米硅晶粒占纳米 硅薄膜体积的 52%。
将纳米硅薄膜层经 450°C退氢工艺处理 90分钟，然后将纳米硅薄膜层经 XeCl准分子激光退火工艺进行处理。工艺参数如下：玻璃基板温度为 350°C , 环境气氛为 20Pa的氮气保护气氛，激光脉沖频率为 300Hz,激光能量密度为 250mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜层。
示例 2
在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 SiNx及 Si02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（¾ ) 的混合气体， 硅 烷的含量为 0.8wt%; 混合气体流量为 250sppm; 射频频率为 13.56MHz; 射 频功率为 150W; 工作气压为 150Pa; 玻璃基板的温度为 200°C ; 沉积时间为 12分钟。 在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳米 硅薄膜的厚度为 50nm, 纳米硅的平均粒度为 18nm, 晶态的纳米硅晶粒占纳 米硅薄膜体积的 57%。
将纳米硅薄膜层经 450°C退氢工艺处理 90分钟，然后将纳米硅薄膜层经 XeCl准分子激光退火工艺进行处理。工艺参数如下：玻璃基板温度为 350°C , 环境气氛为 lOPa的氮气保护气氛，激光脉沖频率为 300Hz,激光能量密度为 240mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜层。
示例 3
在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 8 ^及8 02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（H2 ) 的混合气体， 硅 烷的含量为 lwt%; 混合气体流量为 1300sppm; 射频频率为 13.56MHz; 射 频功率为 200W; 工作气压为 lOOPa; 玻璃基板的温度为 180°C ; 沉积时间为 10分钟。 在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳米 硅薄膜的厚度为 70nm, 纳米硅的平均粒度为 5nm, 晶态的纳米硅晶粒占纳 米硅薄膜体积的 55%。
将纳米硅薄膜层经 480°C退氢工艺处理 85分钟，然后将纳米硅薄膜层经 XeCl准分子激光退火工艺进行处理。工艺参数如下：玻璃基板温度为 350°C , 环境气氛为 20Pa的氮气保护气氛，激光脉沖频率为 220Hz,激光能量密度为 250mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜层。
示例 4 在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 SiNx及 Si02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（¾ ) 的混合气体， 硅 烷的含量为 lwt%; 混合气体流量为 200sppm; 射频频率为 13.56MHz; 射频 功率为 400W; 工作气压为 lOOPa; 玻璃基板的温度为 180°C ; 沉积时间为 10 分钟。 在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳米硅 薄膜的厚度为 lOOnm, 纳米硅的平均粒度为 12nm, 晶态的纳米硅晶粒占纳 米硅薄膜体积的 54%。
将纳米硅薄膜层经 320°C退氢工艺处理 110分钟， 然后将纳米硅薄膜层 经 XeCl 准分子激光退火工艺进行处理。 工艺参数如下： 玻璃基板温度为 350 °C , 环境气氛为 20Pa的氮气保护气氛， 激光脉沖频率为 350Hz, 激光能 量密度为 250mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜 层。
示例 5
在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 8 ^及8 02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（H2 ) 的混合气体， 硅 烷的含量为 lwt%; 混合气体流量为 lOOsppm; 射频频率为 13.56MHz; 射频 功率为 30W; 工作气压为 10—2Pa; 玻璃基板的温度为 180°C ; 沉积时间为 20 秒。 在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳米硅薄 膜的厚度为 30nm, 纳米硅的平均粒度为 lnm, 晶态的纳米硅晶粒占纳米硅 薄膜体积的 50%。
将纳米硅薄膜层经 320°C退氢工艺处理 110分钟， 然后将纳米硅薄膜层 经 XeCl 准分子激光退火工艺进行处理。 工艺参数如下： 玻璃基板温度为 350 °C , 环境气氛为 20Pa的氮气保护气氛， 激光脉沖频率为 200Hz, 激光能 量密度为 245mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜 层。
示例 6 在玻璃基板上使用 PECVD工艺分别沉积 80nm及 lOOnm的 SiNx及 Si02, 形成 SiNx及 Si02双层緩沖层。
使用 PECVD工艺在双緩沖层上沉积纳米硅薄膜层。 工艺参数如下： 反 应气体为 99.999%的硅烷（SiH4 )及 99.999%的氢气（¾ ) 的混合气体， 硅 烷的含量为 lwt%; 混合气体流量为 1500sppm; 射频频率为 13.56MHz; 射 频功率为 500W; 工作气压为 lOOOPa; 玻璃基板的温度为 180°C ; 沉积时间 为 30分钟。在上述工艺参数下沉积得到纳米硅薄膜层； 经测试， 所得到的纳 米硅薄膜的厚度为 90nm, 纳米硅的平均粒度为 40nm, 晶态的纳米硅晶粒占 纳米硅薄膜体积的 60%。
将纳米硅薄膜层经 320°C退氢工艺处理 110分钟， 然后将纳米硅薄膜层 经 XeCl 准分子激光退火工艺进行处理。 工艺参数如下： 玻璃基板温度为 350 °C , 环境气氛为 20Pa的氮气保护气氛， 激光脉沖频率为 400Hz, 激光能 量密度为 248mJ/cm2。 在上述工艺参数下， 纳米硅薄膜层晶化为多晶硅薄膜 层。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种低温多晶硅薄膜的制备方法， 其中， 所述低温多晶硅薄膜通过以 纳米硅薄膜作为前驱体进行晶化而形成。
2、 根据权利要求 1所述的制备方法， 包括下述步骤：
沉积纳米硅薄膜；
对所述沉积的纳米硅薄膜进行退氢处理； 以及
将所述退氢处理后的纳米硅薄膜晶化形成低温多晶硅薄膜。
3、根据权利要求 2所述的制备方法， 其中， 所述沉积的纳米硅薄膜包含 的晶态的纳米硅晶粒的体积占所述沉积的纳米硅薄膜的体积的 50-60%。
4、根据权利要求 2或 3所述的制备方法， 其中， 所述沉积纳米硅薄膜的 步骤包括： 采用等离子增强化学气相沉积法沉积纳米硅薄膜。
5、根据权利要求 4所述的制备方法， 其中， 在所述采用等离子增强化学 气相沉积法沉积纳米硅薄膜的过程中，反应气体为 99.999%的硅烷及 99.999% 的氢气的混合气体， 其中， 硅烷在所述混合气体中的质量百分含量为 0.1-10%, 所述混合气体的流量为 100-1500sppm, 工作气压为 10—2-103Pa。
6、根据权利要求 4或 5所述的制备方法， 其中， 在所述采用等离子增强 化学气相沉积法沉积纳米硅薄膜的过程中， 射频频率为 13.56MHz, 射频功 率为 30-500W。
7、 根据权利要求 4-6任一所述的制备方法， 其中， 在所述采用等离子增 强化学气相沉积法沉积纳米硅薄膜的过程中， 沉积时间为 20秒 -30分钟。
8、 根据权利要求 4-7任一所述的制备方法， 其中， 所述沉积的纳米硅薄 膜的厚度为 30-100nm。
9、 根据权利要求 4-8任一所述的制备方法， 其中， 所述沉积的纳米硅薄 膜中的纳米硅的粒度为 l-40nm, 平均粒度为 l-20nm。
10、 根据权利要求 1-9任一所述的制备方法， 其中， 所述将所述纳米硅 薄膜晶化形成低温多晶硅薄膜的步骤包括：
采用准分子激光退火法、 固相晶化法或金属诱导横向晶化法将所述纳米 硅薄膜晶化形成低温多晶硅薄膜。
11、根据权利要求 10所述的制备方法， 其中， 在所述将所述纳米硅薄膜 晶化形成低温多晶硅薄膜的步骤为采用准分子激光退火法将所述纳米硅薄膜 晶化形成低温多晶硅薄膜的情况下， 激光脉沖频率为 200-400HZ, 激光能量 密度为 240-250mJ/cm2。
12、一种薄膜晶体管的制备方法， 包括采用如权利要求 1-11任一项所述 的低温多晶硅薄膜的制备方法制备作为有源层的低温多晶硅薄膜。
13、一种低温多晶硅薄膜， 通过权利要求 1-11任一项所述的方法制备而 成的。
14、 一种薄膜晶体管， 包括权利要求 13所述的低温多晶硅薄膜。
15、 一种显示面板， 包括如权利要求 14所述的薄膜晶体管。
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