WO2014146358A1 - 阵列基板、阵列基板的制造方法及显示装置 - Google Patents

阵列基板、阵列基板的制造方法及显示装置 Download PDF

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Publication number
WO2014146358A1
WO2014146358A1 PCT/CN2013/077051 CN2013077051W WO2014146358A1 WO 2014146358 A1 WO2014146358 A1 WO 2014146358A1 CN 2013077051 W CN2013077051 W CN 2013077051W WO 2014146358 A1 WO2014146358 A1 WO 2014146358A1
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Prior art keywords
layer
gate
signal line
via hole
line
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English (en)
French (fr)
Inventor
郭建
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/387,504 priority Critical patent/US9929183B2/en
Publication of WO2014146358A1 publication Critical patent/WO2014146358A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Array substrate method of manufacturing array substrate, and display device
  • Embodiments of the present invention relate to an array substrate, a method of fabricating an array substrate, and a display device. Background technique
  • the main structure of the thin film transistor liquid crystal display includes an array substrate and a color filter substrate which are sandwiched together and sandwiched between the liquid crystals, and the gate lines and the data lines are formed on the array substrate. And a plurality of pixel units arranged in a matrix, wherein each of the pixel units is provided with a thin film transistor, a pixel electrode, and the like.
  • FIG. 1 is a cross-sectional view showing the structure of an array substrate obtained during each process step of forming an array substrate according to the prior art array substrate manufacturing method. As shown in FIG. 1, the array substrate according to the prior art is used.
  • the manufacturing method specifically includes:
  • Step S101 forming a gate electrode 1 and a gate line 2;
  • a gate metal material is deposited on the substrate, and the gate electrode 1 and the gate line 2 are formed by a patterning process using a mask, as shown in Fig. 1A.
  • Step S102 forming a gate insulating layer 3 and an active layer 4;
  • An insulating material is deposited over the gate electrode 1 and the gate line 2 to form a gate insulating layer 3, and a semiconductor layer is deposited on the gate insulating layer 3, and an active layer 4 over the gate electrode 1 is formed by a patterning process using a mask. , as shown in Figure 1B.
  • Step S103 forming a pixel electrode 6
  • a transparent conductive film is deposited over the active layer 4 and the transparent conductive film is patterned by a patterning process using a mask to form a pixel electrode 6, as shown in Fig. 1C.
  • Step S104 forming a gate insulating layer via 9 for electrically connecting the gate line and the signal line.
  • a gate insulating layer via 9 is formed at a position corresponding to a signal line to be formed by the gate insulating layer 3 by a patterning process using a mask, so that a subsequently formed signal line passes through the gate insulating layer via 9 and the gate line 2 Connection, as shown in Figure 1D.
  • Step S105 depositing a metal layer to form a signal line 5 and a source 51 and a drain 52.
  • the patterning process of the board forms the source 51 and the drain 52 over the gate electrode 1 and the active layer 4, and the drain 52 is connected to the pixel electrode 6, and needs to be formed above the gate line 2 while forming the source and drain electrodes.
  • the signal line 5, and the signal line 5 is electrically connected to the gate line 2 through the gate insulating via 9 as shown in FIG. 1E.
  • Step S106 forming a passivation layer 7 on the source/drain electrode, and patterning the passivation layer 7 by a patterning process using a mask to form a passivation layer via 10 for electrically connecting the common electrode and the signal line. As shown in Figure 1F.
  • Step S107 depositing a common electrode layer on the passivation layer 7, and performing patterning processing by a patterning process using a mask to form the common electrode 8, and passing the common electrode 8 through the passivation layer via 10 and the signal line 5 Connected so that the gate line 2, the signal line 5 and the common electrode 8 are interconnected as shown in FIG. 1G.
  • the patterning process using the mask includes a photoresist coating, exposure of the photoresist by the mask, development of the photoresist, etching, photoresist stripping, and the like.
  • Embodiments of the present invention provide an array substrate, a method of manufacturing an array substrate, and a display device, which can reduce the number of masks used compared with the prior art.
  • An embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming a gate line and a gate electrode on a substrate; forming a gate insulating layer over the gate line and the gate electrode; A semiconductor layer and a metal layer are sequentially deposited over the gate insulating layer, and an active layer, a source and a drain over the gate electrode, and a residual semiconductor layer over the gate line and covering the residual are formed by a patterning process a signal line of the semiconductor layer; a patterning process of the signal line, the residual semiconductor layer under the signal line, and the gate insulating layer, forming a via hole, a surface of the gate line, a side section of the signal line, a side cross section of the residual semiconductor layer and a side section of the gate insulating layer are exposed through the via hole; and a lapped conductive layer is formed at a position of the via hole to electrically connect the signal line and the gate line Sexual connection.
  • an array substrate including: a gate line and a gate electrode formed on the substrate; a gate insulating layer covering the gate line and the gate electrode; and the gate insulating layer formed on An active layer, a source and a drain on the layer and above the gate electrode; a residual semiconductor layer formed on the gate insulating layer and above the gate line; a signal line covering the residual semiconductor layer; a via hole formed in the signal line, the residual semiconductor layer, and the gate insulating layer, a sidewall of the via hole causing a side cross section of the gate insulating layer, the signal line, and the residual semiconductor layer Exposed, a bottom surface of the via hole exposes a surface of the gate line; and an overlapping conductive layer formed in the via hole and electrically connecting the signal line to the gate line.
  • 1A-1G are cross-sectional views showing the structure of an array substrate obtained during each process step of forming an array substrate according to the prior art array substrate manufacturing method
  • 2A-2F are cross-sectional views showing the structure of an array substrate obtained during the respective process steps of forming an array substrate in accordance with an embodiment of the present invention. detailed description
  • the array substrate, the method for manufacturing the array substrate, and the display device provided by the embodiments of the present invention may perform a patterning process on the metal layer and the semiconductor layer by using the same mask to form an active layer, a source and a drain, and a signal line covering the residual semiconductor layer. And forming a sidewall of the sidewall exposed signal line and the residual semiconductor layer, and a via hole exposing the surface of the gate line, and then forming a lapped conductive layer electrically connecting the signal line and the gate line in the via hole, thereby not only realizing the signal line Electrical connection to the gate lines and the use of the mask can be reduced.
  • Embodiment 1 Embodiment 1
  • a method for fabricating an array substrate according to Embodiment 1 of the present invention first forming a gate electrode on a substrate
  • the patterning process forms the active layer 4 and the source 51 and the drain 52 over the gate electrode 1, and the signal line 5 over the gate line 2 and covering the residual semiconductor layer 401; and the signal line 5, located below the signal line
  • the residual semiconductor layer 401 and the gate insulating layer 3 are subjected to a via forming process to form the via hole 11 such that the sidewall of the via hole 11 exposes the side section of the signal line 5 and the side section of the semiconductor layer 401, and the bottom surface exposes the surface of the gate line 2.
  • a lapped conductive layer for electrically connecting the signal line 5 and the gate line 2 is formed at the position of the via hole 11.
  • the metal layer and the semiconductor layer may be patterned by the same mask to form an active layer, a source and a drain, and a signal line covering the residual semiconductor layer, and then the sidewall is exposed to the signal line and the residual a side cross section of the semiconductor layer, the bottom surface exposing the via hole on the surface of the gate line, and then forming a lapped conductive layer electrically connecting the signal line and the gate line in the via hole, not only capable of electrically connecting the signal line and the gate line, but also capable of electrically connecting the signal line and the gate line Reduce the use of the reticle.
  • the method for fabricating an array substrate according to an embodiment of the present invention includes the following steps:
  • Step S301 performing a first patterning process using the first mask to form the gate electrode 1 and the gate line
  • the first patterning process may be performed by using the first mask to form the gate electrode 1 and the gate line 2. As shown in Figure 2A.
  • Step S302 On the basis of completing the patterning process of step S301, a gate insulating layer, a semiconductor layer and a metal layer are sequentially deposited.
  • a plasma enhanced chemical vapor deposition method may be employed, a gate insulating layer 3 is deposited on the gate electrode 1 and the gate line 2, and then a semiconductor layer is deposited on the gate insulating layer 3.
  • the semiconductor layer is not patterned at this time, but the metal layer is directly deposited by magnetron sputtering or thermal evaporation, and then the process proceeds to step S303.
  • Step S303 performing a second patterning process using the second mask to form the active layer 4, the source 51, the drain 52, and the signal line 5.
  • the active layer 4, the source 51, and the drain 52 over the gate electrode 1 are formed, and at the same time, the signal line 5 is formed over the gate line 2, in the embodiment of the present invention
  • the semiconductor layer and the metal layer are patterned once by using the same mask. Therefore, in the embodiment of the present invention, the etched part of the semiconductor layer remains under the signal line 5, the source 51 and the drain 52, and the active layer 4 itself It is necessary to be under and in contact with the source 51 and the drain 52.
  • the signal line 5 covers a portion of the semiconductor layer. This embodiment of the present invention refers to the portion of the semiconductor layer as the residual semiconductor layer 401.
  • Step S304 performing a third patterning process using the third mask to form a side section of the sidewall exposed signal line 5 and a side section of the residual semiconductor layer 401, and the bottom surface exposes the via hole 11 of the gate line 2.
  • the signal line 5, the residual semiconductor layer 401, and the gate insulating layer 3 are patterned to form vias 11, and the sidewalls of the vias 11 are exposed to the side sections and residuals of the signal lines 5.
  • the side surface of the semiconductor 401, the bottom surface of which exposes the upper surface of the gate line 2, enables subsequent use of the electrical connection gate line 2 and the signal line 5.
  • the sidewall exposed signal line 5 may be formed at a position where the via hole 11 is pre-formed while the active layer 4, the source and drain electrodes 51, and the signal line 5 are formed by the second patterning process.
  • the bottom surface exposes the accommodating space 110 on the surface of the gate insulating layer 3, as shown in FIG. 2B.
  • the gate insulating layer at the exposed position of the accommodating space 110 is subjected to a third patterning process.
  • a gate insulating layer via 9 is formed on the surface of the bottom exposed gate line 2. As shown in FIG. 2C, the accommodating space 110 and the gate insulating via 9 together constitute the via 11.
  • the subsequent process of forming the gate insulating via 9 is directly to the gate insulating layer.
  • the patterning process of a single film layer allows for more precise control of via size and process uniformity.
  • Step S305 performing a fourth patterning process using the fourth mask to form the pixel electrode 6, and simultaneously forming the overlapping conductive layer 12 of the electrical connection signal line 5 and the gate line 2.
  • the lap conductive layer 12 is made of the same conductive material as the pixel electrode 6, and the lap conductive layer 12 is formed while forming the pixel electrode 6.
  • a transparent conductive film may be deposited on the array substrate that completes the above steps, and a fourth patterning process is performed by using the fourth mask to form a pixel electrode connected to the drain, and the electrical connection signal line 5 and the gate are formed.
  • the wire 2 is overlapped with the conductive layer 12 as shown in Fig. 2D.
  • the transparent conductive film forming the pixel electrode 6 and the lap conductive layer 12 may be made of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide, Indium Oxide), or the like. One or more of the metal oxides.
  • the conductive film may be filled only in the via hole, and the signal line 5 exposed by the sidewall of the via hole and the gate line 2 exposed by the bottom surface are electrically turned on without using a mask.
  • a conductive film may be deposited on the signal line 5 and in the via hole to form the electrically conductive signal line 5 and the overlapping conductive layer 12 of the gate line 2, so that the electrical connection between the two is further improved. stable.
  • Step S306 performing a fifth patterning process using the fifth mask to form a passivation layer 7 including the passivation layer via 10.
  • a passivation layer is deposited on the basis of the above-mentioned patterning process, and a passivation layer 7 including a passivation layer via 10 is formed by a patterning process using a fifth mask.
  • the passivation layer via 10 is located above the corresponding position of the signal line 5, and the bottom surface exposes the surface of the signal line 5, as shown in FIG. 2E.
  • Step S307 performing a sixth patterning process through the sixth mask to form the common electrode 8 on the passivation layer 7, and the common electrode 8 and the signal line 5 are electrically connected through the passivation layer via 10, as shown in FIG. 2F. .
  • a patterning process of a gate line and a gate electrode is performed, and then a gate insulating layer, a semiconductor layer, and a metal layer are deposited, and a patterning process is performed by using the same mask to form an active layer and Signal lines, etc., reduce the use of the mask.
  • the embodiment of the present invention in the prior art, it is required to form a via hole corresponding to the gate line, first forming an accommodating space in which the sidewall exposes the active layer and the signal line, and the bottom surface exposes the gate insulating layer, and then Performing a single film via formation process on the gate insulating layer to form a gate insulating layer via hole on the bottom exposed gate line, and reducing the number of mask plates on the basis of retaining the existing single film layer etching process, and realizing The signal line and the gate line are connected.
  • the lapped conductive layer located at the same layer as the pixel electrode is formed, and the number of the reticle can be reduced, and the manufacturing process step can be reduced.
  • the second embodiment of the present invention further provides an array substrate manufactured by the manufacturing method of the above embodiment, the array substrate comprising: a gate line 2 and a gate electrode 1 formed on the substrate; a gate covering the gate line 2 and the gate electrode 1 An insulating layer 3; an active layer 4 and a source 51 and a drain 52 formed on the gate insulating layer 3 and above the gate electrode 2; a residual semiconductor layer 401 formed on the gate insulating layer 3 and above the gate line, and a signal line 5 covering the residual semiconductor layer 401; and a signal line 5, a residual semiconductor layer 401 and the gate insulating layer 3 further have a side cross section of the sidewall exposed signal line 5 and a side cross section of the residual semiconductor layer 401, the bottom surface exposing the via hole 11 on the surface of the gate line 2; the via hole 11 is formed with the signal line 5 and the gate
  • the wire 2 is electrically connected to the overlapping conductive layer 12.
  • the via hole 11 in the embodiment of the present invention may include the accommodating space 110 and the gate insulating layer via hole 9, wherein the accommodating space 110 is formed by the patterning process by the signal line 5 and the residual semiconductor layer 401, and the sidewall is exposed to the signal.
  • the line 5 and the residual semiconductor layer 401, the bottom surface exposes the surface of the gate insulating layer 3; the gate insulating layer via 9 is formed by the gate insulating layer 3 through a via forming process, and the bottom surface exposes the surface of the gate line 2.
  • the overlapping conductive layer 12 is a metal thin film partially located in the via hole 11 and partially located above the signal line 5.
  • the array substrate further includes a pixel electrode 6 connected to the drain, and the overlapping conductive layer 12 is located in the same layer as the pixel electrode 6.
  • the embodiment of the present invention further includes a passivation layer formed on the pixel electrode, the lapped conductive layer, the signal line, or the like; at the position of the corresponding signal line 5 on the passivation layer, the bottom surface has the surface of the signal line 5 exposed a passivation layer via 10; and a common electrode 8 electrically connected to the signal line 5 through the passivation layer via 10.
  • FIG. 2F A cross-sectional structural view of an array substrate provided by an embodiment of the present invention can be seen in FIG. 2F.
  • the array substrate provided by the embodiment of the present invention has a residual semiconductor layer above the gate line and below the signal line. Therefore, in the manufacturing process, the same mask can be used to perform a patterning process to form the active layer, the source, the drain, and the signal line. , reducing the use of masks and increasing product capacity.
  • Embodiment 3 of the present invention also provides a display device including the array substrate according to Embodiment 2 of the present invention.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color film substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • the display device is an organic electroluminescent display device in which each operation of the array substrate is performed.
  • the array substrate included in the display device provided by the third embodiment of the present invention has a residual semiconductor layer above the gate line and below the signal line. Therefore, in the manufacturing process, the same mask can be used to perform a patterning process to form the active layer and the source. , drain and signal lines, which reduce the use of the reticle and increase product throughput.
  • the spirit and scope of the invention Thus, it is intended that the present invention cover the modifications and the modifications of the invention

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  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

本发明的实施例公开了一种阵列基板、阵列基板的制造方法及显示装置，该阵列基板的制造方法包括：在基板上形成栅线和栅电极；在所述栅线和所述栅电极上方形成栅绝缘层；在所述栅绝缘层上方依次沉积半导体层和金属层，采用一次构图工艺形成位于所述栅电极上方的有源层、源极和漏极，以及位于所述栅线上方的残余半导体层和覆盖所述残余半导体层的信号线；对所述信号线、位于信号线下方的残余半导体层以及所述栅绝缘层进行构图工艺，形成过孔，使所述栅线的表面、所述信号线的侧断面、所述残余半导体层的侧断面以及所述栅绝缘层的侧断面通过所述过孔暴露；以及在所述过孔的位置处形成搭接导电层，使所述信号线与所述栅线电性连接。

Description

阵列基板、 阵列基板的制造方法及显示装置 技术领域
本发明的实施例涉及一种阵列基板、 阵列基板的制造方法及显示装置。 背景技术
薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display, 筒 称 TFT-LCD )的主体结构包括对盒在一起并将液晶夹设其间的阵列基板和彩 膜基板， 阵列基板上形成有栅线、 数据线以及以矩阵方式排列的多个像素单 元， 其中每个像素单元中设置有薄膜晶体管和像素电极等。
示例性地， 图 1示出了按照现有技术的阵列基板制造方法在形成阵列基 板的各工艺步骤期间得到的阵列基板的结构截面图， 如图 1所示， 根据现有 技术的阵列基板的制造方法具体包括：
步骤 S101: 形成栅电极 1和栅线 2;
在基板上沉积栅极金属材料， 并通过利用掩模板的构图工艺形成栅电极 1和栅线 2, 如图 1A所示。
步骤 S102: 形成栅绝缘层 3和有源层 4;
在栅电极 1和栅线 2之上沉积绝缘材料而形成栅绝缘层 3 , 并在栅绝缘 层 3上沉积半导体层， 并通过利用掩模板的构图工艺形成位于栅电极 1上方 的有源层 4, 如图 1B所示。
步骤 S103: 形成像素电极 6;
在有源层 4上方沉积透明导电薄膜并通过利用掩模板的构图工艺对该透 明导电薄膜进行图案化处理， 形成像素电极 6, 如图 1C所示。
步骤 S104: 形成用于电性连接栅线与信号线的栅绝缘层过孔 9。
通过利用掩模板的构图工艺， 在栅绝缘层 3对应待形成信号线的位置处 形成栅绝缘层过孔 9,以使后续形成的信号线通过该栅绝缘层过孔 9与栅线 2 电性连接， 如图 1D所示。
步骤 S105: 沉积金属层， 形成信号线 5和源极 51、 漏极 52。
在形成有栅绝缘层过孔 9的栅绝缘层上方沉积金属层， 并通过利用掩模 板的构图工艺形成位于栅电极 1和有源层 4之上的源极 51和漏极 52, 并且 漏极 52与像素电极 6连接，在形成源漏极的同时还需要形成位于栅线 2上方 的信号线 5 , 并且信号线 5通过栅绝缘层过孔 9与栅线 2电性连接， 如图 1E 所示。
步骤 S106: 在源漏电极上形成钝化层 7, 并通过利用掩模板的构图工艺 对钝化层 7进行图案化处理， 形成用于电连接公共电极与信号线的钝化层过 孔 10, 如图 1F所示。
步骤 S107: 在钝化层 7上沉积公共电极层， 并通过利用掩模板的构图工 艺进行图案化处理， 形成公共电极 8, 并使公共电极 8通过钝化层过孔 10与 信号线 5电性连通， 从而使得栅线 2、 信号线 5与公共电极 8实现互联， 如 图 1G所示。
这里， 利用掩模板的构图工艺包括光刻胶涂覆、 利用掩模板对光刻胶进 行曝光、 显影光刻胶、 刻蚀、 光刻胶剥离等工艺。
在现有的上述阵列基板的制造方法中， 通过在栅绝缘层上形成通孔， 然 后沉积金属层， 使得栅线和信号线实现电性连接， 随后再进行源漏极、 钝化 层等的构图工艺， 需要使用七次掩模板进行图案化处理， 而过多的使用掩模 板， 将会严重影响产量，使得成本增加和工艺复杂， 并且还会导致良率降低。 发明内容
本发明实施例提供了一种阵列基板、 阵列基板的制造方法及显示装置， 相对于现有技术， 能够减少所采用的掩模板的数量。
本发明的实施例一方面提供了一种阵列基板的制造方法， 该方法包括： 在基板上形成栅线和栅电极； 在所述栅线和所述栅电极上方形成栅绝缘层； 在所述栅绝缘层上方依次沉积半导体层和金属层， 采用一次构图工艺形成位 于所述栅电极上方的有源层、 源极和漏极， 以及位于所述栅线上方的残余半 导体层和覆盖所述残余半导体层的信号线； 对所述信号线、 位于信号线下方 的残余半导体层以及所述栅绝缘层进行构图工艺， 形成过孔， 使所述栅线的 表面、 所述信号线的侧断面、 所述残余半导体层的侧断面以及所述栅绝缘层 的侧断面通过所述过孔暴露； 以及在所述过孔的位置处形成搭接导电层， 使 所述信号线与所述栅线电性连接。 本发明实施例的另一方面还提供了一种阵列基板， 包括： 形成在基板上 的栅线和栅电极； 覆盖所述栅线和所述栅电极的栅绝缘层； 形成在所述栅绝 缘层上并位于所述栅电极上方的有源层、 源极和漏极； 形成在所述栅绝缘层 上并位于所述栅线上方的残余半导体层； 覆盖所述残余半导体层的信号线； 形成在所述信号线、 所述残余半导体层和所述栅绝缘层中的过孔， 所述过孔 的侧壁使所述栅绝缘层、 所述信号线和所述残余半导体层的侧断面暴露， 所 述过孔的底面使所述栅线的表面暴露； 以及形成在所述过孔内且使所述信号 线与所述栅线电性连接的搭接导电层。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1A-图 1G示出了按照现有技术的阵列基板制造方法在形成阵列基板 的各工艺步骤期间得到的阵列基板的结构截面图；
图 2A-图 2F示出了根据本发明实施例的阵列基板制造方法在形成阵列基 板的各工艺步骤期间得到的阵列基板的结构截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供的阵列基板、 阵列基板的制造方法及显示装置， 对金 属层和半导体层可采用同一掩模板进行一次构图工艺， 形成有源层、 源漏极 以及覆盖残余半导体层的信号线， 然后形成侧壁暴露信号线和残余半导体层 的侧断面、 底面暴露栅线表面的过孔， 接着在过孔内形成电性连接信号线和 栅线的搭接导电层， 不仅能够实现信号线与栅线的电性连接， 而且能够减少 掩模板的使用。 实施例一
本发明实施例一提供的阵列基板的制造方法， 首先在基板上形成栅电极
1和栅线 2, 并在栅线 2和栅电极 1上方形成栅绝缘层 3; 然后在栅绝缘层 3 上方依次沉积半导体层和金属层， 并对半导体层和金属层采用同一掩模板进 行一次构图工艺形成位于栅电极 1上方的有源层 4和源极 51和漏极 52, 以 及位于栅线 2上方并覆盖残余半导体层 401的信号线 5;再对信号线 5、位于 信号线下方的残余半导体层 401以及栅绝缘层 3进行过孔形成工艺以形成过 孔 11 ,并使过孔 11的侧壁暴露信号线 5的侧断面和半导体层 401的侧断面， 底面暴露栅线 2的表面；最后在过孔 11位置处形成使信号线 5与栅线 2电性 连接的搭接导电层。
在本发明的实施例中， 对金属层和半导体层可采用同一掩模板进行一次 构图工艺， 形成有源层、 源漏极以及覆盖残余半导体层的信号线， 然后形成 侧壁暴露信号线和残余半导体层的侧断面， 底面暴露栅线表面的过孔， 接着 在过孔内形成电性连接信号线和栅线的搭接导电层， 不仅能够实现信号线与 栅线的电性连接， 而且能够减少掩模板的使用。
下面， 结合附图 2A-2F对根据本发明实施例的阵列基板的制造方法进行 详细说明， 根据本发明实施例的阵列基板的制造方法包括以下步骤：
步骤 S301 : 采用第一掩模板进行第一次构图工艺， 形成栅电极 1和栅线
2。
示例性地， 本发明实施例中在基板上采用磁控溅射或热蒸发方法沉积栅 极金属薄膜后， 可利用第一掩模板进行第一次构图工艺， 形成栅电极 1和栅 线 2, 如图 2A所示。
步骤 S302: 在完成步骤 S301的构图工艺的基础上，依次沉积栅绝缘层、 半导体层和金属层。
示例性地，本发明实施例中可采用例如等离子体增强化学气相沉积方法， 在栅电极 1和栅线 2上沉积形成栅绝缘层 3 , 然后在栅绝缘层 3上沉积半导 体层， 本发明实施例中此时并不对半导体层进行构图工艺， 而是直接采用磁 控溅射或热蒸发方法沉积金属层， 然后转入步骤 S303。
步骤 S303: 采用第二掩模板进行第二次构图工艺， 形成有源层 4、 源极 51、 漏极 52和信号线 5。 示例性地， 在第二次构图工艺中， 形成位于栅电极 1上方的有源层 4、 源极 51和漏极 52,并同时在栅线 2上方形成信号线 5,本发明实施例中由于 采用同一掩模板对半导体层和金属层进行一次构图工艺， 因此本发明实施例 中在信号线 5、 源极 51和漏极 52下方都会保留有刻蚀后的部分半导体层， 有源层 4本身就需要位于源极 51和漏极 52下方并与之接触。 而本发明实施 例中与现有技术不同的是， 信号线 5会覆盖部分半导体层， 本发明实施例将 这部分的半导体层称为残余半导体层 401。
步骤 S304: 采用第三掩模板进行第三次构图工艺， 形成侧壁暴露信号线 5的侧断面和残余半导体层 401的侧断面， 底面暴露栅线 2的过孔 11。
示例性地， 本发明实施例中需对信号线 5、 残余半导体层 401以及栅绝 缘层 3进行构图工艺， 形成过孔 11 , 并使过孔 11的侧壁暴露信号线 5的侧 断面和残余半导体 401的侧断面， 底面暴露栅线 2的上表面， 以使后续能够 用于电性联通栅线 2和信号线 5。
备选地， 本发明实施例中可在利用第二次构图工艺形成有源层 4、 源漏 极 51和信号线 5的同时， 在预形成过孔 11的位置处形成侧壁暴露信号线 5 的侧断面和半导体层 401 的侧断面， 底面暴露栅绝缘层 3 表面的容置空间 110, 如图 2B所示； 然后对容置空间 110暴露位置处的栅绝缘层进行第三次 构图工艺， 形成底面暴露栅线 2表面的栅绝缘层过孔 9, 如图 2C所示， 容置 空间 110和栅绝缘层过孔 9一起组成过孔 11。
采用上述备选方案， 后续形成栅绝缘层过孔 9的过程是直接对栅绝缘层
3进行的单一膜层的构图工艺， 因此能更精确控制过孔的尺寸和工艺均匀性。
步骤 S305: 采用第四掩模板进行第四次构图工艺， 形成像素电极 6, 同 时形成电性连接信号线 5与栅线 2的搭接导电层 12。
备选地，本发明实施例中搭接导电层 12采用与形成像素电极 6相同的导 电材料， 在形成像素电极 6的同时形成该搭接导电层 12。 示例性地， 可在完 成上述步骤的阵列基板上沉积透明导电薄膜， 利用第四掩模板进行第四次构 图工艺， 形成与漏极连接的像素电极的同时， 形成电性连接信号线 5和栅线 2的搭接导电层 12, 如图 2D所示。
示例性地，形成像素电极 6和搭接导电层 12的透明导电薄膜可以由 ITO ( Indium Tin Oxide, 氧化铟锡） 、 IZO ( Indium Zinc Oxide, 氧化铟辞）等 金属氧化物中的一种或多种构成。
示例性地， 本发明实施例中可也可仅在过孔内填充导电薄膜， 使过孔侧 壁暴露出的信号线 5和底面暴露出的栅线 2电性导通， 而无需使用掩模板。 当然本发明实施例还可在信号线 5的上方以及过孔内均沉积导电薄膜， 形成 电性连接信号线 5和栅线 2的搭接导电层 12,使二者之间的电性连接更稳定。
步骤 S306: 采用第五掩模板进行第五次构图工艺， 形成包含有钝化层过 孔 10的钝化层 7。
示例性地， 本发明实施例中可在完成上述构图工艺的基础上， 沉积一层 钝化层，并通过利用第五掩模板的构图工艺形成包括钝化层过孔 10的钝化层 7, 本发明实施例中钝化层过孔 10位于信号线 5对应位置上方， 并且底面暴 露出信号线 5的表面， 如图 2E所示。
步骤 S307: 通过第六掩模板进行第六次构图工艺， 形成公共电极 8于钝 化层 7之上， 公共电极 8与信号线 5通过钝化层过孔 10电性连接， 如图 2F 所示。
本发明实施例中上述形成阵列基板的方法， 首先进行栅线和栅电极的构 图工艺， 然后进行栅绝缘层、 半导体层和金属层的沉积， 并利用同一掩模板 进行构图工艺形成有源层和信号线等， 减少了掩模板的使用。
备选地， 本发明实施例中在现有技术中需要形成对应于栅线的过孔的位 置处， 先形成侧壁暴露有源层和信号线、 底面暴露栅绝缘层的容置空间， 然 后对栅绝缘层进行单膜层过孔形成工艺而形成底面暴露栅线的栅绝缘层过 孔， 在保留现有的单膜层刻蚀工艺的基础上， 实现掩模板数量的减少， 并能 够实现信号线和栅线的连通。 同时， 本发明实施例中在形成像素电极的同时 形成与其位于同一层的搭接导电层， 还可在减少掩模板数量的同时， 减少制 造工艺步骤。
实施例二
本发明实施例二还提供了一种应用上述实施例的制造方法制造的阵列基 板， 该阵列基板包括： 形成在基板上的栅线 2和栅电极 1; 覆盖栅线 2和栅 电极 1的栅绝缘层 3; 形成在栅绝缘层 3上并位于栅电极 2上方的有源层 4 和源极 51和漏极 52; 形成在栅绝缘层 3上并位于栅线上方的残余半导体层 401 , 以及覆盖残余半导体层 401的信号线 5; 并且信号线 5、 残余半导体层 401以及栅绝缘层 3上还具有侧壁暴露信号线 5的侧断面和残余半导体层 401 的侧断面， 底面暴露栅线 2表面的过孔 11; 过孔 11内形成有使信号线 5与 栅线 2电性连接的搭接导电层 12。
备选地，本发明实施例中过孔 11可包括容置空间 110和栅绝缘层过孔 9, 其中容置空间 110由信号线 5和残余半导体层 401通过构图工艺形成， 并且 侧壁暴露信号线 5和残余半导体层 401、 底面暴露栅绝缘层 3表面； 栅绝缘 层过孔 9由栅绝缘层 3通过过孔形成工艺形成， 并且底面暴露栅线 2表面。
进一步地， 本发明实施例中搭接导电层 12为部分位于过孔 11内以及部 分位于信号线 5上方的金属薄膜。
备选地， 本发明实施例中阵列基板还包括与漏极相连的像素电极 6, 且 搭接导电层 12与像素电极 6位于同一层。
进一步地， 本发明实施例还包括形成于像素电极、 搭接导电层和信号线 等之上的钝化层； 钝化层上对应信号线 5的位置处， 具有底面暴露出信号线 5表面的钝化层过孔 10;以及通过钝化层过孔 10与信号线 5电性连接的公共 电极 8。
本发明实施例提供的阵列基板的截面结构图可参见图 2F。
本发明实施例提供的阵列基板， 在栅线上方且信号线下方具有残余半导 体层， 因此在制造过程中，可采用同一掩模板进行一次构图工艺形成有源层、 源极、 漏极和信号线， 减少了掩模板的使用， 提升了产品产能。
实施例三
本发明的实施例三还提供了一种显示装置， 其包括根据本发明实施例二 的阵列基板。
该显示装置的一个示例为液晶显示装置， 其中， 阵列基板与对置基板彼 此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜 基板。 阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转 的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示装置还包括 为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置， 其中阵列基板的每 示操作。 本发明实施例三提供的显示装置中包括的阵列基板， 在栅线上方且信号 线下方具有残余半导体层， 因此在制造过程中， 可采用同一掩模板进行一次 构图工艺形成有源层、 源极、 漏极和信号线， 从而减少了掩模板的使用， 提 升了产品产能。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、 一种阵列基板的制造方法， 包括：
在基板上形成栅线和栅电极；
在所述栅线和所述栅电极上方形成栅绝缘层；
在所述栅绝缘层上方依次沉积半导体层和金属层， 采用一次构图工艺形 成位于所述栅电极上方的有源层、 源极和漏极， 以及位于所述栅线上方的残 余半导体层和覆盖所述残余半导体层的信号线；
对所述信号线、 位于所述信号线下方的残余半导体层以及所述栅绝缘层 进行构图工艺， 形成过孔， 使所述栅线的表面、 所述信号线的侧断面、 所述 残余半导体层的侧断面以及所述栅绝缘层的侧断面通过所述过孔暴露； 以及 在所述过孔的位置处形成搭接导电层， 使所述信号线与所述栅线电性连 接。
2、 如权利要求 1所述的方法， 其中形成所述过孔包括：
形成所述有源层、 源极和漏极的同时， 形成暴露所述信号线的侧断面、 所述位于信号线下方的残余半导体层的侧断面以及所述栅绝缘层的表面的容 置空间；
对所述栅绝缘层的被暴露的表面进行构图工艺， 形成暴露所述栅线的表 面的栅绝缘层过孔。
3、 如权利要求 1或 2所述的方法， 其中形成所述搭接导电层包括： 在所述过孔内以及所述信号线的上方沉积导电薄膜， 形成电性连接所述 信号线与所述栅线的搭接导电层。
4、 如权利要求 3所述的方法， 其中形成所述搭接导电层包括： 沉积透明导电薄膜， 通过构图工艺形成像素电极和所述搭接导电层， 所 述像素电极与所述漏极连接， 所述搭接导电层电性连接所述信号线与所述栅 线。
5、如权利要求 4所述的方法，其中形成所述像素电极和所述搭接导电层 之后， 该方法还包括：
沉积钝化层薄膜， 通过构图工艺形成钝化层过孔， 所述钝化层过孔位于 所述信号线的对应位置处， 且底面暴露出所述信号线的表面。
6、如权利要求 5所述的方法， 其中形成所述钝化层过孔后， 该方法还包 括：
在所述钝化层之上形成公共电极， 所述公共电极与所述信号线通过所述 钝化层过孔电性连接。
7、 一种阵列基板， 包括：
形成在基板上的栅线和栅电极；
覆盖所述栅线和所述栅电极的栅绝缘层；
形成在所述栅绝缘层上并位于所述栅电极上方的有源层、 源极和漏极； 形成在所述栅绝缘层上并位于所述栅线上方的残余半导体层；
覆盖所述残余半导体层的信号线；
形成在所述信号线、 所述残余半导体层和所述栅绝缘层中的过孔， 所述 过孔的侧壁使所述栅绝缘层、所述信号线和所述残余半导体层的侧断面暴露， 所述过孔的底面使所述栅线的表面暴露； 以及
形成在所述过孔内且使所述信号线与所述栅线电性连接的搭接导电层。
8、 如权利要求 7所述的阵列基板， 其中所述过孔包括：
暴露所述信号线和所述残余半导体层的侧断面， 并暴露所述栅绝缘层的 表面的容置空间； 和
通过对所述栅绝缘层实施的过孔形成工艺形成并暴露所述栅线的表面的 栅绝缘层过孔。
9、如权利要求 7或 8所述的阵列基板，其中所述搭接导电层为部分位于 所述过孔内以及部分位于所述信号线上方的导电薄膜。
10、 如权利要求 9所述的阵列基板， 其中该阵列基板还包括与漏极相连 的像素电极， 且所述搭接导电层与所述像素电极位于同一层。
11、 如权利要求 7所述的阵列基板， 还包括：
钝化层；
形成在所述钝化层中对应于所述信号线的位置处且底面暴露出所述信号 线的表面的钝化层过孔； 以及
通过所述钝化层过孔与所述信号线电性连接的公共电极。
12、 一种显示装置， 包括：
如权利要求 7-11任一项所述的阵列基板； 对置基板， 与所述阵列基板对置,
PCT/CN2013/077051 2013-03-19 2013-06-09 阵列基板、阵列基板的制造方法及显示装置 Ceased WO2014146358A1 (zh)

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