WO2013044760A1 - Tft阵列基板及其制造方法和显示装置 - Google Patents

Tft阵列基板及其制造方法和显示装置 Download PDF

Info

Publication number
WO2013044760A1
WO2013044760A1 PCT/CN2012/081771 CN2012081771W WO2013044760A1 WO 2013044760 A1 WO2013044760 A1 WO 2013044760A1 CN 2012081771 W CN2012081771 W CN 2012081771W WO 2013044760 A1 WO2013044760 A1 WO 2013044760A1
Authority
WO
WIPO (PCT)
Prior art keywords
drain
layer
source
barrier layer
metal
Prior art date
Application number
PCT/CN2012/081771
Other languages
English (en)
French (fr)
Inventor
刘翔
薛建设
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/703,499 priority Critical patent/US9305942B2/en
Publication of WO2013044760A1 publication Critical patent/WO2013044760A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

Definitions

  • TFT array substrate manufacturing method thereof and display device
  • Embodiments of the present invention relate to a TFT array substrate, a method of fabricating the same, and a display device. Background technique
  • the TFT-LCD is a display that displays an image by changing the intensity of the electric field applied to the liquid crystal layer, changing the degree of rotation of the liquid crystal molecules, and thereby controlling the intensity of the light transmission.
  • a TFT-LCD display panel includes a backlight module, a polarizer, a color filter substrate, a TFT array substrate, and a liquid crystal molecular layer between the color filter substrate and the TFT array substrate.
  • TFT-LCD has achieved rapid development.
  • the TFT-LCD uses a higher frequency drive circuit.
  • the charging time of the TFT-LCD is shorter, and thus a semiconductor material having a high mobility is required.
  • the delay of the image signal is also one of the key factors restricting the display effect of the large-size, high-resolution TFT-LCD. Therefore, a low-resistance metal material Cu is usually used in the TFT array substrate to form a data line.
  • the existing process for fabricating a TFT array substrate includes: sequentially forming a gate line, a gate, a gate insulating layer, and a semiconductor active layer on the substrate; in order to prevent metal material from being generated on the semiconductor active layer in subsequent fabrication of the source and the drain Contamination, a protective layer having via holes is formed on the semiconductor active layer; a source and a drain connected to the semiconductor active layer through the via holes are formed on the protective layer.
  • a patterning process is added due to the formation of the protective layer, which lowers the production efficiency of the TFT array substrate and increases the production cost.
  • An embodiment of the present invention provides a thin film transistor (TFT) array substrate including: a base substrate; a gate line, a gate, a gate insulating layer, and a semiconductor active layer formed on the base substrate; a metal barrier layer formed on the semiconductor active layer, the metal barrier layer covering the semiconductor active layer; a source and a drain formed on the metal barrier layer, and a source and a drain formed between the source and the drain a metal oxide portion having a source and a drain insulated from each other; and a protective layer formed on the gate insulating layer and the source and drain, wherein the metal oxide portion is formed by an oxidized metal barrier layer The portion is formed between the source and the drain.
  • TFT thin film transistor
  • a display device including a TFT array substrate, the TFT array substrate including: a base substrate; a gate line, a gate, a gate insulating layer, and a semiconductor active formed on the base substrate a metal barrier layer formed on the semiconductor active layer, the metal barrier layer covering the semiconductor active layer; a source and a drain formed on the metal barrier layer, the source and drain Forming a metal oxide portion insulating the source and the drain from each other; and a protective layer formed on the gate insulating layer and the source and drain, wherein the metal oxide portion It is formed by oxidizing a portion of the metal barrier layer between the source and the drain.
  • a further embodiment of the present invention provides a method of fabricating a thin film transistor (TFT) array substrate, comprising: forming a gate line and a gate on a base substrate; forming on the base substrate and the gate line and the gate a gate insulating layer; forming an active layer on the gate insulating layer; forming a metal barrier layer on the active layer; forming a data metal layer on the metal barrier layer; using a two-tone mask, the data a metal layer, a metal barrier layer, and an active layer perform a patterning process to form a data line, a source, a drain, and a semiconductor active layer, and a metal barrier layer covering the semiconductor active layer; a portion between the source and the drain performs an oxidation process to form a metal oxide portion that insulates the source and drain from each other; and forms a protection on the gate insulating layer and the data lines, the source and the drain Floor.
  • TFT thin film transistor
  • FIG. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram 1 of a substrate structure in a process for fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 3 is a second schematic diagram of a substrate structure in a process for fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 4 is a substrate structure in a process of manufacturing a TFT array substrate according to an embodiment of the present invention. Schematic three;
  • FIG. 5 is a schematic diagram showing a structure of a substrate in a process for fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram 5 of a substrate structure in a process of manufacturing a TFT array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram showing a structure of a substrate in a process of manufacturing a TFT array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 13 is a schematic diagram of a substrate structure in a process of fabricating a TFT array substrate according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram showing the structure of a substrate in a process of fabricating a TFT array substrate according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a TFT array substrate, as shown in FIG.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines cross each other to thereby define Pixel cells arranged in a matrix each of which includes a thin film transistor as a switching element and a pixel electrode for controlling alignment of the liquid crystal.
  • the gate of the thin film transistor of each pixel unit is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • it is mainly performed for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • the TFT array substrate of the embodiment of the present invention includes, for example, a base substrate 11; a gate line (not shown) formed on the base substrate 11, a gate electrode 12, a gate insulating layer 13, and a semiconductor active layer 14; a metal barrier layer 15 having a metal oxide portion 151 formed on the layer 14, a metal barrier layer 15 overlying the semiconductor active layer 14; a source electrode 161 and a drain electrode 162 formed on the metal barrier layer 15, a metal oxide portion 151 is located between the source 161 and the drain 162 which are separated from each other and insulates the source 161 and the drain 162 from each other; the protective layer 18 formed on the gate insulating layer 13 and the source and drain electrodes 161 and 162, the protective layer 18 has The via hole 181 exposing the drain electrode 162; the pixel electrode 19 formed on the protective layer 18 and electrically connected to the drain electrode 162 through the via hole 181.
  • the metal barrier layer 15 and the semiconductor active layer 14 may have, for example, the same area.
  • the metal barrier layer 15 may also have a larger area than the semiconductor active layer 14, but it is ensured that the metal barrier layer 15 can be divided into two parts by a metal oxide to avoid electrical connection between the source and the drain; And the structural connections to other pixels should be avoided.
  • the material of the metal barrier layer 15 may be, for example, titanium (Ti) or an alloy thereof, and the material of the source electrode 161 and the drain electrode 162 may be, for example, copper (Cu), and the material of the pixel electrode 19 may be, for example, oxidation.
  • ITO Indium tin
  • IZO indium oxide
  • the metal barrier layer 15 may be formed of titanium (Ti) or an alloy thereof, but the embodiment of the invention is not limited thereto.
  • other metals may be used to form the metal barrier layer 15 as long as it is capable of undergoing an oxidation reaction to form a metal oxide.
  • a metal barrier layer is formed between the source and the drain and the semiconductor active layer, and oxidation is performed on a portion of the metal barrier layer between the source and the drain.
  • the process forms a metal oxide portion. In this way, contamination of the semiconductor active layer during formation of the source and the drain can be prevented, and the patterning process is not required to be performed on the metal barrier layer. Therefore, the number of patterning processes is reduced and the number of the patterning process is reduced. Production efficiency and production costs are reduced.
  • FIG. 2 to FIG. 14 are schematic diagrams showing the structure of a substrate in each process of a method for fabricating a TFT array substrate according to an embodiment of the present invention.
  • the method for manufacturing a TFT array substrate provided by the embodiment of the present invention includes the following steps.
  • Step S201 forming a gate line and a gate on the base substrate.
  • a gate metal film having a thickness of, for example, 4000 A to 15000 A is deposited on a base substrate 11 of, for example, a glass substrate by, for example, sputtering or evaporation.
  • the gate metal film may be a metal such as chromium, tungsten, copper, titanium, tantalum or molybdenum or an alloy thereof.
  • the gate metal film may be formed of a single layer metal or may be formed of a plurality of layers of metal.
  • the gate electrode 12 and the gate line (not shown in Fig. 2) are formed by performing a patterning process on the gate metal film.
  • the gate electrode 12 and the gate line may be electrically connected to each other or integrally formed.
  • the base substrate 11 such as a glass substrate may also be replaced by a quartz substrate, a plastic substrate or other transparent substrate.
  • Step S202 forming a gate insulating layer on the base substrate and the gate lines and the gate electrodes.
  • a thickness of, for example, 2000 A is deposited on the base substrate 11 and the gate lines and the gate electrodes 12 by, for example, a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 13 is usually made of a material such as an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be silicon hydride, ammonia, and nitrogen or dichlorosilane, ammonia, and nitrogen.
  • Step S203 forming an active layer on the gate insulating layer.
  • a metal oxide active layer 14 having a thickness of, for example, 50 A to 1000 A is deposited on the gate insulating layer 13 by, for example, a sputtering method.
  • the active layer 14 will be formed as a semiconductor active layer after a subsequent patterning process.
  • Step S204 forming a metal barrier layer on the active layer.
  • a metal barrier layer 15 having a thickness of, for example, 50 A - 500 A is deposited on the active layer 14 by, for example, a sputtering method.
  • the metal barrier layer 15 may be formed of titanium (Ti) or an alloy thereof.
  • Step S205 forming a data metal layer on the metal barrier layer.
  • a data metal layer 16 having a thickness of, for example, 1000 A to 5000 A is deposited on the metal barrier layer 15 by, for example, a sputtering method.
  • data metal Layer 16 can be formed of copper (Cu).
  • Step S206 forming a photoresist layer on the data metal layer.
  • a photoresist layer 17 is formed on the data metal layer 16 by, for example, a spin coating method.
  • the photoresist layer 17 is formed of a positive photoresist, but the embodiment of the invention is not limited thereto.
  • Step S207 Perform a photolithography process on the photoresist layer by using a two-tone mask to form a first photoresist pattern.
  • the photoresist layer 17 is exposed using a two-tone mask (including, for example, a gray mask or a semi-transparent mask) 20, and then the exposed light is applied.
  • the engraved layer 17 is developed to form a first photoresist pattern.
  • a photoresist completely remaining region 171, a photoresist half-retained region 172, and a photoresist completely removed region are formed on the base substrate.
  • the photoresist completely reserved region 171 corresponds to the data line, the source and drain regions
  • the photoresist half-retained region 172 corresponds to the region between the source and the drain.
  • the first photoresist pattern (the photoresist including the photoresist completely remaining region 171 and the photoresist half-retained region 172) will be used as an etch mask.
  • Step S208 etching the data metal layer, the metal barrier layer and the active layer by using the first photoresist pattern as a mask.
  • the first photoresist pattern (the photoresist including the photoresist completely remaining region 171 and the photoresist semi-reserved region 172) is used as a mask, and is etched.
  • the process removes the data metal layer 16, the metal barrier layer 15, and the active layer 14 of the photoresist completely removed region.
  • the etching process may employ dry etching, such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the etching process can also be performed by wet etching.
  • Step S209 removing the photoresist in the semi-reserved region of the photoresist to form a second photoresist pattern.
  • the photoresist of the photoresist semi-reserved region 172 is removed by, for example, a plasma ashing process to form a second photoresist pattern (only the photoresist is completely included). The photoresist of the region 171 is retained).
  • Step S210 etching the data metal layer by using the second photoresist pattern as a mask.
  • the photoresist is removed by the etching process using the second photoresist pattern, that is, the photoresist of the photoresist completely remaining region 171 as a mask.
  • Step S211 performing an oxidation process on a portion of the metal barrier layer between the source and the drain to form a metal oxide portion.
  • an oxidation process is performed on a portion of the metal barrier layer 15 between the source electrode 161 and the drain electrode 162 by means of plasma implantation such as ion implantation or oxygen.
  • the metal in the portion of the metal barrier layer 15 between the source electrode 161 and the drain electrode 162 is converted into a metal oxide by the above oxidation process, thereby forming a metal oxide portion 151 which insulates the source electrode 161 from the drain electrode 162.
  • titanium (Ti) is used as the material of the metal barrier layer 15 as an example, but the embodiment of the invention is not limited thereto.
  • other metals may also be used to form the metal barrier layer 15 as long as it is capable of undergoing an oxidation reaction to form a metal oxide.
  • Step S212 removing the second photoresist pattern.
  • the second photoresist pattern is removed by, for example, a lift-off process, i.e., the photoresist completely retains the photoresist of the region 171.
  • a data line (not shown), a source electrode 161, a drain electrode 162, and a semiconductor active layer 14, and a metal barrier layer 15 covering the semiconductor active layer 14 are obtained.
  • the drain 162 and the data line may be electrically connected to each other or integrally formed.
  • the metal barrier layer 15 and the semiconductor active layer 14 may have, for example, the same area.
  • the metal barrier layer 15 may also have a larger area than the semiconductor active layer 14, but it is ensured that the metal barrier layer 15 can be divided into two parts by the metal oxide to avoid electrical connection between the source and the drain; And the structural connections to other pixels should be avoided.
  • the semiconductor material coated on the entire substrate on the base substrate is referred to as an active layer, and the active layer pattern (ie, the active layer of the TFT region) obtained after the patterning process is performed. It is called a semiconductor active layer, and the active layer and the semiconductor active layer are made of the same material.
  • Step S213 forming a protective layer on the gate insulating layer and the source and the drain, the protective layer having a via hole exposing the drain.
  • a protective layer 18 is formed on the gate insulating layer 13 and the source and drain electrodes 161 and 162 by, for example, sputtering or PECVD, and is patterned by a patterning process.
  • a via 181 exposing the drain 162 is formed on the protective layer 18.
  • the protective layer 18 can be an oxide layer, a nitride layer, or an oxynitride layer.
  • Step S214 forming a pixel electrode electrically connected to the drain on the protective layer.
  • a transparent conductive layer is deposited on the protective layer 18 by, for example, a sputtering method, and then a pixel electrode 19 is formed by performing a patterning process on the transparent conductive layer, and the pixel electrode 19 passes through the via 181 and the drain 162. Electrical connection.
  • the transparent conductive layer may be indium tin oxide
  • ITO indium oxide
  • ⁇ indium oxide
  • a metal barrier layer is formed between a source, a drain, and a semiconductor active layer, and is performed by a portion of the metal barrier layer between the source and the drain.
  • the oxidation process forms a metal oxide portion that insulates the source and drain from each other. In this way, contamination of the semiconductor active layer during formation of the source and the drain can be prevented, and the patterning process is not separately performed on the metal barrier layer, thereby reducing the patterning process and improving the production efficiency compared to the prior art. , reducing production costs.
  • Embodiments of the present invention also provide a display device including the TFT array substrate of any of the above embodiments.
  • An example of the display device is a liquid crystal display device in which a TFT array substrate and an opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which a TFT array is subjected to a display operation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种TFT阵列基板及其制造方法和显示装置。TFT阵列基板包括：基板(11)，基板(11)上形成的栅线、栅极(12)、栅绝缘层(13)和半导体有源层(14)，半导体有源层(14)上形成金属阻挡层(15)，金属阻挡层(15)上形成有源极(161)和漏极(162)；金属阻挡层(15)的位于源极(161)、漏极(162)之间的部分被氧化为金属氧化物部分(151)；金属氧化物部分(151)使该源极(161)、漏极(162)相互绝缘；基板(11)和源极(161)、漏极(162)上形成有保护层(18)和与漏极(162)连接的像素电极(19)。

Description

TFT阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及 TFT阵列基板及其制造方法和显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor-Liquid Crystal Display,
TFT-LCD )是利用施加在液晶层上的电场的强度变化， 改变液晶分子的旋转 的程度，从而控制透光的强度来显示图像的一种显示器。一般来讲， TFT-LCD 显示面板包括背光模块、 偏光片、 彩膜基板、 TFT阵列基板以及位于彩膜基 板和 TFT阵列基板之间的液晶分子层。
近年来 TFT-LCD获得了飞速的发展。 随着尺寸的不断增大和分辨率的 不断提高， 为了提高显示质量， TFT-LCD釆用了更高频率的驱动电路。 在这 种情况下， TFT-LCD的充电时间更短， 因此需要高迁移率的半导体材料。 此 夕卜， 图像信号的延迟也成为制约大尺寸、 高分辨率 TFT-LCD 的显示效果的 关键因素之一， 因此 TFT阵列基板中通常使用低电阻的金属材料 Cu来制作 数据线。
现有制作 TFT阵列基板的工艺包括： 在基板上依次形成栅线、 栅极、 栅 绝缘层和半导体有源层； 为了防止在后续的制作源极和漏极时金属材料对半 导体有源层产生污染， 在半导体有源层上形成具有过孔的保护层； 在该保护 层上形成通过过孔与半导体有源层连接的源极和漏极。 这样一来， 由于保护 层的形成而导致增加了一道构图工序， 这降低了 TFT阵列基板的生产效率， 提高了生产成本。 发明内容
本发明的一个实施例提供了一种薄膜晶体管（TFT )阵列基板， 其包括： 基底基板； 在所述基底基板上形成的栅线、栅极、栅绝缘层和半导体有源层； 在所述半导体有源层上形成的金属阻挡层， 所述金属阻挡层覆盖所述半导体 有源层； 在所述金属阻挡层上形成的源极和漏极， 所述源极和漏极之间形成 有使源极和漏极相互绝缘的金属氧化物部分； 以及在所述栅绝缘层以及所述 源极和漏极上形成的保护层， 其中， 所述金属氧化物部分是通过氧化金属阻 挡层的位于源极与漏极之间的部分而形成的。
本发明的另一个实施例提供了一种显示装置， 其包括 TFT阵列基板， 该 TFT阵列基板包括： 基底基板； 在所述基底基板上形成的栅线、 栅极、 栅绝 缘层和半导体有源层； 在所述半导体有源层上形成的金属阻挡层， 所述金属 阻挡层覆盖所述半导体有源层； 在所述金属阻挡层上形成的源极和漏极， 所 述源极和漏极之间形成有使所述源极和漏极相互绝缘的金属氧化物部分； 以 及在所述栅绝缘层以及所述源极和漏极上形成的保护层， 其中， 所述金属氧 化物部分是通过氧化金属阻挡层的位于源极与漏极之间的部分而形成的。
本发明的又一个实施例提供了一种薄膜晶体管 （TFT ) 阵列基板的制造 方法， 包括： 在基底基板上形成栅线和栅极； 在所述基底基板以及所述栅线 和栅极上形成栅绝缘层； 在所述栅绝缘层上形成有源层； 在所述有源层上形 成金属阻挡层； 在所述金属阻挡层上形成数据金属层； 利用双色调掩模板， 对所述数据金属层、 金属阻挡层和有源层执行构图工艺， 以形成数据线、 源 极、 漏极和半导体有源层以及覆盖所述半导体有源层的金属阻挡层； 对所述 金属阻挡层的位于源极与漏极之间的部分执行氧化工艺， 以形成使所述源极 和漏极相互绝缘的金属氧化物部分； 以及在所述栅绝缘层以及数据线、 源极 和漏极上形成保护层。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的 TFT阵列基板的结构示意图；
图 2为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图一；
图 3为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图二；
图 4为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图三；
图 5为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图四；
图 6为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图五；
图 7为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图六；
图 8为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图七；
图 9为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结构 示意图八；
图 10为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结 构示意图九；
图 11为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结 构示意图十；
图 12为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结 构示意图十一；
图 13为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结 构示意图十二；
图 14为本发明实施例提供的 TFT阵列基板制造方法的工艺中的基板结 构示意图十三。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种 TFT阵列基板， 如图 1所示。 本发明实施例的 阵列基板包括多条栅线和多条数据线， 这些栅线和数据线彼此交叉由此限定 了排列为矩阵的像素单元， 每个像素单元包括作为开关元件的薄膜晶体管和 用于控制液晶的排列的像素电极。 每个像素单元的薄膜晶体管的栅极与相应 的栅线电连接或一体形成， 源极与相应的数据线电连接或一体形成， 漏极与 相应的像素电极电连接或一体形成。 在下面的描述中， 主要针对单个或多个 像素单元进行， 但是其他像素单元可以相同地形成。
本发明实施例的 TFT阵列基板例如包括： 基底基板 11 ; 在基底基板 11 上形成的栅线（图中未表示）、栅极 12、栅绝缘层 13和半导体有源层 14; 在 半导体有源层 14上形成的具有金属氧化物部分 151的金属阻挡层 15 , 金属 阻挡层 15覆盖在半导体有源层 14上； 在金属阻挡层 15上形成的源极 161 和漏极 162, 金属氧化物部分 151位于彼此分离的源极 161与漏极 162之间 并使源极 161和漏极 162相互绝缘；在栅绝缘层 13以及源极 161和漏极 162 上形成的保护层 18, 保护层 18具有暴露漏极 162的过孔 181 ; 在保护层 18 上形成的通过过孔 181与漏极 162电连接的像素电极 19。
在本实施例中， 金属阻挡层 15与半导体有源层 14例如可以具有相同面 积。 在一些实施例中， 金属阻挡层 15也可以具有比半导体有源层 14大的面 积，但是要保证通过金属氧化物能够将金属阻挡层 15分成两部分， 以避免源 极和漏极电连接； 并且应该避免与其它的像素的相关结构连接。
在本实施例中， 金属阻挡层 15的材料例如可以为钛（Ti )或其合金， 源 极 161和漏极 162的材料例如可以为铜（ Cu ), 而像素电极 19的材料例如可 以为氧化铟锡（ ITO )、 氧化铟辞（ IZO )或其它透明导电材料。
需要说明的是， 在本发明的实施例中， 金属阻挡层 15可以由钛（ Ti )或 其合金形成， 但本发明的实施例并不限于此。 例如， 其他的金属也可以用于 形成金属阻挡层 15 , 只要其能够发生氧化反应形成金属氧化物即可。
在本发明的实施例提供的 TFT阵列基板中，在源极和漏极与半导体有源 层之间形成金属阻挡层， 并且通过对金属阻挡层的位于源极与漏极之间的部 分执行氧化工艺而形成金属氧化物部分。 这样， 既可以防止源极和漏极的形 成过程中对半导体有源层的污染，又无需单独对该金属阻挡层执行构图工艺， 因此相对现有技术而言， 减少了构图工艺的次数， 提高了生产效率， 降低了 生产成本。
下面参照图 2至图 14对本发明实施例提供的 TFT阵列基板的制造方法 进行说明。
图 2至图 14为本发明实施例提供的 TFT阵列基板制造方法的各工艺中 的基板结构示意图。本发明实施例提供的 TFT阵列基板的制造方法包括以下 步骤。
步骤 S201、 在基底基板上形成栅线和栅极。
在本发明的实施例中， 如图 2所示， 釆用例如溅射或蒸发的方法在例如 玻璃基板的基底基板 11上沉积厚度例如为 4000A ~ 15000A的栅金属膜。 栅 金属膜可以选用铬、 钨、 铜、 钛、 钽、 钼等金属或其合金。 栅金属膜可以由 单层金属形成， 或者可以由多层金属形成。 通过对栅金属膜执行构图工艺形 成栅极 12和栅线（图 2中未表示）。栅极 12和栅线可以相互电连接或者一体 形成。
在本发明的其它实施例中，例如玻璃基板的基底基板 11还可以由石英基 板、 塑料基板或其它透明基板代替。
步骤 S202、 在基底基板以及栅线和栅极上形成栅绝缘层。
在本发明的实施例中， 如图 3所示， 通过例如等离子体增强化学气相沉 积 ( Plasma Enhanced Chemical Vapor Deposition, PECVD )方法在基底基板 11以及栅线和栅极 12上沉积厚度例如为 2000A ~ 5000 A的栅绝缘层 13。栅 绝缘层 13通常釆用的材料例如为氧化物、氮化物或者氮氧化物，对应的反应 气体可以为氢化硅、 氨气和氮气或二氯氢硅、 氨气和氮气。
步骤 S203、 在栅绝缘层上形成有源层。
在本发明的实施例中， 如图 4 所示， 通过例如溅射方法在栅绝缘层 13 上沉积厚度例如为 50 A ~ 1000 A的金属氧化物有源层 14。有源层 14在经过 后续的构图工艺后将形成为半导体有源层。
步骤 S204、 在有源层上形成金属阻挡层。
在本发明的实施例中，如图 5所示，通过例如溅射方法在有源层 14上沉 积厚度例如为 50 A - 500 A的金属阻挡层 15。 作为示例， 金属阻挡层 15可 以由钛 ( Ti )或其合金形成。
步骤 S205、 在金属阻挡层上形成数据金属层。
在本发明的实施例中， 如图 6所示， 通过例如溅射方法在金属阻挡层 15 上沉积厚度例如为 1000 A ~ 5000 A的数据金属层 16。 作为示例， 数据金属 层 16可以由铜（Cu )形成。
步骤 S206、 在数据金属层上形成光刻胶层。
在本发明的实施例中， 如图 7所示， 通过例如旋涂方法在数据金属层 16 上形成光刻胶层 17。 在本实施例中， 光刻胶层 17由正性光刻胶形成， 但本 发明的实施例不限于此。
步骤 S207、 利用双色调掩模板对光刻胶层执行光刻工艺， 以形成第一光 刻胶图案。
在本发明的实施例中， 如图 8所示， 利用双色调掩模板（包括例如灰色 调掩摸板或半透式掩摸板） 20对光刻胶层 17进行曝光， 然后对曝光的光刻 胶层 17进行显影， 以形成第一光刻胶图案。 通过这种方式， 在显影后， 在基 底基板上形成光刻胶完全保留区域 171、 光刻胶半保留区域 172和光刻胶完 全去除区域。 在像素单元中， 光刻胶完全保留区域 171对应数据线、 源极和 漏极的区域， 而光刻胶半保留区域 172对应源极与漏极之间的区域。 在后续 的蚀刻步骤中， 第一光刻胶图案（包括光刻胶完全保留区域 171和光刻胶半 保留区域 172的光刻胶 )将用作刻蚀掩模。
步骤 S208、 利用第一光刻胶图案作为掩模， 刻蚀数据金属层、 金属阻挡 层和有源层。
在本发明的实施例中， 如图 9所示， 利用第一光刻胶图案（包括光刻胶 完全保留区域 171和光刻胶半保留区域 172的光刻胶 )作为掩模， 通过刻蚀 工艺去除掉光刻胶完全去除区域的数据金属层 16、 金属阻挡层 15和有源层 14。 在本发明的一些实施例中， 该刻蚀工艺可以釆用干法刻蚀， 例如反应离 子蚀刻 （RIE )。 在本发明的其它实施例中， 该刻蚀工艺也可以釆用湿法刻蚀 进行。
步骤 S209、 去除光刻胶半保留区域的光刻胶， 以形成第二光刻胶图案。 在本发明的实施例中，如图 10所示，利用例如等离子体灰化工艺去除掉 光刻胶半保留区域 172的光刻胶， 以形成第二光刻胶图案（仅包括光刻胶完 全保留区域 171的光刻胶）。在执行等离子体灰化工艺期间，在光刻胶半保留 区域 172的光刻胶被完全去除的同时， 光刻胶完全保留区域 171的光刻胶在 厚度方向上也被部分地去除并且留下厚度减小的部分光刻胶层（即， 第二光 刻胶图案）。 步骤 S210、 利用第二光刻胶图案作为掩模， 刻蚀数据金属层。
在本发明的实施例中， 如图 11所示， 利用第二光刻胶图案、 即光刻胶完 全保留区域 171的光刻胶作为掩模， 通过刻蚀工艺去除掉光刻胶半保留区域 171的数据金属层 16。
步骤 S211、 对金属阻挡层的位于源极与漏极之间的部分执行氧化工艺， 以形成金属氧化物部分。
在本发明的实施例中，如图 12所示，通过釆用例如离子注入或者氧的等 离子体处理等方式对金属阻挡层 15的位于源极 161与漏极 162之间的部分执 行氧化工艺。 通过上述氧化工艺， 使源极 161与漏极 162之间的部分金属阻 挡层 15中的金属转化成金属氧化物，从而形成使源极 161与漏极 162相互绝 缘的金属氧化物部分 151。
在本发明的上述实施例中， 作为示例， 釆用钛（Ti )作为金属阻挡层 15 的材料， 但本发明的实施例中并不限于此。 例如， 其他的金属也可以用来形 成金属阻挡层 15, 只要其能够发生氧化反应形成金属氧化物即可。
步骤 S212、 去除第二光刻胶图案。
在本发明的实施例中，如图 13所示，通过例如剥离工艺去除第二光刻胶 图案， 即光刻胶完全保留区域 171的光刻胶。 由此， 得到数据线（图中未表 示）、 源极 161、 漏极 162和半导体有源层 14, 以及覆盖半导体有源层 14的 金属阻挡层 15。 漏极 162与数据线可以相互电连接或者一体形成。 在本实施 例中， 金属阻挡层 15与半导体有源层 14例如可以具有相同面积。 在一些实 施例中， 金属阻挡层 15也可以具有比半导体有源层 14大的面积， 但是要保 证通过金属氧化物能够将金属阻挡层 15分成两部分，以避免源极和漏极电连 接； 并且应该避免与其它的像素的相关结构连接。
需要说明的是， 在本实施例中， 将在基底基板上整板涂布的半导体材料 称为有源层，而将执行构图工艺后得到的有源层图案（即 TFT区域的有源层） 称为半导体有源层， 该有源层和半导体有源层的材料相同。
步骤 S213、在栅绝缘层以及源极和漏极上形成保护层， 该保护层具有暴 露漏极的过孔。
在本发明的实施例中， 如图 14所示， 通过例如溅射或 PECVD方法， 在 栅绝缘层 13以及源极 161和漏极 162上形成保护层 18, 并通过构图工艺在 保护层 18上形成暴露漏极 162的过孔 181。 作为示例， 保护层 18可以为氧 化物层、 氮化物层或氮氧化物层。
步骤 S214、 在保护层上形成与漏极电连接的像素电极。
在本发明的实施例中， 通过例如溅射方法在保护层 18 上沉积透明导电 层，然后通过对该透明导电层执行构图工艺而形成像素电极 19,像素电极 19 通过过孔 181 与漏极 162 电连接。 作为示例， 透明导电层可以为氧化铟锡
( ITO )、 氧化铟辞（ΙΖΟ )或其它透明导电材料。
在本发明的实施例提供的 TFT阵列基板的制造方法中， 在源极、 漏极与 半导体有源层之间形成金属阻挡层， 并且通过对源极与漏极之间的部分金属 阻挡层执行氧化工艺而形成使源极与漏极相互绝缘的金属氧化物部分。这样， 既可以防止源极和漏极的形成过程中对半导体有源层的污染， 又无需单独对 金属阻挡层执行构图工艺， 因此相对现有技术而言， 减少了构图工序， 提高 了生产效率， 降低了生产成本。
本发明的实施例还提供了一种显示装置， 其包括上述任一实施例的 TFT 阵列基板。
该显示装置的一个示例为液晶显示装置， 其中， TFT阵列基板与对置基 板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 TFT阵列基板的每个像素单元的像素电极用于施加电场对液晶材 料的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示装 置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置， 其中， TFT阵列基 进行显示操作。
以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照前 述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分技术 特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种薄膜晶体管 （TFT ) 阵列基板， 包括：
基底基板；
在所述基底基板上形成的栅线、 栅极、 栅绝缘层和半导体有源层； 在所述半导体有源层上形成的金属阻挡层， 所述金属阻挡层覆盖所述半 导体有源层；
在所述金属阻挡层上形成的源极和漏极， 所述源极和漏极之间形成有使 所述源极和所述漏极相互绝缘的金属氧化物部分； 以及
在所述栅绝缘层以及所述源极和所述漏极上形成的保护层，
其中， 所述金属氧化物部分是通过氧化所述金属阻挡层的位于所述源极 与所述漏极之间的部分而形成的。
2、根据权利要求 1所述的薄膜晶体管阵列基板，还包括在所述保护层上 形成的像素电极， 所述像素电极与所述漏极电连接。
3、根据权利要求 1所述的薄膜晶体管阵列基板， 其中， 所述金属阻挡层 的材料为钛或其合金。
4、根据权利要求 1所述的薄膜晶体管阵列基板， 其中， 所述数据线、 源 极和漏极的材料包括铜。
5、根据权利要求 2所述的薄膜晶体管阵列基板， 其中， 所述保护层形成 有暴露所述漏极的过孔， 所述像素电极通过所述过孔而与所述漏极电连接。
6、 一种显示装置， 包括薄膜晶体管阵列基板， 所述薄膜晶体管阵列基板 包括：
基底基板；
在所述基底基板上形成的栅线、 栅极、 栅绝缘层和半导体有源层； 在所述半导体有源层上形成的金属阻挡层， 所述金属阻挡层覆盖所述半 导体有源层；
在所述金属阻挡层上形成的源极和漏极， 所述源极和漏极之间形成有使 所述源极和所述漏极相互绝缘的金属氧化物部分； 以及
在所述栅绝缘层以及所述源极和所述漏极上形成的保护层，
其中， 所述金属氧化物部分是通过氧化所述金属阻挡层的位于所述源极 与所述漏极之间的部分而形成的。
7、根据权利要求 6所述的显示装置，还包括在所述保护层上形成的像素 电极， 所述像素电极与所述漏极电连接。
8、根据权利要求 6所述的显示装置， 其中， 所述金属阻挡层的材料为钛 或其合金。
9、根据权利要求 6所述的显示装置， 其中， 所述数据线、 源极和漏极的 材料包括铜。
10、 根据权利要求 7所述的显示装置， 其中， 所述保护层形成有暴露所 述漏极的过孔， 所述像素电极通过所述过孔而与所述漏极电连接。
11、 根据权利要求 6所述的显示装置， 其中， 所述显示装置为液晶显示 装置或有机电致发光显示装置。
12、 一种薄膜晶体管 （TFT ) 阵列基板的制造方法， 包括：
在基底基板上形成栅线和栅极；
在所述基底基板以及所述栅线和栅极上形成栅绝缘层；
在所述栅绝缘层上形成有源层；
在所述有源层上形成金属阻挡层；
在所述金属阻挡层上形成数据金属层；
利用双色调掩模板， 对所述数据金属层、 金属阻挡层和有源层执行构图 工艺， 以形成数据线、 源极、 漏极和半导体有源层以及覆盖所述半导体有源 层的金属阻挡层；
对所述金属阻挡层的位于所述源极与漏极之间的部分执行氧化工艺， 以 形成使所述源极和所述漏极相互绝缘的金属氧化物部分； 以及
在所述栅绝缘层以及所述数据线、 源极和漏极上形成保护层。
13、 根据权利要求 12所述的薄膜晶体管阵列基板的制造方法， 还包括： 在所述保护层上形成与所述漏极电连接的像素电极。
14、根据权利要求 12所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述双色调掩模板为灰色调掩摸板或半透式掩摸板。
15、根据权利要求 13所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述保护层形成有暴露所述漏极的过孔， 所述像素电极通过所述过孔而与所述 漏极电连接。
16、根据权利要求 12所述的薄膜晶体管阵列基板的制造方法， 其中， 利 用双色调掩模板， 对所述数据金属层、 金属阻挡层和有源层执行构图工艺， 以形成数据线、 源极、 漏极和半导体有源层以及覆盖所述半导体有源层的金 属阻挡层， 以及对所述金属阻挡层的位于所述源极与漏极之间的部分执行氧 化工艺以形成使所述源极和所述漏极相互绝缘的金属氧化物部分包括：
在所述数据金属层上形成光刻胶层；
利用所述双色调掩模板， 对所述光刻胶层执行光刻工艺以形成光刻胶完 全保留区域、 光刻胶半保留区域和光刻胶完全去除区域， 所述光刻胶完全保 留区域对应所述数据线、 所述源极和所述漏极的区域， 而所述光刻胶半保留 区域对应所述源极与所述漏极之间的区域， 所述光刻胶完全保留区域和所述 光刻胶半保留区域的光刻胶形成第一光刻胶图案；
利用所述第一光刻胶图案作为掩模， 通过刻蚀工艺去除掉所述光刻胶完 全去除区域的所述数据金属层、 所述金属阻挡层和所述有源层；
利用等离子体灰化工艺去除掉所述光刻胶半保留区域的光刻胶， 以形成 第二光刻胶图案；
利用所述第二光刻胶图案作为掩模， 通过刻蚀工艺去除掉所述光刻胶半 保留区域的所述数据金属层； 以及
对所述金属阻挡层的位于所述源极与所述漏极之间的部分执行氧化工 艺， 以形成使所述源极和所述漏极相互绝缘的所述金属氧化物部分。
17、 根据权利要求 16所述的薄膜晶体管阵列基板的制造方法， 还包括： 在形成所述金属氧化物部分之后， 去除所述第二光刻胶图案。
18、根据权利要求 12所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述金属阻挡层的材料为钛或其合金。
19、根据权利要求 12所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述数据金属层的材料包括铜。
PCT/CN2012/081771 2011-09-29 2012-09-21 Tft阵列基板及其制造方法和显示装置 WO2013044760A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/703,499 US9305942B2 (en) 2011-09-29 2012-09-21 TFT array substrate having metal oxide part and method for manufacturing the same and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110294950.6A CN102629628B (zh) 2011-09-29 2011-09-29 一种tft阵列基板及其制造方法和液晶显示器
CN201110294950.6 2011-09-29

Publications (1)

Publication Number Publication Date
WO2013044760A1 true WO2013044760A1 (zh) 2013-04-04

Family

ID=46587847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/081771 WO2013044760A1 (zh) 2011-09-29 2012-09-21 Tft阵列基板及其制造方法和显示装置

Country Status (3)

Country Link
US (1) US9305942B2 (zh)
CN (1) CN102629628B (zh)
WO (1) WO2013044760A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629628B (zh) * 2011-09-29 2016-06-01 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法和液晶显示器
CN102646699B (zh) * 2012-01-13 2014-12-10 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及其制备方法
CN102651322A (zh) 2012-02-27 2012-08-29 京东方科技集团股份有限公司 一种薄膜晶体管及其制造方法、阵列基板、显示器件
CN103633029B (zh) * 2012-08-28 2016-11-23 中国科学院微电子研究所 半导体结构及其制造方法
CN102956715B (zh) * 2012-11-02 2015-04-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN103018990B (zh) * 2012-12-14 2015-12-02 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置
JP2016021530A (ja) * 2014-07-15 2016-02-04 ルネサスエレクトロニクス株式会社 半導体装置
CN104167365A (zh) 2014-08-06 2014-11-26 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
CN104299915B (zh) * 2014-10-21 2017-03-22 北京大学深圳研究生院 金属氧化物薄膜晶体管制备方法
CN104576760A (zh) * 2015-02-02 2015-04-29 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN104952935B (zh) * 2015-07-14 2018-06-22 深圳市华星光电技术有限公司 一种薄膜晶体管结构及其制备方法
CN105374748B (zh) * 2015-10-13 2018-05-01 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制得的薄膜晶体管基板
CN105702586B (zh) * 2016-04-28 2019-06-07 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、其制作方法及显示装置
US9881956B2 (en) * 2016-05-06 2018-01-30 International Business Machines Corporation Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
CN107195641B (zh) * 2017-06-30 2020-05-05 上海天马有机发光显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN113594181A (zh) * 2021-07-23 2021-11-02 惠州华星光电显示有限公司 阵列基板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1917218A (zh) * 2005-08-17 2007-02-21 株式会社神户制钢所 源极/漏极电极、晶体管衬底及其制造方法和显示装置
US7442588B2 (en) * 2007-02-23 2008-10-28 Silicon Display Technology Co., Ltd. Method for fabricating thin film transistor using local oxidation and transparent thin film transistor
KR20090043748A (ko) * 2007-10-30 2009-05-07 엘지디스플레이 주식회사 인플레인 스위칭 모드의 액정표시장치 및 그 제조방법
CN102629628A (zh) * 2011-09-29 2012-08-08 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法和液晶显示器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070109478A (ko) 2006-05-11 2007-11-15 삼성에스디아이 주식회사 연료 전지의 고분자 전해질막 제조용 복합장치
CN101533191B (zh) * 2008-03-13 2012-02-29 北京京东方光电科技有限公司 Tft-lcd阵列基板结构及其制备方法
KR101671210B1 (ko) * 2009-03-06 2016-11-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1917218A (zh) * 2005-08-17 2007-02-21 株式会社神户制钢所 源极/漏极电极、晶体管衬底及其制造方法和显示装置
US7442588B2 (en) * 2007-02-23 2008-10-28 Silicon Display Technology Co., Ltd. Method for fabricating thin film transistor using local oxidation and transparent thin film transistor
KR20090043748A (ko) * 2007-10-30 2009-05-07 엘지디스플레이 주식회사 인플레인 스위칭 모드의 액정표시장치 및 그 제조방법
CN102629628A (zh) * 2011-09-29 2012-08-08 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法和液晶显示器

Also Published As

Publication number Publication date
CN102629628B (zh) 2016-06-01
CN102629628A (zh) 2012-08-08
US9305942B2 (en) 2016-04-05
US20140071364A1 (en) 2014-03-13

Similar Documents

Publication Publication Date Title
WO2013044760A1 (zh) Tft阵列基板及其制造方法和显示装置
US10304861B2 (en) Array substrate and method of manufacturing the same, and display panel
TWI385760B (zh) 製造陣列基板的方法
KR101447843B1 (ko) 박막 트랜지스터 어레이 기판, 그 제조 방법, 디스플레이 패널 및 디스플레이 장치
US9761616B2 (en) Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device
KR100913819B1 (ko) 박막 트랜지스터 어레이 기판 및 그의 제조방법
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2013155840A1 (zh) 阵列基板及其制造方法和显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
KR20100126228A (ko) Ｔｆｔ-ｌｃｄ 어레이 기판 및 그 제조방법
US9842915B2 (en) Array substrate for liquid crystal display device and method of manufacturing the same
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
JP2019537282A (ja) アレイ基板とその製造方法及び表示装置
WO2016070581A1 (zh) 阵列基板制备方法
WO2013181909A1 (zh) 薄膜晶体管和阵列基板及其制造方法
WO2015043069A1 (zh) 阵列基板及其制备方法、显示装置
JP6899487B2 (ja) Ｔｆｔ基板及びその製造方法
TW200819888A (en) TFT substrate and manufacturing method, and display device with the same
WO2014146358A1 (zh) 阵列基板、阵列基板的制造方法及显示装置
JP2018523140A (ja) アレイ基板の製造方法、アレイ基板および表示装置
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
CN110148601A (zh) 一种阵列基板、其制作方法及显示装置
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置
WO2013143294A1 (zh) 阵列基板、其制作方法以及显示装置
WO2013123786A1 (zh) 薄膜晶体管阵列基板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13703499

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12835761

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (FORM 1205A) 22.07.2014

122 Ep: pct application non-entry in european phase

Ref document number: 12835761

Country of ref document: EP

Kind code of ref document: A1