WO2014141346A1 - Dispositif à semi-conducteurs - Google Patents

Dispositif à semi-conducteurs Download PDF

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Publication number
WO2014141346A1
WO2014141346A1 PCT/JP2013/007628 JP2013007628W WO2014141346A1 WO 2014141346 A1 WO2014141346 A1 WO 2014141346A1 JP 2013007628 W JP2013007628 W JP 2013007628W WO 2014141346 A1 WO2014141346 A1 WO 2014141346A1
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WIPO (PCT)
Prior art keywords
semiconductor device
mold resin
control circuit
heat sink
circuit board
Prior art date
Application number
PCT/JP2013/007628
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English (en)
Japanese (ja)
Inventor
山本 圭
和弘 多田
清文 北井
弘行 芳原
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201380074731.4A priority Critical patent/CN105144373A/zh
Priority to JP2015505089A priority patent/JP6360035B2/ja
Publication of WO2014141346A1 publication Critical patent/WO2014141346A1/fr

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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present invention relates to a molded semiconductor device in which a lead frame on which a power semiconductor element is mounted, a printed wiring board on which electrical components are mounted, a heat sink as a heat radiating member, and the like are sealed by transfer molding.
  • a conventional semiconductor device in order to realize a highly reliable and small semiconductor device, an insulating metal substrate on which an insulating layer is formed in advance is applied, and in order to alleviate stress concentration on the insulating layer at the time of temperature change, A large amount of mold resin is arranged around the power semiconductor element.
  • a conventional semiconductor device includes a mold resin having a material whose linear expansion coefficient is specified in order to integrally reinforce a circuit portion including a power semiconductor element. (For example, patent document 1).
  • a circuit portion, a semiconductor element, a lead frame, and the like formed on an insulating metal substrate are integrally sealed with a mold resin. From the viewpoints of downsizing, cost reduction, and productivity, these members are sealed so that the amount of mold resin used is reduced as much as possible within a range in which insulation can be ensured.
  • control circuit board having the printed wiring board and the electric parts and forming the electric circuit for controlling the power semiconductor element is sealed by transfer molding integrally with the lead frame and the power semiconductor element.
  • the entire semiconductor device can be reduced in size, and the periphery of the electrical components on the control circuit board can be a highly insulating mold. Since it is sealed with resin, the interval between the electrical components can be mounted narrowly, and the control circuit board can be downsized.
  • the control circuit board is sealed with a mold resin integrally with a lead frame, a power semiconductor element, etc.
  • the overall size of the semiconductor device incorporating the control circuit board is much larger than that of a conventional semiconductor device. Therefore, the amount of mold resin used is also increased in proportion.
  • a semiconductor device having a built-in control circuit board causes an increase in warpage and thermal stress as compared with a conventional semiconductor device after molding resin molding or due to a use environment temperature due to an increase in the size of the semiconductor device.
  • the insulating layer provided between the lead frame and the metal plate for heat dissipation is peeled or cracked, resulting in a decrease in reliability.
  • the present invention has been made to solve the above-mentioned problems, and controls the lead frame by suppressing the peeling of the insulating layer provided between the lead frame and the metal plate and the occurrence of cracks.
  • a circuit board and a resin can be integrally sealed with a mold resin, and a highly reliable semiconductor device is obtained.
  • a metal member having a semiconductor element mounted on one surface thereof, a metal plate disposed on the other surface side of the metal member with an insulating layer interposed therebetween, and the semiconductor element electrically
  • the linear expansion coefficient for integrally sealing the printed wiring board on which the electrical components connected to the board are mounted, and the metal member, the printed wiring board, and the metal board is 15 to 23 ⁇ 10 ⁇ 6 (1 / K And a sealing resin.
  • the linear expansion coefficient of the resin for integrally sealing the control circuit board with resin is set to 15 to 23 ⁇ 10 ⁇ 6 (1 / K), and the lead frame and the control circuit board are integrally sealed. Therefore, even in a large-sized semiconductor device, peeling of an insulating layer provided between a lead frame and a metal plate by a reliability test and generation of cracks can be suppressed, and high reliability can be obtained.
  • FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. Note that FIG. 1 is a cross-sectional view schematically showing the structure of the semiconductor device, so that the positional relationship of each part, various wirings, parts, and the like are schematically shown.
  • the semiconductor device 100 includes a lead frame 2, which is a metal member, a control circuit substrate 5, a metal substrate 7, and a mold resin 10 which is a sealing resin.
  • the lead frame 2 is formed with a wiring pattern of a predetermined electric circuit (not shown).
  • a predetermined electric circuit On one surface of the lead frame 2 (hereinafter referred to as a first main surface), an IGBT (Insulated Gate Bipolar Transistor) or a diode as a semiconductor element 11, a shunt resistor as a current detection means for detecting a current value, and temperature are detected.
  • a thermistor or the like (not shown) as temperature detecting means for mounting is mounted by soldering.
  • the semiconductor element 11 is not limited to the IGBT, and may be implemented by using, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or the like.
  • the formed control circuit board 5 is arranged. Necessary portions such as between the control circuit board 5 and the lead frame 2 (not shown) and between the lead frame 2 and the semiconductor element 11 are appropriately electrically connected by bonding wires 6.
  • an aluminum wire is used as a bonding wire, but this is not limited to an aluminum wire.
  • a material having a low resistance value such as a copper wire may be used. By using a material having a low resistance value such as a copper wire, it is possible to cope with a large current. Even when a gold wire is used, the same effect can be obtained.
  • a metal substrate 7 functioning as a heat sink is disposed on a surface opposite to the first main surface of the lead frame 2 (referred to as a second main surface).
  • the metal substrate 7 includes an insulating layer 8 and a heat sink 9 that is a metal plate.
  • the second main surface of the lead frame 2, the insulating layer 8, and the heat sink 9 are arranged in this order.
  • the lead frame 2 on which the semiconductor element 11 and the like are mounted, the control circuit board 5 and the metal board 7 are integrally transfer-molded with a mold resin 10. At this time, the surface of the lead frame 2 opposite to the side where the insulating layer 8 of the heat sink 9 is disposed is sealed in a state where it is exposed from the mold resin 10.
  • the control circuit board 5 includes a printed wiring board 3 on which a wiring pattern is formed and an electrical component 4 mounted on the wiring pattern of the printed wiring board 3.
  • the printed wiring board 3 for example, those generally used in an electronic device having a thickness of 1.6 mm can be used, but the thickness is not limited to this.
  • the heat resistance grade of the printed wiring board is not limited to FR-4. For example, when high-temperature operation of the element is assumed using silicon carbide (SiC) as the semiconductor element 11 mounted on the lead frame 2.
  • SiC silicon carbide
  • a printed wiring board 3 corresponding to FR-5 having a high heat resistance grade can also be used.
  • the electrical component 4 is preferably mounted on both sides of the printed wiring board 3 as shown in FIG. 1, but may be mounted on one side.
  • the difference in thermal expansion coefficient between the front and back surfaces against thermal stress generated by a temperature cycle or the like can be suppressed, and the generated warpage can be suppressed by increasing rigidity. be able to.
  • the area of the printed wiring board can be suppressed to about half that of single-sided mounting, leading to miniaturization of the semiconductor device.
  • the lead frame 2 and the control circuit board 5 are arranged substantially in parallel as shown in FIG.
  • a method of arranging them substantially in parallel as described above a method of supporting a control circuit board 5 by placing a support on the lead frame 2, a method of maintaining with a bonding wire (not shown) connected to the lead frame 2, and the like are used. be able to.
  • the distance between the lead frame 2 and the control circuit board 5 is such that the loop height of the bonding wire 6 that electrically connects the semiconductor elements 11 and the like mounted on the first main surface of the lead frame 2 and the lead of the printed wiring board 3. It is set in consideration of the height of the electric component 4 arranged on the surface facing the frame 2. It is desirable that this distance be as high as possible to prevent contact between the two and be as narrow as possible.
  • it is possible to electrically connect the column and the circuit on the control circuit board 5 by using a conductive column in which a part of the lead frame 2 is deformed as the column of the lead frame 2.
  • control circuit board 5 is placed side by side with the lead frame 2 instead of above the lead frame 2 and the whole is integrally sealed with the mold resin 10, the installation area of the semiconductor device increases, This is not preferable because the amount of the resin 10 is increased and it is not economical, and the warpage of the semiconductor device is increased due to the disequilibrium of the members having different linear expansion coefficients. However, this is not the case when the height of the semiconductor device is more restricted than the restriction due to the installation area of the semiconductor device.
  • the metal substrate 7 includes an insulating layer 8 and a heat sink 9, and serves as a heat radiating plate for radiating heat from the semiconductor element 11 and the like on the first main surface of the lead frame 2.
  • the insulating layer 8 is obtained by filling a thermosetting resin such as an epoxy resin with an inorganic powder filler having high thermal conductivity.
  • a thermosetting resin such as an epoxy resin
  • an inorganic powder filler having high thermal conductivity for example, one type of insulating powder such as silica, alumina, boron nitride, or aluminum nitride is used. Alternatively, a plurality of them are mixed and filled in the resin.
  • the resin is preferably a thermosetting resin such as an epoxy resin because it is excellent in adhesiveness to the lead frame 2 and the heat sink 9, but is not limited to this, and may be a thermoplastic resin, for example.
  • the insulating layer 8 is formed with a thickness of about 200 ⁇ m.
  • the thickness of the insulating layer 8 is not limited to this, and can be appropriately selected within the range of 50 to 300 ⁇ m depending on the thermal resistance, thermal capacity, and withstand voltage required for the semiconductor device.
  • the heat sink 9 is made of a metal plate such as an aluminum plate having a thickness of 5 mm, for example.
  • the metal plate used as the heat sink 9 can be selected in consideration of heat dissipation, and is not limited to the aluminum plate, but the semiconductor device in which the control circuit board 5 is integrally sealed is very large. Therefore, aluminum that is lightweight is preferable.
  • the shape and thickness of the metal plate are not limited, and a thick metal plate or metal foil can be used depending on the thermal resistance and heat capacity required for the semiconductor device, and can be selected as appropriate within a range of 100 ⁇ m to 10 mm. Is possible.
  • As the dimension of the metal plate one having a side length of 50 mm or more is used. When a plurality of semiconductor elements are mounted, heat dissipation is ensured by setting the heat sink to 50 mm or more from the viewpoint of heat dissipation.
  • the semiconductor device 100 is integrally formed by transfer molding with the mold resin 10.
  • the mold molding temperature is usually about 180 ° C., and when the mold resin is cooled to room temperature after molding or when a temperature cycle test, which is one of reliability tests, is performed, the mold resin expands and contracts. Thermal expansion / shrinkage occurs not only in the mold resin but also in each member, and the strain amount is (member length) ⁇ (member linear expansion coefficient ⁇ ) ⁇ (temperature difference ⁇ T). Stress and warp are generated due to temperature differences due to the integral contact of materials with different ⁇ . The amount of strain increases with the member size.
  • a semiconductor device in which a control circuit board is integrally incorporated is dramatically larger in size than that in which a control circuit board is not incorporated, and the volume ratio of the mold resin in the semiconductor device is also increased. For this reason, the stress and warpage generated in the semiconductor device due to the temperature difference greatly depend on the magnitude of the linear expansion coefficient of the mold resin.
  • What is required of semiconductor devices is not only to prevent electrical reliability from being lowered due to peeling of the insulating layer from the heat sink or cracking of the insulating layer in reliability tests such as temperature cycling, but also to make the heat sink contact with the heat sink.
  • the insulating layer 8 is formed by applying an epoxy resin to one surface of the heat sink 9. Then, a circuit pattern (not shown) using, for example, copper is formed on the insulating layer 8 using etching or the like.
  • solder paste (not shown) is applied to a predetermined position on the circuit pattern, and an electronic component such as the semiconductor element 11 is mounted on the solder paste. Then reflow. That is, the metal substrate 7 is heated to a high temperature, and the applied solder paste is melted at a high temperature to electrically connect the electronic component such as the semiconductor element 11 and the circuit pattern.
  • This circuit pattern is connected to the lead frame.
  • solder bonding or ultrasonic bonding can be used.
  • the circuit pattern and the semiconductor element 11 are electrically connected by the bonding wire 6.
  • the electric component 4 is fixed to the printed wiring board 3 on which a predetermined wiring pattern is formed.
  • the control circuit board 5 is formed.
  • the lead frame 2 and the control circuit board 5 are electrically connected by a predetermined method.
  • mold resin 10 is poured. At this time, the mold resin 10 may be poured in a reduced-pressure atmosphere, thereby suppressing generation of voids generated in the mold resin 10.
  • the injected mold resin 10 is cured by being heated to the molding die temperature, and can be taken out from the molding die. Thereafter, heat treatment may be performed in an oven or the like to further cure as necessary. Further, the present invention is not limited to such a method.
  • a heat sink 9 provided with an insulating layer 8 on one surface and copper having a circuit pattern on which a semiconductor element 11 is mounted in advance by a reflow process are used.
  • the existing lead frame 2 may be integrally sealed in a molding die in a transfer molding process.
  • an epoxy resin mold resin can be selected as the mold resin 10.
  • the mold resin 10 is filled with silica or alumina as a filler in an epoxy resin, and is formed in a tablet shape before molding.
  • silica fused silica or crystalline silica can be used, and a single substance can be mixed and filled.
  • the linear expansion coefficient of the mold resin 10 it is effective to fill with fused silica having a small linear expansion coefficient.
  • the silica filling amount is reduced.
  • it is possible to cope with this by replacing a part of the fused silica with crystalline silica without changing the silica filling amount so much.
  • the mold resin 10 is normally solid at room temperature, but in this transfer molding step, it is molded in a liquid state during molding in a molding die set at 180 ° C. Since the mold resin 10 is an epoxy-based thermosetting resin, the curing progresses with time by heating, and solidifies while adhering to the lead frame 2, the control circuit board 5, and the like in the molding die. At this time, since the mold resin 10 changes from liquid to solid, volume shrinkage occurs.
  • the semiconductor device 100 is taken out from the molding die after molding, the semiconductor device 100 is cooled from about 180 ° C. to room temperature, so that a cooling step of 150 ° C. to 160 ° C. is performed.
  • the heat sink 9 can have a thickness of, for example, 5 mm in order to improve heat dissipation. If the heat sink 9 is sufficiently thick compared to the lead frame 2 or the control circuit board 5, the influence on the warp of the entire semiconductor device 100 is large. Since the insulating layer 8 is provided on one surface of the heat sink 9, the warpage of the heat sink 9 has a great influence on the peeling of the insulating layer 8 from the heat sink 9 and the occurrence of cracks in the insulating layer 8.
  • the linear expansion coefficient of the mold resin 10 is equivalent to about 24 ⁇ 10 ⁇ 6 (1 / K) which is the linear expansion coefficient of aluminum, which is the material of the heat sink 9, the heat generated when the mold resin 10 is taken out from the mold and cooled to room temperature. Although the amount of shrinkage is the same as that of the heat sink 9, the mold resin 10 is cured and shrunk in the molding die as it is cured before being taken out from the molding die. Convex warpage.
  • the convex warpage means that the exposed surface side of the heat sink 9 warps in a convex shape.
  • the convex warpage of the semiconductor device 100 is suppressed, and the amount of warpage is reduced. Becomes smaller. If the linear expansion coefficient of the mold resin 10 is further reduced, the semiconductor device 100 will be concavely warped.
  • the linear expansion coefficient of the mold resin 10 at the operating environment temperature is 15 to 23 ⁇ 10 ⁇ 6 (1 / K), so Accordingly, peeling of the insulating layer 8 and the control circuit substrate 5 is suppressed, and the highly reliable semiconductor device 100 can be obtained.
  • the use environment temperature is the ambient temperature in which the semiconductor device is used or the operating temperature of the semiconductor element in contact with the mold resin.
  • a range of ⁇ 40 ° C. to 125 ° C. is conceivable.
  • the semiconductor element 11 uses SiC, it is conceivable that the high temperature side of the use environment temperature is, for example, 150 ° C. to 200 ° C.
  • thermosetting resin material such as a mold resin has a glass transition temperature (Tg), and at a temperature higher than Tg, the linear expansion coefficient increases rapidly from the glass region to the rubber region. It is common. From this, it is desirable that the Tg of the mold resin is higher than the temperature on the high temperature side of the temperature cycle test. For example, when the temperature cycle test is performed at ⁇ 40 ° C.
  • the Tg of the mold resin 10 is preferably 125 ° C. or higher. More preferably, the mold resin 10 has a Tg of 150 ° C. or higher.
  • the warp of the aluminum heat sink 9 is warped. Can be in a state of no warpage or convex warpage. Thereby, peeling of the insulating layer 8 from the heat sink 9 and generation of cracks in the insulating layer 8 are suppressed, and peeling between the mold resin 10 and the control circuit board 5 is also suppressed, thereby improving reliability.
  • the surface of the heat sink 9 exposed on the back surface of the semiconductor device after the molding resin 10 is molded has no warpage or a convex shape (convex warpage). It is also possible to prevent a decrease in thermal resistance due to grease at the center of the semiconductor device, which is important for heat dissipation when attaching the fins to 9. (If the surface of the heat sink 9 is warped, the grease at the center of the semiconductor device, which is important for heat dissipation, becomes thick when the heat dissipation fin is attached using grease, and heat dissipation is impaired.)
  • FIG. The second embodiment is different in that a part of the printed wiring board 13 used in the first embodiment is projected outside the mold resin. As described above, by projecting a part of the printed wiring board 13 to the outside of the mold resin 10, it is possible to easily position the control circuit board 5 at the time of resin sealing.
  • FIG. 2 is a schematic sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device 200 includes a lead frame 2 that is a metal member, a control circuit substrate 5, a metal substrate 7, and a mold resin 10 that is a sealing resin.
  • the control circuit board 5 includes a printed wiring board 13, and a configuration in which a part of the printed wiring board 13 protrudes outside the mold resin 10 of the semiconductor device 200 is an embodiment.
  • the structure is equivalent to 1.
  • the control circuit board 15 is preferably substantially parallel to the lead frame 2 and the fixing method is not particularly limited. However, by exposing a part of the printed wiring board 13 from the mold resin 10 to the outside, The exposed portion can be sandwiched and fixed by a molding die. Thereby, there is an advantage that the arrangement position of the control circuit board 5 and the parallelism with the lead frame can be produced more accurately and without variation. Moreover, a part of wiring pattern can also be arrange
  • the warp of the aluminum heat sink 9 is warped. Can be warp-free or convex warp. Thereby, peeling of the insulating layer 8 and occurrence of cracks are suppressed, and peeling between the mold resin 10 and the control circuit board 5 is also suppressed, thereby improving reliability. Further, since the printed wiring board 13 protrudes to the outside of the mold resin 10, the control circuit board 5 can be easily positioned at the time of resin sealing.
  • Embodiment 3 is different from the first embodiment in that the heat sink 9 used in the first embodiment is replaced with a finned heat sink 12 having irregularities formed thereon. Thus, it becomes possible to improve heat dissipation by forming unevenness in the heat sink.
  • FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention.
  • the semiconductor device 300 includes a lead frame 2 that is a metal member, a control circuit substrate 5, a metal substrate 17, and a mold resin 10 that is a sealing resin.
  • the metal substrate 17 includes a heat sink 12 with fins, and is implemented except that the surface opposite to the surface on which the lead frame 2 of the heat sink 12 with fins is provided is provided with irregularities.
  • the structure is equivalent to that of Form 1.
  • the heat dissipation is further enhanced by providing irregularities on the exposed surface of the finned heat sink 12. At this time, although depending on the length and interval of the unevenness, when the heat sink warps to the exposed surface side of the heat sink, the convex portions serving as the heat radiating fins approach each other and heat dissipation is impaired.
  • the warping of the heat sink 12 made of aluminum is set by setting the linear expansion coefficient of the mold resin 10 used for transfer molding to 15 to 23 ⁇ 10 ⁇ 6 (1 / K). Can be warp-free or convex warp. Thereby, peeling of the insulating layer 8 and occurrence of cracks are suppressed, and peeling between the mold resin 10 and the control circuit board 5 is also suppressed, thereby improving reliability. Furthermore, it is possible to improve heat dissipation by providing irregularities on the surface opposite to the surface on which the metal member of the finned heat sink 12 is disposed.
  • Embodiment 4 the side opposite to the surface on which the insulating layer 8 of the heat sink 9 or the finned heat sink 12 used in the first, second, and third embodiments is provided (the back side).
  • a step 13 which is a stepped portion, is provided on the outer peripheral portion (end portion).
  • FIG. 4 is a schematic back view showing the semiconductor device according to the first embodiment of the present invention.
  • a step 13 is provided on the outer peripheral portion of the heat sink 9 opposite to the surface on which the insulating layer 8 is provided (back surface side).
  • the cross-sectional structure schematic diagram of the heat sink 9 in the dotted line AB in FIG. 4 is a structure as shown in FIG. 1 or FIG.
  • FIG. 5 is a schematic backside view showing a semiconductor device according to the fourth embodiment of the present invention.
  • unevenness is provided on the surface opposite to the surface on which the lead frame 2 of the finned heat sink 12 is disposed (back surface side), and a step 13 is provided on the outer peripheral portion (end portion) of this surface.
  • the cross-sectional structural schematic diagram of the finned heat sink 12 taken along the dotted line AB in FIG. 5 is the structure as shown in FIG.
  • the mold resin 10 wraps around to the back surface side of the metal plates 7 and 17, so that the mold resin 10 holds the heat sink 12, and the reliability can be improved without impairing heat dissipation. Possible and improved reliability by temperature cycle test.
  • the control circuit board 5 is also integrally sealed with the mold resin 10 as in the present embodiment, the molded semiconductor device itself becomes large, and various components are sealed in the mold resin 10. Has been.
  • the shape of the step 13 is not particularly limited, but preferably has a structure for holding a heat sink as shown in the figure, and is opposite to the surface on which the insulating layer 8 of the heat sink 9 or the finned heat sink 12 is provided. It is good to provide continuously with respect to the outer peripheral part of a surface side. Moreover, the shape of the level
  • the size of the heat sink 9 or the finned heat sink 12 is 70 mm ⁇ 50 mm ⁇ thickness 5 mm, and the cross-sectional dimension of the step 13 is about 1 mm ⁇ 1 mm.
  • the reliability can be improved without impairing the above.
  • the structure provided with the step 13 is more effective when an insulating sheet is used as the insulating layer 8.
  • the insulating sheet is used, the insulating sheet itself is peeled off from the sheet sink 9 or the finned heat sink 12 or cracked in the insulating sheet itself due to the stress generated by the temperature cycle, which deteriorates the reliability.
  • Providing such a step 13 makes it possible to suppress peeling and cracking of the insulating sheet and improve reliability.
  • the thicknesses of the metal plates 7 and 17 that can be used as the heat sink 9 and the finned heat sink 12 can be appropriately selected within a range of 0.1 to 10 mm. More preferably, the thickness is more effective within a thick range. It becomes. In particular, when a metal material having a large linear expansion coefficient such as aluminum is used, reliability is affected by the thickness of the heat sink. In the case of a structure in which the control circuit board is disposed facing the heat sink and the whole is resin-sealed with a mold resin as in the present embodiment, balance with members other than the heat sink is also important. In the present embodiment, it is particularly effective when the thickness of the heat sink is larger than the thickness of the control circuit board.
  • the thickness of the control circuit board is 1.6 mm
  • the thickness of the metal plate as the heat sink is It is preferable that it is 1.6 mm or more.
  • copper may be used as the material of the heat sink, and the characteristics of other materials used can be appropriately selected and used in accordance with the heat sink material to be used.
  • the warping of the heat sink 12 made of aluminum is set by setting the linear expansion coefficient of the mold resin 10 used for transfer molding to 15 to 23 ⁇ 10 ⁇ 6 (1 / K). Can be warp-free or convex warp. Thereby, peeling of the insulating layer 8 and occurrence of cracks are suppressed, and peeling between the mold resin 10 and the control circuit board 5 is also suppressed, thereby improving reliability. Further, unevenness is provided on the surface on the opposite side of the surface on which the metal member of the heat sink 9 is disposed or on the surface on the opposite side of the surface on which the metal member of the finned heat sink 12 is disposed, and a step is formed on the outer peripheral portion of these surfaces. By providing 13, it becomes possible to improve heat dissipation.
  • a power module which is a semiconductor device having the structure of the first embodiment, is manufactured, and after the power module is manufactured, the insulation sheet as the insulating layer 8 is peeled off, the peeling between the control circuit board 5 and the mold resin 10 is confirmed, and the temperature cycle reliability test It was thrown into.
  • the linear expansion coefficient after hardening of mold resin can be adjusted by increasing / decreasing the filling amount of the silica used as a filler.
  • fused silica was used as the filler, the filling amount was 80% by weight, and the linear expansion coefficient was adjusted to 15 ⁇ 10 ⁇ 6 (1 / K).
  • Example 2 In this example, fused silica was used as the filler, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 3 In this example, fused silica was used as the filler, the filling amount was 73% by weight, and the linear expansion coefficient was adjusted to 21 ⁇ 10 ⁇ 6 (1 / K).
  • Example 4 In this example, fused silica and crystalline silica were used as fillers, the filling amount was 73 wt%, and the linear expansion coefficient was adjusted to 23 ⁇ 10 ⁇ 6 (1 / K).
  • Example 5 In this example, the thickness of the aluminum base was 0.1 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 6 In this example, the thickness of the aluminum base was 1 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 7 In this example, the thickness of the aluminum base was 2 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 8 In this example, the thickness of the aluminum base was 3 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 9 In this example, the thickness of the aluminum base was 5 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Example 10 In this example, the thickness of the aluminum base was 10 mm. Fused silica was used as a filler for the mold resin, the filling amount was 77% by weight, and the linear expansion coefficient was adjusted to 17 ⁇ 10 ⁇ 6 (1 / K).
  • Comparative Example 1 In this comparative example, fused silica was used as the filler, the filling amount was filled by 86% by weight, and the linear expansion coefficient was adjusted to 10 ⁇ 10 ⁇ 6 (1 / K).
  • Comparative Example 2 In this comparative example, fused silica was used as the filler, the filling amount was 83% by weight, and the linear expansion coefficient was adjusted to 13 ⁇ 10 ⁇ 6 (1 / K).
  • Comparative Example 3 In this comparative example, fused silica and crystalline silica were used as fillers, the filling amount was 73 wt%, and the linear expansion coefficient was adjusted to 25 ⁇ 10 ⁇ 6 (1 / K).
  • the ⁇ of the resin used is between 15 and 23 ⁇ 10 ⁇ 6 (1 / K), the occurrence of peeling is suppressed and there is no deterioration even in the temperature cycle test. More preferably, the ⁇ of the resin used is between 17 and 23 ⁇ 10 ⁇ 6 (1 / K).
  • the ⁇ of the resin used is between 17 ⁇ 10 ⁇ 6 (1 / K).
  • the thickness of the aluminum base plate used is between 0.1 and 10 (mm)
  • the occurrence of peeling is suppressed and there is no deterioration even in the temperature cycle test.
  • the warp of the aluminum base plate after molding differs depending on the thickness of the aluminum base plate, and the thickness of the aluminum base plate with higher reliability and less warpage of the aluminum base plate is the thickness of the control circuit board 1. It is between 6 and about 6 (mm).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

La présente invention a pour objectif de proposer un dispositif à semi-conducteurs de fiabilité élevée, comportant une grille de connexion et une carte de circuit de commande intégralement scellées par une résine de moulage. Le dispositif à semi-conducteurs (100) selon l'invention comprend : un élément métallique (7), sur une surface duquel sont montés des éléments semi-conducteurs (11) ; une plaque métallique (9), disposée sur l'autre côté de surface de l'élément métallique (7) avec une couche isolante (8) disposée entre ; une carte de circuit imprimé (3), sur laquelle sont montés des composants électriques (4) qui sont connectés électriquement aux éléments semi-conducteurs (11) ; et une résine de scellement (10), qui scelle intégralement l'élément métallique (7), la carte de circuit imprimé (3), et la plaque métallique (9), et pour laquelle le coefficient de dilatation linéaire à température de fonctionnement ambiante est de 15 à 23 x 10-6 (1/K).
PCT/JP2013/007628 2013-03-15 2013-12-26 Dispositif à semi-conducteurs WO2014141346A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405830A (zh) * 2015-12-09 2016-03-16 西安华为技术有限公司 系统级封装模块和封装方法
WO2017110614A1 (fr) * 2015-12-25 2017-06-29 三菱電機株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JP2022520691A (ja) * 2019-01-22 2022-04-01 モレックス エルエルシー 特定用途向けエレクトロニクスパッケージング製造プロセスを使用したスマートコネクタ及びその製造方法
JP7080365B1 (ja) 2021-03-02 2022-06-03 三菱電機株式会社 半導体パワーモジュール

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112750796A (zh) * 2019-10-30 2021-05-04 新光电气工业株式会社 半导体装置以及半导体装置的制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179732A (ja) * 2004-12-24 2006-07-06 Hitachi Ltd 半導体パワーモジュール
JP2007165692A (ja) * 2005-12-15 2007-06-28 Denso Corp 電子装置の製造方法
JP2007184315A (ja) * 2006-01-04 2007-07-19 Hitachi Ltd 樹脂封止型パワー半導体モジュール
JP2009123953A (ja) * 2007-11-15 2009-06-04 Omron Corp トランスファーモールド型パワーモジュール
JP2011199110A (ja) * 2010-03-23 2011-10-06 Mitsubishi Electric Corp パワー半導体装置及びその製造方法
JP2012182344A (ja) * 2011-03-02 2012-09-20 Mitsubishi Electric Corp パワーモジュール
JP2012256803A (ja) * 2011-06-10 2012-12-27 Mitsubishi Electric Corp パワーモジュールとその製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3516789B2 (ja) * 1995-11-15 2004-04-05 三菱電機株式会社 半導体パワーモジュール
JP3674333B2 (ja) * 1998-09-11 2005-07-20 株式会社日立製作所 パワー半導体モジュール並びにそれを用いた電動機駆動システム
JP4220641B2 (ja) * 2000-01-13 2009-02-04 電気化学工業株式会社 樹脂モールド用回路基板と電子パッケージ
JP2003158226A (ja) * 2001-11-20 2003-05-30 Sony Corp 半導体装置
JP4455488B2 (ja) * 2005-12-19 2010-04-21 三菱電機株式会社 半導体装置
JP5018355B2 (ja) * 2007-09-05 2012-09-05 株式会社デンソー モールドパッケージ
JP5200037B2 (ja) * 2010-01-21 2013-05-15 三菱電機株式会社 パワーモジュール
JP5373713B2 (ja) * 2010-07-23 2013-12-18 三菱電機株式会社 半導体装置
US8810026B2 (en) * 2010-09-02 2014-08-19 Toyota Jidosha Kabushiki Kaisha Semiconductor module
CN103229295B (zh) * 2010-11-29 2016-01-06 丰田自动车株式会社 动力模块
JP5251991B2 (ja) * 2011-01-14 2013-07-31 トヨタ自動車株式会社 半導体モジュール
JP5807348B2 (ja) * 2011-03-10 2015-11-10 富士電機株式会社 半導体装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179732A (ja) * 2004-12-24 2006-07-06 Hitachi Ltd 半導体パワーモジュール
JP2007165692A (ja) * 2005-12-15 2007-06-28 Denso Corp 電子装置の製造方法
JP2007184315A (ja) * 2006-01-04 2007-07-19 Hitachi Ltd 樹脂封止型パワー半導体モジュール
JP2009123953A (ja) * 2007-11-15 2009-06-04 Omron Corp トランスファーモールド型パワーモジュール
JP2011199110A (ja) * 2010-03-23 2011-10-06 Mitsubishi Electric Corp パワー半導体装置及びその製造方法
JP2012182344A (ja) * 2011-03-02 2012-09-20 Mitsubishi Electric Corp パワーモジュール
JP2012256803A (ja) * 2011-06-10 2012-12-27 Mitsubishi Electric Corp パワーモジュールとその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405830A (zh) * 2015-12-09 2016-03-16 西安华为技术有限公司 系统级封装模块和封装方法
WO2017110614A1 (fr) * 2015-12-25 2017-06-29 三菱電機株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JPWO2017110614A1 (ja) * 2015-12-25 2017-12-28 三菱電機株式会社 半導体装置およびその製造方法
JP2022520691A (ja) * 2019-01-22 2022-04-01 モレックス エルエルシー 特定用途向けエレクトロニクスパッケージング製造プロセスを使用したスマートコネクタ及びその製造方法
JP7080365B1 (ja) 2021-03-02 2022-06-03 三菱電機株式会社 半導体パワーモジュール
JP2022133523A (ja) * 2021-03-02 2022-09-14 三菱電機株式会社 半導体パワーモジュール

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