WO2014127552A1 - 阵列基板的制作方法、阵列基板和显示装置 - Google Patents

阵列基板的制作方法、阵列基板和显示装置 Download PDF

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Publication number
WO2014127552A1
WO2014127552A1 PCT/CN2013/073143 CN2013073143W WO2014127552A1 WO 2014127552 A1 WO2014127552 A1 WO 2014127552A1 CN 2013073143 W CN2013073143 W CN 2013073143W WO 2014127552 A1 WO2014127552 A1 WO 2014127552A1
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Prior art keywords
layer
array substrate
gate
planarization
substrate
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PCT/CN2013/073143
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English (en)
French (fr)
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魏小丹
张兴强
陆忠
张同局
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US14/352,581 priority Critical patent/US10014326B2/en
Publication of WO2014127552A1 publication Critical patent/WO2014127552A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device. Background technique
  • a planarization layer is usually formed before the formation of the pixel electrode to reduce the step difference on the substrate, so that the pixel electrode is more easily formed and reduces defects, and at the same time, in order to reduce the pixel electrode and other conductive metal layers.
  • the parasitic capacitance formed between them is generally made into a layer having a large thickness.
  • a via on the planarization layer such as a via connecting the pixel electrode to the drain electrode of the TFT, or a via connecting the driver circuit to the gate line or the data line, it is necessary to expose the planarization layer due to the exposure process.
  • the planarization layer is relatively thick, and in order to obtain the desired via size, a higher exposure energy is required, thereby reducing the exposure speed and affecting the production efficiency. Summary of the invention
  • the present invention provides a method for fabricating an array substrate, an array substrate, and a display device, which can locally reduce the thickness of the planarization layer, thereby reducing the exposure energy required for via formation, further increasing the exposure speed, and improving Productivity.
  • a method of fabricating an array substrate comprising:
  • a pad high layer is formed on the array substrate, the pad upper layer being located under the planarization layer of the array substrate and corresponding to a position of the via hole of the planarization layer, wherein the planarization layer is formed of a hot melt material.
  • the hot melt material is an acrylic material.
  • the forming a high layer on the array substrate, the high layer of the pad is located under the planarization layer of the array substrate, and the step corresponding to the position of the via of the planarization layer comprises:
  • a planarization layer is formed over the upper layer of the pad, and a via hole is formed in the planarization layer, wherein the pad high layer corresponds to a position of a via hole of the planarization layer.
  • the step of forming a TFT on the substrate of the substrate is specifically: forming a gate layer, a gate insulating layer, an active layer, and a source/drain electrode layer on the substrate of the substrate;
  • the step of forming a high-rise layer above the substrate of the substrate is specifically: forming a high-rise layer on the substrate of the village substrate or on any one of the gate layer, the gate insulating layer, the active layer and the source/drain electrode layer .
  • the manufacturing method further includes:
  • a pixel electrode layer is formed over the planarization layer, and the pixel electrode is connected to a drain electrode of the TFT through a via of the planarization layer.
  • the step of forming a gate layer, a gate insulating layer, an active layer, and a source/drain electrode layer on the substrate of the substrate further includes: forming a gate line in the same layer as the gate, and forming the same
  • the source and drain electrodes are connected to the data lines of the same layer, and the gate lines and the data lines are respectively connected to the driving circuits of the peripheral regions of the array substrate through the via holes on the planarization layer.
  • the step of forming a planarization layer on the substrate substrate on which the high-rise layer is formed includes: coating a layer of acrylic material on the substrate substrate on which the high-rise layer is formed;
  • the exposed acrylic material layer is developed and baked.
  • an array substrate comprising: a planarization layer provided with via holes, further comprising a pad upper layer, the pad upper layer being located under the planarization layer and corresponding to the via hole of the planarization layer Wherein the planarization layer is formed of a hot melt material.
  • the hot melt material is an acrylic material.
  • array substrate is specifically:
  • a planarization layer is formed over the upper layer of the pad, the planarization layer being provided with a via, the upper layer of the pad corresponding to the location of the via of the planarization layer.
  • the TFT includes a gate, a gate insulating layer, an active layer, and source and drain electrodes, and the pad is located on the substrate or on the gate layer, the gate insulating layer, the active layer, and the source and drain electrodes.
  • the pad is located on the substrate or on the gate layer, the gate insulating layer, the active layer, and the source and drain electrodes.
  • the array substrate further includes: a pixel electrode layer, the pixel electrode layer is located above the planarization layer, and the pixel electrode is connected to the TFT drain electrode through the via hole of the planarization layer.
  • the array substrate further includes a passivation layer, and the passivation layer is located on the planarization layer
  • the array substrate further includes a data line in the same layer as the source and drain electrodes, and a gate line in the same layer as the gate, wherein the data line and the gate line respectively pass through the via of the planarization layer and the array substrate The drive circuit connection in the peripheral area.
  • a display device comprising the array substrate as described above.
  • FIG. 1 is a schematic cross-sectional structural view of an array substrate without a high-rise layer
  • FIG. 2 is a cross-sectional structural view of an array substrate according to an embodiment of the invention.
  • FIG. 3 is a cross-sectional structural view of an array substrate according to another embodiment of the present invention.
  • FIG. 4 is a cross-sectional structural view of an array substrate according to another embodiment of the present invention.
  • FIG. 5 is a cross-sectional structural view of an array substrate according to another embodiment of the present invention. detailed description
  • An embodiment of the present invention provides a method for fabricating an array substrate, wherein the array substrate includes a planarization layer provided with via holes, and the fabrication method includes: forming a pad upper layer on the array substrate, wherein the pad upper layer is located on the planarization of the array substrate Below the layer, and corresponding to the location of the via of the planarization layer, wherein the planarization layer is formed of a hot melt material.
  • the hot melt material is a material that has fluidity when heated to a certain temperature.
  • the method for manufacturing the array substrate includes:
  • TFT thin film transistor
  • the hot melt material may be an acrylic material.
  • Acrylic materials are polymers obtained by polymerizing acrylic acid and its esters. They are collectively referred to as acrylic resins.
  • the corresponding plastics are collectively called polyacrylic plastics. They are light in weight, low in cost and easy to form.
  • the molding method is cast. Injection molding, machining, thermoforming, etc., especially injection molding, can be mass-produced, process cartridges, and low cost.
  • the planarization layer is not limited to the acryl material, and any material can be used for planarization in the method for fabricating the array substrate of the embodiment of the present invention as long as it has fluidity upon heating and can be cured at room temperature. The material of the layer.
  • the via hole of the planarization layer may be a via hole in which the pixel electrode of the display region is connected to the drain electrode of the TFT, but is not limited thereto.
  • a driving circuit is required to provide a gate scanning signal and a data signal for the array substrate, and the driving circuit is respectively connected to the gate lines and the data lines disposed on the array substrate through the via holes, and thus, the planarization layer Vias can also be connected to the data line and drive The via of the circuit, or the via that connects the gate line to the driver circuit.
  • the method for fabricating the array substrate according to the embodiment of the present invention may be employed.
  • the via hole in which the via hole is connected to the drain electrode of the TFT will be described as an example.
  • a planarization layer 15 is formed over the upper layer of the pad, and a via hole (portion shown by CD2) is formed on the planarization layer 15, wherein the pad high layer is located below the via position.
  • the step of forming a TFT on the substrate of the substrate comprises: forming a gate layer (not shown), a gate insulating layer 12, and an active layer 13 on the substrate substrate 11. , source and drain electrode layer 14;
  • the step of forming a high layer on the substrate substrate includes: on the substrate substrate or in the gate layer, the gate insulating layer 12 and the active layer 13 And forming a pad high layer on any one of the source/drain electrode layers.
  • the gate layer is a layer where a gate of the TFT is located, and the source/drain electrode layer is a layer where the TFT source electrode and the drain electrode are located. Since there is generally no gate layer below the via locations where the pixel electrode and the TFT drain electrode are connected, it is not shown in the drawing. If in some other methods of fabricating the array substrate, the gate layer is provided under the via position where the pixel electrode and the TFT drain electrode are connected, the pad upper layer may also be formed on the gate layer.
  • the upper layer of the pad may be the same as or different from the layer material adjacent thereto, as long as it does not affect the normal operation of the TFT and the array substrate, but when the via is a pixel electrode and a TFT leakage
  • the via is connected to the source/drain electrode layer, preferably a conductive material, so that the pixel electrode and the TFT drain electrode can be electrically connected.
  • the pad upper layer 16 may be formed directly on the substrate substrate 11.
  • the upper layer of the pad may be formed by a patterning process on the substrate of the village (ie, forming a gate layer on the substrate substrate 11 by a first patterning process, and then forming a gate layer by a second patterning process), or
  • the gate layer is formed by the same patterning process.
  • the pad high layer 16 may be formed on the gate insulating layer 12.
  • the height The layer may be formed by one patterning process on the gate insulating layer or by a half exposure technique in the same patterning process as the gate insulating layer.
  • the pad upper layer 16 may be formed on the active layer 13.
  • the pad upper layer may be formed by one patterning process on the active layer or by a half exposure technique in the same patterning process as the active layer.
  • the pad upper layer 16 may also be formed on the source/drain electrode layer 14.
  • the upper layer of the pad may be formed by one patterning process on the source/drain electrode layer, or formed by a half exposure technique in the same patterning process as the source/drain electrode layer, of course, in order to ensure electrical connection between the pixel electrode and the drain electrode of the TFT.
  • the upper layer of the pad needs to be made of a conductive material.
  • the step of forming a planarization layer 15 over the upper layer of the pad and forming a via hole on the planarization layer 15 includes:
  • the acryl material layer is formed by drying it in a low-pressure environment and further curing it under heating conditions;
  • the development of the exposed acrylic material layer is carried out by forming the via hole with a developing solution for removing the residual developing solution and the cleaning agent for cleaning the developing solution.
  • the method for fabricating the array substrate further includes:
  • a pixel electrode layer is formed over the planarization layer, and the pixel electrode is connected to the TFT drain electrode through the via hole.
  • the pixel electrode layer is a layer where the pixel electrode is located.
  • the step of forming a gate layer, a gate insulating layer, an active layer, and a source/drain electrode layer on the substrate of the substrate further includes:
  • a gate line is formed in the same layer as the gate, and a data line is formed in the same layer as the source and drain electrodes.
  • the pad The upper layer can also be formed in multiple locations, and the upper layers of the pads below the vias at different locations can be formed in the same layer, or Different layers are formed, but for the tubeization of the process, it is preferable that the upper layer of the pad is formed in the same layer, such as on the substrate of the substrate, the via hole corresponding to the pixel electrode and the drain electrode of the TFT, and the gate line is connected to the driving circuit.
  • the pad upper layer is simultaneously formed.
  • the gate layer, the gate insulating layer, the active layer, and the source/drain electrode layer are not necessarily all below the via hole corresponding to the planarization layer. There is no gate layer below the via hole where the corresponding pixel electrode and the TFT drain electrode are connected, and there may be no gate insulating layer and active layer below the via hole where the gate line is connected to the driving circuit. Wait.
  • the order of the gate layer, the gate insulating layer, the active layer, and the source/drain electrode layer is not limited to the one shown in the drawing. Only the bottom gate type TFT array substrate is shown in the figure, and the top gate type TFT array substrate is shown.
  • the method of fabricating the array substrate of the embodiment of the present invention is equally applicable.
  • the planarization layer is formed over the passivation layer, and the via hole should also pass through the passivation layer.
  • a via pattern may be used to fabricate the via hole penetrating the passivation layer and the planarization layer; and the via hole on the through-planarization layer may be separately formed by using a Mask process, and the passivation layer may be penetrated through the passivation layer. Through hole.
  • the manufacturing method may further include: forming a buffer layer on the substrate of the substrate (the buffer layer may include: a silicon nitride buffer layer and a silicon oxide buffer layer); and forming the buffer layer after forming the buffer layer a gate insulating layer, an active layer, and a source/drain electrode layer; the pad upper layer may also be formed on the buffer layer.
  • the buffer layer may include: a silicon nitride buffer layer and a silicon oxide buffer layer
  • the buffer layer after forming the buffer layer a gate insulating layer, an active layer, and a source/drain electrode layer; the pad upper layer may also be formed on the buffer layer.
  • the method further includes: forming an interlayer insulating layer between the layer including the gate and the source/drain electrode layer The high layer of the pad may also be formed on the interlayer insulating layer.
  • the pad upper layer 16 may be formed on the substrate of the substrate or on any layer between the substrate and the planarization layer, such as may be formed on the gate layer or formed on the gate insulating layer. Or formed on the active layer or formed on the source/drain electrode layer.
  • the pad high layer may also be formed on the layers as long as the formation is flat.
  • the pad upper layer 16 is preferably disposed on the substrate substrate or on a layer adjacent to the substrate substrate.
  • the via is connected to the drain electrode of the TFT, and the upper layer of the pad is preferably disposed on the substrate on the substrate or under the source/drain electrode layer; and the via is used as a via for connecting the data line and the driving circuit.
  • the upper layer of the pad is disposed on a substrate on the substrate or under the source/drain electrode layer; and the via is a via for connecting the gate line and the driving circuit, and the upper layer of the pad is preferably disposed on the substrate of the substrate. Above or on the layer below the gate layer.
  • the thickness of the planarization layer is usually greater than 2 ⁇ m, and after the pad layer 16 is increased, the total thickness of the planarization layer from the upper surface of the entire array substrate to the upper surface of the planarization layer is constant;
  • FIG. 1 is a cross-sectional structural view of an array substrate having no high-rise layers
  • FIG. 2 is a cross-sectional structural view of an array substrate provided with a high-layer layer according to an embodiment of the present invention.
  • CD2-CDl 2 x H/tg o
  • ⁇ is the side of the flattening layer and the side of the via hole when there is no high layer
  • the angle of the Due to the presence of the upper layer of the pad, in order to obtain a standard via size, the required exposure energy is lower, and the exposure speed is improved, further increasing the device throughput.
  • An embodiment of the present invention further provides an array substrate including a planarization layer having via holes thereon, the array substrate further including a pad upper layer, the pad upper layer being located under the planarization layer of the array substrate, and Corresponding to the via of the planarization layer, wherein the planarization layer is made of a hot melt material.
  • the hot melt material may be an acrylic material.
  • Acrylic materials are polymers obtained by polymerizing acrylic acid and its esters. They are collectively referred to as acrylic resins.
  • the corresponding plastics are collectively called polyacrylic plastics. They are light in weight, low in cost and easy to form.
  • the molding method is cast. Injection molding, machining, thermoforming, etc., especially injection molding, can be mass-produced, process cartridges, and low cost.
  • the planarization layer is not limited to the acryl material, and any material that has fluidity upon heating and can maintain the curing at room temperature can be used as a planarization layer in the array substrate of the embodiment of the present invention. s material.
  • the via corresponding to the planarization layer may be a via connecting the pixel electrode to the drain electrode of the TFT.
  • the driving circuit is respectively connected to the gate line and the data line through the via hole to provide a line scan signal and a data signal for the array substrate, and therefore, the planarization layer
  • the via hole may also be a via hole connecting the driving circuit and the data line, or a via hole connecting the driving circuit and the gate line.
  • the via holes in the array substrate of the embodiment of the present invention are not limited to the above. In other variations of the array substrate structure, as long as the via holes are formed on the planarization layer, the arrays are applicable to the arrays of the embodiments of the present invention.
  • the structure of the substrate is not limited to the above.
  • the via hole is a via hole in which the pixel electrode is connected to the drain electrode of the TFT as an example.
  • An embodiment of the present invention provides an array substrate, including:
  • a planarization layer is formed over the upper layer of the pad, the planarization layer being provided with a via, the upper layer of the pad corresponding to the location of the via of the planarization layer.
  • the TFT includes a gate, a gate insulating layer, an active layer, and a source/drain electrode; the high layer of the pad is located on the substrate of the substrate, or is located at the gate layer, the gate insulating layer, the active layer, On any of the source and drain electrode layers.
  • the gate layer is a layer where the gate is located
  • the source/drain electrode layer is a layer where the TFT source electrode and the drain electrode are located.
  • the via hole is a via hole to which the pixel electrode and the TFT drain electrode are connected
  • the via hole generally does not have a gate layer under the via hole, and thus is not shown in the drawing.
  • the pad high layer may also be located on the gate layer.
  • the upper layer of the pad may be the same as or different from the layer material adjacent thereto, as long as it does not affect the normal operation of the TFT and the array substrate, but when the via is a pixel electrode and a TFT leakage
  • the via is connected to the source/drain electrode layer, it is preferably a conductive material so that the pixel electrode and the TFT drain electrode can be electrically connected.
  • the pad upper layer 16 may be located on the substrate substrate 11. Specifically, the pad upper layer may be a layer formed separately on the substrate substrate or formed in the same layer as the gate.
  • the pad upper layer 16 may be located on the gate insulating layer 12.
  • the pad upper layer may be a layer formed separately on the gate insulating layer 12 or formed in the same layer as the gate insulating layer by a half exposure technique.
  • the pad upper layer 16 may be located on the active layer 13.
  • the upper layer of the pad may be a layer formed separately on the active layer 13 or may pass through the active layer The exposure technique is formed in the same layer.
  • the pad upper layer 16 may also be located on the source/drain electrode layer 14.
  • the upper layer of the pad may be a layer formed separately on the source/drain electrode layer 14, or may be formed in the same layer as the source/drain electrode layer by a half exposure technique.
  • the upper layer of the pad is a conductive material.
  • the array substrate further includes a pixel electrode layer, the pixel electrode layer being located above the planarization layer, and via holes on the planarization layer for connecting the pixel electrode and the drain electrode of the TFT.
  • the pixel electrode layer is a layer where the pixel electrode is located.
  • the array substrate further includes: forming the same layer as the gate a gate line, a data line formed in the same layer as the source/drain electrode; in the array substrate, the gate line and the number need to be described, since the planarization layer may have a plurality of via holes, the pad upper layer may also be formed In a plurality of positions, the upper layers of the pads below the vias at different positions may be in the same layer or may not be in the same layer, but for the tubeization of the process, it is preferable that the upper layers of the pads are formed in the same layer, as in the substrate of the substrate.
  • the upper layer of the pad is formed at the via of the pixel electrode and the drain electrode of the TFT, the via of the gate line connected to the driving circuit, and the via of the data line and the driving circuit.
  • the gate layer, the gate insulating layer 12, the active layer 13, and the source/drain electrode layer 14 may not all be present, such as leakage in the corresponding pixel electrode and TFT.
  • Below the via-connected via there may be no gate layer, and there is no gate insulating layer and active layer below the via where the driver circuit and the gate line are connected.
  • the order of the gate layer, the gate insulating layer 12, the active layer 13, and the source/drain electrode layer 14 is not limited to the one shown in the drawing, and only the bottom gate type TFT array substrate is shown in the figure, for the top gate type.
  • the TFT array substrate, the array substrate of the embodiment of the present invention is also applicable.
  • the via hole of the planarization layer should also pass through the passivation layer, that is, the via hole penetrates through the passivation layer and the planarization layer, and the pixel electrode and the TFT drain electrode are connected through the via hole; Or, under the via hole of the planarization layer, the passivation layer is also formed with a via hole, and the passivation layer via hole communicates with the via hole of the planarization layer, and the pixel electrode and the TFT drain electrode pass through the The via of the planarization layer is connected to the via of the passivation layer.
  • the array substrate may further include: a buffer formed on the substrate of the substrate a layer (the buffer layer may include: a silicon nitride buffer layer and a silicon oxide buffer layer); a gate layer, a gate insulating layer, an active layer, and a source/drain electrode layer are formed over the buffer layer; Located on the buffer layer.
  • the buffer layer may include: a silicon nitride buffer layer and a silicon oxide buffer layer
  • a gate layer, a gate insulating layer, an active layer, and a source/drain electrode layer are formed over the buffer layer; Located on the buffer layer.
  • the method further includes: an interlayer insulating layer formed between the gate layer and the source/drain electrode layer; The upper layer may also be located on the interlayer insulating layer.
  • the pad upper layer 16 may be located on the substrate substrate or on any layer between the substrate substrate and the planarization layer, such as may be formed on the gate layer, or formed on the gate insulating layer, or Formed on the active layer or formed on the source/drain electrode layer.
  • the pad high layer may also be located on the layers as long as the planarization is formed.
  • the thickness of the material having a hot melt such as an acryl material at a position where the via hole is formed can be reduced by increasing the height below the position of the planarization layer corresponding to the via hole.
  • the mat is high-rise
  • the via is a via connected to the pixel electrode and the drain electrode of the TFT, and the upper layer of the pad is preferably disposed on a substrate on the substrate or under the source/drain electrode layer;
  • the upper layer of the driving circuit is preferably disposed on the substrate on the substrate or on the layer below the source/drain electrode layer; for example, the via is a via connecting the gate line and the driving circuit, and the pad is used as an example.
  • the upper layer is preferably disposed on the substrate on the substrate or on the layer below the gate layer.
  • an embodiment of the present invention further provides a display device comprising the array substrate as described in any of the above embodiments.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color film substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • OLED organic electroluminescence display device
  • an organic light emitting material stack is formed on the array substrate, and a pixel electrode of each pixel unit is used as an anode or a cathode for driving the organic light emitting material to emit light. Perform the display operation.
  • Still another example of the display device is an electronic paper display device, wherein the array substrate is formed with The electronic ink layer, the pixel electrode of each pixel unit serves as a voltage for applying a moving microparticle moving in the driving electronic ink to perform a display operation.
  • the material forming the planarization layer has a heat flowable property
  • the corresponding position of the via hole in the exposure process The thickness of the planarization layer is reduced; due to the reduced thickness of the planarization layer, in order to obtain a standard via size, the required exposure energy is lowered, thereby increasing the exposure speed and further increasing the device throughput.

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Abstract

一种阵列基板的制作方法、阵列基板和显示装置，所属阵列基板的制作方法包括：在阵列基板（11）上形成垫高层（16），所述垫高层（16）位于平坦化层（15）下方，且对应于平坦化层（15）的过孔的位置，其中，所述平坦化层（15）由热熔性材料形成。

Description

阵列基板的制作方法、 阵列基板和显示装置
技术领域
本发明的实施例涉及显示技术领域，特别涉及一种阵列基板的制作方法、 阵列基板和显示装置。 背景技术
在阵列基板的制作过程中， 通常在像素电极形成之前会形成一层平坦化 层， 以减少基板上的段差， 使得像素电极更易形成且减少不良， 同时为了减 小像素电极与其它导电金属层之间形成的寄生电容， 该平坦化层一般都制作 成厚度较大的层。 但是， 在制作平坦化层上的过孔时， 如像素电极与 TFT漏 电极连接的过孔， 或者连接驱动电路与栅线或数据线的过孔等， 需要对平坦 化层进行曝光处理， 由于平坦化层比较厚， 为了获得预期的过孔尺寸， 需要 较高的曝光能量， 从而降低了曝光速度， 影响生产效率。 发明内容
为解决上述技术问题， 本发明提供一种阵列基板的制作方法、 阵列基板 和显示装置， 可以局部减小平坦化层的厚度， 从而减少过孔形成所需要的曝 光能量， 进一步增加曝光速度， 提高生产效率。
根据本发明的第一方面， 提供一种阵列基板的制作方法， 该阵列基板包 括提供有过孔的平坦化层， 该制作方法包括：
在阵列基板上形成垫高层， 所述垫高层位于阵列基板的平坦化层下方， 且对应于所述平坦化层的过孔的位置， 其中， 所述平坦化层由热熔性材料形 成。
进一步的， 所述热熔性材料为亚克力材料。
进一步的， 所述在阵列基板上形成垫高层， 所述垫高层位于阵列基板的 平坦化层下方， 且对应于所述平坦化层的过孔的位置的步骤包括：
提供一村底基板， 在所述村底基板上形成 TFT; 在所述村底基板上方形成垫高层； 及
在所述垫高层上方形成平坦化层， 并在所述平坦化层中形成过孔， 其中 所述垫高层对应所述平坦化层的过孔的位置。
进一步的， 所述在村底基板上形成 TFT的步骤具体为： 在所述村底基板 上形成栅极层、 栅绝缘层、 有源层和源漏电极层；
所述在村底基板上方形成垫高层的步骤具体为： 在所述村底基板上或者 在所述栅极层、 栅绝缘层、 有源层和源漏电极层中任意一层上形成垫高层。
进一步的， 该制作方法还包括：
在所述平坦化层上方形成像素电极层， 所述像素电极通过所述平坦化层 的过孔与所述 TFT的漏电极连接。
进一步的， 所述在村底基板上形成栅极层、 栅绝缘层、 有源层、 源漏电 极层的步骤， 还包括： 形成与所述栅极同层的栅线， 并且形成与所述源漏电 极同层的数据线， 所述栅线和所述数据线分别通过平坦化层上的过孔与阵列 基板周边区域的驱动电路连接。
进一步的，在形成有垫高层的所述村底基板上形成平坦化层的步骤包括： 在形成有垫高层的所述村底基板上涂覆亚克力材料层；
对所述亚克力材料层进行低压干燥和烘烤；
对低压干燥和烘烤后的所述亚克力材料层进行曝光； 及
对曝光后的所述亚克力材料层进行显影和烘烤。
根据本发明的第二方面， 还提供一种阵列基板， 包括提供有过孔的平坦 化层， 还包括垫高层， 所述垫高层位于平坦化层下方， 且对应于平坦化层的 过孔处， 其中， 所述平坦化层由热熔性材料形成。
进一步的， 所述热熔性材料为亚克力材料。
进一步的， 所述阵列基板具体为：
村底基板以及形成于所述村底基板上的 TFT;
形成在所述村底基板上方的垫高层；
形成在所述垫高层上方的平坦化层， 所述平坦化层提供有过孔， 所述垫 高层对应所述平坦化层的过孔的位置。
进一步的， 所述 TFT包括栅极、 栅绝缘层、 有源层和源漏电极， 所述垫 高层位于所述村底基板上或者位于栅极层、 栅绝缘层、 有源层和源漏电极层 中的任意一层上。
进一步的， 该阵列基板还包括： 像素电极层， 所述像素电极层位于平坦 化层上方， 所述像素电极通过所述平坦化层的过孔与 TFT漏电极连接。
进一步的， 该阵列基板还包括钝化层， 所述钝化层位于所述平坦化层的
进一步的， 该阵列基板还包括与源漏电极同层的数据线， 以及与栅极同 层的栅线， 所述数据线与所述栅线分别通过所述平坦化层的过孔与阵列基板 周边区域的驱动电路连接。
根据本发明的第三方面， 还提供一种显示装置， 包括如上所述的阵列基 板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为没有垫高层的阵列基板的剖面结构示意图；
图 2为本发明一实施例的阵列基板的剖面结构示意图；
图 3为本发明另一实施例的阵列基板的剖面结构示意图；
图 4为本发明另一实施例的阵列基板的剖面结构示意图；
图 5为本发明另一实施例的阵列基板的剖面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制，而是表示存在至少一个。 "包括"或者 "包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出 现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其 他元件或者物件。 "连接"或者 "相连"等类似的词语并非限定于物理的或者 机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置 改变后， 则该相对位置关系也可能相应地改变。
本发明的实施例提供一种阵列基板的制作方法， 其中阵列基板包括提供 有过孔的平坦化层， 该制作方法包括： 在阵列基板上形成垫高层， 所述垫高 层位于阵列基板的平坦化层下方， 且对应于所述平坦化层的过孔的位置， 其 中， 所述平坦化层由热熔性材料形成。 所述热熔性材料为在加热到一定温度 时具有流动性的材料。
具体的， 所述阵列基板的制作方法， 包括：
提供一村底基板， 在所述村底基板上形成薄膜晶体管 （TFT, thin film transistor );在所述 TFT上方形成平坦化层，并在所述平坦化层上形成有过孔； 在阵列基板上形成垫高层， 所述垫高层位于所述村底基板上方且所述平坦化 层下方， 且所述垫高层对应于所述平坦化层的过孔的位置。
具体的， 所述热熔性材料可以为亚克力材料。 亚克力材料是以丙烯酸及 其酯类聚合所得到的聚合物， 统称丙烯酸类树酯， 相应的塑料统称聚丙烯酸 类塑料， 具有质轻、 价廉， 易于成型等优点； 它的成型方法有浇铸， 射出成 型， 机械加工、 热成型等， 尤其是射出成型， 可以大批量生产， 制程筒单， 成本低。 当然， 本发明实施例中平坦化层并不限于亚克力材料， 任何材料只 要在加热时具有流动性， 并且常温又可以保持固化， 都可以在本发明实施例 阵列基板的制作方法中用作平坦化层的材料。
所述平坦化层的过孔可以为显示区像素电极与 TFT漏电极连接的过孔， 但不限于此。 例如， 在阵列基板的周边区域， 需要设置驱动电路为阵列基板 提供栅扫描信号和数据信号， 驱动电路通过过孔分别与阵列基板上设置的栅 线和数据线连接， 因此， 所述平坦化层的过孔也可以为连接数据线与驱动电 路的过孔， 或者为连接栅线与驱动电路的过孔。 此外， 如果其他阵列基板的 制作方法的变形中需要在平坦化层上形成过孔， 都可以采用本发明实施例所 述的阵列基板的制作方法。
参见图 2至图 5,下面以所述过孔为像素电极与 TFT漏电极连接的过孔 为例进行说明。
本发明的实施例提供的阵列基板的制作方法包括：
51 , 提供一村底基板 11 , 在所述村底基板上形成 TFT;
52, 在所述村底基板 11上方形成垫高层；
53, 在所述垫高层上方形成平坦化层 15, 并在所述平坦化层 15上形成 过孔（CD2所示的部分）， 其中所述垫高层位于所述过孔位置的下方。
在上述步骤 S1中， 在所述村底基板上形成 TFT的步骤， 具体包括： 在所述村底基板 11上形成栅极层（图中未示出）、 栅绝缘层 12、 有源层 13、 源漏电极层 14;
在上述步骤 S2中， 在所述村底基板上方形成垫高层的步骤， 具体包括： 在所述村底基板上或者在所述栅极层， 所述栅绝缘层 12、所述有源层 13、所 述源漏电极层任意一层上形成垫高层。
需要说明的是， 所述栅极层为 TFT的栅极所在的层， 所述源漏电极层为 TFT源电极和漏电极所在的层。因为在像素电极和 TFT漏电极连接的过孔位 置下方一般不具有栅极层， 所以图中未示出。 如果在其他一些阵列基板的制 作方法中， 在像素电极和 TFT漏电极连接的过孔位置下方具有所述栅极层， 则所述垫高层也可以形成在所述栅极层上。 一般而言， 所述垫高层可以和与 之相邻的层材料相同， 也可以不同， 只要其不影响 TFT以及阵列基板的正常 工作即可， 但是， 当所述过孔为像素电极和 TFT漏电极连接的过孔， 所述垫 高层形成于所述源漏电极层上时优选为导电材料，使得像素电极和 TFT漏电 极能实现电连接。
如图 2所示， 所述垫高层 16可以直接在所述村底基板 11上形成。 所述 垫高层可以为在村底基板上通过一次构图工艺形成（即在村底基板 11上通过 第一次构图工艺形成垫高层后，再通过第二次构图工艺形成栅极层），或者与 所述栅极层同一次构图工艺形成。
如图 3所示， 所述垫高层 16可以在所述栅绝缘层 12上形成。 所述垫高 层可以为在所述栅绝缘层上通过一次构图工艺形成， 或者与所述栅绝缘层同 一次构图工艺通过半曝光技术形成。
如图 4所示， 所述垫高层 16可以在所述有源层 13上形成。 所述垫高层 可以为在所述有源层上通过一次构图工艺形成， 或者与所述有源层同一次构 图工艺通过半曝光技术形成。
如图 5所示， 所述垫高层 16还可以在所述源漏电极层 14上形成。 所述 垫高层可以为在所述源漏电极层上通过一次构图工艺形成， 或者与所述源漏 电极层同一次构图工艺通过半曝光技术形成， 当然为了保证像素电极和 TFT 漏电极的电连接， 所述垫高层需要采用导电材料。
在上述步骤 S3中， 在所述垫高层上方形成平坦化层 15 , 并在所述平坦 化层 15上形成过孔的步骤， 具体包括：
在形成有垫高层的村底基板上涂覆一层亚克力材料； 对所述亚克力材料 层进行低压干燥和烘烤;对低压干燥和烘烤后的所述亚克力材料层进行曝光； 对曝光后的所述亚克力材料层进行显影和烘烤。 需要说明的是， 其中， 对所 述亚克力材料层进行低压干燥和烘烤， 是通过在低压环境中对其进行干燥以 及在加热的条件下进一步使其固化来完成所述亚克力材料层的成型； 对曝光 后的所述亚克力材料层进行显影是利用显影液形成所述过孔， 烘烤是为了将 残留的显影液以及清洗显影液的清洗剂去除。
在一个示例中， 所述阵列基板的制作方法， 还包括：
在所述平坦化层的上方形成像素电极层， 所述像素电极通过所述过孔与 所述 TFT漏电极连接。 其中， 所述像素电极层为像素电极所在的层。
如前所述， 如果所述过孔为连接阵列基板的周边区域中的驱动电路和数 据线的过孔， 或者为连接驱动电路和栅线的过孔， 则在上述步骤 S1 中， 所 述在所述村底基板上形成栅极层、 栅绝缘层、 有源层、 源漏电极层的步骤， 还包括：
在所述阵列基板中， 与所述栅极同层形成栅线， 与所述源漏电极同层形 成数据线； 需要说明的是， 由于平坦化层上可以形成有多个过孔， 因此垫高层也可 以形成在多个位置， 在不同位置的过孔下方的垫高层可以同层形成， 也可以 不同层形成， 但为了工艺的筒化， 优选所述垫高层形成在同层， 如在所述村 底基板上， 对应像素电极和 TFT漏电极连接的过孔处、栅线与驱动电路连接 的过孔处以及数据线与驱动电路连接的过孔处， 同时形成垫高层。
需要说明的是， 在上述阵列基板的制作方法中， 在对应于所述平坦化层 的过孔处的下方， 所述栅极层、 栅绝缘层、 有源层、 源漏电极层不一定全都 存在， 如在对应像素电极和 TFT漏电极连接的过孔处的下方， 可以不具有栅 极层， 在栅线与驱动电路连接的过孔处的下方， 可以不具有栅绝缘层和有源 层等。 当然， 所述栅极层、 栅绝缘层， 有源层、 源漏电极层的顺序也不限于 图中所示， 图中仅示出了底栅型 TFT阵列基板， 对于顶栅型 TFT阵列基板 以及其他结构的变形， 本发明实施例的阵列基板的制作方法同样适用。 钝化层的步骤， 所述平坦化层形成于所述钝化层上方， 所述过孔还应当穿过 所述钝化层。 具体可以采用一次构图 （Mask )工艺制作该贯穿该钝化层以及 该平坦化层的过孔； 也可以采用两次 Mask工艺分别制作该贯穿平坦化层上 的过孔， 以及贯穿该钝化层的过孔。
在其他实施例中，该制作方法还可以包括：在村底基板上形成緩沖层（緩 沖层可以包括： 氮化硅緩沖层和氧化硅緩沖层）；在形成所述緩沖层后再形成 所述栅绝缘层、 有源层和源漏电极层； 所述垫高层还可以形成于所述緩沖层 上。
在其他实施例中， 如在顶栅型低温多晶硅薄膜晶体管（ LTPS TFT )阵列 基板的制作方法中， 还可以包括： 在所述包括栅极的层和源漏电极层之间形 成层间绝缘层； 所述垫高层还可以形成于所述层间绝缘层上。
总之，所述垫高层 16可以在村底基板上或者在村底基板和平坦化层之间 任意一层上形成， 如可以在所述栅极层上形成， 或者所述栅绝缘层上形成， 或者在所述有源层上形成， 或者在所述源漏电极层上形成。 当然， 如果在对 应平坦化层的过孔的位置， 在所述村底基板和所述平坦化层之间还包括其他 的层， 所述垫高层也可以形成在这些层上， 只要在形成平坦化层时， 能通过 增加平坦化层对应过孔的位置下方的高度使得具有热熔性的材料如亚克力材 料在形成过孔的位置的厚度减小即可。 但是， 为了过孔形成的便利， 所述垫 高层 16优选设置于村底基板上或者靠近村底基板的层上。以所述过孔为像素 电极和 TFT漏电极连接的过孔为例，所述垫高层优选设置于村底基板上或者 源漏电极层下方的层上； 以所述过孔为连接数据线和驱动电路的过孔为例， 所述垫高层优选设置于村底基板上或者源漏电极层下方的层上； 以所述过孔 为连接栅线和驱动电路的过孔为例， 所述垫高层优选设置于村底基板上或者 栅极层下方的层上。
在上述各阵列基板的制作方法中， 平坦化层的厚度通常大于 2 μ ιη, 在 增加垫高层 16之后，从整个阵列基板的上表面到平坦化层上表面，其总厚度 不变； 但由于垫高层的存在， 在曝光工艺中， 由于形成平坦化层的亚克力材 料具有易于流动的性质， 使过孔对应位置处的平坦化层厚度降低了； 由于平 坦化层厚度降低， 导致在同样的曝光能量的条件下， 其所得到的过孔的关键 尺寸 CD ( critical dimension ) (过孔的直径 )增加。 如图 1和图 2所示， 图 1 为没有垫高层的阵列基板的剖面结构图， 图 2为本发明一实施例设置有垫高 层的阵列基板的剖面结构图。 当设置垫高层厚度为 H时， CD (过孔的直径） 改变量为： CD2-CDl=2 x H/tg o , 其中， α为没有垫高层时， 平坦化层的底 面与过孔的侧面的夹角。 由于垫高层的存在， 为了获得标准的过孔尺寸， 需 要的曝光能量较低， 从而曝光速度得到提高， 进一步增加设备产能。
本发明的实施例还提供一种阵列基板， 包括平坦化层， 所述平坦化层上 具有过孔， 所述阵列基板还包括垫高层， 所述垫高层位于阵列基板的平坦化 层下方， 且对应于平坦化层的过孔处， 其中， 所述平坦化层由热熔性材料制 成。
具体的， 所述热熔性材料可以为亚克力材料。 亚克力材料是以丙烯酸及 其酯类聚合所得到的聚合物， 统称丙烯酸类树酯， 相应的塑料统称聚丙烯酸 类塑料， 具有质轻、 价廉， 易于成型等优点； 它的成型方法有浇铸， 射出成 型， 机械加工、 热成型等， 尤其是射出成型， 可以大批量生产， 制程筒单， 成本低。 当然， 本发明实施例中平坦化层并不限于亚克力材料， 任何材料只 要在加热时具有流动性， 并且常温又可以保持固化的材料， 都可以在本发明 实施例阵列基板中用作平坦化层的材料。
其中， 所述对应于该平坦化层处的过孔可以为所述像素电极与 TFT漏 电极连接的过孔。 在阵列基板的周边区域， 驱动电路通过过孔分别与栅线和 数据线连接， 为阵列基板提供行扫描信号和数据信号， 因此， 所述平坦化层 上的过孔还可以为连接驱动电路和数据线的过孔， 或者为连接驱动电路和栅 线的过孔等。 当然， 本发明实施例的阵列基板中的过孔不限于以上几种， 在 其他阵列基板结构的变形中， 只要在平坦化层上形成有过孔， 都适用于本发 明实施例所述的阵列基板的结构。
具体的， 以所述过孔为像素电极与 TFT漏电极连接的过孔为例进行说 明。
本发明实施例提供一种阵列基板， 包括：
村底基板以及形成在所述村底基板上的 TFT;
形成在所述村底基板上方的垫高层；
形成在所述垫高层上方的平坦化层， 所述平坦化层提供有过孔， 所述垫 高层对应所述平坦化层的过孔的位置。
具体的， 所述 TFT包括栅极、 栅绝缘层、 有源层、 源漏电极； 所述垫高 层位于所述村底基板上， 或者位于所述栅极层、 栅绝缘层、 有源层、 源漏电 极层中的任意一层上。 其中， 所述栅极层为所述栅极所在的层， 所述源漏电 极层为所述 TFT源电极和漏电极所在的层。
当然， 对于所述过孔为像素电极和 TFT漏电极连接的过孔的情况， 所述 过孔下方一般不具有栅极层， 所以图中未示出。 如果所述过孔下方具有所述 栅极层， 则所述垫高层还可以位于所述栅极层上。 一般而言， 所述垫高层可 以和与之相邻的层材料相同， 也可以不同， 只要其不影响 TFT以及阵列基板 的正常工作即可，但是，当所述过孔为像素电极和 TFT漏电极连接的过孔时， 所述垫高层形成于所述源漏电极层上时， 优选为导电材料， 使得像素电极和 TFT漏电极能实现电连接。
如图 2所示， 所述垫高层 16可以位于所述村底基板 11上。 具体的， 所 述垫高层可以为在所述村底基板上单独形成的一层， 或者与所述栅极同层形 成。
如图 3所示， 所述垫高层 16可以位于所述栅绝缘层 12上。 具体的， 所 述垫高层可以为在所述栅绝缘层 12上单独形成的一层，或者与所述栅绝缘层 通过半曝光技术同层形成。
如图 4所示， 所述垫高层 16可以位于所述有源层 13上。 具体的， 所述 垫高层可以为在所述有源层 13上单独形成的一层，或者与所述有源层通过半 曝光技术同层形成。
如图 5所示，所述垫高层 16还可以位于所述源漏电极层 14上。具体的， 所述垫高层可以为在所述源漏电极层 14上单独形成的一层，或者与所述源漏 电极层通过半曝光技术同层形成。 当然为了保证像素电极和 TFT漏电极的电 连接， 所述垫高层为导电材料。
在一个示例中， 所述阵列基板还包括像素电极层， 所述像素电极层位于 平坦化层上方，所述平坦化层上的过孔用于连接所述像素电极和 TFT的漏电 极。 其中， 所述像素电极层为像素电极所在的层。
如果所述平坦化层的过孔还包括连接驱动电路和数据线的过孔， 以及连 接驱动电路和栅线的过孔， 则所述阵列基板， 还包括： 与所述栅极同层形成 的栅线， 与所述源漏电极同层形成的数据线； 在阵列基板中， 所述栅线和数 需要说明的是， 由于平坦化层上可以具有多个过孔， 因此垫高层也可以 形成在多个位置， 在不同位置的过孔下方的垫高层可以在同层， 也可以不在 同层， 但为了工艺的筒化， 优选所述垫高层形成在同层， 如在所述村底基板 上， 对应像素电极和 TFT漏电极连接的过孔处、栅线与驱动电路连接的过孔 处以及数据线与驱动电路连接的过孔处， 同时形成垫高层。
在对应于所述平坦化层的过孔处的下方， 所述栅极层， 栅绝缘层 12, 有 源层 13、 源漏电极层 14也不一定全都存在， 如在对应像素电极和 TFT漏电 极连接的过孔处的下方， 可以不具有栅极层， 在驱动电路和栅线连接的过孔 处的下方， 不具有栅绝缘层和有源层。 当然， 所述栅极层， 栅绝缘层 12, 有 源层 13、源漏电极层 14的顺序也不限于图中所示，图中仅示出了底栅型 TFT 阵列基板， 对于顶栅型 TFT阵列基板， 本发明实施例的阵列基板同样适用。 述平坦化层的过孔还应当穿过所述钝化层， 即所述过孔贯穿所述钝化层和所 述平坦化层， 所述像素电极与 TFT漏电极通过所述过孔连接； 或者在所述平 坦化层的过孔下方， 所述钝化层也形成有过孔， 且钝化层过孔与平坦化层的 过孔上下相通，所述像素电极与 TFT漏电极通过所述平坦化层的过孔和钝化 层的过孔连接。
在其他实施例中， 上述阵列基板还可以包括： 在村底基板上形成的緩沖 层（緩沖层可以包括： 氮化硅緩沖层和氧化硅緩沖层）； 在所述緩沖层上方形 成有栅极层、 栅绝缘层、 有源层和源漏电极层； 所述垫高层还可以位于所述 緩沖层上。
在其他实施例中， 如在顶栅型低温多晶硅薄膜晶体管（LTPS TFT )阵列 基板中， 还可以包括： 形成于所述栅极层和源漏电极层之间的层间绝缘层； 所述垫高层还可以位于所述层间绝缘层上。
总之，所述垫高层 16可以位于村底基板上或者在村底基板和平坦化层之 间任意一层上， 如可以在所述栅极层上形成， 或者所述栅绝缘层上形成， 或 者在所述有源层上形成， 或者在所述源漏电极层上形成。 当然， 如果在对应 平坦化层的过孔的位置， 在所述村底基板和所述平坦化层之间还包括其他的 层， 所述垫高层也可以位于这些层上， 只要在形成平坦化层时， 能通过增加 平坦化层对应过孔的位置下方的高度使得具有热熔性的材料如亚克力材料在 形成过孔的位置的厚度减小即可。 但是， 为了过孔形成的便利， 所述垫高层
16优选设置于村底基板上或者靠近村底基板的层上。以所述过孔为像素电极 和 TFT漏电极连接的过孔为例，所述垫高层优选设置于村底基板上或者源漏 电极层下方的层上； 以所述过孔为连接数据线和驱动电路的过孔为例， 所述 垫高层优选设置于村底基板上或者源漏电极层下方的层上； 以所述过孔为连 接栅线和驱动电路的过孔为例， 所述垫高层优选设置于村底基板上或者栅极 层下方的层上。
另外， 本发明的实施例还提供一种显示装置， 包括如上述任一实施例所 述的阵列基板。
该显示装置的一个示例为液晶显示装置， 其中， 阵列基板与对置基板彼 此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜 基板。 阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转 的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示装置还包括 为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置（OLED ), 其中， 阵 列基板上形成有有机发光材料叠层， 每个像素单元的像素电极作为阳极或阴 极用于驱动有机发光材料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置， 其中， 阵列基板上形成有 电子墨水层， 每个像素单元的像素电极作为用于施加驱动电子墨水中的带电 微颗粒移动以进行显示操作的电压。
在本发明实施例的显示装置中， 由于在阵列基板的平坦化层过孔处下方 存在垫高层， 以及形成平坦化层的材料具有加热可流动的性质， 使得在曝光 工艺中， 过孔对应位置处的平坦化层厚度降低； 由于平坦化层厚度降低， 使 得为了获得标准的过孔尺寸， 需要的曝光能量降低， 从而提高曝光速度， 进 一步增加设备产能。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的制作方法， 该阵列基板包括提供有过孔的平坦化层， 该制作方法包括：
在阵列基板上形成垫高层， 所述垫高层位于阵列基板的平坦化层下方， 且对应于所述平坦化层的过孔的位置， 其中， 所述平坦化层由热熔性材料形 成。
2、根据权利要求 1所述的阵列基板的制作方法，其中所述热熔性材料为 亚克力材料。
3、根据权利要求 1或 2所述的阵列基板的制作方法，其中所述在阵列基 板上形成垫高层， 所述垫高层位于阵列基板的平坦化层下方， 且对应于所述 平坦化层的过孔的位置的步骤包括：
提供一村底基板， 在所述村底基板上形成 TFT;
在所述村底基板上方形成垫高层； 及
在所述垫高层上方形成平坦化层， 并在所述平坦化层中形成过孔， 其中 所述垫高层对应所述平坦化层的过孔的位置。
4、 根据权利要求 3所述的阵列基板的制作方法， 其中
所述在村底基板上形成 TFT的步骤具体为：在所述村底基板上形成栅极 层、 栅绝缘层、 有源层和源漏电极层；
所述在村底基板上方形成垫高层的步骤具体为： 在所述村底基板上或者 在所述栅极层、 栅绝缘层、 有源层和源漏电极层中任意一层上形成垫高层。
5、 根据权利要求 3或 4所述的阵列基板的制作方法， 还包括： 在所述平坦化层上方形成像素电极层， 所述像素电极通过所述平坦化层 的过孔与所述 TFT的漏电极连接。
6、 根据权利要求 4所述的阵列基板的制作方法， 其中，
所述在村底基板上形成栅极层、栅绝缘层、有源层、 源漏电极层的步骤， 还包括： 形成与所述栅极同层的栅线， 并且形成与所述源漏电极同层的数据 线， 所述栅线和所述数据线分别通过平坦化层上的过孔与阵列基板周边区域 的驱动电路连接。
7、根据权利要求 3至 6中任一项所述的阵列基板的制作方法，其中在形 成有垫高层的所述村底基板上形成平坦化层的步骤包括：
在形成有垫高层的所述村底基板上涂覆亚克力材料层；
对所述亚克力材料层进行低压干燥和烘烤；
对低压干燥和烘烤后的所述亚克力材料层进行曝光； 及
对曝光后的所述亚克力材料层进行显影和烘烤。
8、 一种阵列基板， 包括提供有过孔的平坦化层， 还包括垫高层， 所述垫 高层位于平坦化层下方， 且对应于平坦化层的过孔处， 其中， 所述平坦化层 由热熔性材料形成。
9、根据权利要求 8所述的阵列基板,其中所述热熔性材料为亚克力材料。
10、 根据权利要求 8或 9所述的阵列基板， 其中所述阵列基板具体为： 村底基板以及形成于所述村底基板上的 TFT;
形成在所述村底基板上方的垫高层；
形成在所述垫高层上方的平坦化层， 所述平坦化层提供有过孔， 所述垫 高层对应所述平坦化层的过孔的位置。
11、 根据权利要求 10所述的阵列基板， 其中所述 TFT包括栅极、 栅绝 缘层、有源层和源漏电极，所述垫高层位于所述村底基板上或者位于栅极层、 栅绝缘层、 有源层和源漏电极层中的任意一层上。
12、 根据权利要求 10或 11所述的阵列基板， 还包括： 像素电极层， 所 述像素电极层位于平坦化层上方， 所述像素电极通过所述平坦化层的过孔与 TFT漏电极连接。
13、根据权利要求 12所述的阵列基板，还包括钝化层， 所述钝化层位于 孔，所述像素电极与 TFT漏电极通过所述平坦化层的过孔和钝化层的过孔连 接。
14、根据权利要求 11所述的阵列基板,还包括与源漏电极同层的数据线， 以及与栅极同层的栅线， 所述数据线与所述栅线分别通过所述平坦化层的过 孔与阵列基板周边区域的驱动电路连接。
15、 一种显示装置， 包括如权利要求 8-14任一项所述的阵列基板。
PCT/CN2013/073143 2013-02-19 2013-03-25 阵列基板的制作方法、阵列基板和显示装置 WO2014127552A1 (zh)

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