WO2014048988A1 - Verfahren zur herstellung eines optoelektronischen bauelements - Google Patents
Verfahren zur herstellung eines optoelektronischen bauelements Download PDFInfo
- Publication number
- WO2014048988A1 WO2014048988A1 PCT/EP2013/069966 EP2013069966W WO2014048988A1 WO 2014048988 A1 WO2014048988 A1 WO 2014048988A1 EP 2013069966 W EP2013069966 W EP 2013069966W WO 2014048988 A1 WO2014048988 A1 WO 2014048988A1
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- WIPO (PCT)
- Prior art keywords
- layer
- carrier
- contact
- recess
- semiconductor layer
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- the invention relates to a method according to claim 1 and a component according to another independent
- an optically active layer is grown on a growth substrate. Subsequently, the optically active layer is patterned from the free side, wherein electrical contacts are introduced. The electrical contacts are provided with a positively doped layer and with a negatively doped layer in
- the object of the invention is to provide an improved method for the production of the component and a simply constructed component.
- the object of the invention is achieved by the method according to claim 1 and by the device according to a
- the carrier is integrated into the device. Thus omitted the
- optoelectronic component both the structure of the carrier and the size of the carrier are optimally adapted to the device.
- the connecting layer is an electrically insulating material, in particular a
- Adhesive material used used.
- the use of the electrically insulating material as a connecting layer offers the advantage that it is also possible to use electrically conductive materials or semiconducting materials as the carrier.
- the use of an adhesive material offers the possibility of enabling a secure and firm connection between the layer structure and the carrier with a small layer thickness.
- Adhesive material can be achieved a saving of cost.
- a carrier is used
- electrically semiconductive or electrically conductive material in particular used in the form of a film.
- conductive material as a carrier in particular in the form of a film has the advantage that the processing is easily possible.
- thin carriers can be formed which represent sufficient stability for the optoelectronic component.
- the introduction of the recess in the carrier for forming the contacts is carried out quickly. Thus process time and thus costs are saved.
- the contacts are formed in each case or together in a common method step.
- the contacts in each case completely fill a recess, wherein the recess extends through the carrier and in particular additionally through a semiconductor layer extends through.
- a contact for the electrical contacting of a semiconductor layer may be formed continuously, for instance between the carrier and including the semiconductor layer to be contacted. This means that the contact is seamless and no connecting layers, such as a solder layer or a
- the contact has only an electrically conductive material, which may be, for example, a metal or a metal alloy.
- the contact is in one piece in one
- the electrical contacts are provided with a mirror layer to improve the reflective properties.
- a bonding material is used which is substantially transparent to the light emitted by the device.
- a carrier is used, whose side of the
- the first contact is formed in such a way that the first contact on a side facing the negatively doped semiconductor layer
- a filling material with inhomogeneities is used, wherein the filling material
- the filler material for introducing a contact for example, with a DRIE process can be quickly and easily removed.
- Bonding layer are generated by laser ablation, wherein an opening of the carrier can act as a shutter. This also makes fast and easy processing possible.
- FIGS. 1 to 3 a first method section
- FIG. 4 a second method section
- FIGS. 5 and 6 a third method section
- FIGS. 7 and 8 a fourth method section
- FIGS. 9 and 10 a fifth method section
- FIG. 11 a sixth method section
- FIG. 12 shows a view with regard to the carrier of a first embodiment according to FIG. 11,
- FIG. 13 shows a view with regard to the carrier of a second embodiment according to the sixth method section
- FIG. 14 shows a view of a carrier according to a third embodiment
- FIGS. 15 to 17 a fourth process section
- FIG. 18 shows a thinned wafer
- Figure 19 is a schematic representation of an optical element
- FIG. 20 shows components with converter and lens
- FIG. 21 shows a component with a carrier structure.
- FIG. 1 shows a first method step, in which a negatively doped semiconductor layer 2 is grown on a growth substrate 1. On the negatively doped semiconductor layer 2 is a positively doped semiconductor layer 3rd
- the negatively doped semiconductor layer 2 will be referred to as the first
- the first semiconductor layer 2 can also be p-doped and the second semiconductor layer can be n-doped.
- the first and second semiconductor layers 2, 3 form e.g. a thin-film diode.
- Semiconductor layer 2,3 form a layer structure.
- the growth substrate 1 may be formed, for example, in the form of sapphire or crystalline silicon.
- the growth substrate 1 may be constructed of silicon carbide or gallium nitride.
- the first and second semiconductor layers 2, 3 are epitaxially grown on the growth substrate 1. Depending on the chosen embodiment, a
- Intermediate layer can be applied to the growth substrate 1, which has substantially the same lattice structure as the layer structure to be grown. In this way, growth of the first semiconductor layer 2 can be improved be so less or no errors in the
- Grid structure of the first semiconductor layer can be generated during growth. Subsequently, as shown in Figure 2, a
- the mirror layer 4 may be a metal
- the opening 5 can simultaneously with the application of the mirror layer 4th
- an electrically conductive layer is applied to the mirror layer 4.
- the conductive layer 6 like the mirror layer 4, has the opening 5. This can be generated separately or together with the opening in the mirror layer 4. Thereby, the opening 5 in the two layers 4 and 6, the same or different
- the first and second semiconductor layers 2, 3 can be used as
- Layer structures fall in particular those in which the epitaxially produced layer structure usually a layer sequence of different individual layers
- the layer structures, the at least one active For example, layer or active region based on InGaAlN may preferably have electromagnetic radiation in an ultraviolet to green
- the semiconductor layers 2, 3 or the semiconductor chip may also be based on InGaAlP
- Layer structure having at least one active layer or an active region based on InGaAlP can be
- the semiconductor layers 2, 3 may also comprise other III-V compound semiconductor material systems, for example an AlGaAs-based material, or II-VI compound semiconductor material systems.
- an active layer comprising an AlGaAs-based material may be capable of emitting electromagnetic radiation having one or more spectral components in a red to infrared wavelength range.
- An II-VI compound semiconductor material system may include at least one second main group element such as Be, Mg, Ca, Sr, and a sixth main group element such as O, S, Se.
- an II-VI compound semiconductor material system comprises a binary, ternary or quaternary compound containing at least one
- Element from the sixth main group includes.
- Such a binary, ternary or quaternary compound can also be used.
- the growth substrate 1 can be a semiconductor material, for example an abovementioned one
- the growth substrate 1 may include or be made of sapphire, GaAs, GaP, GaN, InP, SiC, Si, and / or Ge.
- the semiconductor layers 2, 3 may have, for example, a conventional pn junction, an active region
- Double heterostructure a single quantum well structure (SQW structure) or a multiple quantum well structure (MQW structure) have.
- the term quantum well structure includes in the context of the application in particular any
- quantum well structure does not include information about the dimensionality of the quantization. It thus includes quantum wells, quantum wires and quantum dots and any combination of these structures.
- the semiconductor layers 2, 3 may contain, in addition to the active region, further functional layers and
- Charge carrier transport layers ie electron or
- Barrier layers planarization layers, buffer layers, protective layers, contact layers and / or electrodes and combinations thereof.
- a trench 7 is introduced into the first and second semiconductor layer 2, 3, which forms part of Layer structure consisting of the first and the second semiconductor layer 2, 3 of the remaining part of the
- the trench 7 is formed circumferentially around a part of the layer structure 2, 3 and up to the
- Process step according to Figure 4 are areas of
- Figure 5 shows the arrangement of Figure 4, wherein the arrangement is reversed.
- the arrangement according to FIG. 5 is fastened via a connecting layer 8 to an upper side 9 of a carrier 10.
- the material of the bonding layer is also filled in the area of the opening 5.
- the opening 5 can be filled with a further filling material 11.
- the filling material 11 completely fills the opening 5.
- the filling material is adjacent to the second
- the filling material 11 and the second semiconductor layer 3 are removed in regions, so that the first semiconductor layer 2 is partially exposed in the first recess 14.
- the remaining filling material 11 surrounds the first recess 14 in the lateral direction.
- the remaining filling material 14 is arranged in the lateral direction between the first recess 14 and the mirror layer 4.
- the filling material 11 may be reflective.
- the filler contains particles to increase the Reflectivity, such as titanium oxide particles.
- Connecting layer 8 become the first and the second
- Semiconductor layer 2,3 is attached to the mirror layer 5 and the conductive layer 4 at the top 9 of the carrier 10.
- a filling material 11 with inhomogeneities for example cavities and / or
- the filling material 11 may be formed, for example, as a photosensitive material. This way can be a simple
- the bonding layer 8 may be made of an adhesive material
- the connecting layer 8 may also be in the form of an electrically conductive material, for example made of metal, which fixes the semiconductor layers 2, 3 to the upper side 9 of the carrier 10 via a solder connection.
- Adhesives are the following materials: thermoplastics (e.g., Brewer Science Waferbond), bicomponent
- Polyurethanes (DELO-PUR 9604), two-component epoxy resins (di- or polyepoxides based on bisphenol A,
- Novolaks etc. hardeners polyamines, mercaptans), polyimides (Adhesives HD 3007 / HD 7010 Dupont / HD Microsystems)
- the bonding process according to FIG. 6 is carried out, for example, in a membrane bonder. Depending on the selected
- Connecting layer 8 in the range less than 10 ym between the top of the carrier 10 and the free top of the free mirror layer or the free upper surface of the conductive layer 6 can be achieved.
- Bond layer 8 may also be less than 1 ym, for example.
- Connecting layer 8 can also be electrically conductive
- Example Si, Ge, GaAs can be used as the carrier 10.
- the carrier 10 can also be in the form of a film, wherein the layer thicknesses can be, for example, in the range of 100 ⁇ m, but also smaller up to the range of 10 ⁇ m.
- the carrier may be provided with an electrical insulation layer, for example, with an ALD, CVD or PVD process.
- the carrier 10 may also be in the form of an electrically insulating layer, in particular in the form of a film, for example in the form of a plastic film.
- Suitable filler material 11 is, for example, a photosensitive material (ProTEK) or a coating, which can be removed again with a DRIE process.
- connection carrier 10 in the form of films, in particular in the form of metal foils
- connection carrier 10 to the semiconductor layers 2, 3 due to the process sequence planar, very thin and homogeneous configured.
- an ESD diode can be integrated directly into the system, for example between the contact pads on a bottom side of the carrier.
- the ESD diode can also be integrated directly into the silicon. This can be done by a local implantation, wherein the connection via a Bondpadmetallmaschine or the associated Umverdrahtungsebenen done.
- Passivation takes place, for example, with an ALD method after etching back the mirror layer 4.
- a first recess 14 in the region of the opening 5 of the mirror layer 4 is introduced from an underside 13 of the carrier 10 ago.
- a second recess 14 in the region of the opening 5 of the mirror layer 4 is introduced from an underside 13 of the carrier 10 ago.
- the first and the second recess 14, 15 are introduced depending on the material of the carrier 10 with appropriate methods.
- etching methods can be used.
- metal-removing methods such as e.g.
- Connecting layer 8 is removed, so that the second recess 15 to the conductive layer 6 or missing
- Bonding layer 8 for example, a DRIE process for removing the bonding layer 8 and the filling material 11 may be used.
- the filling material 11 and the bonding layer 8 may be provided, for example, with a
- Side wall of the recess 14 may be formed in the form of a mirror layer. After the application of the insulating layer 17 and structuring thereof, the first recess 14 still directly adjoins the first semiconductor layer 2. In addition, the second recess 15 adjoins the conductive layer 6
- the insulating layer 17 can
- a TEOS-based CVD process For example, be deposited using an ALD or a TEOS-based CVD process.
- Embodiment is applied before the introduction of the electrically conductive material for producing the first contact, an electrically conductive and reflective metal layer on the free surface of the negatively doped semiconductor layer 2 and the free surface of the insulating layer 17 in the region of the first recess 14.
- Material for example, filled with a metal using a galvanic process and then a first or a second contact pad 18, 19 applied to a bottom of the insulating layer 17.
- a planarization step may take place before or after the application of the contact pads 18, 19, for example by means of CMP. This process status is shown in FIG.
- a first contact 32 is formed in the first recess 14.
- a second contact 33 may be in the second
- Recess 15 are formed.
- the introduction of the first contact 32 or the second contact 33 can in a
- Process step are performed, such as by filling the recess 14 or 15 with an electrically conductive Material in particular using a galvanic process.
- the first contact 32 extends through the carrier 10, the connection layer 8, the mirror layer 4 and the second semiconductor layer 3 into the first semiconductor layer 2.
- the formation of the first contact 32 for electrical contacting of the first semiconductor layer 2 is thus simultaneously in the carrier 10 and in the second
- the first contact 32 between the first semiconductor layer 2 and the first contact pad 18 is formed in particular continuously. That means the first one
- Contact 32 is approximately integrally formed within the first recess between the first semiconductor layer 2 and the first contact pad 18.
- the first contact 32 has only one electrically conductive material that is used in a method step for filling the first recess 14 between the first semiconductor layer 2 and the first contact pad 18.
- the first contact 32 has only one electrically conductive material that is used in a method step for filling the first recess 14 between the first semiconductor layer 2 and the first contact pad 18.
- connection layer is a different material from the first part or from the further part of the contact 32
- the second contact 32 extends through the carrier 10 and the connection layer 8. Within the second recess 15, the second contact 33 is in particular
- Silicon dioxide layer are formed.
- the growth substrate 1 is removed.
- the growth substrate 1 for example, with a
- Laser Abhebvon be lifted or removed with a CMP process. Subsequently, an upper side surface 20 of the first semiconductor layer 2 is roughened. This process state is shown in FIG. 11, wherein the thickness of the first semiconductor layer 2 is shown enlarged. In addition, the individual components are isolated.
- FIG. 12 shows a first component 21 with a top view of the first and the second contact pads 18, 19.
- the first and the second contact pads 18, 19 are electrically separated by a second trench 22.
- Embodiment a plurality of first and second recesses 14, 15 are provided, which are filled with electrically conductive material and the first and second electrical
- the first electrical contacts for the negatively doped semiconductor layer 2 are arranged in a 4 ⁇ 4 arrangement.
- the second electrical contacts for the positively doped semiconductor layer 3 are arranged in the form of four second electrical contacts arranged in series.
- FIG. 13 shows an embodiment of a second one
- Component 34 wherein arranged in four corner regions second contact pads 19 are provided.
- Contact pads 19 are separated from the first contact pad 18 via a respective second trench 22. Analogous to the arrangement of the second contact pads 19 and the second electrical contacts 33 are arranged in the corner regions of the square. Analogous to the formation of the shape of the first contact pad 18, the first electrical contacts 32 are distributed uniformly over the surface of the first contact pad 18.
- Figure 14 shows an embodiment of a third
- Component 35 wherein only a second contact pad 19 is disposed in a corner region, which is electrically insulated via a second trench 22 from the first contact pad 18, which is formed substantially square. In an analogous manner, only a second electrical contact 33 to
- FIGS. 12 to 14 are only examples of possible division of the first and second contact pads 18, 19 and the corresponding first and second electrical contacts 32, 33.
- FIG. 15 shows a further embodiment which is shown in FIG.
- Insulation layer 23 is formed.
- the first is a first
- Contact pad 18 formed in two layers, wherein the first layer rests on the insulating layer 17 and the second layer on the first layer and on the further insulating layer 23.
- the additional insulation layer 23 has in the region of the first recess 14 a recess which is formed by a missing planarization process.
- the first contact pad 18 has an indentation 24 in the region of the second layer.
- Figure 17 shows a view of the first and the second contact pad 18, 19.
- Insulation layer 23 it is possible to make the geometry of the first and second contact pads 18, 19 more flexible and decouple from the actual arrangement of the first and second contacts.
- Figure 18 shows a carrier 10 in the form of a
- Semiconductor wafer having an annular peripheral edge 24 having a relation to a central region 36 increased thickness is designed as a silicon wafer.
- This shape of the carrier is achieved by thinning an inner region of the wafer, wherein a circumferential edge region remains in a greater thickness.
- the carrier according to Figure 18 is e.g. produced with a Taiko process of the company Disco. The thickness of the
- Silicon wafer has in the middle region 36, for example, 10 ym.
- the carrier shown in FIG. 18 is used as carrier 10 according to FIG. Subsequently, appropriate
- Figure 19 illustrates the process status of Figure 8. Analogous to the arrangement shown in FIG. 19, a multiplicity of components can be processed onto the carrier according to FIG. 19.
- FIG. 20 shows a process state in which two
- Components are arranged according to Figure 16 on a support 10, wherein between the components 21 is a circumferential
- Separating structure 25 has been applied in the form of a frame, for example by means of a photoresist.
- a converter layer 26 and a lens 27 applied in the Frame on the negatively doped semiconductor layer 2, a converter layer 26 and a lens 27 applied.
- the frame-shaped separation structure 25 is produced, for example, by means of a photoresist process.
- Frame structure may be made of, for example, a plastic, for example benzocyclobutenes.
- Converter layer 26 comprises, for example, silicone, in which a luminescent conversion substance, for example YAG: Ce or other substances, is embedded.
- an ESD diode 28 is schematically introduced into the carrier 10 by a corresponding doping.
- the ESD diode 28 may also be formed on an underside of the carrier 10, for example between the contact pads 18, 19.
- the component shown in FIG. 20 can then be applied to a further carrier structure 29 with vias 30 and further
- Component 21 is arranged on the upper side of the support structure 29.
- the other contacts are on the bottom of the
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020157010780A KR20150058504A (ko) | 2012-09-27 | 2013-09-25 | 광전자 소자를 제조하기 위한 방법 |
CN201380050764.5A CN104704642B (zh) | 2012-09-27 | 2013-09-25 | 用于制造光电子器件的方法 |
JP2015533571A JP6099752B2 (ja) | 2012-09-27 | 2013-09-25 | オプトエレクトロニクスコンポーネントの製造方法、およびオプトエレクトロニクスコンポーネント |
US14/430,893 US20150255685A1 (en) | 2012-09-27 | 2013-09-25 | Method for producing an optoelectronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012217533.4 | 2012-09-27 | ||
DE102012217533.4A DE102012217533A1 (de) | 2012-09-27 | 2012-09-27 | Verfahren zur Herstellung eines optoelektronischen Bauelements |
Publications (1)
Publication Number | Publication Date |
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WO2014048988A1 true WO2014048988A1 (de) | 2014-04-03 |
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PCT/EP2013/069966 WO2014048988A1 (de) | 2012-09-27 | 2013-09-25 | Verfahren zur herstellung eines optoelektronischen bauelements |
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Country | Link |
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US (1) | US20150255685A1 (de) |
JP (1) | JP6099752B2 (de) |
KR (1) | KR20150058504A (de) |
DE (1) | DE102012217533A1 (de) |
WO (1) | WO2014048988A1 (de) |
Cited By (4)
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KR20150142327A (ko) * | 2014-06-11 | 2015-12-22 | 엘지이노텍 주식회사 | 발광 소자 및 발광 소자 패키지 |
KR20160003739A (ko) * | 2013-04-23 | 2016-01-11 | 코닌클리케 필립스 엔.브이. | 발광 장치를 위한 측면 상호접속부 |
US10388824B2 (en) | 2017-08-31 | 2019-08-20 | Toyoda Gosei Co., Ltd. | Method for producing light-emitting device |
KR20190104968A (ko) * | 2019-09-03 | 2019-09-11 | 엘지이노텍 주식회사 | 발광 소자 및 발광 소자 패키지 |
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DE102014103828A1 (de) | 2014-03-20 | 2015-09-24 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zur Herstellung von optoelektronischen Halbleiterbauelementen |
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DE102014116935A1 (de) | 2014-11-19 | 2016-05-19 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
DE102015100578A1 (de) * | 2015-01-15 | 2016-07-21 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
DE102015105509A1 (de) | 2015-04-10 | 2016-10-13 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
DE102015108056A1 (de) | 2015-05-21 | 2016-11-24 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil, optoelektronische Anordnung und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils |
DE102015211185A1 (de) * | 2015-06-18 | 2016-12-22 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips |
DE102015113310B4 (de) * | 2015-08-12 | 2022-08-04 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Halbleiterchip |
DE102015114587A1 (de) * | 2015-09-01 | 2017-03-02 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung |
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DE102018122568A1 (de) * | 2018-09-14 | 2020-03-19 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauelement mit erstem und zweitem kontaktelement und verfahren zur herstellung des optoelektronischen halbleiterbauelements |
DE102018123930A1 (de) * | 2018-09-27 | 2020-04-02 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip mit erstem und zweitem Kontaktelement und Verfahren zur Herstellung des optoelektronischen Halbleiterchips |
DE102018125281A1 (de) * | 2018-10-12 | 2020-04-16 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil |
DE102018128692A1 (de) * | 2018-11-15 | 2020-05-20 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement mit ersten Verbindungsbereichen und optoelektronische Vorrichtung |
DE102019106938A1 (de) * | 2019-03-19 | 2020-09-24 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches Halbleiterbauelement mit isolierender Schicht und Verfahren zur Herstellung des optoelektronischen Halbleiterbauelements |
DE102019108216A1 (de) * | 2019-03-29 | 2020-10-01 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches Halbleiterbauelement mit dielektrischer Schicht und transparenter leitfähiger Schicht und Verfahren zur Herstellung des optoelektronischen Halbleiterbauelements |
DE102021202026A1 (de) | 2021-03-03 | 2022-09-08 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches halbleiterbauelement und verfahren zur herstellung zumindest eines optoelektronischen halbleiterbauelements |
DE102021123996A1 (de) | 2021-09-16 | 2023-03-16 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektornisches halbleiterbauelement und verfahren zur herstellung eines optoelektronischen halbleiterbauelements |
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KR20160003739A (ko) * | 2013-04-23 | 2016-01-11 | 코닌클리케 필립스 엔.브이. | 발광 장치를 위한 측면 상호접속부 |
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KR102019914B1 (ko) | 2014-06-11 | 2019-11-04 | 엘지이노텍 주식회사 | 발광 소자 |
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Also Published As
Publication number | Publication date |
---|---|
US20150255685A1 (en) | 2015-09-10 |
CN104704642A (zh) | 2015-06-10 |
KR20150058504A (ko) | 2015-05-28 |
JP6099752B2 (ja) | 2017-03-22 |
JP2015530755A (ja) | 2015-10-15 |
DE102012217533A1 (de) | 2014-03-27 |
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