WO2014040356A1 - 用于替代dram及flash的相变存储单元及其制作方法 - Google Patents

用于替代dram及flash的相变存储单元及其制作方法 Download PDF

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WO2014040356A1
WO2014040356A1 PCT/CN2012/087578 CN2012087578W WO2014040356A1 WO 2014040356 A1 WO2014040356 A1 WO 2014040356A1 CN 2012087578 W CN2012087578 W CN 2012087578W WO 2014040356 A1 WO2014040356 A1 WO 2014040356A1
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Prior art keywords
phase change
layer
lower electrode
change material
change memory
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PCT/CN2012/087578
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English (en)
French (fr)
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饶峰
任堃
宋志棠
龚岳峰
任万春
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中国科学院上海微系统与信息技术研究所
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Priority to US14/129,955 priority Critical patent/US9362493B2/en
Publication of WO2014040356A1 publication Critical patent/WO2014040356A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa or cup type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of the switching material, e.g. post-treatment, doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes

Definitions

  • Phase change memory unit for replacing DRAM and FLASH and manufacturing method thereof
  • the invention belongs to the field of microelectronics, and particularly relates to a phase change memory unit for replacing DRAM and FLASH and a manufacturing method thereof. Background technique
  • phase change memory uses the operating signal to generate Joule heat to operate the phase change material to change between different phases, thereby reflecting the difference between high and low resistance values and completing the storage of information.
  • Phase change memory is considered to be the most promising next generation non-volatile due to its fast operation speed, good data retention, strong cycle operation capability, compatibility with traditional CMOS processes, and its ability to maintain its operation at small sizes.
  • One of the memories As device size shrinks, the effect of size effects on phase change materials remains a hot topic in phase change memory research.
  • phase change material film thickness is above 10 nm, the crystallization temperature of the phase change material changes very little with thickness.
  • the thickness of the phase change material film is less than 10 nm, the crystallization temperature of the phase change material increases with the decrease of the film thickness. For example, as the film is reduced from 10 nanometers to 2 nanometers, the crystallization temperatures of Sb2Te, GeSb, GST, and AIST materials are increased by nearly 150, 50, 200, and 100 degrees Celsius, respectively.
  • the literature reports that the size effect also affects the crystallization rate of the phase change material film.
  • the thickness of the phase change material is reduced, the specific surface area of the material increases, and the interface is liable to form crystal nuclei due to defects.
  • the presence of the nucleus is a crystallization process of the phase change material, which shortens the nucleation time, reduces the time required for the crystallization process, and further improves the operation speed of the phase change memory.
  • the nucleation time is shortened, grain growth becomes a major factor affecting the crystallization time. The grain growth time becomes shorter as the size shrinks, which ensures a faster phase transition speed for small-sized devices.
  • the phase change memory uses the operating signal to generate Joule heat to operate the phase change material to change between different phases, thereby reflecting the difference between high and low resistance values and completing the storage of information.
  • the effective part of the operating power dissipation is the energy that is used to achieve the phase transition of the phase change material.
  • the limited structure phase change memory reduces the operating power consumption of the device by reducing the phase change region.
  • the fabrication of small-sized electrodes such as blade structures and ring structures is also aimed at reducing the phase change region and thereby reducing power consumption.
  • the main cause of failure of the phase change memory is the decrease in material uniformity due to elemental segregation of the phase change material.
  • the elemental diffusion mainly occurs under the high temperature conditions generated by the current during operation, and the longer the high temperature duration, the more severe the element segregation. So right Long-term high-power operation of phase-change materials promotes element segregation, accelerates device failure, and reduces the number of cycles that the device can cycle.
  • the low-power fast operation specific phase change memory has a short operation time during operation, and the element segregation effect on the material is reduced in each operation, which is advantageous for improving the number of times of device cycle operation. Summary of the invention
  • an object of the present invention is to provide a phase change memory cell for replacing DRAM and FLASH and a manufacturing method thereof for solving the phase change material size of a phase change memory cell in the prior art. Large problems that result in slow device operation, high power consumption, and low cycle operation.
  • the present invention provides a phase change memory cell for replacing DRAM and FLASH and a method of fabricating the same.
  • the phase change memory cell of the present invention has the characteristics of high data retention, high speed and low power consumption.
  • phase change memory unit comprising a phase change material layer and a cylindrical lower electrode contacting the same and below the bottom layer, wherein the phase change material layer is formed by connecting a sidewall layer and a circular bottom layer. And forming a hollow cylinder or a hollow round table with an upper opening, the hollow cylinder or the hollow round table is filled with a dielectric layer.
  • the diameter of the circular bottom layer is equal to or larger than the diameter of the lower electrode of the cylinder.
  • the circular bottom layer has a diameter ranging from 5 to 30 nm.
  • the diameter of the lower electrode of the cylinder ranges from 2 to 30 nm.
  • the circular bottom layer has a thickness ranging from 1 to 10 nm
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the depth of the cylindrical hole is equal to the thickness of the first dielectric layer;
  • step 2) depositing a lower electrode metal material on the first dielectric layer with a cylindrical hole, and performing polishing to remove the lower electrode metal material outside the cylindrical hole, leaving the lower electrode metal material and the first The dielectric layer is flush; c) in the step 2), the polished structure is etched back to form a hole of a cylindrical structure or a round table structure; the remaining lower electrode metal material forms a cylindrical lower electrode;
  • phase change material layer depositing a phase change material layer to form a hollow cylinder or a hollow round table which is connected by a side wall layer and a circular bottom layer and is open at the upper portion; and then depositing a portion for filling the inside of the hollow cylinder or the hollow round table Two dielectric layers; then removing the excess second medium and phase change material outside the holes of the cylindrical structure or the round table structure until being flush with the first dielectric layer, and then preparing the upper electrode.
  • in-situ heating is performed when depositing the phase change material layer in the step 4); the temperature range of the in-situ heating It is 200 ⁇ 400 °C.
  • heating is performed when the second dielectric layer is deposited in the step 4), and the heating temperature ranges from 200 to 400 V.
  • the diameter of the circular bottom layer is equal to or larger than the diameter of the lower electrode of the cylinder.
  • the thickness of the circular bottom layer ranges from 1 to 10 nm
  • the thickness of the sidewall layer ranges from 2 to 15 nm.
  • FIG. 1 is a schematic view showing a phase change memory cell of a sidewall vertical structure of the present invention.
  • FIGS 2 to 3 are views showing the structure of the phase change memory cell of the present invention in the first embodiment of the first embodiment.
  • 4 to 5 are views showing the structure of the phase change memory cell of the present invention, which is presented in the second step of the first embodiment.
  • Fig. 6 is a view showing the structure of the phase change memory cell of the present invention in the first step of the first embodiment.
  • FIG 7 to 9 are views showing the structure of the phase change memory cell of the present invention, which is presented in the first step of the first embodiment.
  • Figure 10 is a schematic view showing a phase change memory cell of a vertical structure of a small electrode sidewall of the present invention.
  • FIG 11 to 12 are views showing the configuration of the phase change memory cell of the present invention in the first embodiment of the second embodiment.
  • FIG. 13 to 14 are views showing the structure of the phase change memory cell of the present invention in the second embodiment of the second embodiment.
  • FIG. 15 is a schematic view showing the structure of the phase change memory cell of the present invention in step 3 of Embodiment 2.
  • 16 to FIG. 18 are schematic diagrams showing the structure of the phase change memory cell of the present invention in step 4 of Embodiment 2.
  • Figure 19 is a schematic view showing a phase change memory cell of the sidewall inclined structure of the present invention.
  • 20 to 21 are views showing the structure of the phase change memory cell of the present invention in the first embodiment of the third embodiment.
  • 22 to 23 are views showing the structure of the phase change memory cell of the present invention which is presented in the second step of the embodiment 3.
  • Fig. 24 is a view showing the construction of the phase change memory cell of the present invention in the third embodiment of the third embodiment.
  • 25 to 27 are views showing the structure of the phase change memory cell of the present invention in the step 4 of the third embodiment.
  • Figure 28 is a schematic view showing a phase change memory cell of the small electrode sidewall inclined structure of the present invention.
  • 29 to 30 are views showing the structure of the phase change memory cell of the present invention, which is presented in the first step of the embodiment 4.
  • 31 to 32 are views showing the configuration of the phase change memory cell of the present invention in the second step of the embodiment 4.
  • Fig. 33 is a view showing the structure of the phase change memory cell of the present invention which is presented in the third step of the fourth embodiment.
  • 34 to 36 are views showing the structure of the phase change memory cell of the present invention which is presented in the fourth step of the fourth embodiment.
  • Component label description
  • FIG. 1 a schematic diagram of a phase change memory cell of a sidewall vertical structure of the present invention is shown.
  • the present invention provides a phase change memory cell including a metal electrode layer 1 located at the metal electrode layer. a cylindrical lower electrode 2 on the first lower electrode 2, a phase change material layer 3 connected by a circular bottom layer 31 and a sidewall layer 32, enclosing the phase change material layer 3 and the lower electrode a first dielectric layer 4 of 2, a second dielectric layer 5 filled in the phase change material layer 3, and upper electrodes on the first dielectric layer 4, the second dielectric layer 5, and the phase change material layer 3. 6.
  • the sidewall layer 32 of the phase change material layer 3 is perpendicular to the circular bottom layer 31 to form a hollow cylinder with an upper opening.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the diameter of the cylindrical lower electrode 2 is equal to the diameter of the circular bottom layer 31.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the invention also provides a method for fabricating a phase change memory unit, the method comprising the following steps:
  • Step 1 please refer to FIG. 2 to FIG. 3, as shown in FIG. 2, a metal electrode layer 1 is provided, and a first dielectric layer 4 is grown on the metal electrode layer; as shown in FIG. Engraving, developing, etching, and stripping operations, in the A cylindrical hole 7 is formed in the first dielectric layer 4 to form a first dielectric layer with a cylindrical hole, the cylindrical hole 7 having a depth equal to the thickness of the first dielectric layer 4, exposing the metal electrode layer 1.
  • the diameter of the cylindrical bore is in the range of 5 to 30 nm.
  • Step 2 referring to FIG. 4 to FIG. 5, as shown in FIG. 4, depositing a lower electrode metal material 21 on the first dielectric layer with a cylindrical hole by PVD, ALD or CVD to make the lower electrode a metal material 21 fills the cylindrical hole 7 and covers the upper surface of the first dielectric layer 4; as shown in FIG. 5, polishing is performed to remove the outside of the cylindrical hole 7 and the first dielectric layer Lower electrode metal material.
  • Step 3 refer to FIG. 6, as shown in the figure, using the glue coating, photolithography, development, etching, and de-glue operations to etch back, forming a hole 8 of a cylindrical structure on the structure shown in FIG.
  • the height of the electrode metal material 21 is smaller than the depth of the cylindrical hole 7.
  • the lower electrode metal material 21 remaining between the bottom of the hole 8 of the cylindrical structure and the metal electrode layer forms a cylindrical lower electrode 2.
  • the diameter of the hole 8 of the cylindrical structure is equal to the diameter of the cylindrical hole 7, that is, only the upper portion of the upper electrode of the cylindrical hole in the cylindrical hole 7 is etched without etching the periphery thereof. medium.
  • Step 4 referring to FIG. 7 to FIG. 9, as shown in FIG. 7, the phase change material layer 3 is deposited by PVD, ALD or CVD to form a hollow which is connected by the sidewall layer 32 and the circular bottom layer 31 and is open at the upper portion.
  • a second dielectric layer 5 for filling the inside of the hollow cylinder is deposited by low temperature ALD or low temperature CVD; as shown in FIG. 8, polishing is performed to remove the hole 8 of the cylindrical structure and The excess second medium and phase change material on the first dielectric layer 4 are until flush with the first dielectric layer; as shown in FIG. 9, the upper electrode 6 is then prepared by PVD, ALD or CVD.
  • the phase change region 10 of the phase change memory cell of this embodiment is illustrated in FIG.
  • the in-situ heating is performed when depositing the phase change material layer, so that the phase change material layer is crystallized at the time of preparation, and the volume shrinkage during the amorphous to crystalline transition is prevented from remaining to the device; the in-situ heating temperature
  • the range is 200 ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the phase change material layer may also be heated without being heated, and the phase change material layer may be heated while the second dielectric layer is deposited to crystallize the phase change material layer, and the heating temperature range is 200. ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the diameter of the lower electrode of the cylinder ranges from 5 to 30 nm, and the diameter of the circular bottom layer of the phase change material layer is equal to the diameter of the lower electrode of the cylinder.
  • the side wall layer and the circle of the phase change material layer The bottom layer is vertical, forming a phase change memory cell with a sidewall vertical structure.
  • Embodiment 2 and Embodiment 1 adopt substantially the same technical scheme, except that the cylindrical lower electrodes of the two are different.
  • the diameter of the lower electrode of the cylinder ranges from 5 to 30 nm
  • the circular bottom layer of the phase change material layer is the same as the diameter of the lower electrode of the cylinder, but in the embodiment, under the cylinder
  • the diameter of the electrode ranges from 2 to 5 nm
  • the diameter of the circular bottom layer of the phase change material layer is larger than the diameter of the lower electrode of the cylinder.
  • FIG. 10 there is shown a schematic diagram of a phase change memory cell of a vertical structure of a small electrode sidewall of the present invention.
  • the present invention provides a phase change memory cell including a metal electrode layer 1 located at the metal. a cylindrical lower electrode 2 on the electrode layer 1, a phase change material layer 3 on the cylindrical lower electrode 2 connected by a circular bottom layer 31 and a sidewall layer 32, wrapping the phase change material layer 3 and a first dielectric layer 4 of the lower electrode 2, a second dielectric layer 5 filled in the phase change material layer 3, and the first dielectric layer 4, the second dielectric layer 5, and the phase change material layer 3 Upper electrode 6.
  • the sidewall layer 32 of the phase change material layer 3 is perpendicular to the circular bottom layer 31 to form a hollow cylinder with an upper opening.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the diameter of the cylindrical lower electrode 2 is smaller than the diameter of the circular bottom layer 31.
  • the cylindrical lower electrode 2 has a diameter ranging from 2 to 5 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the invention also provides a method for fabricating a phase change memory unit, the method comprising the following steps:
  • Step 1 referring to FIG. 11 to FIG. 12, as shown in FIG. 11, a metal electrode layer 1 is provided, and a first dielectric layer 4 is grown on the metal electrode layer; as shown in FIG. Engraving, developing, etching, and stripping operations, preparing a cylindrical hole 7 in the first dielectric layer 4 to form a first dielectric layer with a cylindrical hole, the depth of the cylindrical hole 7 Equal to the thickness of the first dielectric layer 4, the metal electrode layer 1 is exposed.
  • the cylindrical hole 7 has a diameter ranging from 2 to 5 nm.
  • Step 2 referring to FIG. 13 to FIG. 14, as shown in FIG. 13, depositing a lower electrode metal material 21 on the first dielectric layer with a cylindrical hole by PVD, ALD or CVD to make the lower electrode a metal material 21 fills the cylindrical hole 7 and covers the upper surface of the first dielectric layer 4; as shown in FIG. 14, polishing is performed to remove the cylindrical hole 7 and the first dielectric layer Lower electrode metal material.
  • Step 3 please refer to Figure 15, as shown in the figure, using glue, lithography, development, etching, and de-glue operations.
  • the hole 8 of the cylindrical structure is formed on the structure shown in Fig. 14, so that the height of the lower electrode metal material 21 is smaller than the depth of the cylindrical hole 7.
  • the lower electrode metal material 21 remaining between the bottom of the hole 8 of the cylindrical structure and the metal electrode layer forms a cylindrical lower electrode 2.
  • the diameter of the hole 8 of the cylindrical structure ranges from 5 to 30 nm, that is, not only the upper portion of the upper electrode of the cylindrical hole, but also a part of the medium around the cylindrical hole is etched away.
  • Step 4 referring to FIG. 16 to FIG. 18, as shown in FIG. 16, the phase change material layer 3 is deposited by PVD, ALD or CVD, and the hollow layer is formed by connecting the sidewall layer 32 and the circular bottom layer 31.
  • a second dielectric layer 5 for filling the inside of the hollow cylinder by a low temperature ALD or a low temperature CVD method as shown in FIG. 17, polishing and removing the hole 8 of the cylindrical structure and the The excess second medium and phase change material on the first dielectric layer 4 are until flush with the first dielectric layer; as shown in FIG. 18, the upper electrode 6 is then prepared by PVD, ALD or CVD.
  • the phase change region 10 of the phase change memory cell of this embodiment is illustrated in FIG.
  • the in-situ heating is performed when depositing the phase change material layer, so that the phase change material layer is crystallized at the time of preparation, and the volume shrinkage during the amorphous to crystalline transition is prevented from remaining to the device; the in-situ heating temperature
  • the range is 200 ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the phase change material layer may also be heated without being heated, and the phase change material layer may be heated while the second dielectric layer is deposited to crystallize the phase change material layer, and the heating temperature range is 200. ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Ah Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the diameter of the lower electrode of the cylinder ranges from 2 to 5 nm, and the diameter of the circular bottom layer of the phase change material layer is larger than the diameter of the lower electrode of the cylinder.
  • the sidewall layer of the phase change material layer is perpendicular to the circular underlayer, forming a phase change memory cell having a vertical structure of the small electrode sidewall.
  • Embodiment 3 and Embodiment 1 adopt substantially the same technical scheme, except that the phase change material layers of the two are different.
  • the side wall layer of the phase change material layer is perpendicular to the circular bottom layer to form a hollow cylinder having an upper opening.
  • the sidewall layer of the phase change material layer is not perpendicular to the circular bottom layer, and a hollow round table having an upper opening is formed.
  • phase change memory cell including a metal electrode layer 1 located at the metal electrode layer. Cylindrical power down on 1 a pole 2, a phase change material layer 3 connected by a circular bottom layer 31 and a sidewall layer 32 on the cylindrical lower electrode 2, and a first dielectric layer encapsulating the phase change material layer 3 and the lower electrode 2 4. A second dielectric layer 5 filled in the phase change material layer 3, and an upper electrode 6 on the first dielectric layer 4, the second dielectric layer 5, and the phase change material layer 3.
  • the sidewall layer 32 of the phase change material layer 3 is not perpendicular to the circular bottom layer 31, and forms a hollow round table with an upper opening.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the diameter of the cylindrical lower electrode 2 is equal to the diameter of the circular bottom layer 31.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the invention also provides a method for fabricating a phase change memory unit, the method comprising the following steps:
  • Step 1 please refer to FIG. 20 to FIG. 21.
  • a metal electrode layer 1 is provided, and a first dielectric layer 4 is grown on the metal electrode layer; as shown in FIG. Engraving, developing, etching, and stripping operations, preparing a cylindrical hole 7 in the first dielectric layer 4 to form a first dielectric layer with a cylindrical hole, the depth of the cylindrical hole 7 Equal to the thickness of the first dielectric layer 4, the metal electrode layer 1 is exposed.
  • the diameter of the cylindrical hole 7 ranges from 5 to 30 nm.
  • Step 2 referring to FIG. 22 to FIG. 23, as shown in FIG. 22, depositing a lower electrode metal material 21 on the first dielectric layer with a cylindrical hole by PVD, ALD or CVD to make the lower electrode a metal material 21 fills the cylindrical hole 7 and covers the upper surface of the first dielectric layer 4; as shown in FIG. 23, polishing is performed to remove the outer surface of the cylindrical hole 7 and the first dielectric layer Lower electrode metal material.
  • Step 3 referring to FIG. 24, as shown in the figure, using the glue coating, photolithography, development, etching, and de-glue operations to etch back, forming a hole 9 of a round table structure on the structure shown in FIG.
  • the height of the electrode metal material 21 is smaller than the depth of the cylindrical hole 7.
  • the lower electrode metal material 21 remaining between the bottom of the hole 9 of the round table structure and the metal electrode layer forms a cylindrical lower electrode 2.
  • the diameter of the lower bottom of the hole 9 of the round table structure is equal to the diameter of the cylindrical hole 7, and the diameter of the upper bottom is larger than the diameter of the lower bottom, that is, not only the upper electrode of the cylinder in the cylindrical hole 7 is etched away. In the upper part, a part of the medium around it is also etched.
  • Step 4 referring to FIG. 25 to FIG. 27, as shown in FIG. 25, the phase change material layer 3 is deposited by PVD, ALD or CVD, and the hollow layer is formed by connecting the sidewall layer 32 and the circular bottom layer 31. a round table; then depositing a second dielectric layer 5 for filling the inside of the hollow round table by low temperature ALD or low temperature CVD; as shown in FIG. 26, polishing and removing the hole 8 of the cylindrical structure and the Excess second medium and phase change material on the first dielectric layer 4 until flush with the first dielectric layer; as shown in FIG. 27, then prepared by PVD, ALD or CVD Electrode 6.
  • the phase change region 10 of the phase change memory cell of this embodiment is illustrated in FIG.
  • the in-situ heating is performed when depositing the phase change material layer, so that the phase change material layer is crystallized at the time of preparation, and the volume shrinkage during the amorphous to crystalline transition is prevented from remaining to the device; the in-situ heating temperature
  • the range is 200 ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the phase change material layer may also be heated without being heated, and the phase change material layer may be heated while the second dielectric layer is deposited to crystallize the phase change material layer, and the heating temperature range is 200. ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the diameter of the lower electrode of the cylinder ranges from 5 to 30 nm, and the diameter of the circular bottom layer of the phase change material layer is equal to the diameter of the lower electrode of the cylinder.
  • the sidewall layer of the phase change material layer is not perpendicular to the circular underlayer, and forms a phase change memory cell with a sidewall inclined structure.
  • Embodiment 4 and Embodiment 3 adopt substantially the same technical scheme, except that the cylindrical lower electrodes of the two are different.
  • the diameter of the lower electrode of the cylinder ranges from 5 to 30 nm
  • the circular bottom layer of the phase change material layer is the same as the diameter of the lower electrode of the cylinder, but in the embodiment, under the cylinder
  • the diameter of the electrode ranges from 2 to 5 nm
  • the diameter of the circular bottom layer of the phase change material layer is larger than the diameter of the lower electrode of the cylinder.
  • FIG. 28 a schematic diagram of a phase change memory cell of a small electrode sidewall tilt structure of the present invention is shown.
  • the present invention provides a phase change memory cell including a metal electrode layer 1 at the metal. a cylindrical lower electrode 2 on the electrode layer 1, a phase change material layer 3 on the cylindrical lower electrode 2 connected by a circular bottom layer 31 and a sidewall layer 32, wrapping the phase change material layer 3 and a first dielectric layer 4 of the lower electrode 2, a second dielectric layer 5 filled in the phase change material layer 3, and the first dielectric layer 4, the second dielectric layer 5, and the phase change material layer 3 Upper electrode 6.
  • the sidewall layer 32 of the phase change material layer 3 is not perpendicular to the circular bottom layer 31, and forms a hollow round table with an upper opening.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the diameter of the cylindrical lower electrode 2 is smaller than the diameter of the circular bottom layer 31.
  • the cylindrical lower electrode 2 has a diameter ranging from 2 to 5 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the invention also provides a method for fabricating a phase change memory unit, the method comprising the following steps:
  • Step 1 referring to FIG. 29 to FIG. 30, as shown in FIG. 29, a metal electrode layer 1 is provided, and a first dielectric layer 4 is grown on the metal electrode layer; as shown in FIG. Engraving, developing, etching, and stripping operations, preparing a cylindrical hole 7 in the first dielectric layer 4 to form a first dielectric layer with a cylindrical hole, the depth of the cylindrical hole 7 Equal to the thickness of the first dielectric layer 4, the metal electrode layer 1 is exposed.
  • the cylindrical hole 7 has a diameter ranging from 2 to 5 nm.
  • Step 2 referring to FIG. 31 to FIG. 32, as shown in FIG. 31, depositing a lower electrode metal material 21 on the first dielectric layer with a cylindrical hole by PVD, ALD or CVD to make the lower electrode a metal material 21 fills the cylindrical hole 7 and covers the upper surface of the first dielectric layer 4; as shown in FIG. 32, polishing is performed to remove the outer surface of the cylindrical hole 7 and the first dielectric layer Lower electrode metal material 21.
  • Step 3 refer to FIG. 33, as shown in the figure, using the glue coating, photolithography, development, etching, and de-glue operations to etch back, forming a hole 9 of a round table structure on the structure shown in FIG.
  • the height of the lower electrode 2 is smaller than the depth of the cylindrical hole 7.
  • the lower electrode metal material 21 remaining between the bottom of the hole 9 of the round table structure and the metal electrode layer forms a cylindrical lower electrode 2.
  • the diameter of the lower bottom of the hole 9 of the round table structure is larger than the diameter of the cylindrical hole 7, and the diameter of the upper bottom is larger than the diameter of the lower bottom, that is, not only the upper electrode of the cylindrical body in the cylindrical hole 7 is etched away. In the upper part, a part of the medium around it is also etched.
  • Step 4 referring to FIG. 34 to FIG. 36, as shown in FIG. 34, the phase change material layer 3 is deposited by PVD, ALD or CVD to form a hollow which is connected by the sidewall layer 32 and the circular bottom layer 31 and is open at the upper portion. a round table; then depositing a second dielectric layer 5 for filling the inside of the hollow round table by low temperature ALD or low temperature CVD; as shown in FIG. 35, polishing and removing the hole 8 of the cylindrical structure and the The excess second medium and phase change material on the first dielectric layer 4 are until flush with the first dielectric layer; as shown in Fig. 36, the upper electrode 6 is then prepared by PVD, ALD or CVD.
  • the phase change region 10 of the phase change memory cell of this embodiment is illustrated in FIG.
  • the in-situ heating is performed when depositing the phase change material layer, so that the phase change material layer is crystallized at the time of preparation, and the volume shrinkage during the amorphous to crystalline transition is prevented from remaining to the device; the in-situ heating temperature
  • the range is 200 ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the phase change material layer may also be heated without being heated, and the phase change material layer may be heated while the second dielectric layer is deposited to crystallize the phase change material layer, and the heating temperature range is 200. ⁇ 400 °C to avoid element segregation or volatilization of the phase change material layer.
  • the circular bottom layer 31 has a diameter ranging from 5 to 30 nm and a thickness ranging from 1 to 10 nm.
  • the sidewall layer has a thickness ranging from 2 to 15 nm.
  • the cylindrical lower electrode 2 and the upper electrode 6 may be TiN, W, Al, Ti, Cu, graphite or other conductive material, and the height of the cylindrical lower electrode 2 is less than or equal to 500 nm.
  • the first dielectric layer 4 and the second dielectric layer 5 may be SiO 2 , Si 3 N 4 or other insulating materials.
  • the cylindrical lower electrode 2 is preferably ⁇ or W
  • the upper electrode 6 is preferably TiN.
  • the diameter of the lower electrode of the cylinder ranges from 2 to 5 nm, and the diameter of the circular bottom layer of the phase change material layer is larger than the diameter of the lower electrode of the cylinder.
  • the sidewall layer of the phase change material layer is not perpendicular to the circular underlayer, and forms a phase change memory cell with a small electrode sidewall tilt structure.
  • the phase change memory cell for replacing DRAM and FLASH of the present invention and the manufacturing method thereof, the phase change material is prepared into a film, the inner filling medium, and the thickness of the film is very thin (the thickness of the circular bottom layer is 1 ⁇ ) 10 nm, the thickness of the sidewall layer is 2 ⁇ 15 nm), and the dielectric material is used to limit the thickness of the phase change film as much as possible.
  • the device size is reduced in three dimensions, the phase transition of the one-dimensional scale can be further reduced inside the device. Thin film for improved device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

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Abstract

本发明提供一种用于替代DRAM及FLASH的相变存储单元及其制作方法，其包括相变材料层和与其接触并位于其下方的圆柱体下电极，其特征在于，所述相变材料层由侧壁层与圆形底层连接而成，并形成上部开口的空心圆柱体或空心倒圆台，所述空心圆柱体或空心倒圆台内部填充介质层。本发明采用制备内部填充介质材料的侧壁层垂直的相变材料层和侧壁层倾斜的相变材料层以及采用小电极的手段，减少相变材料层的厚度，从而减小操作时的相变区域、提高相变材料层的热稳定性及相变速度，最终达到减小操作功耗、提高器件数据保持力、提高器件操作速度和提高器件循环操作次数的目的。

Description

用于替代 DRAM及 FLASH的相变存储单元及其制作方法
技术领域
本发明属于微电子技术领域， 特别是涉及一种用于替代 DRAM 及 FLASH 的相变存储 单元及其制作方法。 背景技术
相变存储器利用操作信号产生焦耳热对相变材料进行操作， 使其在不同的相之间进行转 变， 从而体现出高低电阻值差异， 完成对信息的存储。 相变存储器由于其操作速度快， 数据 保持力好， 循环操作能力强， 与传统 CMOS 工艺兼容， 并且在小尺寸时仍能保持其操作性 能， 所以被认为是最有希望的下一代非挥发性存储器之一。 随着器件尺寸的縮小， 尺寸效应 对相变材料的影响仍是现在相变存储器研究的热点。
研究者对尺寸效应对相变材料热稳定性的影响屡见报道。 例如， 文献 （JOURNAL OF APPLIED PHYSICS 103, 114310 (2008) ) 曾报道了 GeSb， Sb2Te， NGST, GST, AIST的 结晶温度随薄膜厚度的变化。 当相变材料薄膜厚度在 10 纳米以上时， 相变材料的结晶温度 随厚度的变化非常微弱。 当相变材料薄膜厚度低于 10 纳米时， 相变材料的结晶温度随着薄 膜厚度的减小有不同程度的提高。 例如随着薄膜由 10纳米减小到 2纳米， Sb2Te, GeSb, GST, AIST材料的结晶温度分别提高了将近 150， 50， 200， 100摄氏度。
文献 （SCIENTIFIC REPORTS 2:360 DOI:10.1038/srep00360) 报道了尺寸效应同时也影 响着相变材料薄膜结晶速度。 当相变材料厚度减薄， 材料的比表面积增加， 而界面由于存在 缺陷而容易形成晶核。 而晶核的存在为相变材料的结晶过程縮短了晶核形成时间， 减少了结 晶过程所需时间， 进而提升了相变存储器的操作速度。 当晶核形成时间縮短， 晶粒成长变成 为影响结晶时间的主要因素。 而晶粒生长时间随着尺寸縮小而变短， 这就保证了小尺寸器件 更快的相变速度。
相变存储器利用操作信号产生焦耳热对相变材料进行操作， 使其在不同的相之间进行转 变， 从而体现出高低电阻值差异， 完成对信息的存储。 操作功耗的有效部分为实现相变材料 相转变部分的能量。 相变区域越小， 所需能量越小， 器件功耗降低。 而限制型结构相变存储 器正是通过减小相变区域降低了器件操作功耗。 刀片结构， 环形结构等小尺寸电极的制备其 目的也是减小相变区域， 从而降低功耗。
相变存储器的主要失效原因是由于相变材料的元素偏析导致的材料均匀性降低。 而元素 扩散主要发生在操作时电流产生的高温条件下， 高温持续时间越长元素偏析越严重。 所以对 相变材料长时间高功率操作会促使元素偏析， 加快器件失效， 降低器件可循环操作次数。 而 具有低功耗快速操作特定的相变存储器在操作时由于操作时间短， 每次操作对材料的元素偏 析效果降低， 有利于提高器件循环操作次数的能力。 发明内容
鉴于以上所述现有技术的缺点， 本发明的目的在于提供一种用于替代 DRAM及 FLASH 的相变存储单元及其制作方法， 用于解决现有技术中相变存储单元的相变材料尺寸大导致器 件操作速度慢、 功耗高以及循环操作能力低的问题。
为实现上述目的及其他相关目的， 本发明提供一种用于替代 DRAM及 FLASH 的相变 存储单元及其制作方法。 本发明的相变存储单元具有高数据保持力， 高速低功耗的特点。
本发明采用如下技术方案， 一种相变存储单元， 其包括相变材料层和与其接触并位于其 下方的圆柱体下电极， 所述相变材料层由侧壁层与圆形底层连接而成， 并形成上部开口的空 心圆柱体或空心倒圆台， 所述空心圆柱体或空心倒圆台内部填充介质层。
可选地， 所述圆形底层的直径等于或大于圆柱体下电极的直径。
可选地， 所述圆形底层的直径范围是 5~30 nm。
可选地， 所述圆柱体下电极的直径范围是 2~30 nm。
可选地， 所述圆形底层的厚度范围是 l~10 nm， 所述侧壁层的厚度范围是 2~15 nm。 本发明还提供一种相变存储单元的制作方法， 该方法包括以下步骤：
a) 提供一金属电极层， 在所述金属电极层上生长第一介质层， 并在所述第一介质层上 制备出圆柱形孔， 形成带有圆柱形孔的第一介质层； 所述圆柱形孔的深度等于所述 第一介质层的厚度；
b) 在所述带有圆柱形孔的第一介质层上沉积下电极金属材料， 并进行抛光去除所述圆 柱形孔外的下电极金属材料， 留下的下电极金属材料与所述第一介质层齐平； c) 在所述步骤 2) 中抛光后的结构上进行回刻， 形成圆柱体结构或倒圆台结构的孔洞； 剩余的下电极金属材料形成圆柱体下电极；
d) 沉积相变材料层， 形成由侧壁层与圆形底层连接而成并上部开口的空心圆柱体或空 心倒圆台； 接着沉积用于填充在所述空心圆柱体或空心倒圆台内部的第二介质层； 然后抛光去除所述圆柱体结构或倒圆台结构的孔洞外多余的第二介质和相变材料， 直至与所述第一介质层齐平， 然后制备出上电极。
可选地， 于所述步骤 4) 中沉积相变材料层时进行原位加温； 所述原位加温的温度范围 是 200~400 °C。
可选地， 于所述步骤 4 ) 中沉积第二介质层时进行加温， 所述加温的温度范围是 200-400 V。
可选地， 所述圆形底层的直径等于或大于圆柱体下电极的直径。
可选地， 所述圆形底层的厚度范围是 l~10 nm， 所述侧壁层的厚度范围是 2~15 nm。 如上所述， 本发明的用于替代 DRAM及 FLASH 的相变存储单元及其制作方法， 具有 以下有益效果： 采用的相变材料薄膜的厚度薄， 减小了相变区域， 从而将存储单元 RESET操 作功耗降低至 1E-11焦耳； 相变材料厚度薄使界面对结晶速度提升的效果变得更加明显， 从 而将器件的 SET操作速度提高到 500皮秒； 操作功耗的降低和操作时间的縮短减少了每次操 作过程对相变材料的损害， 增加了器件的最大可操作次数， 从而使得器件的疲劳能达到 1E11 ; 相变材料厚度薄能提升材料的热稳定性， 使利用 Ge2Sb2Te5材料作为存储介质的器件的 数据保持力达到十年 120摄氏度。 附图说明
图 1显示为本发明的侧壁垂直结构的相变存储单元的示意图。
图 2至图 3显示为本发明的相变存储单元的制作方法在实施例 1步骤 1中所呈现的结构 示意图。
图 4至图 5显示为本发明的相变存储单元的制作方法在实施例 1步骤 2中所呈现的结构 示意图。
图 6显示为本发明的相变存储单元的制作方法在实施例 1 步骤 3 中所呈现的结构示意 图。
图 7至图 9显示为本发明的相变存储单元的制作方法在实施例 1步骤 4中所呈现的结构 示意图。
图 10显示为本发明的小电极侧壁垂直结构的相变存储单元的示意图。
图 11至图 12显示为本发明的相变存储单元的制作方法在实施例 2步骤 1中所呈现的结 构示意图。
图 13至图 14显示为本发明的相变存储单元的制作方法在实施例 2步骤 2中所呈现的结 构示意图。
图 15显示为本发明的相变存储单元的制作方法在实施例 2步骤 3中所呈现的结构示意 图。 图 16至图 18显示为本发明的相变存储单元的制作方法在实施例 2步骤 4中所呈现的结 构示意图。
图 19显示为本发明的侧壁倾斜结构的相变存储单元的示意图。
图 20至图 21显示为本发明的相变存储单元的制作方法在实施例 3步骤 1中所呈现的结 构示意图。
图 22至图 23显示为本发明的相变存储单元的制作方法在实施例 3步骤 2中所呈现的结 构示意图。
图 24显示为本发明的相变存储单元的制作方法在实施例 3步骤 3中所呈现的结构示意 图。
图 25至图 27显示为本发明的相变存储单元的制作方法在实施例 3步骤 4中所呈现的结 构示意图。
图 28显示为本发明的小电极侧壁倾斜结构的相变存储单元的示意图。
图 29至图 30显示为本发明的相变存储单元的制作方法在实施例 4步骤 1中所呈现的结 构示意图。
图 31至图 32显示为本发明的相变存储单元的制作方法在实施例 4步骤 2中所呈现的结 构示意图。
图 33显示为本发明的相变存储单元的制作方法在实施例 4步骤 3中所呈现的结构示意 图。
图 34至图 36显示为本发明的相变存储单元的制作方法在实施例 4步骤 4中所呈现的结 构示意图。 元件标号说明
1 金属电极层
21 下电极金属材料
2 圆柱形下电极
31 圆形底层
32 侧壁层
3 相变材料层
4 第一介质层
5 第二介质层 6 上电极
7 圆柱形孔
8 圆柱体结构的孔洞
9 倒圆台结构的孔洞
10 相变区域 具体实施方式
以下通过特定的具体实例说明本发明的实施方式， 本领域技术人员可由本说明书所揭露 的内容轻易地了解本发明的其他优点与功效。 本发明还可以通过另外不同的具体实施方式加 以实施或应用， 本说明书中的各项细节也可以基于不同观点与应用， 在没有背离本发明的精 神下进行各种修饰或改变。
请参阅图 1~图 36。 需要说明的是， 本实施例中所提供的图示仅以示意方式说明本发明 的基本构想， 遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、 形状 及尺寸绘制， 其实际实施时各组件的型态、 数量及比例可为一种随意的改变， 且其组件布局 型态也可能更为复杂。 实施例 1
请参阅图 1， 显示为本发明的侧壁垂直结构的相变存储单元的示意图， 如图所示， 本发 明提供一种相变存储单元， 其包括金属电极层 1， 位于所述金属电极层 1上的圆柱形下电极 2， 位于所述圆柱形下电极 2上的由圆形底层 31与侧壁层 32连接而成的相变材料层 3， 包 裹所述相变材料层 3和下电极 2的第一介质层 4， 填充于所述相变材料层 3内的第二介质层 5， 以及位于所述第一介质层 4、 第二介质层 5和相变材料层 3上的上电极 6。
具体的， 所述相变材料层 3的侧壁层 32与圆形底层 31垂直， 形成上部开口的空心圆柱 体。 所述圆形底层 31的直径范围是 5~30 nm， 厚度范围是 l~10 nm。 所述侧壁层的厚度范围 是 2~15 nm。 所述圆柱体下电极 2的直径等于圆形底层 31的直径。 圆柱形下电极 2和上电 极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或等 于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例 中， 圆柱形下电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本发明还提供一种相变存储单元的制作方法， 该方法包括以下步骤：
步骤 1， 请参阅图 2至图 3， 如图 2所示， 提供一金属电极层 1， 在所述金属电极层上 生长第一介质层 4; 如图 3所示， 接着进行涂胶、 光刻、 显影、 刻蚀、 及去胶操作， 在所述 第一介质层 4上制备出圆柱形孔 7， 形成带有圆柱形孔的第一介质层， 所述圆柱形孔 7的深 度等于所述第一介质层 4的厚度， 露出所述金属电极层 1。 具体的， 所述圆柱形孔 Ί的直径 范围是 5~30 nm。
步骤 2， 请参阅图 4至图 5， 如图 4所示， 采用 PVD、 ALD或 CVD法在所述带有圆柱 形孔的第一介质层上沉积下电极金属材料 21， 使所述下电极金属材料 21填满所述圆柱形孔 7并覆盖于所述第一介质层 4的上表面； 如图 5所示， 进行抛光去除所述圆柱形孔 7外及所 述第一介质层上的下电极金属材料。
步骤 3， 请参阅图 6， 如图所示， 采用涂胶、 光刻、 显影、 刻蚀、 及去胶操作进行回 刻， 在图 5所示结构上形成圆柱体结构的孔洞 8， 使所述下电极金属材料 21 的高度小于所 述圆柱形孔 7的深度。 所述圆柱体结构的孔洞 8下底与所述金属电极层之间剩余的所述下电 极金属材料 21 形成圆柱体下电极 2。 具体的， 所述圆柱体结构的孔洞 8 的直径等于所述圆 柱形孔 7的直径， 即只刻蚀掉所述圆柱形孔洞 7内圆柱体上电极的上面一部分， 而不刻蚀其 周边的介质。
步骤 4， 请参阅图 7至图 9， 如图 7所示， 采用 PVD、 ALD或 CVD法沉积相变材料层 3， 形成由侧壁层 32与圆形底层 31连接而成并上部开口的空心圆柱体； 接着采用低温 ALD 或低温 CVD法沉积用于填充在所述空心圆柱体内部的第二介质层 5; 如图 8所示， 进行抛 光去除所述圆柱体结构的孔洞 8外和所述第一介质层 4上多余的第二介质和相变材料， 直至 与所述第一介质层齐平； 如图 9所示， 然后采用 PVD、 ALD或 CVD法制备出上电极 6。 图 9中示意出了本实施例中相变存储单元的相变区域 10。
具体的， 沉积相变材料层时进行原位加温， 使相变材料层在制备时即晶化， 避免非晶到 晶态转变时的体积收縮遗留给器件； 所述原位加温的温度范围是 200~400 °C， 以避免所述相 变材料层产生元素偏析或挥发。 也可以在沉积相变材料层时不加温， 而在沉积第二介质层时 对所述相变材料层加温， 使所述相变材料层晶化， 所述加温的温度范围是 200~400 °C， 以避 免所述相变材料层产生元素偏析或挥发。 所述圆形底层 31 的直径范围是 5~30 nm， 厚度范 围是 1~10 nm。 所述侧壁层的厚度范围是 2~15 nm。 所述圆柱形下电极 2和上电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下 电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本实施中制备出的相变存储单元中， 所述圆柱体下电极的直径范围是 5~30 nm， 所述相 变材料层的圆形底层的直径等于所述圆柱体下电极的直径， 所述相变材料层的侧壁层与圆形 底层垂直， 形成侧壁垂直结构的相变存储单元。 实施例 2
实施例 2 与实施例 1 采用基本相同的技术方案， 不同之处在于二者的圆柱体下电极不 同。 在实施例 1中， 所述圆柱体下电极的直径范围是 5~30 nm， 所述相变材料层的圆形底层 与圆柱体下电极的直径相同， 而在本实施例中， 圆柱体下电极的直径范围是 2~5 nm， 所述 相变材料层的圆形底层的直径大于圆柱体下电极的直径。
请参阅图 10， 显示为本发明的小电极侧壁垂直结构的相变存储单元的示意图， 如图所 示， 本发明提供一种相变存储单元， 其包括金属电极层 1， 位于所述金属电极层 1上的圆柱 形下电极 2， 位于所述圆柱形下电极 2上的由圆形底层 31与侧壁层 32连接而成的相变材料 层 3， 包裹所述相变材料层 3和下电极 2的第一介质层 4， 填充于所述相变材料层 3内的第 二介质层 5， 以及位于所述第一介质层 4、 第二介质层 5和相变材料层 3上的上电极 6。
具体的， 所述相变材料层 3的侧壁层 32与圆形底层 31垂直， 形成上部开口的空心圆柱 体。 所述圆形底层 31的直径范围是 5~30 nm， 厚度范围是 l~10 nm。 所述侧壁层的厚度范围 是 2~15 nm。 所述圆柱体下电极 2的直径小于圆形底层 31的直径。 所述圆柱形下电极 2的 直径范围是 2~5 nm。 圆柱形下电极 2和上电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他 导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可以 是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下电极 2优选为 ΉΝ或 W， 上电极 6 优选为 TiN。
本发明还提供一种相变存储单元的制作方法， 该方法包括以下步骤：
步骤 1， 请参阅图 11至图 12， 如图 11所示， 提供一金属电极层 1， 在所述金属电极层 上生长第一介质层 4; 如图 3所示， 接着进行涂胶、 光刻、 显影、 刻蚀、 及去胶操作， 在所 述第一介质层 4上制备出圆柱形孔 7， 形成带有圆柱形孔的第一介质层， 所述所述圆柱形孔 7 的深度等于所述第一介质层 4的厚度， 露出所述金属电极层 1。 具体的， 所述圆柱形孔洞 7的直径范围是 2~5 nm。
步骤 2， 请参阅图 13至图 14， 如图 13所示， 采用 PVD、 ALD或 CVD法在所述带有 圆柱形孔的第一介质层上沉积下电极金属材料 21， 使所述下电极金属材料 21填满所述圆柱 形孔 7并覆盖于所述第一介质层 4的上表面； 如图 14所示， 进行抛光去除所述圆柱形孔 7 外及所述第一介质层上的下电极金属材料。
步骤 3， 请参阅图 15， 如图所示， 采用涂胶、 光刻、 显影、 刻蚀、 及去胶操作进行回 刻， 在图 14所示结构上形成圆柱体结构的孔洞 8， 使所述下电极金属材料 21的高度小于所 述圆柱形孔 7的深度。 所述圆柱体结构的孔洞 8下底与所述金属电极层之间剩余的所述下电 极金属材料 21形成圆柱体下电极 2。 具体的， 所述圆柱体结构的孔洞 8的直径范围是 5~30 nm， 即不仅刻蚀掉所述圆柱形孔洞 Ί 内圆柱体上电极的上面一部分， 还刻蚀其周边的一部 分介质。
步骤 4， 请参阅图 16至图 18， 如图 16所示， 采用 PVD、 ALD或 CVD法沉积相变材 料层 3， 形成由侧壁层 32与圆形底层 31连接而成并上部开口的空心圆柱体； 接着采用低温 ALD或低温 CVD法沉积用于填充在所述空心圆柱体内部的第二介质层 5; 如图 17所示， 进行抛光去除所述圆柱体结构的孔洞 8 外和所述第一介质层 4 上多余的第二介质和相变材 料， 直至与所述第一介质层齐平； 如图 18所示， 然后采用 PVD、 ALD或 CVD法制备出上 电极 6。 图 18中示意出了本实施例中相变存储单元的相变区域 10。
具体的， 沉积相变材料层时进行原位加温， 使相变材料层在制备时即晶化， 避免非晶到 晶态转变时的体积收縮遗留给器件； 所述原位加温的温度范围是 200~400 °C， 以避免所述相 变材料层产生元素偏析或挥发。 也可以在沉积相变材料层时不加温， 而在沉积第二介质层时 对所述相变材料层加温， 使所述相变材料层晶化， 所述加温的温度范围是 200~400 °C， 以避 免所述相变材料层产生元素偏析或挥发。 所述圆形底层 31 的直径范围是 5~30 nm， 厚度范 围是 1~10 nm。 所述侧壁层的厚度范围是 2~15 nm。 所述圆柱形下电极 2和上电极 6可以是 TiN、 W、 Ah Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下 电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本实施中制备出的相变存储单元中， 所述圆柱体下电极的直径范围是 2~5 nm， 所述相变 材料层的圆形底层的直径大于所述圆柱体下电极的直径， 所述相变材料层的侧壁层与圆形底 层垂直， 形成小电极侧壁垂直结构的相变存储单元。 实施例 3
实施例 3与实施例 1采用基本相同的技术方案， 不同之处在于二者的相变材料层不同。 在实施例 1中， 所述相变材料层的侧壁层与圆形底层垂直， 形成上部开口的空心圆柱体。 而 在本实施例中， 所述相变材料层的侧壁层与圆形底层不垂直， 形成上部开口的空心倒圆台。
请参阅图 19， 如图所示， 显示为本发明的侧壁倾斜结构的相变存储单元的示意图， 本 发明提供一种相变存储单元， 其包括金属电极层 1， 位于所述金属电极层 1上的圆柱形下电 极 2， 位于所述圆柱形下电极 2上的由圆形底层 31与侧壁层 32连接而成的相变材料层 3， 包裹所述相变材料层 3和下电极 2的第一介质层 4， 填充于所述相变材料层 3内的第二介质 层 5， 以及位于所述第一介质层 4、 第二介质层 5和相变材料层 3上的上电极 6。
具体的， 所述相变材料层 3的侧壁层 32与圆形底层 31不垂直， 形成上部开口的空心倒 圆台。 所述圆形底层 31的直径范围是 5~30 nm， 厚度范围是 l~10 nm。 所述侧壁层的厚度范 围是 2~15 nm。 所述圆柱体下电极 2的直径等于圆形底层 31的直径。 圆柱形下电极 2和上 电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或 等于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例 中， 圆柱形下电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本发明还提供一种相变存储单元的制作方法， 该方法包括以下步骤：
步骤 1， 请参阅图 20至图 21， 如图 20所示， 提供一金属电极层 1， 在所述金属电极层 上生长第一介质层 4; 如图 21 所示， 接着进行涂胶、 光刻、 显影、 刻蚀、 及去胶操作， 在 所述第一介质层 4上制备出圆柱形孔 7， 形成带有圆柱形孔的第一介质层， 所述所述圆柱形 孔 7的深度等于所述第一介质层 4的厚度， 露出所述金属电极层 1。 具体的， 所述圆柱形孔 7的直径范围是 5~30 nm。
步骤 2， 请参阅图 22至图 23， 如图 22所示， 采用 PVD、 ALD或 CVD法在所述带有 圆柱形孔的第一介质层上沉积下电极金属材料 21， 使所述下电极金属材料 21填满所述圆柱 形孔 7并覆盖于所述第一介质层 4的上表面； 如图 23所示， 进行抛光去除所述圆柱形孔 7 外及所述第一介质层上的下电极金属材料。
步骤 3， 请参阅图 24， 如图所示， 采用涂胶、 光刻、 显影、 刻蚀、 及去胶操作进行回 刻， 在图 23所示结构上形成倒圆台结构的孔洞 9， 使所述下电极金属材料 21的高度小于所 述圆柱形孔 7的深度。 所述倒圆台结构的孔洞 9下底与所述金属电极层之间剩余的所述下电 极金属材料 21 形成圆柱体下电极 2。 具体的， 所述倒圆台结构的孔洞 9 的下底直径等于所 述圆柱形孔 7的直径， 上底直径大于下底直径， 即不仅刻蚀掉所述圆柱形孔洞 7内圆柱体上 电极的上面一部分， 还刻蚀其周边的一部分介质。
步骤 4， 请参阅图 25至图 27， 如图 25所示， 采用 PVD、 ALD或 CVD法沉积相变材 料层 3， 形成由侧壁层 32与圆形底层 31连接而成并上部开口的空心倒圆台； 接着采用低温 ALD或低温 CVD法沉积用于填充在所述空心倒圆台内部的第二介质层 5; 如图 26所示， 进行抛光去除所述圆柱体结构的孔洞 8 外和所述第一介质层 4 上多余的第二介质和相变材 料， 直至与所述第一介质层齐平； 如图 27所示， 然后采用 PVD、 ALD或 CVD法制备出上 电极 6。 图 27中示意出了本实施例中相变存储单元的相变区域 10。
具体的， 沉积相变材料层时进行原位加温， 使相变材料层在制备时即晶化， 避免非晶到 晶态转变时的体积收縮遗留给器件； 所述原位加温的温度范围是 200~400 °C， 以避免所述相 变材料层产生元素偏析或挥发。 也可以在沉积相变材料层时不加温， 而在沉积第二介质层时 对所述相变材料层加温， 使所述相变材料层晶化， 所述加温的温度范围是 200~400 °C， 以避 免所述相变材料层产生元素偏析或挥发。 所述圆形底层 31 的直径范围是 5~30 nm， 厚度范 围是 1~10 nm。 所述侧壁层的厚度范围是 2~15 nm。 所述圆柱形下电极 2和上电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下 电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本实施中制备出的相变存储单元中， 所述圆柱体下电极的直径范围是 5~30 nm， 所述相 变材料层的圆形底层的直径等于所述圆柱体下电极的直径， 所述相变材料层的侧壁层与圆形 底层不垂直， 形成侧壁倾斜结构的相变存储单元。 实施例 4
实施例 4 与实施例 3 采用基本相同的技术方案， 不同之处在于二者的圆柱体下电极不 同。 在实施例 3中， 所述圆柱体下电极的直径范围是 5~30 nm， 所述相变材料层的圆形底层 与圆柱体下电极的直径相同， 而在本实施例中， 圆柱体下电极的直径范围是 2~5 nm， 所述 相变材料层的圆形底层的直径大于圆柱体下电极的直径。
请参阅图 28， 显示为本发明的小电极侧壁倾斜结构的相变存储单元的示意图， 如图所 示， 本发明提供一种相变存储单元， 其包括金属电极层 1， 位于所述金属电极层 1上的圆柱 形下电极 2， 位于所述圆柱形下电极 2上的由圆形底层 31与侧壁层 32连接而成的相变材料 层 3， 包裹所述相变材料层 3和下电极 2的第一介质层 4， 填充于所述相变材料层 3内的第 二介质层 5， 以及位于所述第一介质层 4、 第二介质层 5和相变材料层 3上的上电极 6。
具体的， 所述相变材料层 3的侧壁层 32与圆形底层 31不垂直， 形成上部开口的空心倒 圆台。 所述圆形底层 31的直径范围是 5~30 nm， 厚度范围是 l~10 nm。 所述侧壁层的厚度范 围是 2~15 nm。 所述圆柱体下电极 2的直径小于圆形底层 31 的直径。 所述圆柱形下电极 2 的直径范围是 2~5 nm。 圆柱形下电极 2和上电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其 他导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可 以是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本发明还提供一种相变存储单元的制作方法， 该方法包括以下步骤：
步骤 1， 请参阅图 29至图 30， 如图 29所示， 提供一金属电极层 1， 在所述金属电极层 上生长第一介质层 4; 如图 30 所示， 接着进行涂胶、 光刻、 显影、 刻蚀、 及去胶操作， 在 所述第一介质层 4上制备出圆柱形孔 7， 形成带有圆柱形孔的第一介质层， 所述所述圆柱形 孔 7的深度等于所述第一介质层 4的厚度， 露出所述金属电极层 1。 具体的， 所述圆柱形孔 洞 7的直径范围是 2~5 nm。
步骤 2， 请参阅图 31至图 32， 如图 31所示， 采用 PVD、 ALD或 CVD法在所述带有 圆柱形孔的第一介质层上沉积下电极金属材料 21， 使所述下电极金属材料 21填满所述圆柱 形孔 7并覆盖于所述第一介质层 4的上表面； 如图 32所示， 进行抛光去除所述圆柱形孔 7 外及所述第一介质层上的下电极金属材料 21。
步骤 3， 请参阅图 33， 如图所示， 采用涂胶、 光刻、 显影、 刻蚀、 及去胶操作进行回 刻， 在图 32所示结构上形成倒圆台结构的孔洞 9， 使所述下电极 2的高度小于所述圆柱形 孔 7的深度。 所述倒圆台结构的孔洞 9下底与所述金属电极层之间剩余的所述下电极金属材 料 21 形成圆柱体下电极 2。 具体的， 所述倒圆台结构的孔洞 9 的下底直径大于所述圆柱形 孔 7的直径， 上底直径大于下底直径， 即不仅刻蚀掉所述圆柱形孔洞 7内圆柱体上电极的上 面一部分， 还刻蚀其周边的一部分介质。
步骤 4， 请参阅图 34至图 36， 如图 34所示， 采用 PVD、 ALD或 CVD法沉积相变材 料层 3， 形成由侧壁层 32与圆形底层 31连接而成并上部开口的空心倒圆台； 接着采用低温 ALD或低温 CVD法沉积用于填充在所述空心倒圆台内部的第二介质层 5; 如图 35所示， 进行抛光去除所述圆柱体结构的孔洞 8 外和所述第一介质层 4 上多余的第二介质和相变材 料， 直至与所述第一介质层齐平； 如图 36所示， 然后采用 PVD、 ALD或 CVD法制备出上 电极 6。 图 36中示意出了本实施例中相变存储单元的相变区域 10。
具体的， 沉积相变材料层时进行原位加温， 使相变材料层在制备时即晶化， 避免非晶到 晶态转变时的体积收縮遗留给器件； 所述原位加温的温度范围是 200~400 °C， 以避免所述相 变材料层产生元素偏析或挥发。 也可以在沉积相变材料层时不加温， 而在沉积第二介质层时 对所述相变材料层加温， 使所述相变材料层晶化， 所述加温的温度范围是 200~400 °C， 以避 免所述相变材料层产生元素偏析或挥发。 所述圆形底层 31 的直径范围是 5~30 nm， 厚度范 围是 1~10 nm。 所述侧壁层的厚度范围是 2~15 nm。 所述圆柱形下电极 2和上电极 6可以是 TiN、 W、 Al、 Ti、 Cu、 石墨或其他导电材料， 圆柱形下电极 2的高度小于或等于 500 nm。 第一介质层 4和第二介质层 5可以是 Si02、 Si3N4或其他绝缘材料。 本实施例中， 圆柱形下 电极 2优选为 ΉΝ或 W， 上电极 6优选为 TiN。
本实施中制备出的相变存储单元中， 所述圆柱体下电极的直径范围是 2~5 nm， 所述相 变材料层的圆形底层的直径大于所述圆柱体下电极的直径， 所述相变材料层的侧壁层与圆形 底层不垂直， 形成小电极侧壁倾斜结构的相变存储单元。
综上所述， 本发明的用于替代 DRAM及 FLASH 的相变存储单元及其制作方法， 将相 变材料制备成薄膜， 内部填充介质， 且薄膜的厚度很薄 （圆形底层厚度为 1~10 nm， 侧壁层 厚度为 2~15 nm)， 并采用介质材料将相变薄膜的厚度尽量的限制， 在器件尺寸三维等比縮 小的同时在器件内部构造一维尺度可继续縮小的相变薄膜， 使器件性能提升。 所以， 本发明 有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效， 而非用于限制本发明。 任何熟悉此技 术的人士皆可在不违背本发明的精神及范畴下， 对上述实施例进行修饰或改变。 因此， 举凡 所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等 效修饰或改变， 仍应由本发明的权利要求所涵盖。

Claims

权利要求书 、 一种相变存储单元， 其包括相变材料层和与其接触并位于其下方的圆柱体下电极， 其 特征在于， 所述相变材料层由侧壁层与圆形底层连接而成， 并形成上部开口的空心圆 柱体或空心倒圆台， 所述空心圆柱体或空心倒圆台内部填充介质层。 、 根据权利要求 1 所述的相变存储单元， 其特征在于： 所述圆形底层的直径等于或大于 圆柱体下电极的直径。 、 根据权利要求 1 或 2所述的相变存储单元， 其特征在于： 所述圆形底层的直径范围是 5-30 nm。 、 根据权利要求 1 或 2所述的相变存储单元， 其特征在于： 所述圆柱体下电极的直径范 围是 2~5 nm， 高度小于或等于 500 nm。 、 根据权利要求 1 或 2所述的相变存储单元， 其特征在于： 所述圆柱体下电极的直径范 围是 5~30 nm， 高度小于或等于 500 nm。 、 根据权利要求 1所述的相变存储单元， 其特征在于： 所述圆形底层的厚度范围是 1~10 nm， 所述侧壁层的厚度范围是 2~15 nm。 、 一种相变存储单元的制作方法， 其特征在于， 该方法包括以下步骤：
a) 提供一金属电极层， 在所述金属电极层上生长第一介质层， 并在所述第一介质层上 制备出圆柱形孔， 形成带有圆柱形孔的第一介质层； 所述圆柱形孔的深度等于所述 第一介质层的厚度；
b) 在所述带有圆柱形孔的第一介质层上沉积下电极金属材料， 并进行抛光去除所述圆 柱形孔外的下电极金属材料， 留下的下电极金属材料与所述第一介质层齐平； c) 在所述步骤 2) 中抛光后的结构上进行回刻， 形成圆柱体结构或倒圆台结构的孔洞； 剩余的下电极金属材料形成圆柱体下电极；
d) 沉积相变材料层， 形成由侧壁层与圆形底层连接而成并上部开口的空心圆柱体或空 心倒圆台； 接着沉积用于填充在所述空心圆柱体或空心倒圆台内部的第二介质层； 然后抛光去除所述圆柱体结构或倒圆台结构的孔洞外多余的第二介质和相变材料， 直至与所述第一介质层齐平， 然后制备出上电极。 、 根据权利要求 7所述的相变存储单元的制作方法， 其特征在于： 于所述步骤 4) 中沉积 相变材料层时进行原位加温； 所述原位加温的温度范围是 200~400 。C。 、 根据权利要求 7所述的相变存储单元的制作方法， 其特征在于： 于所述步骤 4) 中沉积 第二介质层时进行加温； 所述加温的温度范围是 200~400 。C。
0、 根据权利要求 7所述的相变存储单元的制作方法， 其特征在于： 所述圆形底层的直径 等于或大于圆柱体下电极的直径。 1、 根据权利要求 7或 10所述的相变存储单元的制作方法， 其特征在于： 所述圆形底层 的厚度范围是 1~10 nm， 所述侧壁层的厚度范围是 2~15 nm。
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