WO2014032417A1 - 一种Sigma-Delta调制器及模数转换器 - Google Patents

一种Sigma-Delta调制器及模数转换器 Download PDF

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Publication number
WO2014032417A1
WO2014032417A1 PCT/CN2013/071961 CN2013071961W WO2014032417A1 WO 2014032417 A1 WO2014032417 A1 WO 2014032417A1 CN 2013071961 W CN2013071961 W CN 2013071961W WO 2014032417 A1 WO2014032417 A1 WO 2014032417A1
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Prior art keywords
resistor
integrator
signal
correction
input
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PCT/CN2013/071961
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English (en)
French (fr)
Inventor
赵喆
陈岚
吕志强
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/425,095 priority Critical patent/US9350380B2/en
Publication of WO2014032417A1 publication Critical patent/WO2014032417A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/38—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path

Definitions

  • the present invention relates to the field of analog-to-digital converter technologies, and in particular, to a sigma-delta modulator and an analog-to-digital converter.
  • Sigma-Delta analog-to-digital converters have received more and more attention due to their high precision, high integration, and low power consumption.
  • the Sigma-Delta analog-to-digital converter is divided into two types, continuous time and discrete time, according to the implementation of the integrator.
  • continuous-time Sigma-Delta analog-to-digital converters offer lower power consumption, faster speeds, and inherent anti-aliasing advantages, which can effectively increase battery life. Reducing the complexity of the system is very important for portable wireless devices. Therefore, continuous-time Sigma-Delta analog-to-digital converters have received more and more attention in recent years.
  • the Sigma-Delta modulator is part of the Sigma-Delta analog-to-digital converter.
  • the integrator is the most basic and core module in the Sigma-Delta modulator.
  • the main advantage of the RC integrator over the Gm-C integrator is its high linearity and large input signal amplitude.
  • the virtual ground feature of the RC integrator also enables the output of the feedback DAC to be connected to the virtual ground input of the op amp, increasing the linearity of the feedback DAC. Therefore, the RC integrator is more suitable for applications requiring high linearity and large input signal swing.
  • the integral coefficient 1/RC of the RC integrator also deviates with the deviation of the process. Deviations in the integral coefficients may cause a drop in the overall performance of the Sigma-Delta modulator, and may even cause the overall circuit to lose its modulation function or oscillate. Therefore, resistors and/or capacitors should be modified during the design process to avoid the effects of process variations on the overall performance of the modulator.
  • the technical problem to be solved by the present invention is to provide a Sigma-Delta modulator that designs a single package without increasing loop delay without adding additional chip area, power consumption, and cost.
  • Embodiments of the present invention provide a Sigma-Delta modulator, including: a quantizer, a correction module, and
  • the correction module includes a predetermined resistance, and a correction level is generated by the predetermined resistance; the correction module is configured to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer to generate a digital Correcting a signal, correcting a resistance in the resistance correction array in the RC integrator according to the digital correction signal; the predetermined resistance being the same as a resistance in a resistance correction array in the RC integrator.
  • the Sigma-Delta modulator further includes a DAC and a D flip-flop, an input end of the D flip-flop is electrically connected to an output end of the comparator, and an output end of the D flip-flop is connected to the DAC
  • the input signal of the DAC is fed back to the input end of the RC integrator; wherein the D flip-flop synchronizes the RC integrator with the comparison signal A of the predetermined reference voltage, and the synchronized comparison signal A passes The DAC is then fed back to the input of the RC integrator as part of the input signal of the RC integrator;
  • the number of the DACs is less than or equal to the number of RC integrators, and the output end of one DAC is connected to the input end of at least one RC integrator, and the output signal of the one DAC is used as part of the input signal of the at least one RC integrator
  • An RC integrator corresponding to the output of one DAC at most as part of the input signal of the one RC integrator, and the first stage RC integrator in the RC integrator is connected to the output of one DAC in the DAC, one DAC in the DAC The output is part of the input of the first stage RC integrator.
  • the method further includes a feedforward resistor array, one end of the feedforward resistor array is connected to the output end of the front stage circuit, and the other end is connected to the input end of the rear stage circuit;
  • the front stage circuit includes the first stage RC integrator An input circuit or an RC integrator circuit, the subsequent stage circuit comprising an RC integrator circuit or a circuit receiving the output of the last stage RC integrator, the output signal of the preamplifier circuit being fed forward to the subsequent stage through the feedforward resistor array
  • the input end of the circuit serves as a partial input signal to the subsequent stage circuit, and the feedforward resistor array is controlled by a digital correction signal to select its resistance value.
  • the correction module further includes a current source, a combination logic circuit and a plurality of first pulse switches; the predetermined resistance is grounded at one end, and the other end of the predetermined resistor is connected to the current source, so that the other end of the predetermined resistor is generated
  • the correction level, one end of the first pulse switch is connected between the current source and the predetermined resistor, and the other end of the first pulse switch is connected to a first input end of a comparator in the quantizer,
  • the predetermined reference voltage is input to the second input end of the comparator in the quantizer
  • the predetermined reference voltage is provided by a bias module;
  • the quantizer includes a plurality of comparators, and an output of each comparator is connected to an input end of the combinational logic circuit through one of the first pulse switches, when the one first pulse switch is connected to a signal,
  • the comparison result B of the correction level and the predetermined reference voltage is input to the input end of the combinational logic circuit;
  • An output of the combinational logic circuit is coupled to the resistance correction array, and the logic combination circuit logically transforms the comparison result B to restore a signal sequence, and outputs a digital correction signal having the same number of bits as the comparator.
  • the output of the last stage RC integrator being connected to the first input of the comparator in the quantizer via one of the second pulse switches, when the second pulse switch is connected to the signal
  • the output signal of the last stage RC integrator is output to the first input of the comparator in the quantizer
  • each of the comparators is connected to an input end of the D flip-flop through a second pulse switch, and when the second pulse switch is connected to the signal, the output of the last stage RC integrator is The comparison result A of the predetermined reference voltage is input to the input terminal of the D flip-flop.
  • the resistance correction array comprises a plurality of resistors connected in series, which are respectively a first resistor up to a Nth resistor, and N is an integer; a switch is connected in parallel to each end of the first resistor to the N-1th resistor, the switch The number of the digits is the same as the number of digits of the digital correction signal, and the switch is connected to the output of the logic combination circuit; the resistance of the first resistor to the N-1th resistor is respectively the second resistor The first resistor is connected to the front stage circuit, and the Nth resistor is connected to the second stage circuit;
  • Each of the RC integrators includes two of the resistance correction arrays; one of the resistance correction arrays is connected in series with the non-inverting input of the operational amplifier in the RC integrator; and the other of the resistance correction arrays is connected in series with the inverse of the operational amplifier in the RC integrator Phase input.
  • the feedforward resistor array includes a plurality of resistors connected in series in sequence; respectively, a first resistor to an Nth resistor, and a switch is connected in parallel to both ends of the first resistor to the N-1 resistor, and the number of the switches is The digits of the digital correction signal are the same, and the switch is connected to the input of the logic combination circuit; the resistance of the first resistor to the N-1th resistor is twice that of the previous resistor; One end of a resistor is connected to the front stage circuit, and one end of the Nth resistor is connected to the second stage circuit.
  • the first pulse switch is controlled by a first clock signal
  • the second pulse switch is controlled by a second clock signal
  • the first clock signal is at a high level, the corresponding first pulse switch is turned on, the second clock signal is at a low level, and the corresponding second pulse switch is turned off;
  • the first clock signal After the first clock signal is at a high level for a preset number of clock cycles, the first clock signal is at a low level, the corresponding first pulse switch is turned off, and the second clock signal is at a high level. The corresponding second pulse switches are all turned on.
  • An embodiment of the present invention further provides a Sigma-Delta analog-to-digital converter, including the
  • the present invention has the following advantages:
  • the Sigma-Delta modulator includes: a quantizer, a correction module, and an RC integrator; the Sigma-Delta modulator provided by the embodiment of the present invention adds a correction module based on the existing Sigma-Delta modulator, and the correction module utilizes The comparator in the existing quantizer performs the correction of the resistance correction array in the RC integrator. Since the predetermined resistance that produces the positive level is the same as the type of the resistor in the positive resistor array, the process variation of the predetermined resistance (resistance process angular deviation) can accurately characterize the positive resistance in the positive array. The resistance of the resistance changes. Similarly, the positive level on the predetermined resistance can also characterize the change in resistance of the resistor in the resistance correction array.
  • the present invention does not require the addition of too many additional components, and therefore does not require the addition of more additional chip area, nor does it increase power consumption and cost.
  • FIG. 1 is a schematic diagram of a first embodiment of a Sigma-Delta modulator provided by the present invention
  • Embodiment 2 is a schematic diagram of Embodiment 2 of a Sigma-Delta modulator provided by the present invention.
  • FIG. 3 is a schematic diagram of Embodiment 3 of a Sigma-Delta modulator provided by the present invention.
  • 4 is a schematic diagram of a resistance correction array/feedforward resistor array provided by the present invention.
  • Figure 5 is a schematic diagram of a correction module provided by the present invention.
  • FIG. 6 is a timing diagram of a first clock signal and a second clock signal provided by the present invention.
  • FIG. 7 is a schematic diagram of Embodiment 4 of a Sigma-Delta modulator provided by the present invention.
  • FIG. 1 the figure is a schematic diagram of a first embodiment of a Sigma-Delta modulator provided by the present invention.
  • An embodiment of the present invention provides a sigma-delta modulator, including: a quantizer 300, a correction module 400, and an RC integrator I;
  • the correction module 400 includes a predetermined resistance, and a correction level is generated by the predetermined resistance; the correction module 400 is configured to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer 300, Thereby generating a digital correction signal for correcting the resistance in the resistance correction array in the RC integrator I according to the digital correction signal; the predetermined resistance and the resistance in the RC integrator I correcting the resistance in the array The same type.
  • the Sigma-Delta modulator provided by the embodiment of the present invention adds a correction module 400 based on the existing Sigma-Delta modulator, and the correction module 400 completes the resistance in the RC integrator I by using the comparator in the existing quantizer 300. Correct the correction of the array. Since the predetermined resistance that produces the correction level is the same as the type of the resistance in the modified resistance correction array, the process variation of the predetermined resistance (resistance process angular deviation) can accurately characterize the resistance of the resistor in the modified resistance correction array. Variety. Similarly, the correction level on the predetermined resistance can also characterize the resistance change of the resistor in the resistance correction array.
  • the present invention does not require the addition of too many additional components, and therefore does not require an increase in additional chip area, nor does it increase power consumption and cost.
  • FIG. 2 the figure is a schematic diagram of Embodiment 2 of a Sigma-Delta modulator provided by the present invention.
  • the sigma-delta modulator provided in this embodiment further includes a DAC and a D flip-flop.
  • the input end of the D flip-flop is electrically connected to the output end of the comparator, and the output end of the D flip-flop is connected to the DAC.
  • the output signal of the DAC is fed back to the input end of the RC integrator; wherein the D flip-flop synchronizes the RC integrator with the comparison signal A of the predetermined reference voltage, The over-synchronized comparison signal A is fed back to the input of the RC integrator as part of the input signal of the RC integrator through the DAC, and the RC integrator part input signal is added to the other signals at the input of the RC integrator to form The input of the RC integrator;
  • the number of the DACs is less than or equal to the number of RC integrators, and the output end of one DAC is connected to the input end of at least one RC integrator, and the output signal of the one DAC is used as part of the input signal of the at least one RC integrator
  • An RC integrator corresponds to the output of one DAC at most as part of the input signal of the one RC integrator, and the first stage RC integrator in the RC integrator is connected to the output of one DAC in the DAC, one DAC in the DAC The output is part of the input of the first stage RC integrator.
  • the Sigma-Delta modulator may include a multi-stage RC integrator, and may correspondingly include a plurality of DACs and an addition module, and the addition module adds the RC integrator part input signal to other signals at the input of the RC integrator to form The input of the RC integrator, it can be understood that, in principle, only one RC integrator, one DAC and one addition module can be implemented; but in practical applications, at least a two-stage RC integrator is generally included.
  • the Sigma-Delta modulator shown in Figure 2 includes only one RC integrator and one DAC, one adder module as an example.
  • the Sigma-Delta modulator provided by the embodiment of the present invention includes: a quantizer 300, a correction module 400, a D flip-flop 500, at least one adding module A, at least one DAC 600 and at least one RC integrator I;
  • the adding module A is configured to superimpose an analog signal input by the front stage circuit and an analog signal fed back by the DAC 600;
  • the RC integrator I is configured to integrate an analog signal output by the adding module A, and the RC integrator 1 includes a resistance correction array;
  • the quantizer 300 is configured to convert an analog signal obtained by integrating the RC integrator I into a digital signal; the quantizer 300 includes a comparator for using a correction level generated on a predetermined resistance and a predetermined reference voltage Compare and produce comparison results;
  • the D flip-flop 500 is configured to synchronize a digital signal output by the quantizer with a clock while canceling a delay of the quantizer to the digital signal;
  • the DAC 600 is configured to convert the digital signal output by the D flip-flop 500 into an analog signal and feed back to the adding module A;
  • the correction module 400 is configured to generate a digital correction signal according to the comparison result to correct a resistance in the resistance correction array in the RC integrator 1; the predetermined resistance and a resistance correction in the RC integrator I
  • the types of resistors in the array are the same.
  • the RC integrator includes a resistance correction array, a capacitor and an operational amplifier; wherein the resistor and the resistor in the resistance correction array complete the integration function; the forward input of the operational amplifier is connected to the resistance correction array, and the operational amplifier is inverted. The input is connected to the resistance correction array; the operational amplifier is connected between the non-inverting input and the negative output; the operational amplifier is connected between the inverting input and the positive output.
  • an RC integrator in the Sigma-Delta modulator can also work, but at least two RC integrators are used in general applications. It can be understood that, in general application, the number of RC integrators can be an integer greater than or equal to two.
  • the following is an example of a Sigma-Delta modulator including three RC integrators.
  • the figure is a schematic diagram of Embodiment 3 of a Sigma-Delta modulator provided by the present invention.
  • the number of the DACs is less than or equal to the number of RC integrators.
  • the DAC is used to convert the digital signals output by the D flip-flops into analog signals.
  • the addition module fed back to the first stage RC integrator can also feed back to the addition module before the other stage RC integrator;
  • one of the DACs is used to convert the digital signal output by the D flip-flop into an analog signal before the analog signal is fed back to the first stage RC integrator, and the remaining DACs are used to turn D
  • the digital signal output by the flip-flop is converted to the summing module before the analog signal is fed back to the corresponding RC integrator.
  • the RC integrator closest to the input of the modulator is the first stage RC integrator.
  • one DAC can be fed back to the first stage RC integrator input; there can also be two DAC feedback signals, one feedback to the first stage RC integrator, and one feedback to the second stage RC integral. Or a third stage RC integrator.
  • the input of the first-stage RC integrator must have a DAC feedback signal, but the subsequent stages of the RC integrator can have a DAC feedback signal.
  • the number of DACs is not necessarily the same as the number of RC integrators.
  • the DAC in the Sigma-Delta modulator can be an RC integrator feedback. Analog signals can also be used to feed back analog signals for some or all of the RC integrators.
  • the Sigma-Delta modulator includes three RC integrators, one adder module, and one DAC; the DAC only feeds back the analog signal for the first stage RC integrator.
  • the Sigma-Delta modulator includes three RC integrators, three addition modules, and one DAC; the DAC feeds back analog signals for all RC integrators.
  • the Sigma-Delta modulator includes three RC integrators, two summing modules, and two DACs; one of the DACs is the first stage RC integrator; the other DAC is the third stage RC integrator feedback simulation. signal.
  • the Sigma-Delta modulator includes three RC integrators, three summing modules, and three DACs; each DAC feeds back an analog signal for the corresponding RC integrator.
  • the RC integrator needs to have an adder module before.
  • the adder module is usually a resistor connected to the input of the operational amplifier to perform the add function.
  • the RC integrator in the Sigma-Delta modulator is three, which are a first-stage RC integrator II, a second-stage RC integrator 12, and a third-stage RC integrator 13;
  • the addition module is three, which are a first-stage addition module A1, a second-stage addition module A2, and a third-stage addition module A3;
  • the DAC 600 is one;
  • the input end of the first stage adding module A1 is connected to the externally input analog signal Vin and the output signal of the DAC 600;
  • An output end of the first stage adding module A1 is connected to an input end of the first stage RC integrator II;
  • the output end of the first stage RC integrator II is connected to the input end of the second stage adding module A2, and the input end of the second stage adding module A2 is also connected to the output end of the DAC 600;
  • An output end of the second stage adding module A2 is connected to an input end of the second stage RC integrator 12;
  • the output end of the second stage RC integrator 12 is connected to the input end of the third stage adding module A3, and the input end of the third stage adding module A3 is also connected to the output end of the DAC 600;
  • An output end of the third stage adding module A3 is connected to an input end of the third stage RC integrator 13;
  • the output of the third stage RC integrator 13 is connected to the input end of the quantizer 300; the output of the quantizer 300 is connected to the D flip-flop 500; An output end of the D flip-flop 500 is connected to an input end of the DAC 600;
  • the N-bit digital correction signal output by the correction module 400 is supplied to the resistance correction array in each RC integrator, where N is an integer.
  • the resistance is a resistance correction array
  • the resistance correction array may be a series array or a parallel array, or may be used. Series and parallel arrays.
  • the resistance correction array includes a plurality of resistors connected in series, which are respectively a first resistor up to an Nth resistor, and a switch is connected in parallel between the two ends of the first resistor to the N-1th resistor, the number of the switches and the digital correction signal The number of bits is the same, the switch is connected to the output of the logic combination circuit; the resistance of the first resistor to the N-1th resistor is twice the value of the previous resistor; one end of the first resistor Accessing the pre-stage circuit, one end of the Nth resistor is connected to the subsequent stage circuit;
  • the following is an example of the resistance correction array by taking N as an integer 5 and corresponding to a four-digit correction signal.
  • FIG. 4 the figure is a schematic diagram of a resistance correction array provided by the present invention.
  • the resistance correction array includes a first resistor R, a second resistor 2R, a third resistor 4R, a fourth resistor 8R and a fifth resistor R0 connected in series;
  • a switch is connected in parallel between the two ends of the first resistor 1, the second resistor 2R, the third resistor 4R and the fourth resistor 8R;
  • the first resistor R-terminal a is one end not connected to the second resistor 2R; the other end b of the fifth resistor R0 is one end not connected to the fourth resistor 4R;
  • Each of the RC integrators includes two of the resistance correction arrays; one of the resistance correction arrays is connected in series with the non-inverting input of the operational amplifier in the RC integrator; and the other of the resistance correction arrays is connected in series with the operational amplifier of the RC integrator Inverting input.
  • the resistance values of the fourth resistor 8R, the third resistor 4R, and the second resistor 2R are respectively eight, four, and two times the resistance of the first resistor R.
  • the reason why the multiple relationship between the four resistors is selected in this way is that the resistance of the resistance correction array can be continuously jumped from 1 to 15 times the first resistance R.
  • the resistance of the first resistor R is lk.
  • the resistance of the external resistance array of the resistance correction array can obtain the resistance value of each integer multiple of lk from 1 to 15 by changing the state of the switch, that is, lk, 2k, 3k, 4k, 5k, 6k, 7k, 8k, 9k, 10k, llk, 12k, 13k, 14k, 15k.
  • the switch in the resistance correction array is controlled by the four-digit digital correction signal output from the correction module.
  • the correction module is described below.
  • the number of bits of the digital correction signal may be an integer greater than or equal to 1, but the number of digits of the digital correction signal is the same as the number of comparators in the quantizer.
  • the correction module further includes a current source, a combination logic circuit and a first pulse switch; the predetermined resistance is grounded at one end, and the other end of the predetermined resistor is connected to the current source, so that the other end of the predetermined resistor generates the correction level Connecting one end of a first pulse switch between the current source and the predetermined resistor, and connecting the other end of the first pulse switch to a first input end of a comparator in the quantizer, when the first pulse switch When the signal is connected, the correction level is input to the first input end of the comparator through the first pulse switch; the predetermined reference voltage is input to the second input end of the comparator in the quantizer, and the predetermined reference voltage is Provided by the bias module;
  • the quantizer includes a plurality of comparators, and an output end of each comparator is connected to an input end of the combination logic circuit through a first pulse switch, and the correction current is when the first pulse switch is connected to a signal Comparing the result of the comparison with the predetermined reference voltage to the input terminal of the combinational logic circuit; the output of the combinational logic circuit is coupled to the resistance correction array, and the logic combination circuit logically transforms the comparison result B In the order of the restored signal, a digital correction signal having the same number of bits as the comparator is output.
  • correction module The specific implementation of the correction module will be described below with reference to the embodiments.
  • FIG. 5 the figure is a schematic diagram of a modification module provided by the present invention.
  • the correction module includes a predetermined resistor Rx, a combinational logic circuit 401, five first pulse switches, and five second pulse switches; the first pulse switch is controlled by a first clock signal CLK1, and the second pulse switch is controlled by a second clock Signal CLK2 control;
  • a correction level Vx generated on the predetermined resistor Rx is coupled to a first input terminal of four comparators B of the quantizer via one of the first pulse switches;
  • the summed signal Vsum is coupled to the first input of the four comparators B of the quantizer via a second pulse switch;
  • Vref1, Vref2, Vref3, and Vref4 are respectively connected to the second input terminals of the four comparators B in the quantizer; the four predetermined reference voltages are generated by the bias module;
  • the output ends of the four comparators B are respectively connected to the input ends of the combinational logic circuit 401 through four first pulse switches; meanwhile, the output ends of the four comparators B respectively pass through the four said a two-pulse switch is connected to the input end of the D flip-flop 500;
  • the combinational logic circuit 401 outputs four-bit switch signals D ⁇ 3>, D ⁇ 2>, D ⁇ 1>, and D ⁇ 0>, and the four-bit switch signal is the digital correction signal, and the digital correction signal is used.
  • combinational logic circuit 401 is composed of logic gates.
  • the function of the combination logic circuit 401 is to logically output the input four-digit digital signals into required four-digit digital correction signals, for example, input combination logic.
  • the four-bit digital signal of circuit 401 is 1100, but the required four-bit digital correction signal is 1010, then combinational logic circuit 401 requires an internal logic gate circuit to change 1100 to 1010 for output.
  • the Sigma-Delta modulator may include a feedforward resistor array or may not include a feedforward resistor array.
  • a feedforward resistor array is taken as an example for introduction.
  • the pre-stage circuit includes a circuit or an RC integrator circuit for providing input to the first-stage RC integrator,
  • the latter stage circuit includes an RC integrator circuit or a circuit that receives the output of the last stage RC integrator, and an output signal of the preamplifier circuit is fed forward through the feedforward resistor array to an input terminal of the subsequent stage circuit as the latter stage circuit Part of the input signal, the feedforward resistor array is controlled by a digital correction signal to select its resistance value.
  • the structure of the feedforward resistor array is identical to that of the resistor correction array.
  • the feedforward resistor array includes a plurality of resistors connected in series in sequence; respectively, a first resistor to an Nth resistor, and a switch is connected in parallel to each of the two ends of the first resistor to the N-1th resistor, the number of the switches and the number The number of digits of the correction signal is the same, the switch is connected to the input of the logic combination circuit; the resistance of the first resistor to the N-1th resistor is twice the value of the previous resistor; The resistor is connected to the pre-stage circuit, and the N-th resistor is connected to the subsequent-stage circuit, and the front-rear stage circuit distinguishes the total flow direction of the signal in the circuit, the circuit that passes the signal rate first is the pre-stage circuit, and the circuit that passes the signal is the latter stage circuit .
  • the feedforward resistor array includes a sixth resistor, a seventh resistor, and a second serially connected in series. Eight resistance, ninth resistance, and tenth resistance;
  • the two ends of the sixth resistor, the seventh resistor, the eighth resistor and the ninth resistor are respectively connected in parallel with one of the switches;
  • the resistance values of the ninth resistor, the eighth resistor, and the seventh resistor are eight, four, and two times the resistance of the sixth resistor, respectively.
  • the positions of the sixth resistor, the seventh resistor, the eighth resistor, the ninth resistor, and the tenth resistor in the feedforward resistor and the connection relationship therebetween are the first resistor in the resistance correction array. 1.
  • the second resistor 2R, the third resistor 4R, the fourth resistor 8R, and the fifth resistor R0 are respectively the same, and will not be described in detail herein.
  • the modulator includes a three-stage RC integrator, the embodiment shown in FIG.
  • the positive input of the first stage RC integrator (the output of the front stage circuit of the first stage RC integrator) and the negative output of the third stage RC integrator (the input of the last stage RC integrator post stage circuit) Connecting a feedforward resistor array between the terminals; connecting the feedforward resistor array between the negative input terminal of the first stage RC integrator and the positive output terminal of the third stage RC integrator;
  • Embodiments of the present invention only show feedforward resistor array connections that are fed forward to the output of the last stage RC integrator (the input of the last stage RC integrator post stage circuit), as will be understood by those skilled in the art,
  • the feedforward resistor can also feed forward the output signal of the pre-stage circuit to the input of any stage RC integrator, but the input of the pre-stage circuit output signal to the input of the post-stage circuit is in phase.
  • the first clock signal CLK1 is at a high level, the corresponding first pulse switch is turned on, the second clock signal CLK2 is at a low level, and the corresponding second pulse switch is turned off;
  • the four-position switch signal is used as the input of the resistor correction array in the RC integrator, and is connected to the array through the control resistor.
  • the resistance value completes the correction of the resistance array, that is, changes the resistance value presented by the resistance correction array shown in FIG.
  • the first clock signal CLK1 is at a high level for a predetermined number of clock cycles, that is, after the correction process ends, the first clock signal CLK1 is at a low level, and the corresponding first pulse switch is turned off.
  • the second clock signal CLK2 is at a high level, and the corresponding second pulse switches are all turned on.
  • Vsum in the modulator is used as the input of the comparator, and the output of the comparator is connected to the input of the D flip-flop, and the modulator starts to work normally.
  • the figure is a timing diagram of a first clock signal and a second clock signal provided by the present invention.
  • the first clock signal CLK1 is at a high level
  • the second clock signal CLK2 is at a low level
  • the figure shows that the three clock cycles CLK1 in the T0-T3 period are at a high level. That is, the resistance of the RC integrator is corrected in the first three clock cycles.
  • FIG. 7 is a schematic diagram of Embodiment 4 of a Sigma-Delta modulator provided by the present invention.
  • each RC integrator corresponds to a feedforward resistor array, and the feedforward resistor array is used to feed forward the input signals of the corresponding RC integrator to the last stage RC integrator.
  • the output of the last stage RC integrator is connected to a summation module for summing the output signal of the last stage RC integrator and the signals fed forward by all feedforward resistor arrays, and summing the summed The signal is output to the quantizer.
  • the feedforward resistor array of the first stage RC integrator is R4
  • the feedforward resistor array of the second stage RC integrator is R5
  • the feedforward resistor array of the third stage RC integrator is R6.
  • the modulator also includes a summation module 700 due to the presence of a feedforward resistor array.
  • the modulator provided in this embodiment includes a DAC 600 for converting the digital signal outputted by the D flip-flop into an analog signal and feeding back to the adding module before the first stage RC integrator.
  • R1 ⁇ R3 in the RC integrator is a resistive positive array, and its schematic diagram is shown in Fig. 4.
  • a specific implementation of the resistance correction module for digitally correcting the resistance correction array is shown in FIG. 5.
  • the resistor Rx and the resistor correction array R1 ⁇ R3 in the integrator are composed of the same type of resistor, so the chip system During the manufacturing process, the process deviation of Rx can accurately characterize the resistance value change of the resistance correction array R1 ⁇ R3 in the integrator.
  • the correction level Vx generated by a steady current source Iref flowing through the predetermined resistance Rx can also characterize the resistance value change of the resistance correction arrays R1 to R3.
  • the quantizer is an indispensable module.
  • the quantizer consists of one or more comparators.
  • the Sigma-Delta modulator provided by the present invention reduces the performance of the Sigma-Delta modulator due to changes in the resistance process angle, and the resistance correction utilizes the comparator of the Sigma-Delta modulator itself without adding additional chip area.
  • the resistance correction module of the present invention performs the adjustment only in a few cycles of the start of the operation, and then processes the off state until it does not consume any additional power and area.
  • the resistance correction module is flexible and the resulting corrected number of digits can be flexibly designed based on the trade-off between adjustment accuracy and area.

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Abstract

一种Sigma-Delta调制器及模数转换器；Sigma-Delta调制器包括量化器、修正模块和RC积分器；其中，所述修正模块包括预定电阻，通过所述预定电阻产生修正电平；所述修正模块，用于利用所述量化器中的比较器将所述修正电平与预定参考电压进行比较，从而产生数字修正信号，根据所述数字修正信号对所述RC积分器中的电阻修正阵列中的电阻进行修正；所述预定电阻与所述RC积分器中的电阻修正阵列中的电阻的类型相同；该Sigma-Delta调制器及模数转换器能够修正RC积分器中的电阻偏差。

Description

一种 Sigma-Delta调制器及 «转换器
本申请要求于 2012 年 09 月 03 日提交中国专利局、 申请号为 201210322266.9、 发明名称为"一种 Sigma-Delta调制器及模数转换器"的中国 专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及模数转换器技术领域， 特别涉及一种 Sigma-Delta调制器及模 数转换器。
背景技术
近年来 Sigma-Delta模数转换器由于高精度、 高集成度、 低功耗等优点受 到越来越多的关注。 Sigma-Delta模数转换器根据其中积分器的实现方式分为 连续时间与离散时间两种类型。 与离散时间 Sigma-Delta模数转换器相比， 连 续时间 Sigma-Delta模数转换器具有更低的功耗， 更快的速度以及固有的抗混 叠优势， 这些优点可以有效地增加电池寿命， 降低系统的复杂程度， 对于便携 式无线设备是非常重要的。 因此， 近年来连续时间 Sigma-Delta模数转换器得 到越来越多的关注。 Sigma-Delta调制器属于 Sigma-Delta模数转换器中的一部 分。 积分器是 Sigma-Delta 调制器中的最基本、 最核心的模块， 目前在 Sigma-Delta调制器中应用比较广泛的积分器主要有两种， RC 积分器以及 Gm-C积分器。 RC积分器相比于 Gm-C积分器的主要优势是具有较高的线性 度及较大的输入信号幅度。 另外， RC积分器的虚地特性也能使反馈 DAC的 输出连接到运放的虚地输入端， 从而增加反馈 DAC的线性度。 因此 RC积分 器更适用于要求线性度高、 输入信号摆幅大的应用场合。
由于电阻随着工艺的偏差较大， 例如 25% , 因此 RC积分器的积分系数 1/RC也会随着工艺的偏差而偏差。积分系数的偏差有可能导致 Sigma-Delta调 制器整体性能的下降， 甚至有可能导致整体电路失去调制功能或产生振荡。 因 此在设计过程中， 要对电阻和（或）电容进行修正， 以避免工艺偏差对调制器 整体性能的影响。
但是， 现有技术对 RC积分器中电阻的修正主要是增加新的器件来完成， 这样将增加环路延迟， 加大设计难度， 同时也会增加额外的芯片面积、 功耗和 成本。 发明内容 本发明要解决的技术问题是提供一种 Sigma-Delta调制器， 设计筒单、 没 有增加环路延迟， 同时不需要增加额外的芯片面积、 功耗和成本。
本发明实施例提供一种 Sigma-Delta调制器， 包括： 量化器、 修正模块和
RC积分器； 其中，
所述修正模块包括预定电阻， 通过所述预定电阻产生修正电平； 所述修正模块，用于利用所述量化器中的比较器将所述修正电平与预定参 考电压进行比较， 从而产生数字修正信号， 根据所述数字修正信号对所述 RC 积分器中的电阻修正阵列中的电阻进行修正； 所述预定电阻与所述 RC积分器 中的电阻修正阵列中的电阻的类型相同。
优选地， 所述 Sigma-Delta调制器还包括 DAC和 D触发器， 所述 D触发 器的输入端与所述比较器的输出端电性相连， 所述 D触发器的输出端连接所 述 DAC的输入端， 所述 DAC的输出信号反馈至 RC积分器的输入端； 其中， 所述 D触发器将 RC积分器与预定参考电压的比较信号 A进行同步， 经 过同步的所述比较信号 A通过所述 DAC后作为 RC积分器的部分输入信号反 馈至 RC积分器的输入端；
所述 DAC的个数小于或等于 RC积分器的个数，一个 DAC的输出端连接 至少一个 RC积分器的输入端， 所述一个 DAC的输出信号作为所述至少一个 RC积分器的部分输入信号；一个 RC积分器最多对应一个 DAC的输出作为所 述一个 RC积分器的部分输入信号， 而 RC积分器中的第一级 RC积分器连接 DAC中一个 DAC的输出端， 所述 DAC中一个 DAC的输出作为所述第一级 RC积分器的部分输入。
优选地，还包括前馈电阻阵列， 前馈电阻阵列的一端接至前级电路的输出 端， 另一端接至后级电路的输入端； 所述前级电路包括为第一级 RC积分器提 供输入的电路或 RC积分器电路， 所述后级电路包括 RC积分器电路或接收最 后一级 RC积分器输出的电路，前级电路的输出信号通过所述前馈电阻阵列后 前馈至后级电路的输入端作为所述后级电路的部分输入信号，所述前馈电阻阵 列由数字修正信号控制选取其电阻值。 优选地，所述修正模块还包括电流源、组合逻辑电路和多个第一脉沖开关； 所述预定电阻一端接地， 所述预定电阻另一端与电流源连接，从而使所述预定 电阻另一端产生所述修正电平，所述电流源与所述预定电阻之间连接一个所述 第一脉沖开关的一端，所述第一脉沖开关的另一端连接至量化器中比较器的第 一输入端， 当所述第一脉沖开关连通信号时， 所述修正电平通过所述第一脉沖 开关输至所述比较器的第一输入端；预定参考电压输至量化器中比较器的第二 输入端， 所述预定参考电压由偏置模块提供；
所述量化器包括多个比较器，每个比较器的输出端均通过一个所述第一脉 沖开关连接所述组合逻辑电路的输入端， 当所述一个第一脉沖开关连通信号 时， 所述修正电平与预定参考电压的比较结果 B输至所述组合逻辑电路的输 入端；
所述组合逻辑电路的输出端连接至所述电阻修正阵列 ,所述逻辑组合电路 对所述比较结果 B 进行逻辑变换以还原信号顺序， 输出与比较器位数相同的 数字修正信号。
优选地， 还包括第二脉沖开关， 最后一级 RC积分器的输出端通过一个所 述第二脉沖开关连接至量化器中比较器的第一输入端，当所述第二脉沖开关连 通信号时，所述最后一级 RC积分器的输出信号输至所述量化器中比较器的第 一输入端，
每个所述比较器的输出端均通过一个所述第二脉沖开关连接至 D触发器 的输入端， 当所述一个第二脉沖开关连通信号时， 所述最后一级 RC积分器的 输出与预定参考电压的比较结果 A输至所述 D触发器的输入端。
优选地， 所述电阻修正阵列包括依次串联的多个电阻， 分别为第一电阻直 至第 N电阻， N为整数； 第一电阻至第 N-1电阻的两端分别并联一个开关， 所述开关的数量与所述数字修正信号的位数相同，所述开关与所述逻辑组合电 路的输出——对应相连；所述第一电阻至第 N-1电阻的阻值分别是前一电阻的 二倍； 所述第一电阻接入前级电路， 所述第 N电阻接入后级电路；
每个所述 RC积分器包括两个所述电阻修正阵列； 其中一个电阻修正阵列 串联于 RC 积分器中运算放大器的正相输入端； 另一个电阻修正阵列串联于 RC积分器中运算放大器的反相输入端。 优选地， 所述前馈电阻阵列包括依次串联的多个电阻； 分别为第一电阻直 至第 N电阻， 第一电阻至第 N-1 电阻的两端分别并联一个开关， 所述开关的 数量与所述数字修正信号的位数相同，所述开关与逻辑组合电路的输入——对 应相连； 所述第一电阻至第 N-1电阻的阻值分别是前一电阻的二倍； 所述第一 电阻的一端接入前级电路， 所述第 N电阻的一端接入后级电路。
优选地， 所述第一脉沖开关由第一时钟信号控制， 第二脉沖开关由第二时 钟信号控制；
当调制器开始工作时， 第一时钟信号为高电平，对应的第一脉沖开关均导 通， 第二时钟信号为低电平， 对应的第二脉沖开关均关断；
当第一时钟信号为高电平持续了预设个数的时钟周期后，所述第一时钟信 号为低电平， 对应的第一脉沖开关均关断， 第二时钟信号为高电平， 对应的第 二脉沖开关均导通。
本发明实施例还提供一种 Sigma-Delta 模数转换器， 包括所述的
Sigma-Delta调制器。
与现有技术相比， 本发明具有以下优点：
该 Sigma-Delta调制器， 包括： 量化器、 修正模块和 RC积分器； 本发明 实施例提供的 Sigma-Delta调制器在现有 Sigma-Delta调制器的基础上，增加了 修正模块，修正模块利用现有量化器中的比较器完成对 RC积分器中电阻修正 阵列的爹正。由于产生爹正电平的预定电阻与被爹正的电阻爹正阵列中的电阻 的类型相同， 因此， 预定电阻的工艺偏差（电阻工艺角偏差）可以准确表征被 爹正的电阻爹正阵列中的电阻的阻值变化。 同理，预定电阻上的爹正电平也可 以表征电阻修正阵列中的电阻的阻值变化。 本发明不需要添加太多的额外器 件， 因此也不需要增加较多的额外芯片面积， 也不增加功耗和成本。
附图说明 图 1是本发明提供的 Sigma-Delta调制器实施例一示意图
图 2是本发明提供的 Sigma-Delta调制器实施例二示意图
图 3是本发明提供的 Sigma-Delta调制器实施例三示意图 图 4是本发明提供的电阻修正阵列 /前馈电阻阵列示意图；
图 5是本发明提供的修正模块示意图；
图 6是本发明提供的第一时钟信号和第二时钟信号时序图；
图 7是本发明提供的 Sigma-Delta调制器实施例四示意图。
具体实施方式 为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
参见图 1 , 该图为本发明提供的 Sigma-Delta调制器实施例一示意图。 本发明实施例提供一种 Sigma-Delta调制器， 包括： 量化器 300、 修正模 块 400和 RC积分器 I； 其中，
所述修正模块 400包括预定电阻， 通过所述预定电阻产生修正电平； 所述修正模块 400, 用于利用所述量化器 300中的比较器将所述修正电平 与预定参考电压进行比较，从而产生数字修正信号，根据所述数字修正信号对 所述 RC积分器 I中的电阻修正阵列中的电阻进行修正； 所述预定电阻与所述 RC积分器 I中的电阻修正阵列中的电阻的类型相同。
本发明实施例提供的 Sigma-Delta调制器在现有 Sigma-Delta调制器的基础 上， 增加了修正模块 400, 修正模块 400利用现有量化器 300中的比较器完成 对 RC积分器 I中电阻修正阵列的修正。 由于产生修正电平的预定电阻与被修 正的电阻修正阵列中的电阻的类型相同， 因此， 预定电阻的工艺偏差（电阻工 艺角偏差）可以准确表征被修正的电阻修正阵列中的电阻的阻值变化。 同理， 预定电阻上的修正电平也可以表征电阻修正阵列中的电阻的阻值变化。本发明 不需要添加太多的额外器件， 因此也不需要增加较多的额外芯片面积，也不增 力口功耗和成本。
参见图 2, 该图为本发明提供的 Sigma-Delta调制器实施例二示意图。 本实施例提供的 Sigma-Delta调制器还包括 DAC和 D触发器， 所述 D触 发器的输入端与所述比较器的输出端电性相连， 所述 D触发器的输出端连接 所述 DAC的输入端，所述 DAC的输出信号反馈至 RC积分器的输入端；其中， 所述 D触发器将 RC积分器与预定参考电压的比较信号 A进行同步， 经 过同步的所述比较信号 A通过所述 DAC后作为 RC积分器的部分输入信号反 馈至 RC积分器的输入端， 所述 RC积分器部分输入信号与该 RC积分器输入 端的其他信号相加形成该 RC积分器的输入；
所述 DAC的个数小于或等于 RC积分器的个数， 一个 DAC的输出端连 接至少一个 RC积分器的输入端， 所述一个 DAC的输出信号作为所述至少一 个 RC积分器的部分输入信号； 一个 RC积分器最多对应一个 DAC的输出作 为所述一个 RC积分器的部分输入信号， 而 RC积分器中的第一级 RC积分器 连接 DAC中一个 DAC的输出端， 所述 DAC中一个 DAC的输出作为所述第 一级 RC积分器的部分输入。
需要说明的是， Sigma-Delta调制器可以包括多级 RC积分器， 相应地可 以包括多个 DAC和加法模块， 加法模块将 RC积分器部分输入信号与该 RC 积分器输入端的其他信号相加形成该 RC积分器的输入， 可以理解的是， 从原 理上来讲， 只包括一个 RC积分器、 一个 DAC和一个加法模块也可以实现； 但是实际应用中， 一般至少包括两级 RC积分器。 图 2所示的 Sigma-Delta调 制器中仅包括一个 RC积分器和一个 DAC、 一个加法模块为例。
本发明实施例提供的 Sigma-Delta调制器， 包括： 量化器 300、 修正模块 400、 D触发器 500、 至少一个加法模块 A、 至少一个 DAC600和至少一个 RC 积分器 I；
所述加法模块 A,用于将前级电路输入的模拟信号与所述 DAC600反馈的 模拟信号叠加；
所述 RC积分器 I,用于将加法模块 A输出的模拟信号进行积分，所述 RC 积分器 I包括电阻修正阵列；
所述量化器 300, 用于将所述 RC积分器 I积分得到的模拟信号转换为数 字信号； 所述量化器 300中包括比较器， 用于将预定电阻上产生的修正电平与 预定参考电压进行比较， 产生比较结果；
所述 D触发器 500, 用于将量化器输出的数字信号与时钟同步， 同时抵消 量化器对数字信号的延迟；
所述 DAC600,用于将所述 D触发器 500输出的数字信号转换为模拟信号 反馈到所述加法模块 A; 所述修正模块 400, 用于根据所述比较结果产生数字修正信号对所述 RC 积分器 I中的电阻修正阵列中的电阻进行修正； 所述预定电阻与所述 RC积分 器 I中的电阻修正阵列中的电阻的类型相同。
需要说明的是， RC积分器包括电阻修正阵列、 电容和运算放大器； 其中， 电容和电阻修正阵列中的电阻完成积分的功能；运算放大器的正向输入端连接 电阻修正阵列，运算放大器的反相输入端连接电阻修正阵列；运算放大器的正 相输入端和负输出端之间连接电容；运算放大器的反相输入端和正输出端之间 连接电容。
需要说明的是，从工作原理上来说， Sigma-Delta调制器中一个 RC积分器 也可以工作， 但是一般应用时均最少使用两个 RC积分器。 可以理解的是， 一 般应用时， RC积分器的数量可以为大于或等于 2的整数。
下面以 Sigma-Delta调制器中包括三个 RC积分器为例进行介绍。
参见图 3, 该图为本发明提供的 Sigma-Delta调制器实施例三示意图。 需要说明的是， 所述 DAC的个数小于或等于 RC积分器的个数， 当所述 DAC的个数为一时， 所述 DAC用于将所述 D触发器输出的数字信号转换为 模拟信号反馈到第一级 RC 积分器前的加法模块， 还可以同时反馈到其他级 RC积分器前的加法模块；
当所述 DAC的个数大于一时， 其中一个 DAC用于将所述 D触发器输出 的数字信号转换为模拟信号反馈到第一级 RC积分器前的所述加法模块，其余 DAC用于将 D触发器输出的数字信号转换为模拟信号反馈到对应的 RC积分 器之前的所述加法模块。
需要说明的是， 距离调制器的输入端最近的 RC积分器为所述第一级 RC 积分器。
比如有三个 RC积分器， 可以有 1个 DAC反馈到第一级 RC积分器输入 端； 也可以有两个 DAC反馈信号， 一个反馈到第一级 RC积分器， 一个反馈 到第二级 RC积分器或第三级 RC积分器。 筒单来说， 第一级 RC积分器的输 入端一定有 DAC反馈信号，但是后面几级 RC积分器有没有 DAC反馈信号都 可以， DAC的个数与 RC积分器的个数不一定相同。
需要说明的是， Sigma-Delta调制器中的 DAC可以为一个 RC积分器反馈 模拟信号， 也可以为部分或所有 RC积分器反馈模拟信号。 例如， Sigma-Delta 调制器中包括三个 RC积分器， 一个加法模块， 一个 DAC; DAC只为第一级 RC积分器反馈模拟信号。 可以理解的是， 例如， Sigma-Delta调制器中包括三 个 RC积分器， 三个加法模块， 一个 DAC; DAC为所有 RC积分器反馈模拟 信号。 同理， 例如， Sigma-Delta调制器中包括三个 RC积分器， 两个加法模 块， 两个 DAC; 其中一个 DAC为第一级 RC积分器； 另一个 DAC为第三级 RC积分器反馈模拟信号。 可以理解的是， 例如， Sigma-Delta调制器中包括三 个 RC积分器， 三个加法模块， 三个 DAC; 每个 DAC为对应的 RC积分器反 馈模拟信号。 当然， 只要 DAC反馈模拟信号给对应的 RC积分器， 则 RC积 分器之前就需要有加法模块，加法模块通常为一个电阻接入运算放大器的输入 端， 以执行加法功能。
图 3所示实施例， Sigma-Delta调制器中所述 RC积分器为三个， 分别为 第一级 RC积分器 II、第二级 RC积分器 12和第三级 RC积分器 13; 所述加法 模块为三个， 分别为第一级加法模块 Al、 第二级加法模块 A2和第三级加法 模块 A3; 所述 DAC600为一个；
所述第一级加法模块 A1 的输入端连接外部输入的模拟信号 Vin 和 DAC600的输出信号；
所述第一级加法模块 A1 的输出端连接所述第一级 RC积分器 II 的输入 端；
所述第一级 RC积分器 II的输出端连接第二级加法模块 A2的输入端， 同 时第二级加法模块 A2的输入端还连接所述 DAC600的输出端；
所述第二级加法模块 A2的输出端连接所述第二级 RC积分器 12的输入 端；
所述第二级 RC积分器 12的输出端连接第三级加法模块 A3的输入端， 同 时第三级加法模块 A3的输入端还连接所述 DAC600的输出端；
所述第三级加法模块 A3的输出端连接所述第三级 RC积分器 13的输入 端；
所述第三级 RC积分器 13的输出端连接所述量化器 300的输入端； 所述量化器 300的输出端连接所述 D触发器 500; 所述 D触发器 500的输出端连接所述 DAC600的输入端；
修正模块 400输出的 N位数字修正信号输送给每个 RC积分器中的电阻修 正阵列， N为整数。
需要说明的是， 本发明实施例中的 RC积分器与现有的 RC积分器的区别 是， 其中的电阻是电阻修正阵列， 电阻修正阵列可以采用串联阵列， 也可以采 用并联阵列， 还可以采用串并联阵列。
本发明实施例中的电阻修正阵列选择串联阵列为例进行介绍。
电阻修正阵列包括依次串联的多个电阻， 分别为第一电阻直至第 N电阻， 第一电阻至第 N-1电阻的两端分别并联一个开关，所述开关的数量与所述数字 修正信号的位数相同， 所述开关与所述逻辑组合电路的输出——对应相连； 所 述第一电阻至第 N-1电阻的阻值分别是前一电阻的二倍；所述第一电阻的一端 接入前级电路， 所述第 N电阻的一端接入后级电路；
下面以 N为整数 5 , 及对应四位数字修正信号， 进行举例说明电阻修正阵 列。
参见图 4, 该图为本发明提供的电阻修正阵列示意图。
所述电阻修正阵列包括依次串联的第一电阻 R、 第二电阻 2R、 第三电阻 4R、 第四电阻 8R和第五电阻 R0;
第一电阻1、 第二电阻 2R、 第三电阻 4R和第四电阻 8R的两端分别并联 一个开关；
其中， 第一电阻 R—端 a为不连接第二电阻 2R的一端； 第五电阻 R0的 另一端 b为不连接第四电阻 4R的一端；
每个所述 RC积分器中包括两个所述电阻修正阵列； 其中一个电阻修正阵 列串联于 RC积分器中运算放大器的正相输入端； 另一个电阻修正阵列串联于 RC积分器中运算放大器的反相输入端。
所述第四电阻 8R、 第三电阻 4R和第二电阻 2R的阻值分别是第一电阻 R 的阻值的八倍、 四倍和二倍。 之所以这样选择四个电阻之间的倍数关系， 是为 了使电阻修正阵列对外呈现的电阻可以从 1倍到 15倍的第一电阻 R连续跳变， 例如第一电阻 R的阻值是 lk, 则该电阻修正阵列对外呈现的电阻通过改变开 关的状态可以获得 lk的从 1到 15每个整数倍的阻值， 即 lk、 2k、 3k、 4k、 5k、 6k、 7k、 8k、 9k、 10k、 llk、 12k、 13k、 14k、 15k。
电阻修正阵列中的开关由修正模块输出的四位数字修正信号进行控制，下 面介绍修正模块。
需要说明的是， 在实际应用中， 数字修正信号的位数可以为大于等于 1的 整数， 但是数字修正信号的位数与量化器中比较器的个数相同。
所述修正模块还包括电流源、组合逻辑电路和第一脉沖开关； 所述预定电 阻一端接地， 所述预定电阻另一端与电流源连接，从而使所述预定电阻另一端 产生所述修正电平，所述电流源与所述预定电阻之间连接一个第一脉沖开关的 一端， 所述第一脉沖开关的另一端连接至量化器中比较器的第一输入端， 当所 述第一脉沖开关连通信号时，所述修正电平通过所述第一脉沖开关输至所述比 较器的第一输入端； 预定参考电压输至量化器中比较器的第二输入端， 所述预 定参考电压由偏置模块提供；
所述量化器包括多个比较器，每个比较器的输出端均通过一个第一脉沖开 关连接所述组合逻辑电路的输入端， 当所述一个第一脉沖开关连通信号时， 所 述修正电平与预定参考电压的比较结果 B输至所述组合逻辑电路的输入端； 所述组合逻辑电路的输出端连接至所述电阻修正阵列，所述逻辑组合电路 对所述比较结果 B 进行逻辑变换以还原信号顺序， 输出与比较器位数相同的 数字修正信号。
下面结合实施例介绍修正模块的具体实现方式。
参见图 5, 该图为本发明提供的修正模块示意图。
所述修正模块包括预定电阻 Rx、 组合逻辑电路 401、 五个第一脉沖开关 和五个第二脉沖开关； 所述第一脉沖开关由第一时钟信号 CLK1控制， 第二脉 沖开关由第二时钟信号 CLK2控制；
所述预定电阻 Rx上产生的修正电平 Vx通过一个所述第一脉沖开关连接 量化器中四个比较器 B的第一输入端；
求和后的信号 Vsum通过一个所述第二脉沖开关连接量化器中四个比较 器 B的第一输入端；
四个预定参考电压 Vrefl、 Vref2、 Vref3、 和 Vref4分别连接量化器中四个 比较器 B的第二输入端； 所述四个预定参考电压由偏置模块产生； 所述四个比较器 B 的输出端分别经过四个所述第一脉沖开关连接所述组 合逻辑电路 401的输入端； 同时， 所述四个比较器 B的输出端分别经过四个 所述第二脉沖开关连接所述 D触发器 500的输入端；
所述组合逻辑电路 401输出四位开关信号 D<3>、 D<2>、 D<1>和 D<0>, 该四位开关信号便是所述数字修正信号，所述数字修正信号用于控制电阻修正 阵列和 /或前馈电阻阵列中的四个开关。
需要说明的是， 所述组合逻辑电路 401是由逻辑门组成的， 组合逻辑电路 401 的作用是将输入的四位数字信号经过逻辑组合输出为需要的四位数字修 正信号， 例如， 输入组合逻辑电路 401 的四位数字信号是 1100, 但是需要的 四位数字修正信号是 1010,则组合逻辑电路 401需要内部的逻辑门电路将 1100 变为 1010进行输出。
需要说明的是， Sigma-Delta调制器可以包括前馈电阻阵列， 也可以不包 括前馈电阻阵列。 本发明实施例中以包括前馈电阻阵列为例进行介绍。
前馈电阻阵列的一端接至前级电路的输出端，另一端接至后级电路的输入 端；所述前级电路包括为第一级 RC积分器提供输入的电路或 RC积分器电路， 所述后级电路包括 RC积分器电路或接收最后一级 RC积分器输出的电路， 前 级电路的输出信号通过所述前馈电阻阵列后前馈至后级电路的输入端作为所 述后级电路的部分输入信号，所述前馈电阻阵列由数字修正信号控制选取其电 阻值。
前馈电阻阵列的结构与电阻修正阵列的结构完全相同。
所述前馈电阻阵列包括依次串联的多个电阻；分别为第一电阻直至第 N电 阻， 第一电阻至第 N-1电阻的两端分别并联一个开关，所述开关的数量与所述 数字修正信号的位数相同， 所述开关与所述逻辑组合电路的输入——对应相 连； 所述第一电阻至第 N-1电阻的阻值分别是前一电阻的二倍； 所述第一电阻 接入前级电路， 所述第 N 电阻接入后级电路， 前后级电路以电路中信号总的 流向进行区分，信号率先通过的电路为前级电路，信号后通过的电路为后级电 路。
下面以前馈电阻阵列中 N为 5进行举例说明。
可参见图 4, 所述前馈电阻阵列包括依次串联的第六电阻、 第七电阻、 第 八电阻、 第九电阻和第十电阻；
所述第六电阻、第七电阻、第八电阻和第九电阻的两端分别并联一个所述 开关；
所述第九电阻、 第八电阻和第七电阻的阻值分别是第六电阻的阻值的八 倍、 四倍和二倍。
需要说明的是， 所述前馈电阻中的第六电阻、 第七电阻、 第八电阻、 第九 电阻和第十电阻的位置以及之间的连接关系与所述电阻修正阵列中的第一电 阻1、 第二电阻 2R、 第三电阻 4R、 第四电阻 8R和第五电阻 R0分别相同， 在 此不再详细赘述。
当调制器包括三级 RC积分器时， 如图 7所示的实施例。
所述第一级 RC积分器的正输入端（第一级 RC积分器的前级电路的输出 端 )和第三级 RC积分器的负输出端（最后一级 RC积分器后级电路的输入端 ) 之间连接一个该前馈电阻阵列； 所述第一级 RC 积分器的负输入端和第三级 RC积分器的正输出端之间连接一个该前馈电阻阵列；
所述第二级 RC积分器的正输入端（第一级 RC积分器的负输出端）和第 三级 RC积分器的正输出端之间连接一个该前馈电阻阵列； 所述第二级 RC积 分器的负输入端（第一级 RC积分器的正输出端）和第三级 RC积分器的负输 出端之间连接一个该前馈电阻阵列；
所述第三级 RC积分器的正输入端 （第二级 RC积分器的负输出端）和第 三级 RC积分器的负输出端之间连接一个该前馈电阻阵列； 所述第三级 RC积 分器的负输入端（第二级 RC积分器的正输出端）和第三级 RC积分器的正输 出端之间连接一个该前馈电阻阵列。
本发明实施例仅示出了前馈至最后一级 RC积分器输出端 （最后一级 RC 积分器后级电路的输入端）的前馈电阻阵列连接方式， 本领域技术人员可以理 解的是，前馈电阻也可将前级电路的输出信号前馈至任何一级 RC积分器的输 入， 但需要前级电路输出信号前馈至后级电路的输入是同相的。
当调制器开始工作时， 第一时钟信号 CLK1为高电平，对应的第一脉沖开 关均导通，第二时钟信号 CLK2为低电平，对应的第二脉沖开关均关断；此时， 四位开关信号作为 RC积分器中电阻修正阵列的输入，通过控制电阻接入阵列 的阻值完成对电阻阵列的修正，即改变图 4所示的电阻修正阵列对外呈现的电 阻值。
当第一时钟信号 CLK1为高电平持续了预设个数的时钟周期后， 即当修正 过程结束后，所述第一时钟信号 CLK1为低电平，对应的第一脉沖开关均关断， 第二时钟信号 CLK2为高电平，对应的第二脉沖开关均导通。此时调制器中的 Vsum作为比较器的输入， 比较器的输出端接 D触发器的输入端， 调制器开始 正常工作。
参见图 6, 该图为本发明提供的第一时钟信号和第二时钟信号时序图。 Sigma-Delta调制器开始工作时， 第一时钟信号 CLK1 为高电平， 第二时 钟信号 CLK2为低电平；图中示出 T0-T3时间段内的三个时钟周期 CLK1为高 电平， 即在前三个时钟周期内对 RC积分器的电阻进行修正。
三个时钟周期后， 对电阻的修正完成， CLK1跳变为低电平， CLK2跳变 为高电平， Sigma-Delta调制器开始正常工作。图中示出了，在 T4-T5之间 CLK2 跳变为高电平， 从 T5以后 Sigma-Delta调制器开始正常工作。
参见图 7, 该图为本发明提供的 Sigma-Delta调制器实施例四示意图。 本实施例提供的 Sigma-Delta调制器中， 每个 RC积分器对应一个前馈电 阻阵列，所述前馈电阻阵列用于将对应 RC积分器的输入信号均前馈到最后一 级 RC积分器的输出端；
最后一级 RC积分器的输出端连接求和模块， 所述求和模块用于将最后一 级 RC积分器的输出信号和所有前馈电阻阵列前馈的信号进行求和，将求和后 的信号输出给所述量化器。
如图所示， 第一级 RC积分器的前馈电阻阵列为 R4, 第二级 RC积分器的 前馈电阻阵列为 R5 , 第三级 RC积分器的前馈电阻阵列为 R6。
由于前馈电阻阵列的存在， 所以调制器还包括求和模块 700。
本实施例提供的调制器中包括一个 DAC600,用于将 D触发器输出的数字 信号转换为模拟信号后反馈给第一级 RC积分器之前的加法模块。
RC积分器中的 R1~R3为电阻爹正阵列， 其示意图如图 4所示。 对此电阻 修正阵列进行数字修正的电阻修正模块的具体实现方式如图 5所示。其中， 电 阻 Rx与积分器中电阻修正阵列 R1~R3是由相同类型电阻组成，因此在芯片制 造过程中， Rx的工艺偏差能够准确表征积分器中电阻修正阵列 R1~R3的电阻 值变化。 同样， 一个稳定电流源 Iref流过预定电阻 Rx产生的修正电平 Vx也 能表征电阻修正阵列 R1~R3的电阻值变化。
在 Sigma-Delta调制器中， 量化器是必不可少的模块， 通常量化器由一个 或多个比较器组成。
本发明提供的 Sigma-Delta调制器降低了 Sigma-Delta调制器的性能受电阻 工艺角变化的影响， 且电阻修正利用了 Sigma-Delta调制器本身的比较器， 不 增加额外的芯片面积。本发明中的电阻修正模块只在工作开始的几个周期内完 成调整， 之后一直处理关断状态， 因此不消耗任何额外功耗和面积。 电阻修正 模块的灵活性强，产生的修正数字位数可以根据调节精度和面积的折衷进行灵 活设计。
以上所述，仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的 限制。 虽然本发明已以较佳实施例揭露如上， 然而并非用以限定本发明。 任何 熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述 揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改 为等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本 于本发明技术方案保护的范围内。

Claims

权 利 要 求
1、 一种 Sigma-Delta调制器， 其特征在于， 包括： 量化器、 修正模块和 RC积分器； 其中，
所述修正模块包括预定电阻， 通过所述预定电阻产生修正电平； 所述修正模块，用于利用所述量化器中的比较器将所述修正电平与预定参 考电压进行比较， 从而产生数字修正信号， 根据所述数字修正信号对所述 RC 积分器中的电阻修正阵列中的电阻进行修正； 所述预定电阻与所述 RC积分器 中的电阻修正阵列中的电阻的类型相同。
2、 根据权利要求 1 所述的 Sigma-Delta 调制器， 其特征在于， 所述 Sigma-Delta调制器还包括 DAC和 D触发器， 所述 D触发器的输入端与所述 比较器的输出端电性相连， 所述 D触发器的输出端连接所述 DAC的输入端， 所述 DAC的输出信号反馈至 RC积分器的输入端； 其中，
所述 D触发器将 RC积分器与预定参考电压的比较信号 A进行同步， 经 过同步的所述比较信号 A通过所述 DAC后作为 RC积分器的部分输入信号反 馈至 RC积分器的输入端；
所述 DAC的个数小于或等于 RC积分器的个数，一个 DAC的输出端连接 至少一个 RC积分器的输入端， 所述一个 DAC的输出信号作为所述至少一个 RC积分器的部分输入信号；一个 RC积分器最多对应一个 DAC的输出作为所 述一个 RC积分器的部分输入信号， 而 RC积分器中的第一级 RC积分器连接 DAC中一个 DAC的输出端， 所述 DAC中一个 DAC的输出作为所述第一级 RC积分器的部分输入。
3、根据权利要求 1或 2所述的 Sigma-Delta调制器， 其特征在于， 还包括 前馈电阻阵列， 前馈电阻阵列的一端接至前级电路的输出端， 另一端接至后级 电路的输入端； 所述前级电路包括为第一级 RC积分器提供输入的电路或 RC 积分器电路， 所述后级电路包括 RC积分器电路或接收最后一级 RC积分器输 出的电路，前级电路的输出信号通过所述前馈电阻阵列后前馈至后级电路的输 入端作为所述后级电路的部分输入信号，所述前馈电阻阵列由数字修正信号控 制选取其电阻值。
4、根据权利要求 1或 2所述的 Sigma-Delta调制器， 其特征在于， 所述修 正模块还包括电流源、组合逻辑电路和多个第一脉沖开关； 所述预定电阻一端 接地， 所述预定电阻另一端与电流源连接，从而使所述预定电阻另一端产生所 述修正电平，所述电流源与所述预定电阻之间连接一个所述第一脉沖开关的一 端， 所述第一脉沖开关的另一端连接至量化器中比较器的第一输入端， 当所述 第一脉沖开关连通信号时，所述修正电平通过所述第一脉沖开关输至所述比较 器的第一输入端； 预定参考电压输至量化器中比较器的第二输入端， 所述预定 参考电压由偏置模块提供；
所述量化器包括多个比较器，每个比较器的输出端均通过一个所述第一脉 沖开关连接所述组合逻辑电路的输入端， 当所述一个第一脉沖开关连通信号 时， 所述修正电平与预定参考电压的比较结果 B输至所述组合逻辑电路的输 入端；
所述组合逻辑电路的输出端连接至所述电阻修正阵列 ,所述逻辑组合电路 对所述比较结果 B 进行逻辑变换以还原信号顺序， 输出与比较器位数相同的 数字修正信号。
5、根据权利要求 2所述的 Sigma-Delta调制器， 其特征在于， 还包括第二 脉沖开关，最后一级 RC积分器的输出端通过一个所述第二脉沖开关连接至量 化器中比较器的第一输入端， 当所述第二脉沖开关连通信号时， 所述最后一级 RC积分器的输出信号输至所述量化器中比较器的第一输入端，
每个所述比较器的输出端均通过一个所述第二脉沖开关连接至 D触发器 的输入端， 当所述一个第二脉沖开关连通信号时， 所述最后一级 RC积分器的 输出与预定参考电压的比较结果 A输至所述 D触发器的输入端。
6、根据权利要求 4所述的 Sigma-Delta调制器， 其特征在于， 所述电阻修 正阵列包括依次串联的多个电阻， 分别为第一电阻直至第 N电阻， N为整数； 第一电阻至第 N-1电阻的两端分别并联一个开关，所述开关的数量与所述数字 修正信号的位数相同， 所述开关与所述逻辑组合电路的输出——对应相连； 所 述第一电阻至第 N-1电阻的阻值分别是前一电阻的二倍；所述第一电阻接入前 级电路， 所述第 N电阻接入后级电路；
每个所述 RC积分器包括两个所述电阻修正阵列； 其中一个电阻修正阵列 串联于 RC 积分器中运算放大器的正相输入端； 另一个电阻修正阵列串联于 RC积分器中运算放大器的反相输入端。
7、根据权利要求 3所述的 Sigma-Delta调制器， 其特征在于， 所述前馈电 阻阵列包括依次串联的多个电阻； 分别为第一电阻直至第 N 电阻， 第一电阻 至第 N-1电阻的两端分别并联一个开关，所述开关的数量与所述数字修正信号 的位数相同， 所述开关与逻辑组合电路的输入——对应相连； 所述第一电阻至 第 N-1 电阻的阻值分别是前一电阻的二倍； 所述第一电阻的一端接入前级电 路， 所述第 N电阻的一端接入后级电路。
8、根据权利要求 5所述的 Sigma-Delta调制器， 其特征在于， 所述第一脉 沖开关由第一时钟信号控制， 第二脉沖开关由第二时钟信号控制；
当调制器开始工作时， 第一时钟信号为高电平，对应的第一脉沖开关均导 通， 第二时钟信号为低电平， 对应的第二脉沖开关均关断；
当第一时钟信号为高电平持续了预设个数的时钟周期后，所述第一时钟信 号为低电平， 对应的第一脉沖开关均关断， 第二时钟信号为高电平， 对应的第 二脉沖开关均导通。
9、 一种 Sigma-Delta模数转换器， 其特征在于， 包括权利要求 1-9任一项 所述的 Sigma-Delta调制器。
PCT/CN2013/071961 2012-09-03 2013-02-28 一种Sigma-Delta调制器及模数转换器 Ceased WO2014032417A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571828A (zh) * 2015-10-10 2017-04-19 深圳市博巨兴实业发展有限公司 一种连续时间Sigma-Delta调制器

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102801424B (zh) 2012-09-03 2015-06-24 中国科学院微电子研究所 一种Sigma-Delta调制器及模数转换器
CN103607203B (zh) * 2013-11-25 2017-01-11 深圳市芯海科技有限公司 一种基于σ-δ的模数转换电路、adc芯片及数字天平
JP5915669B2 (ja) * 2014-01-14 2016-05-11 株式会社デンソー Ａ／ｄ変換装置
JP6455695B2 (ja) * 2015-04-01 2019-01-23 Tdk株式会社 シグマデルタ変調器構成体、連続時間シグマデルタ変調器を較正するための方法および制御装置
US9923572B2 (en) * 2015-11-18 2018-03-20 Cypress Semiconductor Corporation Delta modulator receive channel for capacitance measurement circuits
CN105356885B (zh) * 2015-11-24 2018-09-11 广州一芯信息科技有限公司 一种轨到轨输入的连续时间差异积分调制器
EP3340475B1 (en) * 2016-12-22 2021-04-28 Nxp B.V. Metastability compensation
CN110364061A (zh) * 2019-07-12 2019-10-22 上海图菱新能源科技有限公司 模电数电教学实验电路及方法
CN111010188B (zh) * 2019-12-03 2023-06-30 芯创智创新设计服务中心(宁波)有限公司 一种连续时间sigma-delta模数转换器的电阻电容校准电路
CN110995272A (zh) * 2019-12-25 2020-04-10 重庆大学 基于可变电阻的开关电容电阻反馈连续时间调制器
US11211940B2 (en) * 2019-12-31 2021-12-28 Texas Instruments Incorporated Pinstrap detection circuit
TWI719811B (zh) * 2020-01-21 2021-02-21 瑞昱半導體股份有限公司 負回授系統架構及其迴圈濾波器
US11901919B2 (en) 2021-04-26 2024-02-13 Stmicroelectronics International N.V. On chip test architecture for continuous time delta sigma analog-to-digital converter
US11863205B2 (en) * 2021-11-30 2024-01-02 Analog Devices International Unlimited Company Adaptive bias techniques for amplifiers in sigma delta modulators
CN114200995A (zh) * 2021-12-10 2022-03-18 上海富芮坤微电子有限公司 参考电压产生电路及Sigma Delta调制器
CN115955246A (zh) * 2022-10-13 2023-04-11 北京奕斯伟计算技术股份有限公司 SDMADC电路及其方法、Sigma-Delta调制器模数转换器
CN115549686A (zh) * 2022-10-13 2022-12-30 北京奕斯伟计算技术股份有限公司 应用于SDMADC的输入电路及方法、Sigma-Delta调制器模数转换器
CN119995607B (zh) * 2023-11-13 2025-11-14 圣邦微电子（北京）股份有限公司 Sigma-Delta模数转换器及其量化电路
CN119154888B (zh) * 2024-06-25 2025-11-28 中山大学 一种Delta-Sigma调制器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404503A (zh) * 2007-10-04 2009-04-08 联发科技股份有限公司 连续时间∑-△调制器及其补偿环路延迟的方法
CN102386929A (zh) * 2011-09-22 2012-03-21 北京大学 Sigma-Delta调制器及包括该调制器的Sigma-Delta模数转换器
CN102420614A (zh) * 2011-11-22 2012-04-18 北京大学 Sigma-Delta调制器及包含其的Sigma-Delta模数转换器
CN102801424A (zh) * 2012-09-03 2012-11-28 中国科学院微电子研究所 一种Sigma-Delta调制器及模数转换器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729230A (en) * 1996-01-17 1998-03-17 Hughes Aircraft Company Delta-Sigma Δ-Σ modulator having a dynamically tunable continuous time Gm-C architecture
US7002417B2 (en) * 2003-03-21 2006-02-21 Nokia Corporation RC and SC filter compensation in a radio transceiver
US7098730B1 (en) * 2004-06-22 2006-08-29 Maxim Integrated Products, Inc. Process variation trim/tuning for continuous time filters and Δ-Σ analog to digital converters
US7221302B1 (en) * 2005-12-20 2007-05-22 Cirrus Logic, Inc. Delta-sigma modulator coefficient calibration method and apparatus
US7944378B1 (en) * 2008-08-18 2011-05-17 Marvell International Ltd. Circuits and methods for calibrating analog and digital circuits
CN101640539B (zh) * 2009-06-19 2013-04-10 浙江大学 Sigma-Delta模数转换器
JP5696508B2 (ja) * 2011-02-04 2015-04-08 ソニー株式会社 Δς変調器および信号処理システム
US9160356B1 (en) * 2014-07-17 2015-10-13 Analog Devices Global Analog to digital convertor and a method of calibrating same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404503A (zh) * 2007-10-04 2009-04-08 联发科技股份有限公司 连续时间∑-△调制器及其补偿环路延迟的方法
CN102386929A (zh) * 2011-09-22 2012-03-21 北京大学 Sigma-Delta调制器及包括该调制器的Sigma-Delta模数转换器
CN102420614A (zh) * 2011-11-22 2012-04-18 北京大学 Sigma-Delta调制器及包含其的Sigma-Delta模数转换器
CN102801424A (zh) * 2012-09-03 2012-11-28 中国科学院微电子研究所 一种Sigma-Delta调制器及模数转换器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571828A (zh) * 2015-10-10 2017-04-19 深圳市博巨兴实业发展有限公司 一种连续时间Sigma-Delta调制器
CN106571828B (zh) * 2015-10-10 2023-04-11 深圳市博巨兴微电子科技有限公司 一种连续时间Sigma-Delta调制器

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