WO2014008698A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

Info

Publication number
WO2014008698A1
WO2014008698A1 PCT/CN2012/079717 CN2012079717W WO2014008698A1 WO 2014008698 A1 WO2014008698 A1 WO 2014008698A1 CN 2012079717 W CN2012079717 W CN 2012079717W WO 2014008698 A1 WO2014008698 A1 WO 2014008698A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
contact
drain
forming
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/079717
Other languages
English (en)
French (fr)
Inventor
尹海洲
张珂珂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to US14/414,355 priority Critical patent/US9614050B2/en
Publication of WO2014008698A1 publication Critical patent/WO2014008698A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0218—Manufacture or treatment of FETs having insulated gates [IGFET] having pocket halo regions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a MOSFET having an increased contact area. Background technique
  • the object of the present invention is to replace the conventional replacement gate process by a new manufacturing method to contact the sacrificial layer process, thereby greatly reducing the spacing between the contact region and the gate, thereby effectively reducing device parasitic resistance.
  • the above object of the present invention is achieved by providing a semiconductor device manufacturing method comprising: forming a contact sacrificial pattern on a substrate, covering a source region and a drain region, and exposing a gate region; forming an interlayer on the substrate a dielectric layer covering the contact sacrificial pattern and exposing the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern, leaving a source/drain contact trench; forming a source drain in the source/drain contact trench contact.
  • the substrate further includes shallow trench isolation, and the contact sacrificial pattern exposes a portion of the shallow trench isolation.
  • the interlayer dielectric layer covers part of the shallow trench isolation.
  • the source and drain contact sidewalls are silicon nitride and silicon oxynitride.
  • forming the gate stack structure includes depositing a gate insulating layer of a high-k material, a work function adjusting layer of the metal nitride, and a resistance adjusting layer of the metal in the exposed gate region.
  • the planarization resistance adjustment layer, the work function adjustment layer, and the interlayer dielectric layer are further formed until the contact sacrificial pattern is exposed.
  • the step of forming a source-drain contact further comprises: performing source-drain ion implantation, forming a source-drain heavily doped region in the substrate exposed in the source-drain contact trench; forming a metal in the source-drain heavily doped region a silicide; a liner layer and a fill layer are sequentially deposited on the metal silicide in the source-drain contact trench; the fill layer and the liner layer are planarized until the gate stack structure is exposed.
  • the step of forming a metal silicide further comprises: depositing a metal layer in the source/drain contact trench, annealing to cause the metal layer to react with silicon in the substrate to form a metal silicide, and stripping the unreacted metal layer.
  • the contact sacrificial pattern is polysilicon, amorphous silicon, amorphous carbon, and combinations thereof.
  • a contact oxide layer is further included between the contact sacrificial pattern and the substrate.
  • the pitch between the gate spacer and the contact region is effectively reduced by the contact sacrificial layer process, and the contact region area is increased, thereby effectively reducing the parasitic resistance of the device.
  • 1 to 12 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • FIG. 13 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • a contact sacrificial pattern is formed on the substrate, covering the source and drain regions and exposing the gate region.
  • a contact sacrificial layer 3 is deposited on the substrate 1.
  • a substrate 1 is provided, which may be made of (substrate) Si (for example, single crystal Si wafer), SOL single crystal Ge, GeOI (Ge on insulator), or other compound semiconductors such as GaAs, SiGe, GeSn, InP, InSb. , GaN, etc.
  • the substrate 1 is selected from a bulk Si or SOI for compatibility with a CMOS process.
  • shallow trenches are formed by etching in the substrate 1 and an insulating material such as silicon oxide is deposited to form shallow trench isolation (STI) 2.
  • STI shallow trench isolation
  • the sacrificial layer 3 is deposited on the substrate 1 by a conventional method such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, or the like.
  • the contact sacrificial layer 3 is used to define a region where source-drain contacts are to be formed later, similar to the function of the dummy gate in the gate-last process, and thus may also be referred to as a dummy-drain contact region.
  • the material contacting the sacrificial layer 3 is, for example, polycrystalline silicon, amorphous silicon, amorphous carbon or the like, and its thickness is, for example, larger than the height of the gate electrode to be formed later, for example, 50 to 500 nm.
  • a thin pad oxide layer 4 is further provided between the contact sacrificial layer 3 and the substrate 1, and the material thereof is, for example, silicon oxide, and the thickness is, for example, 1 to 10 nm.
  • the sacrificial contact layer 3 is etched to expose the gate region and a portion of the STI region.
  • the sacrificial layer 3 is etched by anisotropic etching, such as dry etching by plasma etching, reactive ion etching, or wet etching such as TMAH.
  • anisotropic etching such as dry etching by plasma etching, reactive ion etching, or wet etching such as TMAH.
  • the pad oxide layer 4 is formed until the substrate is exposed to form a contact sacrificial pattern 3A. Where, contact with the sacrificial figure 3A
  • the source and drain regions of the device to be formed are covered, and the gate region is exposed through the opening 3B and the portion of the STI2 is exposed through the opening 3C.
  • the opening 3B is used for later deposition of the gate stack structure and is therefore also referred to as a gate opening (the gate opening width is equal to the sum of the width of the gate stack structure to be formed later and the width of the source/drain contact sidewall), the opening 3C
  • the isolation used between the devices is therefore also referred to as an isolation opening.
  • source-drain doping is performed.
  • a low-dose, low-energy oblique source-drain ion implantation is used, and a dopant effect is controlled by a shadow effect to form a lightly doped source-drain extension region 1 A.
  • a rapid anneal e.g., laser rapid annealing
  • the type, dose, and concentration of the doping ions are set according to the electrical performance requirements of the device.
  • a sidewall (not shown) containing a diffusion source is formed on both sides of the contact sacrificial pattern 3A and the pad oxide layer 4 to form a lightly doped source/drain extension region 1A by ion diffusion.
  • a source/drain contact sidewall is formed on the side of the contact sacrificial pattern.
  • an insulating material such as silicon nitride or silicon oxynitride is deposited and then etched to form a source/drain contact spacer 5 which is located on the side contacting the sacrificial pattern 3A.
  • the source/drain contact sidewalls 5 are located on both sides of the gate opening 3B, and on both sides of the isolation opening 3C.
  • the thickness of the source/drain contact sidewall 5 is not greater than the width of the isolation opening 3C, for example, 5 to 10 nm.
  • an interlayer dielectric layer is formed to cover the contact sacrificial pattern and expose the gate region.
  • an interlayer dielectric layer (ILD) 6 is deposited over the entire device.
  • ILD6 typically silicon oxide and low-k materials
  • low-k materials include, but are not limited to, organic low-k materials (eg, organic polymers containing aryl or polycyclic rings) ), inorganic low-k materials (such as amorphous carbon-nitrogen thin films, polycrystalline boron-nitrogen thin films, fluorosilicate glass, BSG PSG BPSG), porous low-k materials (such as disilane trioxane (SSQ)-based porous low-k materials, porous Silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer).
  • the thickness of the ILD 6 is greater than the thickness of the contact sacrificial pattern 3A, for example, 100 to 1000
  • a photoresist 7 is spin-coated on the ILD 6, and a photoresist opening 7A is formed by photolithography to expose the ILD6, and then the ILD 6 is selectively etched to form an ILD opening 6A to expose the gate region (the aforementioned gate). Opening 3B).
  • the ILD6 is silicon oxide
  • the source/drain contact sidewall 5 is silicon nitride
  • the substrate 1 is silicon
  • Process parameters such as the type, flow rate, and pressure of the fluorocarbon-based etching gas make the rate of etching silicon oxide significantly faster than the rate of etching silicon nitride/silicon, for example, the etching ratio is controlled to be 10:1 or more.
  • the etch stop point is controlled by the choice of etch rate and time.
  • the SiO-based wet etching solution is used to remove the silicon oxide.
  • ILD6 still covers STI2 and some source-drain contact sidewalls 5 at this time, so as to provide isolation insulation between devices.
  • the gate opening 3B has been occupied by the partial source-drain contact sidewall 5 with the remaining width being the width of the gate stack.
  • a gate stack structure is formed in the exposed gate region.
  • a gate insulating layer 8 is deposited on a surface of the bottom of the gate opening 3B that is in contact with the substrate 1 by a method such as PECVD, HDPCVD, MOCVD, MBE, ALD, or the like.
  • the material of the gate insulating layer 8 is a high-k material, including but not limited to nitrides (for example, SiN, AlN, TiN), metal oxides (mainly sub-group and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), perovskite phase oxide (eg PbZr x Ti 1-x 0 3 ( PZT ), Ba x Sr 1-x Ti0 3 ( BST ) ).
  • nitrides for example, SiN, AlN, TiN
  • metal oxides mainly sub-group and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2
  • the gate conductive layer 9 is deposited on the ILD 6 and in the gate opening 3B by PECVD, MOCVD, MBE, ALD, evaporation, sputtering, or the like.
  • the gate conductive layer 9 preferably includes a work function adjusting layer made of a metal nitride such as TiN or TaN, and a resistance adjusting layer made of a metal such as Cu, Al, Ti, Mo, Ta, W or the like.
  • the gate insulating layer 8 and the gate conductive layer 9 together form a gate stack structure
  • the gate conductive layer 9, ILD6 is planarized by a etch back process or a CMP process until the contact sacrificial pattern 3A is exposed.
  • the contact sacrificial pattern is removed leaving the source and drain contact trenches.
  • an anisotropic wet etching solution such as TMAH is used to etch away the contact sacrificial pattern 3 A of polycrystalline silicon or amorphous silicon material, or the contact sacrificial pattern 3 A of amorphous carbon material is removed by oxygen plasma etching.
  • the pad oxide layer 4 of the silicon oxide material is removed by using an HF-based etching solution.
  • the source/drain contact trench 3D (the space previously occupied by the sacrificial pattern 3A) is left, and the substrate 1, the source/drain extension region 1A, the portion STI2, and the source/drain contact are exposed.
  • Side wall 5 the space previously occupied by the sacrificial pattern 3A
  • source-drain contacts are formed in the source/drain contact trenches.
  • source-drain implantation is performed to form a source-drain heavily doped region 1D
  • the implanted ion species is of the same kind as the lightly doped implant source-drain extension region 1 A, and is doped with Halo source and drain.
  • the type of zone 1B is different, but the injection dose and energy are larger, so that the source and drain with larger junction depth and higher concentration are obtained.
  • Heavy doped zone 1C is formed on the substrate 1 in the source/drain contact trench 3D by selective epitaxy. In-situ doping is performed while forming a source-drain epitaxial region, or implant doping is performed and annealing activation is performed after forming a source-drain epitaxial region.
  • a thin metal layer such as Ni, Pt, Co, Ti, and combinations thereof, followed by rapid annealing or low temperature annealing (400 ⁇ 600 ° C)
  • the metal thin layer is reacted with Si in the source and drain regions to form a metal silicide 10 for further reducing the contact resistance.
  • the metal silicide 10 is formed only in the substrate 1 (source/drain heavily doped region 1C).
  • a barrier layer 11A (pad layer) of a material of TiN and TaN and a filling of materials such as W, Al, Mo, Ti, etc. are sequentially deposited on the metal silicide 10 in the source/drain contact trench 3D.
  • Layer 11B is formed to form source and drain contacts 11.
  • the barrier layer 11A/filler layer 11B is planarized by a process such as CMP until the gate conductive layer 9 (resistance adjusting layer 9B) of the gate stack structure is exposed.
  • the distance between the source/drain contact 11 and the gate stack structure is only the thickness of the source/drain contact sidewall 5, and the pitch is greatly reduced; in addition, the source/drain contact 11 covers the entire source and drain regions, and the area thereof is relatively smaller.
  • the existing technology has been greatly improved. Therefore, such a large-area source-drain contact in accordance with the present invention effectively reduces parasitic resistance.
  • a second ILD 12 of a silicon nitride material is deposited on the entire device, the ILD 12 is etched to form a source/drain contact hole, and the source and drain contact holes are filled with a metal material to form a second source/drain contact 11C, for example, depositing on the entire device.
  • a third ILD 13 of silicon oxide an interconnection hole is formed by etching, and a metal such as Al, Ti or the like is deposited in the interconnection hole to form the interconnection line 14.
  • the pitch between the gate spacer and the contact region is effectively reduced by the contact sacrificial layer process, and the contact region area is increased, thereby effectively reducing the parasitic resistance of the device.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种半导体器件制造方法，包括：在衬底（1）上形成接触牺牲图形（3A），覆盖源区与漏区并且暴露栅极区域；在衬底（1）上形成层间介质层（6），覆盖接触牺牲图形（3A）并且暴露栅极区域；在暴露的栅极区域中形成栅极堆叠结构；去除接触牺牲图形（3A），留下了源漏接触沟槽（3D）；在源漏接触沟槽（3D）中形成源漏接触（11）。该方法通过接触牺牲层工艺降低了栅极侧墙与接触区域之间的距离，增大了接触区域面积，从而减小了器件的寄生电阻。

Description

半导体器件制造方法
[0001]本申请要求了 2012月 7月 13日提交的、 申请号为 201210245140.6、发明 名称为"半导体器件制造方法 "的中国专利申请的优先权， 其全部内容通过引 用结合在本申请中。 技术领域
[0002]本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种具有增大 接触区域的 MOSFET的制造方法。 背景技术
[0003]随着 MOSFET的特征尺寸持续缩减， 寄生电阻在器件的总电阻中占据 的比重越来越大， 严重制约了小尺寸器件性能的提升。 现有的降低寄生电阻 的结构 /方法包括形成提升源漏、 在源漏区中 /上形成金属硅化物、 提高接触 面积等等。
[0004]然而， 无论采用何种结构 /方法， 源 /漏区的接触区域（或接触孔， CA ) 与栅极侧墙之间仍然有较大的间距，电子 /空穴的载流子从源区穿越沟道区达 到漏区的距离仍然较大， 因此寄生电阻依然无法有效的减小， 器件性能提升 程度有限。 发明内容
[0005]有鉴于此，本发明的目的在于采用新的制造方法以接触牺牲层工艺代 替传统的替代栅工艺， 大幅减小接触区域与栅极之间的间距， 从而有效地减 小器件寄生电阻。
[0006] 实现本发明的上述目的，是通过提供一种半导体器件制造方法，包括： 在衬底上形成接触牺牲图形， 覆盖源区与漏区并且暴露栅极区域； 在衬底上 形成层间介质层， 覆盖接触牺牲图形并且暴露栅极区域； 在暴露的栅极区域 中形成栅极堆叠结构； 去除接触牺牲图形， 留下了源漏接触沟槽； 在源漏接 触沟槽中形成源漏接触。 [0007]其中， 衬底中还包括浅沟槽隔离， 接触牺牲图形暴露了部分浅沟槽隔 离。 其中， 层间介质层覆盖了部分浅沟槽隔离。
[0008】其中， 形成接触牺牲图形之后、 形成层间介质层之前， 还包括在接触 牺牲图形侧面上形成源漏接触侧墙。 其中， 源漏接触侧墙为氮化硅、 氮氧化 硅。
[0009】其中， 形成接触牺牲图形之后， 还包括执行离子注入， 在衬底中形成 轻掺杂的源漏延伸区和晕状源漏掺杂区。
[0010]其中， 形成栅极堆叠结构包括在暴露的栅极区域中沉积高 k材料的栅 极绝缘层、 金属氮化物的功函数调节层以及金属的电阻调节层。 其中， 形成 栅极堆叠结构之后还包括平坦化电阻调节层、 功函数调节层、 层间介质层直 至暴露接触牺牲图形。
[0011】其中， 形成源漏接触的步骤进一步包括： 执行源漏离子注入， 在源漏 接触沟槽中暴露的衬底中形成源漏重掺杂区； 在源漏重掺杂区中形成金属硅 化物； 在源漏接触沟槽中金属硅化物上依次沉积衬垫层和填充层； 平坦化填 充层和衬垫层直至暴露栅极堆叠结构。
[0012】其中， 平坦化填充层和衬垫层之后， 进一步包括： 沉积第二层间介质 层； 刻蚀第二层间介质层形成源漏接触孔， 在源漏接触孔中填充形成第二源 漏接触； 沉积第三层间介质层； 刻蚀第三层间介质层形成互连孔， 在互连孔 中填充形成互连线。
[0013】其中， 形成金属硅化物的步骤进一步包括： 在源漏接触沟槽中沉积金 属层， 退火使得金属层与衬底中硅反应形成金属硅化物， 剥除未反应的金属 层。
[0014】其中， 接触牺牲图形为多晶硅、 非晶硅、 非晶碳及其组合。
[0015]其中， 接触牺牲图形与衬底之间还包括垫氧化层。
[0016]依照本发明的半导体器件制造方法，通过接触牺牲层工艺有效降低了 栅极侧墙与接触区域之间的间距， 并且增大了接触区域面积， 从而有效减小 了器件寄生电阻。 附图说明 [0017] 以下参照附图来详细说明本发明的技术方案， 其中：
[0018] 图 1至图 12为根据本发明的半导体器件制造方法各个步骤的剖视图； 以及
[0019] 图 13为根据本发明的半导体器件制造方法的流程图。 具体实施方式
[0020] 以下参照附图并结合示意性的实施例来详细说明本发明技术方案的 特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本申 请中所用的术语"第一"、 "第二"、 "上"、 "下"、 "厚"、 "薄"等等可用于修饰 各种器件结构。 这些修饰除非特别说明并非暗示所修饰器件结构的空间、 次 序或层级关系。
[0021]参照图 13以及图 1〜图 3 , 在衬底上形成接触牺牲图形， 覆盖源区与漏 区并且暴露栅极区域。
[0022]如图 1所示， 在衬底 1上沉积接触牺牲层 3。 提供衬底 1 , 其材质可以是 (体） Si (例如单晶 Si晶片）、 SOL 单晶 Ge、 GeOI (绝缘体上 Ge ), 也可以 是其他化合物半导体， 例如 GaAs、 SiGe、 GeSn、 InP、 InSb、 GaN等等。 优 选地， 衬底 1选用体 Si或 SOI, 以便与 CMOS工艺兼容。 优选地， 在衬底 1中刻 蚀形成浅沟槽并且沉积填充氧化硅等绝缘材料形成浅沟槽隔离 （STI ) 2。 采 用 LPCVD、 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD、 蒸发、 溅射等常 规方法， 在衬底 1上沉积接触牺牲层 3。 接触牺牲层 3用于限定稍后要形成源 漏接触的区域， 与后栅工艺中假栅极所起的作用类似， 因此也可以称作假源 漏接触区。 接触牺牲层 3的材质例如是多晶硅、 非晶硅、 非晶碳等， 其厚度 例如要大于稍后需要形成的栅极的高度， 例如是 50 ~ 500nm。 优选地， 在接 触牺牲层 3与衬底 1之间还包括较薄的垫氧化层 4, 其材质例如是氧化硅， 厚 度例如是 1 ~ 10nm。
[0023]如图 2所示， 刻蚀接触牺牲层 3 , 暴露了栅极区域以及部分 STI区域。 光刻形成掩模图形之后（未示出）， 采用各向异性的刻蚀， 例如等离子刻蚀、 反应离子刻蚀等干法刻蚀或者 TMAH等湿法刻蚀， 刻蚀接触牺牲层 3以及垫 氧化层 4直至暴露衬底， 形成了接触牺牲图形 3A。 其中， 接触牺牲图形 3A覆 盖了未来要形成的器件的源漏区，而通过开口 3B暴露了栅极区域以及通过开 口 3C暴露了部分 STI2的区域。 开口 3B用于稍后沉积栅极堆叠结构因此也称 作栅极开口（栅极开口宽度要等于稍后要形成的栅极堆叠结构的宽度与源漏 接触侧墙的宽度之和）， 开口 3C用于器件之间的隔离因此也称作隔离开口。
[0024]优选地， 如图 3所示， 执行源漏掺杂注入。 以接触牺牲图形 3A为掩模， 采用低剂量、 低能量的倾斜源漏离子注入， 利用阴影效应 （ Shadow Effect ) 控制了掺杂剂注入位置而形成了轻掺杂的源漏延伸区 1 A、 以及源漏延伸区 1A下方衬底中的晕状（Halo ) 源漏掺杂区 1B。 随后快速退火（例如激光快 速退火）以激活掺杂剂。 掺杂离子的种类、 剂量、 浓度依照器件电学性能需 要而设定。 可选地， 在接触牺牲图形 3A、 垫氧化层 4两侧形成含有扩散源的 侧墙（未示出）， 通过离子扩散作用形成轻掺杂的源漏延伸区 1A
[0025]参照图 13以及图 4, 在接触牺牲图形侧面形成源漏接触侧墙。
[0026】如图 4所示， 沉积例如为氮化硅、 氮氧化硅的绝缘材质并且随后刻蚀 形成了源漏接触侧墙 5 , 位于接触牺牲图形 3A的侧面。 具体地， 源漏接触侧 墙 5位于栅极开口 3B的两个侧面上， 以及隔离开口 3C的两个侧面上。 源漏接 触侧墙 5的厚度不大于隔离开口 3C的宽度， 例如为 5 ~ 10nm
[0027]参照图 13以及图 5、 图 6, 形成层间介质层， 覆盖接触牺牲图形并且暴 露栅极区域。
[0028]如图 5所示， 在整个器件上沉积层间介质层（ILD ) 6。 采用 LPCVD PECVD、 旋涂、 喷涂、 丝网印刷等方法， 形成通常为氧化硅以及低 k材料的 ILD6,低 k材料包括但不限于有机低 k材料（例如含芳基或者多元环的有机聚 合物）、无机低 k材料（例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、 BSG PSG BPSG )、 多孔低 k材料（例如二硅三氧烷（SSQ )基多孔低 k材料、 多 孔二氧化硅、 多孔 SiOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多孔金刚石、 多孔有机聚合物）。 ILD 6的厚度要大于接触牺牲图形 3A的厚度，例如为 100 ~ 1000
[0029]如图 6所示， 在 ILD6上旋涂光刻胶 7 , 光刻形成光刻胶开口 7A以暴露 ILD6, 随后选择性刻蚀 ILD6形成 ILD开口 6A以暴露栅极区域 (前述栅极开口 3B )。 当 ILD6为氧化硅、 源漏接触侧墙 5为氮化硅、 衬底 1为硅时， 可以选择 碳氟基刻蚀气体的种类、 流速以及压力等工艺参数， 使得刻蚀氧化硅的速率 显著快于刻蚀氮化硅 /硅的速率，例如刻蚀比控制在 10:1以上。通过刻蚀速率、 时间的选择来控制刻蚀停止点。或者采用 HF基湿法腐蚀液去除氧化硅。值得 注意的是， ILD6此时仍然覆盖了 STI2以及部分源漏接触侧墙 5 , 以便能提供 器件之间的隔离绝缘。 此时， 栅极开口 3B已经被部分源漏接触侧墙 5占据了 侧壁， 其剩余宽度为栅极堆叠的宽度。
[0030]参照图 13以及图 7、 图 8 , 在暴露的栅极区域中形成栅极堆叠结构。
[0031]如图 7所示， 通过 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD等方法， 在栅极开口 3B底部与衬底 1接触的面上沉积形成栅极绝缘层 8。 栅极绝缘层 8 的材质为高 k材料， 包括但不限于氮化物 （例如 SiN、 A1N、 TiN )、 金属氧化 物 （主要为副族和镧系金属元素氧化物， 例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203、 La203 )、钙钛矿相氧化物（例如 PbZrxTi1-x03 ( PZT )、 BaxSr1-xTi03 ( BST ) )。 随后， 通过 PECVD、 MOCVD、 MBE、 ALD、 蒸发、 溅射等方法在 ILD6上以及栅极开口 3B中沉积栅极导电层 9。 栅极导电层 9优 选地包括材质为 TiN、 TaN等金属氮化物的功函数调节层， 以及材质为 Cu、 Al、 Ti、 Mo、 Ta、 W等金属的电阻调节层。 栅极绝缘层 8与栅极导电层 9共同 构成栅极堆叠结构
[0032】优选地， 如图 8所示， 采用回刻工艺或者 CMP工艺， 平坦化栅极导电 层 9、 ILD6直至暴露接触牺牲图形 3A。
[0033】参照图 13以及图 9 , 去除接触牺牲图形， 留下了源漏接触沟槽。 例如 采用 TMAH等各向异性的湿法腐蚀液， 刻蚀去除多晶硅、 非晶硅材质的接触 牺牲图形 3 A , 或者采用氧等离子刻蚀去除非晶碳材质的接触牺牲图形 3 A。 随后， 采用 HF基腐蚀液去除氧化硅材质的垫氧化层 4。 由此， 去除了接触牺 牲图形之后，留下了源漏接触沟槽 3D (先前接触牺牲图形 3A所占据的空间）， 暴露了衬底 1、 源漏延伸区 1A、 部分 STI2、 以及源漏接触侧墙 5。
[0034]参照图 13以及图 10〜图 12 , 在源漏接触沟槽中形成源漏接触。
[0035]如图 10所示， 优选地， 执行源漏注入形成源漏重掺杂区 1D, 注入离子 种类与轻掺杂注入形成源漏延伸区 1 A的种类相同、 与 Halo源漏掺杂区 1B的 种类不同， 但是注入剂量、 能量更大， 从而获得结深更大、 浓度更高的源漏 重掺杂区 1C。 可选地， 采用选择性外延的方式在源漏接触沟槽 3D中、 衬底 1 上形成提升源漏 （未示出）。 在形成源漏外延区的同时执行原位掺杂， 或者 在形成源漏外延区之后执行注入掺杂并退火激活。
[0036]在源漏接触沟槽 3D中溅射、 蒸发形成金属薄层（未示出）， 例如是 Ni、 Pt、 Co、 Ti及其组合， 然后快速退火或者低温退火（400 ~ 600°C ), 使得金 属薄层与衬底 1、 源漏区中的 Si反应形成金属硅化物 10, 用于进一步降低接 触电阻。 剥除未反应的金属薄层。 此时由于氧化物材料的 STI2、 氮化硅材质 的源漏接触侧墙 5与金属薄层不反应， 因此金属硅化物 10仅形成在衬底 1 (源 漏重掺杂区 1C ) 中。
[0037]如图 11所示，在源漏接触沟槽 3D中金属硅化物 10上依次沉积 TiN、 TaN 的材质的阻挡层 11A (衬垫层） 以及 W、 Al、 Mo、 Ti等材质的填充层 11B, 以形成了源漏接触 11。 优选地， 采用 CMP等工艺平坦化阻挡层 11A/填充层 11B, 直至暴露栅极堆叠结构的栅极导电层 9 (电阻调节层 9B )。 此时， 源漏 接触 11与栅极堆叠结构之间的间距仅为源漏接触侧墙 5的厚度， 该间距大幅 减小了； 此外， 源漏接触 11覆盖了整个源漏区， 其面积较之现有技术大幅提 升。 因此， 依照本发明的这种大面积源漏接触有效降低了寄生电阻。
[0038]如图 12所示， 完成后续工艺。 例如在整个器件上沉积例如氮化硅材质 的第二 ILD 12, 刻蚀 ILD 12形成源漏接触孔， 在源漏接触孔中填充金属材料 形成第二源漏接触 11C, 在整个器件上沉积例如为氧化硅的第三 ILD 13 , 刻 蚀形成互连孔， 在互连孔中沉积 Al、 Ti等金属形成互连线 14。
[0039]依照本发明的半导体器件制造方法，通过接触牺牲层工艺有效降低了 栅极侧墙与接触区域之间的间距， 并且增大了接触区域面积， 从而有效减小 了器件寄生电阻。
[0040]尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可 以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变 和等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材料的 修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作为用于实现 本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造 方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括：
在衬底上形成接触牺牲图形， 覆盖源区与漏区并且暴露栅极区域； 在衬底上形成层间介质层， 覆盖接触牺牲图形并且暴露栅极区域； 在暴露的栅极区域中形成栅极堆叠结构；
去除接触牺牲图形， 留下了源漏接触沟槽；
在源漏接触沟槽中形成源漏接触。
2. 如权利要求 1的半导体器件制造方法， 其中， 衬底中还包括浅沟槽 隔离， 接触牺牲图形暴露了部分浅沟槽隔离。
3. 如权利要求 2的半导体器件制造方法， 其中， 层间介质层覆盖了部 分浅沟槽隔离。
4. 如权利要求 1的半导体器件制造方法， 其中， 形成接触牺牲图形之 后、形成层间介质层之前，还包括在接触牺牲图形侧面上形成源漏接触侧墙。
5. 如权利要求 4的半导体器件制造方法， 其中， 源漏接触侧墙为氮化 硅、 氮氧化硅。
6. 如权利要求 1的半导体器件制造方法， 其中， 形成接触牺牲图形之 后， 还包括在衬底中形成轻掺杂的源漏延伸区和晕状源漏掺杂区。
7. 如权利要求 1的半导体器件制造方法， 其中， 形成栅极堆叠结构包 括在暴露的栅极区域中沉积高 k材料的栅极绝缘层、 金属氮化物的功函数调 节层以及金属的电阻调节层。
8. 如权利要求 7的半导体器件制造方法， 其中， 形成栅极堆叠结构之 后还包括平坦化电阻调节层、 功函数调节层、 层间介质层直至暴露接触牺牲 图形。
9. 如权利要求 1的半导体器件制造方法， 其中， 形成源漏接触的步骤 进一步包括：
在源漏接触沟槽中暴露的衬底中形成源漏重掺杂区；
在源漏重掺杂区中形成金属硅化物；
在源漏接触沟槽中金属硅化物上依次沉积衬垫层和填充层； 平坦化填充层和衬垫层直至暴露栅极堆叠结构。
10. 如权利要求 9的半导体器件制造方法， 其中， 平坦化填充层和衬垫 层之后， 进一步包括： 沉积第二层间介质层； 刻蚀第二层间介质层形成源漏 接触孔， 在源漏接触孔中填充形成第二源漏接触； 沉积第三层间介质层； 刻 蚀第三层间介质层形成互连孔， 在互连孔中填充形成互连线。
11. 如权利要求 9的半导体器件制造方法， 其中， 形成金属硅化物的步 骤进一步包括： 在源漏接触沟槽中沉积金属层， 退火使得金属层与衬底中硅 反应形成金属硅化物， 剥除未反应的金属层。
12. 如权利要求 1的半导体器件制造方法， 其中， 接触牺牲图形为多晶 硅、 非晶硅、 非晶碳及其组合。
13. 如权利要求 1的半导体器件制造方法， 其中， 接触牺牲图形与衬底 之间还包括垫氧化层。
PCT/CN2012/079717 2012-07-13 2012-08-06 半导体器件制造方法 Ceased WO2014008698A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/414,355 US9614050B2 (en) 2012-07-13 2012-08-06 Method for manufacturing semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210245140.6A CN103545188B (zh) 2012-07-13 2012-07-13 半导体器件制造方法
CN201210245140.6 2012-07-13

Publications (1)

Publication Number Publication Date
WO2014008698A1 true WO2014008698A1 (zh) 2014-01-16

Family

ID=49915347

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/079717 Ceased WO2014008698A1 (zh) 2012-07-13 2012-08-06 半导体器件制造方法

Country Status (3)

Country Link
US (1) US9614050B2 (zh)
CN (1) CN103545188B (zh)
WO (1) WO2014008698A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578991B (zh) * 2012-07-24 2017-12-12 中国科学院微电子研究所 半导体器件制造方法
CN104900501B (zh) * 2014-03-04 2017-11-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
CN105632906B (zh) * 2014-10-27 2019-10-29 中国科学院微电子研究所 自对准接触制造方法
CN105762189A (zh) * 2014-12-17 2016-07-13 中国科学院微电子研究所 半导体器件及其制造方法
CN105762187B (zh) * 2014-12-17 2020-01-03 中国科学院微电子研究所 半导体器件及其制造方法
US9755030B2 (en) 2015-12-17 2017-09-05 International Business Machines Corporation Method for reduced source and drain contact to gate stack capacitance
WO2018052760A1 (en) * 2016-09-13 2018-03-22 Applied Materials, Inc. Borane mediated dehydrogenation process from silane and alkylsilane species for spacer and hardmask application
US10833017B2 (en) 2016-09-13 2020-11-10 Qualcomm Incorporated Contact for semiconductor device
US9911736B1 (en) 2017-06-14 2018-03-06 Globalfoundries Inc. Method of forming field effect transistors with replacement metal gates and contacts and resulting structure
EP3787006A1 (en) * 2019-08-30 2021-03-03 Imec VZW Contact isolation in semiconductor devices
CN110634801B (zh) * 2019-10-18 2022-04-22 中国科学院微电子研究所 一种接触孔制备方法
US11784228B2 (en) * 2021-04-09 2023-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process and structure for source/drain contacts
US20230050925A1 (en) * 2021-08-12 2023-02-16 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
CN115706053A (zh) * 2021-08-12 2023-02-17 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN120730765B (zh) * 2025-08-28 2025-11-25 合肥晶合集成电路股份有限公司 半导体器件制备方法及半导体器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339001B1 (en) * 2000-06-16 2002-01-15 International Business Machines Corporation Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist
CN1477719A (zh) * 2003-06-03 2004-02-25 北京大学 电学感应源漏扩展区mos晶体管及其制作方法
CN101000925A (zh) * 2006-01-09 2007-07-18 国际商业机器公司 场效应晶体管及其形成方法
CN102386217A (zh) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 栅极堆叠结构及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037232A (en) * 1997-09-15 2000-03-14 Advanced Micro Devices Semiconductor device having elevated silicidation layer and process for fabrication thereof
US6190980B1 (en) * 1998-09-10 2001-02-20 Advanced Micro Devices Method of tilted implant for pocket, halo and source/drain extension in ULSI dense structures
US6159835A (en) * 1998-12-18 2000-12-12 Texas Instruments Incorporated Encapsulated low resistance gate structure and method for forming same
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
JP2002141503A (ja) * 2000-08-24 2002-05-17 National Institute Of Advanced Industrial & Technology 自己整合型トランジスタの製造方法
US6506639B1 (en) * 2000-10-18 2003-01-14 Advanced Micro Devices, Inc. Method of forming low resistance reduced channel length transistors
DE102005046978B4 (de) * 2005-09-30 2007-10-04 Advanced Micro Devices, Inc., Sunnyvale Technik zum Erzeugen einer unterschiedlichen mechanischen Verformung durch Bilden eines Kontaktätzstoppschichtstapels mit unterschiedlich modifizierter innerer Verspannung
KR101615654B1 (ko) * 2010-05-14 2016-05-12 삼성전자주식회사 반도체 소자의 형성방법
CN102468326B (zh) * 2010-10-29 2015-01-07 中国科学院微电子研究所 接触电极制造方法和半导体器件
US8546211B2 (en) * 2010-11-17 2013-10-01 International Business Machines Corporation Replacement gate having work function at valence band edge
US8546212B2 (en) * 2011-12-21 2013-10-01 United Microelectronics Corp. Semiconductor device and fabricating method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339001B1 (en) * 2000-06-16 2002-01-15 International Business Machines Corporation Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist
CN1477719A (zh) * 2003-06-03 2004-02-25 北京大学 电学感应源漏扩展区mos晶体管及其制作方法
CN101000925A (zh) * 2006-01-09 2007-07-18 国际商业机器公司 场效应晶体管及其形成方法
CN102386217A (zh) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 栅极堆叠结构及其制作方法

Also Published As

Publication number Publication date
US9614050B2 (en) 2017-04-04
CN103545188A (zh) 2014-01-29
CN103545188B (zh) 2017-03-08
US20150200269A1 (en) 2015-07-16

Similar Documents

Publication Publication Date Title
CN103545188B (zh) 半导体器件制造方法
CN103390644B (zh) 半导体器件及其制造方法
KR101815527B1 (ko) 반도체 소자 및 그 제조 방법
CN104112665B (zh) 半导体器件及其制造方法
US8835232B2 (en) Low external resistance ETSOI transistors
CN103578991B (zh) 半导体器件制造方法
US9240454B1 (en) Integrated circuit including a liner silicide with low contact resistance
US20130020658A1 (en) Replacement gate electrode with planar work function material layers
CN103545208B (zh) 半导体器件制造方法
US20140103404A1 (en) Replacement gate with an inner dielectric spacer
WO2013053085A1 (zh) 半导体器件及其制造方法
US9385212B2 (en) Method for manufacturing semiconductor device
CN103390556B (zh) 半导体器件制造方法
CN103531455B (zh) 半导体器件及其制造方法
CN104167357B (zh) 半导体器件及其制造方法
CN103811543B (zh) 半导体器件及其制造方法
CN103730498B (zh) 半导体器件及其制造方法
CN103681291B (zh) 一种金属硅化物的形成方法
CN104124164A (zh) 半导体器件及其制造方法
CN105762187B (zh) 半导体器件及其制造方法
CN105529327B (zh) Cmos器件及其制造方法
CN104218081A (zh) 半导体器件及其制造方法
CN103594511B (zh) 半导体器件及其制造方法
CN104064462A (zh) 半导体器件制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12880946

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14414355

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12880946

Country of ref document: EP

Kind code of ref document: A1