CN103578991B - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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CN103578991B
CN103578991B CN201210258807.6A CN201210258807A CN103578991B CN 103578991 B CN103578991 B CN 103578991B CN 201210258807 A CN201210258807 A CN 201210258807A CN 103578991 B CN103578991 B CN 103578991B
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CN103578991A (zh
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尹海洲
张珂珂
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Institute of Microelectronics of CAS
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Priority to US14/416,698 priority patent/US20150187892A1/en
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Abstract

本发明公开了一种半导体器件制造方法，包括：在衬底上形成接触牺牲层，刻蚀接触牺牲层形成接触牺牲图形，其中接触牺牲图形覆盖源区与漏区并且具有暴露衬底的栅极沟槽；在栅极沟槽中形成栅极侧墙和栅极堆叠结构；部分或者完全刻蚀去除覆盖源区与漏区的接触牺牲图形，形成源漏接触沟槽；在源漏接触沟槽中形成源漏接触。依照本发明的半导体器件制造方法，通过双层接触牺牲层工艺有效降低了栅极侧墙与接触区域之间的间距，并且增大了接触区域面积，从而有效减小了器件寄生电阻。

Description

半导体器件制造方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种具有增大接触区域的MOSFET的制造方法。
背景技术
随着MOSFET的特征尺寸持续缩减，寄生电阻在器件的总电阻中占据的比重越来越大，严重制约了小尺寸器件性能的提升。现有的降低寄生电阻的结构/方法包括形成提升源漏、在源漏区中/上形成金属硅化物、提高接触面积等等。
然而，无论采用何种结构/方法，源/漏区的接触区域(或接触孔，CA)与栅极侧墙之间仍然有较大的间距，电子/空穴的载流子从源区穿越沟道区达到漏区的距离仍然较大，因此寄生电阻依然无法有效的减小，器件性能提升程度有限。
发明内容
有鉴于此，本发明的目的在于采用新的制造方法以接触牺牲层工艺代替传统的替代栅工艺，大幅减小接触区域与栅极之间的间距，从而有效地减小器件寄生电阻。
实现本发明的上述目的，是通过提供一种半导体器件制造方法，包括：在衬底上形成接触牺牲层，刻蚀接触牺牲层形成接触牺牲图形，其中接触牺牲图形覆盖源区与漏区并且具有暴露衬底的栅极沟槽；在栅极沟槽中形成栅极侧墙和栅极堆叠结构；部分或者完全刻蚀去除覆盖源区与漏区的接触牺牲图形，形成源漏接触沟槽；在源漏接触沟槽中形成源漏接触。
其中，接触牺牲层包括第一接触牺牲层和第二接触牺牲层。
其中，第一接触牺牲层包括应变Si、SiGe、Si：C、多晶硅、非晶硅、微晶硅、非晶碳、氧化硅、氮化硅及其组合，第二接触牺牲层包括单晶硅、多晶硅、非晶硅、微晶硅、非晶碳、氧化硅、氮化硅及其组合。
其中，形成源漏接触沟槽的步骤包括：部分刻蚀去除第二接触牺牲层；或者完全刻蚀去除第二接触牺牲层以及部分刻蚀去除第一接触牺牲层；或者完全刻蚀去除第二接触牺牲层和第一接触牺牲层；或者完全刻蚀去除第二接触牺牲层和第一接触牺牲层以及部分刻蚀衬底。
其中，通过外延生长形成接触牺牲层并且掺杂具有第一导电类型。
其中，形成接触牺牲层之后，刻蚀接触牺牲层以及衬底形成浅沟槽，在浅沟槽中填充绝缘材料形成浅沟槽隔离。
其中，形成栅极沟槽之后，刻蚀浅沟槽隔离使其在有源区宽度方向上向隔离区倾斜。
其中，刻蚀形成接触牺牲图形之后，在栅极沟槽两侧衬底中形成轻掺杂源漏区。
其中，形成栅极堆叠结构包括在栅极沟槽中沉积高k材料的栅极绝缘层、金属氮化物的功函数调节层以及金属的电阻调节层。
其中，形成源漏接触的步骤进一步包括：在源漏接触沟槽中形成金属硅化物；在金属硅化物上依次沉积衬垫层和填充层；平坦化填充层和衬垫层直至暴露栅极堆叠结构。
依照本发明的半导体器件制造方法，通过双层接触牺牲层工艺有效降低了栅极侧墙与接触区域之间的间距，并且增大了接触区域面积，从而有效减小了器件寄生电阻。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图9为根据本发明的半导体器件制造方法各个步骤的剖视图；以及
图10为根据本发明的半导体器件制造方法的流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
参照图10以及图1～图4，在衬底上形成接触牺牲图形，覆盖源区与漏区并且暴露栅极区域。
如图1所示，在衬底1上依次形成第一接触牺牲层2和第二接触牺牲层3。提供衬底1，其材质可以是(体)Si(例如单晶Si晶片)、SOI、单晶Ge、GeOI(绝缘体上Ge)，也可以是其他化合物半导体，例如GaAs、SiGe、GeSn、InP、InSb、GaN等等。优选地，衬底1选用体Si或SOI，以便与CMOS工艺兼容。
采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规方法并合理控制工艺参数，在衬底1上外延生长了第一接触牺牲层2。第一接触牺牲层2用于稍后器件的实际源漏区(作为提升源漏的一部分)，其材质可以是应变Si、SiGe、Si：C及其组合，其厚度例如是10～100nm。由于第一接触牺牲层2的材质与衬底1的材质之间晶格常数不同，可以向沟道区引入应力，因此有助于提高载流子迁移率进而提高器件驱动能力。优选地，通过外延生长同时原位掺杂或者外延生长后额外的离子注入工艺，使得第一接触牺牲层2具有第一导电类型，例如n或者p。此外，第一接触牺牲层2还可以是多晶硅、非晶硅、微晶硅、非晶碳、氧化硅、氮化硅等，此时第一接触牺牲层2将在稍后的图7所示形成源漏接触沟槽的过程中完全去除。
随后，通过类似的外延工艺，在第一接触牺牲层2之上再外延形成第二接触牺牲层3，用于限定稍后要形成源漏接触的区域，与后栅工艺中假栅极所起的作用类似，因此也可以称作假源漏接触区。第二接触牺牲层3材质可以与衬底1相同例如均为Si(可以是单晶硅，也可以是多晶硅、非晶硅、微晶硅，此时第二接触牺牲层3在后续工艺中不被完全刻蚀去除而是保留一部分用作提升源漏区的一部分)，材质也可以不同，例如为非晶碳、氮化硅、氧化硅、氮氧化硅(此时第二接触牺牲层3在后续工艺中将刻蚀完全去除而直至暴露第一接触牺牲层2)。第二接触牺牲层3厚度要大于第一接触牺牲层2，并且优选的是40～500nm。第一接触牺牲层2与第二接触牺牲层3的厚度之和要大于稍后要形成的栅极的高度，例如是50～500nm。优选地，当第二接触牺牲层3材质包括Si时(也即稍后将要保留一部分用作提升源漏区的一部分时)，通过外延生长同时原位掺杂或者外延生长后额外的离子注入工艺，使得第二接触牺牲层3也具有第一导电类型并且浓度更高，例如n+或者p+。
如图2所示，形成浅沟槽隔离(STI)4。利用传统的光刻/刻蚀技术，依次刻蚀穿透第二接触牺牲层3、第一接触牺牲层2，以及部分刻蚀衬底1，形成浅沟槽(未示出)。通过PECVD、H DPCVD、RTO(快速热氧化)、MBE、ALD等方法，在浅沟槽中沉积填充氧化硅或者氮氧化硅材质的绝缘膜，从而构成浅沟槽隔离(STI)4。此外优选地，STI4的填充的隔离氧化物还可以是100K的温度下线性体积膨胀系数的绝对值大于10-4/K的巨热膨胀介质材料，例如包括Bi0.95La0.05NiO3、BiNiO3、ZrW2O8等的钙钛矿型氧化物，或者诸如Ag3[Co(CN)6]的框架材料。这些巨热膨胀介质材料可以向有源区施加应力，进一步增大载流子迁移率，提高器件性能。STI4的剖面形状不限于图2中所示的上宽下窄的梯形，还可以是上下等宽的矩形、或者是上窄下宽的梯形(以增大有源区下部的应力)。
如图3所示，刻蚀第二接触牺牲层3和第一接触牺牲层2通过栅极沟槽6暴露栅极区域，而形成了接触牺牲图形。在整个器件上旋涂光刻胶层5并曝光显影形成光刻胶图形，仅暴露未来要形成栅极堆叠结构的区域。随后，采用各向异性的刻蚀，例如等离子刻蚀、反应离子刻蚀等干法刻蚀，或者TMAH(针对Si材料)、强酸(HF)与强氧化剂(硫酸、双氧水)组合(针对SiGe材料)等湿法刻蚀，刻蚀第二接触牺牲层3以及第一接触牺牲层2直至暴露衬底1，形成了栅极沟槽6。其中，栅极沟槽6的宽度要等于稍后要形成的栅极堆叠结构(栅极绝缘层以及栅极导电层)的实际宽度与栅极侧墙的宽度之和。剩余的第二接触牺牲层3和第一接触牺牲层2继续覆盖了未来器件的源区和漏区。
优选地，执行源漏轻掺杂工艺，在衬底中形成源漏轻掺杂区。例如以光刻胶图形5及其下方的接触牺牲层3/2为掩模，采用低剂量、低能量的倾斜源漏离子注入，利用阴影效应(Shadow Effect)控制了掺杂剂注入位置而形成了轻掺杂的源漏延伸区1A、以及源漏延伸区1A下方衬底中的晕状(Halo)源漏掺杂区1B。随后快速退火(例如激光快速退火)以激活掺杂剂。掺杂离子的种类、剂量、浓度依照器件电学性能需要而设定。此外，可选地，在栅极沟槽6中在接触牺牲层3/2两侧，形成含有扩散源的侧墙，通过例子扩散作用形成轻掺杂的源漏延伸区1A，随后将该层侧墙去除。
如图4所示，为图3去除顶部光刻胶图形5之后的顶视图。其中，执行STI刻蚀工艺，使得如图中所示的STI4暴露于栅极沟槽6部分的侧面向浅沟槽隔离区倾斜而不是向栅极沟槽6倾斜，以避免在STI4上形成栅极侧墙。
参照图10以及图5，在栅极沟槽6中形成栅极侧墙7。通过PECVD、HDPCVD、MBE、ALD、(磁控)溅射等方法沉积例如为氮化硅、氮氧化硅、类金刚石无定形碳(DLC)的绝缘材质并且随后刻蚀形成了栅极侧墙7，位于栅极沟槽6中沿有源区长度方向(沟道区方向)的两个侧面上，并且与第一和第二接触牺牲层2/3接触。由于栅极沟槽6中沿有源区宽度方向(器件延伸方向)的STI4向浅沟槽隔离区倾斜，两个侧面上的绝缘材质被完全刻蚀，而不会形成栅极侧墙。栅极侧墙7的厚度依照栅极绝缘隔离性能需要而设定，例如为5～30nm。
参照图10以及图6，在栅极沟槽6中形成栅极堆叠结构8/9。通过PECVD、HDPCVD、MOCVD、MBE、ALD等方法，在栅极沟槽6底部与衬底1接触的面上沉积形成栅极绝缘层8。栅极绝缘层8的材质为高k材料，包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))。随后，通过PECVD、MOCVD、MBE、ALD、蒸发、溅射等方法在第二接触牺牲层3上以及栅极沟槽6中沉积栅极导电层9。栅极导电层9优选地包括材质为TiN、TaN等金属氮化物的功函数调节层9A，以及材质为Cu、Al、Ti、Mo、Ta、W等金属的电阻调节层9B。栅极绝缘层8与栅极导电层9A/9B共同构成栅极堆叠结构。随后采用回刻工艺或者CMP工艺，平坦化栅极导电层9A/9B直至暴露第二接触牺牲层3。
参照图10以及图7，部分或者完全去除接触牺牲图形，形成源漏接触沟槽，在源漏接触沟槽中形成金属硅化物。例如采用TMAH等各向异性的湿法腐蚀液，刻蚀去除单晶硅、多晶硅、非晶硅、微晶硅等硅基材质的第二接触牺牲层3，或者采用氧等离子刻蚀去除非晶碳材质的第二接触牺牲层3。由此，部分(或者完全)去除了第二接触牺牲层3之后，留下了源漏接触沟槽3A，暴露了剩余的第二接触牺牲层以及栅极侧墙7。根据本发明一个实施例的如图7所示的源漏接触沟槽3A深度小于第二接触牺牲层3的原始厚度，也即仅部分去除了第二接触牺牲层3(此时剩余的部分第二接触牺牲层3将要作为未来源漏区的一部分或者作为源漏接触之一，因此其材质优选的为硅基材质)。但是在本发明其他实施例中，源漏接触沟槽3A的深度可以大于第二接触牺牲层3的原始厚度。具体地，可以完全去除第二接触牺牲层3(未示出，此时第二接触牺牲层3可以是非晶碳等其他材质，甚至可以是氮化硅)，还可以继续刻蚀去除部分或者全部的第一接触牺牲层2(未示出，此时第一接触牺牲层2将不再用于源漏区一部分，因此材质不必为SiGe、SiC等)，甚至可以进一步刻蚀去除部分衬底1，形成的源漏接触沟槽3A深入衬底(此时可以在深沟槽中外延形成SiGe、SiC并且进一步形成提升源漏)。
特别地，若完全去除第二接触牺牲层3及第一接触牺牲层2(或外延生长接触牺牲层2/3过程中没有进行原位掺杂并且外延生长后没有进行额外的离子注入)，对源漏接触沟槽3A中暴露的衬底(或第二接触牺牲层3和/或第一接触牺牲层2)进行重掺杂，使其形成n+或者p+型的重掺杂区，以作为源漏重掺杂区。
此后，在源漏接触沟槽3A中溅射、蒸发形成金属薄层(未示出)，例如是Ni、Pt、Co、Ti及其组合，然后快速退火或者低温退火(400～600℃)，使得金属薄层与源漏区中的Si反应形成金属硅化物10，用于进一步降低接触电阻。剥除未反应的金属薄层。此时由于氧化物材料的STI4、氮化硅材质的栅极侧墙7与金属薄层不反应，因此金属硅化物10仅形成在源漏区中。
参照图10和图8，在源漏接触沟槽3A中金属硅化物10上依次沉积TiN、TaN的材质的阻挡层11A(衬垫层)以及W、Al、Mo、Ti等材质的填充层11B，以形成了源漏接触11。优选地，采用CM P等工艺平坦化阻挡层11A/填充层11B，直至暴露栅极堆叠结构的栅极导电层9(电阻调节层9B)。此时，源漏接触11与栅极堆叠结构之间的间距仅为栅极侧墙7的厚度，该间距大幅减小了；此外，源漏接触11覆盖了整个源漏区，其面积较之现有技术大幅提升。因此，依照本发明的这种大面积源漏接触有效降低了寄生电阻。
参照图10和图9，完成后续工艺。例如在整个器件上沉积氧化硅、氮化硅、低k材质的层间介质层(ILD)12，刻蚀ILD12形成源漏接触孔，在源漏接触孔中填充金属材料形成第二源漏接触11C，在整个器件上沉积例如为氧化硅、氮化硅或者其他低k材料并且与ILD12材质不同的第二ILD13，刻蚀形成互连孔，在互连孔中沉积Al、Ti等金属形成互连线14。
依照本发明的半导体器件制造方法，通过双层接触牺牲层工艺有效降低了栅极侧墙与接触区域之间的间距，并且增大了接触区域面积，从而有效减小了器件寄生电阻。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (9)

1.一种半导体器件制造方法，包括：
在衬底上形成接触牺牲层，刻蚀接触牺牲层形成接触牺牲图形，其中接触牺牲图形覆盖源区与漏区并且具有暴露衬底的栅极沟槽，其中接触牺牲图形作为提升源漏的一部分，其中接触牺牲层包括第一接触牺牲层和第二接触牺牲层，第一接触牺牲层的材质与衬底的材质之间晶格常数不同以向沟道区引入应力；
在栅极沟槽中形成栅极侧墙和栅极堆叠结构；
部分刻蚀去除覆盖源区与漏区的接触牺牲图形，形成源漏接触沟槽；
在源漏接触沟槽中形成源漏接触。
2.如权利要求1的半导体器件制造方法，其中，第一接触牺牲层包括应变Si、SiGe、Si:C、多晶硅、非晶硅、微晶硅及其组合，第二接触牺牲层包括单晶硅、多晶硅、非晶硅、微晶硅、非晶碳、氧化硅、氮化硅及其组合。
3.如权利要求1的半导体器件制造方法，其中，形成源漏接触沟槽的步骤包括：部分刻蚀去除第二接触牺牲层；或者完全刻蚀去除第二接触牺牲层以及部分刻蚀去除第一接触牺牲层。
4.如权利要求1的半导体器件制造方法，其中，通过外延生长形成接触牺牲层并且掺杂具有第一导电类型。
5.如权利要求1的半导体器件制造方法，其中，形成接触牺牲层之后，刻蚀接触牺牲层以及衬底形成浅沟槽，在浅沟槽中填充绝缘材料形成浅沟槽隔离。
6.如权利要求5的半导体器件制造方法，其中，形成栅极沟槽之后，刻蚀浅沟槽隔离使其在有源区宽度方向上向隔离区倾斜。
7.如权利要求1的半导体器件制造方法，其中，刻蚀形成接触牺牲图形之后，在栅极沟槽两侧衬底中形成轻掺杂源漏区。
8.如权利要求1的半导体器件制造方法，其中，形成栅极堆叠结构包括在栅极沟槽中沉积高k材料的栅极绝缘层、金属氮化物的功函数调节层以及金属的电阻调节层。
9.如权利要求1的半导体器件制造方法，其中，形成源漏接触的步骤进一步包括：
在源漏接触沟槽中形成金属硅化物；
在金属硅化物上依次沉积衬垫层和填充层；
平坦化填充层和衬垫层直至暴露栅极堆叠结构。
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