Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
  • H04B10/60—Receivers
  • H04B10/66—Non-coherent receivers, e.g. using direct detection
  • H04B10/69—Electrical arrangements in the receiver
  • H04B10/697—Arrangements for reducing noise and distortion
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
  • H04B10/60—Receivers
  • H04B10/66—Non-coherent receivers, e.g. using direct detection
  • H04B10/69—Electrical arrangements in the receiver
  • H04B10/691—Arrangements for optimizing the photodetector in the receiver
  • H04B10/6911—Photodiode bias control, e.g. for compensating temperature variations

Definitions

• the present invention generally relates to the technical field of serialized optical and / or electrical signal connections; More particularly, the present invention relates to a circuit arrangement according to the preamble of claim 1 and a method according to the
• the data stream initially not preconditioned for the optical transmission is as a rule DC unbalanced, that is to say that the logical "1" and the logical "0" in the data stream arriving through the optical transmission do not generally occur uniformly by means of conventionally employed methods, it can not be properly extracted at which voltage level of the incoming data stream the middle lies between the logical "1" and logic "0".
• a DC current compensation can now be controlled automatically depending on the input data, but this is associated with a certain circuit complexity, which delays the processing of the incoming signals.
• the present invention has the object, a circuit arrangement according to the preamble of claim 1 and a method according to the preamble of claim 1 1 educate so that any digital optical data streams in the bandwidth range from zero bits per second to the high Gbit / s range with the lowest possible circuit complexity and processed with the least possible expenditure of energy for further processing.
• the present invention in a circuit arrangement and in a method for receiving digital optical signals by means of at least one at least one signal input terminal upstream light-receiving device, in particular by means of at least one photodiode, coming from the light-receiving device through the signal input terminal unipolar Current signal by means of a provided by at least one current source compensation current whose value is defined by means of at least one digital register, converted into a bipolar current signal.
• the present invention is based on a static adjustment, in particular static
• the D [irect] C [urrent] - Kompensationsstroms this compensation current in a preferred manner by at least one static digital signal, in particular by at least one static digital data word, for example, with a length of more than one bit , adjusted or adapted and / or can be determined.
• At least one current source formed as, for example, 9-bit programmable current-to-digital-to-analog converter or current-to-digital converter can be controlled and / or that the DC compensation current is provided in such a way that the unipolar current signal available at the signal input terminal is converted into a bipolar current signal.
• the DC compensation current signal of suitable size by means of the current DAC from the signal input terminal against a reference potential or reference potential (GND), in particular against ground potential or ground potential or zero potential, passed or “dropped" (the technical term
• the setting or control or regulation of the input DC current compensation thus does not take place as a function of the input data, but rather by fixed values which are defined, in particular predetermined, by the digital register.
• any digital optical data stream can be converted and conditioned such that a differential load of, for example, one hundred ohms can be driven at the output of the opto-electrical converter such that a differential voltage signal of, for example, + / -200 millivolts is provided.
• the digital register has at least one memory controller that is at least one, in particular programmable and / or in particular circuit-internal, memory module volatile and / or non-volatile type can access in such a way that the memory module can be controlled and / or programmed by the memory controller.
• circuit arrangement is modified in characteristic details such that it can be used for specific logic levels, for example for logic "0" or for logic "1", of the input current signal on
• Signal input terminal is optimally set, for example, finds the, in particular arithmetic and / or geometric particular, average value between the high optical input power (logical "1") and the low optical input power (logic "0"), from which the value of the DC compensation which in turn is subtracted from the unipolar current input signal coming through the signal input terminal to further the bipolar current signal
• the gain (so-called TIA gain) of at least one input stage connected downstream of the signal input terminal and designed as a transimpedance amplifier can be determined by means of at least one, for example 2-bit programmable, voltage-digital-analog converter or voltage D [digital-to -] A [nalog] C [onverter].
• a single programming is sufficient in the construction of the optical transmission link to ensure a correct function of the opto-electrical converter according to the present invention.
• circuit arrangement according to the present invention as well as the method according to the present invention represent a possibility of optically transmitting both uncoded DC signals and highest frequency data over the same transmission channel.
• the receiver part of the circuit arrangement and its mode of operation make it possible to receive an arbitrarily coded or uncoded, non-DC-balanced, serial bit stream of an optical data transmission link error-free. Unlike solutions from the state of
• the circuit arrangement according to the present invention and the method according to the present invention offer the possibility of processing a bit stream in an energy-saving manner and with significantly reduced circuit complexity in the data processing.
• the present invention relates to the use of at least one circuit arrangement according to the type set out above and / or a method according to the above-described type for the opto-electrical conversion of high bit rate serial digital optical signals.
• Fig. 1 in conceptual schematic representation of an embodiment of a circuit arrangement according to the present invention, which operates according to the method according to the present invention.
• the circuit arrangement E illustrated in FIG. 1 By means of the circuit arrangement E illustrated in FIG. 1 according to the present invention, digital optical signals S can be received.
• the circuit arrangement E is a light-receiving component in the form of a photodiode PD in front of a
• the photodiode PD is preceded by a filter input terminal FILT, which via a
• Vs upp iy is assigned, which can move by way of example in the range between about 2.5 volts and about 3.3 volts.
• the filter plate R F facing away from the capacitor plate of the filter capacitor C F is at reference or reference potential GND, in particular at ground potential or ground potential or zero potential.
• a voltage regulator VR is additionally provided in Fig. 1.
• the circuit E in particular a the
• a differential voltage signal of, for example, +/- 200 millivolts can be available and / or
• a differential load of, for example, one hundred ohms can be driven.
• the transimpedance input stage IS is followed by a pre- or intermediate stage PS, by means of which the amplitude of the output signal of the transimpedance input stage IS can be adjusted such that the amplitude of this signal is as large as possible, but the signal itself still has the highest possible degree of signal integrity that is not appreciably jittered by distortion.
• a compensation current I DC which can be provided by a current source IDAC, by means of which the unipolar current signal I PD coming from the light-receiving component PD through the signal input terminal PiN-signai can be converted into a bipolar current signal I PD -I D c, according to FIG 1, a digital register MM, MC is provided which
• MC memory controller
• this memory controller MC which is assigned an interface or interface IF for setting and / or changing digital values, the signal input terminal PiN-signai for specific logic levels, in particular for logic "0" or logic "1", the incoming unipolar current signal l PD .
• a diagnostic connection of the circuit arrangement E is arranged in FIG. 1 adjacent to the interface IF.
• the current-to-digital-to-analog converter IDAC is acted upon by the digital register MM, MC with a static digital signal in the form of a multi-bit data word.
• Analog converter IDAC converts the (digital) information contained in this data word into the (analogue) D [irect] C [urrent] compensation current I DC ; in other words, the D [irect] C [urrent] compensation current I DC of the current-to-digital-to-analog converter IDAC is set and defined by this data word.
• the 9-bit programmable current-digital-analog converter IDAC is connected between the memory module MM of the digital register MM, MC, the signal input terminal PiN-signai and the reference or reference potential GND.
• a 2-bit programmable voltage-to-digital-to-analog converter VDAC may be connected between the memory module MM and the input terminal of the input stage IS in order to amplify (so-called TIA gain) the transimpedance Input stage IS adapt, in particular to control and / or to regulate.
• any digital data streams S for example, uncoded video signals, an optical transmission ungsumble of zero bits per second to the high Gbit / s Area are received.
• the circuit arrangement E can be part of the connection of two devices in a Centrai Office environment, for example at least one server with at least one network storage device (network storage device).
• GND reference potential or reference potential in particular ground potential or ground potential or zero potential
• IDAC power source in particular current-to-digital-to-analog converter, for example 9-bit programmable current-digital-analog converter
• l DC compensation current in particular adjustable and / or adaptable and / or determined by at least one static digital signal, for example by at least one static digital data word, such as more than one bit in length
• IS input stage in particular single-ended input stage, for example
• Transimpedance stage such as transimpedance amplifier or
• MC memory controller in particular memory controller module for driving and / or
• R F ohmic resistance, in particular ohmic filter resistance
• VDAC voltage digital-to-analog converter in particular 2-bit programmable voltage

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• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Optical Communication System (AREA)
• Amplifiers (AREA)
• Control Of Amplification And Gain Control (AREA)

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• 2013
  • 2013-05-22 WO PCT/DE2013/200015 patent/WO2013174376A2/de not_active Ceased
  • 2013-05-22 DE DE112013002641.4T patent/DE112013002641A5/de not_active Withdrawn
  • 2013-05-22 EP EP13756810.1A patent/EP2853046B1/de active Active
  • 2013-05-22 JP JP2015513017A patent/JP2015517774A/ja active Pending
• 2014
  • 2014-11-24 US US14/552,159 patent/US9425901B2/en active Active

Patent Citations (1)

Non-Patent Citations (1)

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