WO2013168237A1 - 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 - Google Patents
半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 Download PDFInfo
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- WO2013168237A1 WO2013168237A1 PCT/JP2012/061777 JP2012061777W WO2013168237A1 WO 2013168237 A1 WO2013168237 A1 WO 2013168237A1 JP 2012061777 W JP2012061777 W JP 2012061777W WO 2013168237 A1 WO2013168237 A1 WO 2013168237A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device.
- a semiconductor device manufacturing method is known in which a passivation glass layer is formed so as to cover a pn junction exposed portion in the process of manufacturing a mesa type semiconductor device (see, for example, Patent Document 1).
- FIGS. 14 and 15 are views for explaining such a conventional method of manufacturing a semiconductor device.
- 14 (a) to 14 (d) and FIGS. 15 (a) to 15 (d) are process diagrams.
- the conventional semiconductor device manufacturing method includes a “semiconductor substrate forming step”, “groove forming step”, “glass layer forming step”, “photoresist forming step”, and “oxide removal”. Step, “roughened region forming step”, “electrode forming step” and “semiconductor substrate cutting step” are included in this order.
- a conventional method for manufacturing a semiconductor device will be described in the order of steps.
- n + -type diffusion layer 912 is diffused from one surface of n ⁇ -type semiconductor substrate (n ⁇ -type silicon substrate) 910, and n-type impurities from the other surface are diffused.
- An n + -type diffusion layer 914 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 916 and 918 are formed on the surfaces of the p + type diffusion layer 912 and the n + type diffusion layer 914 by thermal oxidation (see FIG. 14A).
- oxide film 916 is etched using the photoresist 926 as a mask to remove the oxide films 916 and 918 in the portion 930 where the Ni plating electrode film is to be formed (see FIG. 15A). ).
- the mesa type semiconductor device (pn diode) 900 is manufactured by cutting the semiconductor substrate at the center of the glass layer 924 by dicing or the like to chip the semiconductor substrate (FIG. 15 ( See d).).
- the step of forming the groove 920 exceeding the pn junction from one surface of the semiconductor substrate on which the pn junction parallel to the main surface is formed (FIG. 14A and FIG.
- a step of forming a passivation glass layer 924 so as to cover the exposed portion of the pn junction inside the groove 920 (see FIG. 14C). Therefore, according to the conventional method for manufacturing a semiconductor device, a high-breakdown-voltage mesa semiconductor device can be manufactured by forming a passivation glass layer 924 in the groove 920 and then cutting the semiconductor substrate. .
- a glass material used for the glass layer for passivation (a) it can be fired at an appropriate temperature, (b) can withstand chemicals used in the process, and (c) silicon to prevent warping of the wafer during the process.
- the linear expansion coefficient is close to the linear expansion coefficient (particularly, the average linear expansion coefficient at 50 ° C. to 550 ° C. is close to the linear expansion coefficient of silicon) and (d) it must have excellent insulation properties. Therefore, conventionally, “glass materials mainly composed of lead silicate” have been widely used.
- glass material based on lead silicate contains lead with a large environmental load, and in the near future, the use of such “glass material based on lead silicate” is prohibited. It is thought that it will go.
- An object of the present invention is to provide a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device, which make it possible to manufacture the semiconductor device.
- [1] glass composition for protecting a semiconductor junction of the present invention at least SiO 2, and B 2 O 3, and Al 2 O 3, ZnO and, CaO, of MgO and at least two alkaline earth metals out of BaO
- a glass composition for protecting a semiconductor junction which contains an oxide and does not substantially contain Pb, As, Sb, Li, Na, and K, and has a temperature of 50 ° C. to 550 ° C.
- the average linear expansion coefficient in the range is in the range of 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 .
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is in the range of 3.33 ⁇ 10 ⁇ 6 to 4.08 ⁇ 10 ⁇ 6. It is preferable.
- the glass composition for protecting a semiconductor junction comprises at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, and at least two alkaline earth metals among CaO, MgO and BaO.
- a glass composition for protecting a semiconductor junction which contains an oxide and does not substantially contain Pb, As, Sb, Li, Na, and K, and the content of SiO 2 is 49 In the range of 0.5 mol% to 64.3 mol%, the content of B 2 O 3 is in the range of 8.4 mol% to 17.9 mol%, and the content of Al 2 O 3 is in the range of 3.7 mol% to It is in the range of 14.8 mol%, the content of ZnO is in the range of 3.9 mol% to 14.2 mol%, and the content of the alkaline earth metal oxide is 7.4 mol% to 12.9 mol% It is preferable to be within the range.
- the total value of the content of SiO 2 and the content of B 2 O 3 is preferably in the range of 65 mol% to 75 mol%.
- the glass composition for protecting a semiconductor junction according to the present invention preferably contains all of CaO, MgO and BaO as the oxide of the alkaline earth metal.
- the CaO content is in the range of 2.0 mol% to 5.3 mol%, and the MgO content is in the range of 1.0 mol% to 2.3 mol%.
- the BaO content is preferably in the range of 2.6 mol% to 5.3 mol%.
- the glass composition for protecting a semiconductor junction of the present invention preferably contains CaO and BaO as the oxide of the alkaline earth metal.
- the CaO content is in the range of 2.0 mol% to 7.6 mol%, and the BaO content is It is preferably in the range of 3.7 mol% to 5.9 mol%.
- the glass composition for protecting a semiconductor junction according to the present invention may further contain at least one metal oxide selected from the group consisting of nickel oxide, copper oxide, manganese oxide, and zirconium oxide. preferable.
- the content of at least one metal oxide selected from the group consisting of nickel oxide, copper oxide, manganese oxide and zirconium oxide is 0.00. It is preferably in the range of 01 mol% to 2.0 mol%.
- a method of manufacturing a semiconductor device includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion.
- the second step at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, CaO, MgO, and BaO are included in this order.
- a glass composition for protecting a semiconductor junction comprising at least two oxides of an alkaline earth metal and substantially free of Pb, As, Sb, Li, Na, and K.
- the glass layer is formed using a glass composition for protecting a semiconductor junction having an average coefficient of linear expansion in a temperature range of 50 ° C. to 550 ° C. within a range of 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6. It is characterized by .
- a method for manufacturing a semiconductor device includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion.
- the second step at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, CaO, MgO, and BaO are included in this order.
- a glass composition for protecting a semiconductor junction comprising at least two oxides of an alkaline earth metal and substantially free of Pb, As, Sb, Li, Na, and K.
- SiO 2 content is in the range of 49.5 mol% to 64.3 mol%
- B 2 O 3 content is in the range of 8.4 mol% to 17.9 mol%
- Al 2 O 3 Content is 3.7 mol% It is in the range of 14.8 mol%
- the content of ZnO is in the range of 3.9 mol% to 14.2 mol%
- the content of the alkaline earth metal oxide is 7.4 mol% to 12.9 mol%
- the glass layer is formed using a glass composition for protecting a semiconductor junction in the range of.
- the first step includes a step of preparing a semiconductor substrate having a pn junction parallel to the main surface, and the pn junction is exceeded from one surface of the semiconductor substrate. Forming the pn junction exposed portion in the groove by forming a groove having a depth, and the second step covers the pn junction exposed portion in the groove. It is preferable to include a step of forming a layer.
- the second step includes a step of forming the glass layer so as to directly cover the exposed pn junction in the trench.
- the second step includes a step of forming an insulating layer on the pn junction exposed portion in the trench, and the pn junction exposure through the insulating layer. And forming the glass layer so as to cover the portion.
- the first step includes a step of forming the pn junction exposed portion on the surface of the semiconductor substrate
- the second step includes the step of forming the pn junction on the surface of the semiconductor substrate. It is preferable to include a step of forming the glass layer so as to cover the pn junction exposed portion.
- the second step includes a step of forming the glass layer so as to directly cover the pn junction exposed portion on the surface of the semiconductor substrate.
- the second step includes a step of forming an insulating layer on the exposed portion of the pn junction on the surface of the semiconductor substrate, and the pn junction via the insulating layer. And a step of forming the glass layer so as to cover the exposed portion.
- a semiconductor device is a semiconductor device including a semiconductor element having a pn junction exposed portion from which a pn junction is exposed, and a glass layer formed so as to cover the pn junction exposed portion, wherein the glass layers, at least SiO 2, and B 2 O 3, contains a Al 2 O 3, and ZnO, CaO, and at least two oxides of alkaline earth metals of MgO and BaO, and a Pb,
- a glass composition for protecting a semiconductor junction which does not substantially contain As, Sb, Li, Na and K, and has an average linear expansion coefficient of 3.33 ⁇ 10 5 in a temperature range of 50 ° C. to 550 ° C. It is characterized by being formed using a glass composition for protecting a semiconductor junction in the range of ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 .
- a semiconductor device is a semiconductor device including a semiconductor element having a pn junction exposed portion from which a pn junction is exposed, and a glass layer formed so as to cover the pn junction exposed portion.
- layers, at least SiO 2, and B 2 O 3 contains a Al 2 O 3, and ZnO, CaO, and at least two oxides of alkaline earth metals of MgO and BaO, and a Pb
- a glass composition for protecting a semiconductor junction that does not substantially contain As, Sb, Li, Na, and K, and the content of SiO 2 is in the range of 49.5 mol% to 64.3 mol%.
- the content of B 2 O 3 is in the range of 8.4 mol% to 17.9 mol%
- the content of Al 2 O 3 is in the range of 3.7 mol% to 14.8 mol%
- Content is 3.9 mol
- a glass material containing no lead is used, A high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using “a glass material having a main component”.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is 3.33 ⁇ 10 ⁇ 6 to 4.13. Since it has a linear expansion coefficient that is ⁇ 10 ⁇ 6 and is close to that of silicon, the warpage of the wafer during the process can be made extremely small. Therefore, it becomes possible to manufacture a semiconductor device excellent in forward characteristics using a thin wafer, and to manufacture a semiconductor device excellent in reverse characteristics by increasing the thickness of the glass layer. Become.
- the content of SiO 2 is in the range of 49.5 mol% to 64.3 mol%
- B 2 O 3 The content of Al is within the range of 8.4 mol% to 17.9 mol%
- the content of Al 2 O 3 is within the range of 3.7 mol% to 14.8 mol%
- the content of ZnO is 3.9 mol % To 14.2 mol%
- the alkaline earth metal oxide content is in the range of 7.4 mol% to 12.9 mol% without crystallization during the vitrification process.
- the phrase “containing at least a specific component (SiO 2 , B 2 O 3, etc.) includes not only the specific component but also the specific component. In addition, the case where it contains further the component which can be normally contained in a glass composition is included.
- substantially not containing a specific element means that the specific element is not contained as a component, and constitutes glass. It does not exclude a glass composition in which the above-mentioned specific element is mixed as an impurity in the raw material of each component. The same applies to the semiconductor device manufacturing method and the semiconductor device of the present invention.
- the glass composition for protecting a semiconductor junction is a so-called oxide glass composition as in the present invention, it does not contain a specific element (Pb, As, etc.) It means not containing a nitride or the like of the specific element.
- Pb is not substantially contained because the purpose of the present invention is to use a conventional “glass material containing lead silicate as a main component using a glass material not containing lead”. Similarly, it is possible to manufacture a semiconductor device having a high breakdown voltage.
- Li, Na, and K are not substantially contained is advantageous in terms of average linear expansion coefficient and firing temperature when these components are contained, This is because it may decrease.
- At least SiO 2 and A glass composition containing B 2 O 3 , Al 2 O 3 , ZnO, and an oxide of at least two alkaline earth metals among CaO, MgO and BaO is used as a glass composition for protecting a semiconductor junction. It turns out that it is fully usable. That is, according to the glass composition for protecting a semiconductor junction of the present invention, a high breakdown voltage semiconductor device using a glass material containing no lead as in the case of using a conventional “glass material mainly composed of lead silicate”. Can be manufactured.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fifth embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fifth embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the sixth embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the sixth embodiment. It is a figure shown in order to demonstrate the manufacturing method of the semiconductor device concerning Embodiment 7. It is a figure shown in order to demonstrate the manufacturing method of the semiconductor device concerning Embodiment 7.
- Embodiment 1 is an embodiment according to a glass composition for protecting a semiconductor junction.
- the glass composition for protecting a semiconductor junction according to Embodiment 1 includes at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, and oxides of all alkaline earth metals among CaO, MgO, and BaO. And nickel oxide, and substantially free of Pb, As, Sb, Li, Na, and K.
- containing a specific component includes not only the case where only the specific component is contained, but also the case where the glass composition further contains a component that can be normally contained in addition to the specific component. .
- substantially not containing a specific element means that the specific element is not included as a component, and a glass composition in which the specific element is mixed as an impurity in the raw material of each component constituting the glass. Is not to be excluded.
- “not containing a specific element” means not containing an oxide of the specific element, a nitride of the specific element, or the like.
- the content of SiO 2 is in the range of 49.5 mol% to 64.3 mol%
- the content of B 2 O 3 is in the range of 8.4 mol% to 17.9 mol%
- Al The content of 2 O 3 is in the range of 3.7 mol% to 14.8 mol%
- the content of ZnO is in the range of 3.9 mol% to 14.2 mol%
- the alkaline earth metal oxide The content is in the range of 7.4 mol% to 12.9 mol%
- the content of nickel oxide is in the range of 0.01 mol% to 2.0 mol%.
- the CaO content is in the range of 2.0 mol% to 5.3 mol%
- the MgO content is in the range of 1.0 mol% to 2.3 mol%
- the BaO content is in the range of 2.6 mol% to 5.3 mol%.
- the total value of the content of SiO 2 and the content of B 2 O 3 is in the range of 65 mol% to 75 mol%.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is in the range of 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 .
- a conventional “glass material mainly composed of lead silicate” using a glass material not containing lead can be manufactured in the same manner as in the case of using.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 and silicon Therefore, the warpage of the wafer during the process can be made extremely small. Therefore, it becomes possible to manufacture a semiconductor device excellent in forward characteristics using a thin wafer, and to manufacture a semiconductor device excellent in reverse characteristics by increasing the thickness of the glass layer. Become.
- the content of SiO 2 is in the range of 49.5 mol% to 64.3 mol%
- the content of B 2 O 3 is 8.4 mol. %
- Al 2 O 3 content is in the range of 3.7 mol% to 14.8 mol%
- ZnO content is in the range of 3.9 mol% to 14.2 mol%.
- the content of the alkaline earth metal oxide is in the range of 7.4 mol% to 12.9 mol%, it is 50 ° C. to 550 ° C. without crystallization in the process of vitrification.
- the average linear expansion coefficient in the temperature range can be a value close to the linear expansion coefficient of silicon (for example, 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 ). For this reason, since the warpage of the wafer during the process can be extremely reduced, it becomes possible to manufacture a semiconductor device having excellent forward characteristics using a thin wafer, and the glass layer is made thicker in the reverse direction. A semiconductor device having excellent characteristics can be manufactured.
- the content of SiO 2 is set in the range of 49.5 mol% to 64.3 mol%.
- the content of SiO 2 is less than 49.5 mol%, the chemical resistance is reduced. This is because the insulating property may be lowered, and when the content of SiO 2 exceeds 64.3 mol%, the firing temperature tends to increase.
- the content of B 2 O 3 is in the range of 8.4 mol% to 17.9 mol% because the firing temperature is high when the content of B 2 O 3 is less than 8.4 mol%. This is because, when the content of B 2 O 3 exceeds 17.9 mol%, the average linear expansion coefficient tends to increase.
- the content of Al 2 O 3 is set within the range of 3.7 mol% to 14.8 mol% when the content of Al 2 O 3 is less than 3.7 mol% in the process of vitrification This is because when the content of Al 2 O 3 exceeds 14.8 mol%, the insulating property tends to decrease.
- the reason why the ZnO content is in the range of 3.9 mol% to 14.2 mol% is that the firing temperature tends to increase when the ZnO content is less than 3.9 mol%. Yes, if the ZnO content exceeds 14.2 mol%, chemical resistance may decrease or insulation may decrease, and further, crystallization tends to occur during vitrification. Because there is.
- the reason why the content of the alkaline earth metal oxide is in the range of 7.4 mol% to 12.9 mol% is that the content of the alkaline earth metal oxide is less than 7.4 mol%. Is because the firing temperature tends to be high. When the content of the alkaline earth metal oxide exceeds 12.9 mol%, the chemical resistance is lowered or the insulating property is lowered. Because there are cases.
- the CaO content is set in the range of 2.0 mol% to 5.3 mol% when the CaO content is less than 2.0 mol%. This is because the firing temperature tends to increase, and when the CaO content exceeds 5.3 mol%, chemical resistance may be lowered or insulation may be lowered.
- the reason why the MgO content is in the range of 1.0 mol% to 2.3 mol% is that the firing temperature tends to increase when the MgO content is less than 1.0 mol%. In other words, when the content of MgO exceeds 2.3 mol%, chemical resistance may be lowered or insulation may be lowered.
- the reason why the BaO content is in the range of 2.6 mol% to 5.3 mol% is that the firing temperature tends to increase when the BaO content is less than 2.6 mol%. In other words, when the content of BaO exceeds 5.3 mol%, the chemical resistance may be lowered or the insulating property may be lowered.
- the nickel oxide content was in the range of 0.01 mol% to 2.0 mol% when the nickel oxide content was less than 0.01 mol%, formed by electrophoresis. This is because it may be difficult to suppress the generation of bubbles that may be generated from the interface with the silicon substrate in the process of firing the “layer comprising the glass composition for protecting a semiconductor junction”. This is because, when the content of C exceeds 2.0 mol%, it tends to be easily crystallized in the process of vitrification.
- the total value of the content of SiO 2 and the content of B 2 O 3 was set in the range of 65 mol% to 75 mol%.
- this value is less than 65 mol%, the linear expansion coefficient is This is because it tends to be too high, and when this value exceeds 75 mol%, it tends to be easily crystallized in the process of vitrification.
- the glass composition for protecting a semiconductor junction according to Embodiment 1 can be manufactured as follows. That is, raw materials (SiO 2 , H 3 BO 3 , Al 2 O 3 , ZnO, CaCO 3 , MgO, BaCO 3 and NiO) are prepared so as to have the above-described composition ratio (molar ratio), and stirred well with a mixer. After that, the mixed raw material is put in a platinum crucible raised to a predetermined temperature (for example, 1550 ° C.) in an electric furnace and melted for a predetermined time. Thereafter, the melt is poured into a water-cooled roll to obtain flaky glass flakes. Thereafter, the glass flakes are pulverized with a ball mill or the like until a predetermined average particle diameter is obtained to obtain a powdery glass composition.
- a predetermined temperature for example, 1550 ° C.
- Embodiment 2 is an embodiment according to a glass composition for protecting a semiconductor junction.
- the glass composition for protecting a semiconductor junction according to Embodiment 2 includes at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, and at least two alkaline earth metal oxides (CaO and BaO).
- nickel oxide is contained, and Pb, As, Sb, Li, Na, and K are substantially not contained.
- containing a specific component includes not only the case where only the specific component is contained, but also the case where the glass composition further contains a component that can be normally contained in addition to the specific component. .
- substantially not containing a specific element means that the specific element is not included as a component, and a glass composition in which the specific element is mixed as an impurity in the raw material of each component constituting the glass. Is not to be excluded.
- “not containing a specific element” means not containing an oxide of the specific element, a nitride of the specific element, or the like.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 as in the case of the glass composition for protecting a semiconductor junction according to Embodiment 1. Is in range.
- the CaO content is in the range of 2.0 mol% to 7.6 mol%
- the BaO content is in the range of 3.7 mol% to 5.9 mol%.
- the glass composition for protecting a semiconductor junction according to Embodiment 2 is different from the glass composition for protecting a semiconductor junction according to Embodiment 1 in that CaO and BaO are contained as oxides of an alkaline earth metal.
- a high-breakdown-voltage semiconductor device is manufactured using a glass material that does not contain lead as in the case of using a conventional “glass material mainly composed of lead silicate”. Is possible.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is in the range of 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 . Since it has a linear expansion coefficient close to that of silicon, the warpage of the wafer during the process can be made extremely small. Therefore, it becomes possible to manufacture a semiconductor device excellent in forward characteristics using a thin wafer, and to manufacture a semiconductor device excellent in reverse characteristics by increasing the thickness of the glass layer. Become.
- the content of SiO 2, content of B 2 O 3, content of Al 2 O 3, the content of ZnO, alkaline earth metal Since the oxide content and the nickel oxide content are the same as those of the glass composition for protecting a semiconductor junction according to the first embodiment, it is 50 ° C. to 550 ° C. without crystallization in the process of vitrification.
- the average linear expansion coefficient can be set to a linear expansion coefficient close to that of silicon (for example, 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 ).
- the warpage of the wafer during the process can be made extremely small.
- the CaO content is in the range of 2.0 mol% to 7.6 mol% when the CaO content is less than 2.0 mol%. This is because the firing temperature tends to be high, and when the CaO content exceeds 7.6 mol%, chemical resistance may be lowered or insulation may be lowered.
- the reason why the BaO content is in the range of 3.7 mol% to 5.9 mol% is that the firing temperature tends to increase when the BaO content is less than 3.7 mol%. If the BaO content exceeds 5.9 mol%, the chemical resistance may be lowered or the insulation may be lowered.
- the glass composition for protecting a semiconductor junction according to Embodiment 2 can be manufactured as follows. That is, raw material materials (SiO 2 , H 3 BO 3 , Al 2 O 3 , ZnO, CaCO 3 , BaCO 3 and NiO) were prepared so as to have the composition ratio (molar ratio) described above, and stirred well with a mixer. Then, the mixed raw material is put in a platinum crucible raised to a predetermined temperature (for example, 1550 ° C.) in an electric furnace and melted for a predetermined time. Thereafter, the melt is poured into a water-cooled roll to obtain flaky glass flakes. Thereafter, the glass flakes are pulverized with a ball mill or the like until a predetermined average particle diameter is obtained to obtain a powdery glass composition.
- a predetermined temperature for example, 1550 ° C.
- Embodiment 3 is an embodiment according to a glass composition for protecting a semiconductor junction.
- the glass composition for protecting a semiconductor junction according to the third embodiment basically includes the same components as the glass composition for protecting a semiconductor junction according to the first embodiment, but does not contain nickel oxide. This is different from the glass composition for protecting a semiconductor junction according to the present invention. That is, the glass composition for protecting a semiconductor junction according to Embodiment 3 includes at least SiO 2 , B 2 O 3 , Al 2 O 3 , ZnO, CaO, MgO, and BaO. It contains an oxide and does not substantially contain Pb, As, Sb, Li, Na, and K. In addition, in this case, containing a specific component includes not only the case where only the specific component is contained, but also the case where the glass composition further contains a component that can be normally contained in addition to the specific component. .
- substantially not containing a specific element means that the specific element is not included as a component, and a glass composition in which the specific element is mixed as an impurity in the raw material of each component constituting the glass. Is not to be excluded.
- “not containing a specific element” means not containing an oxide of the specific element, a nitride of the specific element, or the like.
- the total content and the content of SiO 2 and the content of B 2 O 3 are the same as in the case of the glass composition for protecting a semiconductor junction according to Embodiment 1.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 as in the case of the glass composition for protecting a semiconductor junction according to Embodiment 1. Is in range.
- a conventional “lead silicate is used by using a glass material not containing lead.
- a high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using “a glass material having a main component”.
- the average linear expansion coefficient in the temperature range of 50 ° C. to 550 ° C. is 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 and silicon Therefore, the warpage of the wafer during the process can be made extremely small. Therefore, it becomes possible to manufacture a semiconductor device excellent in forward characteristics using a thin wafer, and to manufacture a semiconductor device excellent in reverse characteristics by increasing the thickness of the glass layer. Become.
- embodiments according to the embodiment glass composition for protecting a semiconductor junction according to 2 the content of SiO 2, content of B 2 O 3, content of Al 2 O 3, the content and the alkaline earth metal ZnO Since the oxide content is the same as that of the glass composition for protecting a semiconductor junction according to Embodiment 1, the average linear expansion in the temperature range of 50 ° C. to 550 ° C. without crystallization in the process of vitrification
- the rate can be a value close to the linear expansion coefficient of silicon (for example, 3.33 ⁇ 10 ⁇ 6 to 4.13 ⁇ 10 ⁇ 6 ).
- the warpage of the wafer during the process can be made extremely small.
- a semiconductor device having excellent characteristics can be manufactured.
- the sum of the content of BaO and the content of SiO 2 and the content of B 2 O 3 is within the above-described range, as in the case of the glass composition for protecting a semiconductor junction according to Embodiment 1. Depending on the reason.
- the glass composition for protecting a semiconductor junction according to Embodiment 3 can be manufactured as follows. That is, after preparing the raw materials (SiO 2 , H 3 BO 3 , Al 2 O 3 , ZnO, CaCO 3 , MgO and BaCO 3 ) so as to have the above-described composition ratio (molar ratio), and thoroughly stirring with a mixer
- the mixed raw material is put in a platinum crucible raised to a predetermined temperature (for example, 1550 ° C.) in an electric furnace and melted for a predetermined time. Thereafter, the melt is poured into a water-cooled roll to obtain flaky glass flakes. Thereafter, the glass flakes are pulverized with a ball mill or the like until a predetermined average particle diameter is obtained to obtain a powdery glass composition.
- the fourth embodiment is an embodiment according to a method for manufacturing a semiconductor device.
- the method for manufacturing a semiconductor device includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion. In this order. And in the said 2nd process, a glass layer is formed using the glass composition for semiconductor joining protection which concerns on Embodiment 1.
- FIG. 1 a semiconductor substrate having a pn junction parallel to the main surface is prepared, and a groove having a depth exceeding the pn junction is formed from one surface of the semiconductor substrate to expose the pn junction inside the groove.
- the second step includes a step of forming a glass layer so as to directly cover the pn junction exposed portion inside the groove.
- FIGS. 1 and 2 are views for explaining a method of manufacturing a semiconductor device according to the fourth embodiment.
- FIGS. 2A to 2D are process diagrams.
- the semiconductor device manufacturing method according to the fourth embodiment includes a “semiconductor substrate forming step”, a “groove forming step”, a “glass layer forming step”, a “photoresist forming step”, “ The “oxide film removing step”, “roughened region forming step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order.
- the method for manufacturing the semiconductor device according to the fourth embodiment will be described in the order of steps.
- p + -type diffusion layer 112 is diffused by diffusion of p-type impurities from one surface of n ⁇ -type semiconductor substrate (n ⁇ -type silicon substrate) 110, and n-type impurities from the other surface.
- An n + -type diffusion layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (see FIG. 1A).
- (F) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed.
- the formation region 132 is formed (see FIG. 2B).
- Electrode forming step Ni plating is performed on the semiconductor substrate to form the anode electrode 134 on the roughened region 132 and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 2C). )reference.).
- the high-breakdown-voltage mesa semiconductor device (semiconductor device according to the fourth embodiment) 100 can be manufactured.
- the fifth embodiment relates to a method for manufacturing a semiconductor device.
- the semiconductor device manufacturing method according to the fifth embodiment is similar to the semiconductor device manufacturing method according to the fourth embodiment.
- the first step is to prepare a semiconductor element having a pn junction exposed portion where the pn junction is exposed, and the pn junction exposure.
- a glass layer is formed using the glass composition for semiconductor joining protection which concerns on Embodiment 1.
- the first step includes a step of forming a pn junction exposed portion on the surface of the semiconductor substrate, and the second step includes a pn on the surface of the semiconductor substrate. Forming a glass layer so as to directly cover the joint exposed portion.
- FIGS. 3 and 4 are views for explaining the method for manufacturing the semiconductor device according to the fifth embodiment.
- 3A to FIG. 3C and FIG. 4A to FIG. 4C are process diagrams.
- the semiconductor device manufacturing method according to the fifth embodiment includes a “semiconductor substrate preparation step”, a “p + -type diffusion layer formation step”, an “n + -type diffusion layer formation step”, “ The “glass layer forming step”, “glass layer etching step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order.
- the semiconductor device manufacturing method according to the fifth embodiment will be described below in the order of steps.
- a p-type impurity for example, boron ions
- a p + type diffusion layer 214 is formed by thermal diffusion (see FIG. 3B).
- n + -type diffusion layer forming step Next, after removing the mask M1 and forming the mask M2, an n - type is formed on the surface of the n ⁇ -type epitaxial layer 212 via the mask M2 by ion implantation. Impurities (for example, arsenic ions) are introduced. Thereafter, an n + -type diffusion layer 216 is formed by thermal diffusion (see FIG. 3C).
- the high breakdown voltage planar semiconductor device (semiconductor device according to the fifth embodiment) 200 can be manufactured.
- the semiconductor device manufacturing method according to the sixth embodiment is similar to the semiconductor device manufacturing method according to the fourth embodiment.
- the first step is to prepare a semiconductor element having a pn junction exposed portion where the pn junction is exposed, and the pn junction exposure.
- a glass layer is formed using the glass composition for semiconductor joining protection which concerns on Embodiment 1.
- the second step forms an insulating layer on the exposed pn junction in the trench.
- a mesa-type pn diode is manufactured as the semiconductor device.
- FIGS. 5 and 6 are views for explaining the method for manufacturing the semiconductor device according to the sixth embodiment.
- 5 (a) to 5 (d) and FIGS. 6 (a) to 6 (d) are process diagrams.
- the method for manufacturing a semiconductor device according to the sixth embodiment includes a “semiconductor substrate forming step”, a “groove forming step”, an “insulating layer forming step”, a “glass layer forming step”, “ The “photoresist forming step”, “oxide film removing step”, “roughened region forming step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order.
- the semiconductor device manufacturing method according to the sixth embodiment will be described below in the order of steps.
- p + -type diffusion layer 112 is diffused by diffusion of p-type impurities from one surface of n ⁇ -type semiconductor substrate (n ⁇ -type silicon substrate) 110, and n-type impurities from the other surface.
- An n + -type diffusion layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (see FIG. 5A).
- an insulating layer 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (see FIG. 5C).
- the thickness of the insulating layer 121 is in the range of 5 nm to 60 nm (for example, 20 nm).
- the insulating layer is formed by placing the semiconductor substrate in a diffusion furnace and then treating it at 900 ° C. for 10 minutes while flowing oxygen gas. If the thickness of the insulating layer 121 is less than 5 nm, the effect of reducing the reverse current may not be obtained. On the other hand, if the thickness of the insulating layer 121 exceeds 60 nm, a layer made of a glass composition may not be formed by electrophoresis in the next glass layer forming step.
- a layer made of the glass composition for protecting a semiconductor junction according to Embodiment 1 is formed on the inner surface of the groove 120 and the surface of the semiconductor substrate in the vicinity thereof by electrophoresis, and then the semiconductor junction A layer made of the protective glass composition is baked to form a passivation glass layer 124 (see FIG. 5D).
- a layer made of the glass composition for protecting a semiconductor junction is so formed as to cover the inner surface of the groove 120 with an insulating layer 121 interposed therebetween. Form. Therefore, the pn junction exposed portion A inside the groove 120 is covered with the glass layer 124 via the insulating layer 121.
- (F) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed.
- the formation region 132 is formed (see FIG. 6B).
- a high-breakdown-voltage mesa semiconductor device semiconductor device according to Embodiment 6 102 can be manufactured.
- the semiconductor device manufacturing method according to the seventh embodiment is similar to the semiconductor device manufacturing method according to the fifth embodiment, in which a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a pn junction exposure. And a second step of forming a glass layer so as to cover the part in this order. And in the said 2nd process, a glass layer is formed using the glass composition for semiconductor joining protection which concerns on Embodiment 1.
- the second step includes forming an insulating layer on the pn junction exposed portion on the surface of the semiconductor substrate. And a step of forming a glass layer so as to cover the pn junction exposed portion via the insulating layer.
- a planar pn diode is manufactured as the semiconductor device.
- FIG. 7 and 8 are views for explaining the method for manufacturing the semiconductor device according to the fifth embodiment.
- FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D are process diagrams.
- the semiconductor device manufacturing method according to the fifth embodiment includes a “semiconductor substrate preparation step”, a “p + -type diffusion layer formation step”, an “n + -type diffusion layer formation step”, “ The “insulating layer forming step”, “glass layer forming step”, “etching step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order.
- the semiconductor device manufacturing method according to the seventh embodiment will be described below in the order of steps.
- a p-type impurity for example, boron ions
- a p + type diffusion layer 214 is formed by thermal diffusion (see FIG. 7B).
- n + -type diffusion layer forming step Next, after removing the mask M1 and forming the mask M2, an n - type is formed on the surface of the n ⁇ -type epitaxial layer 212 via the mask M2 by ion implantation. Impurities (for example, arsenic ions) are introduced. Thereafter, an n + -type diffusion layer 216 is formed by thermal diffusion (see FIG. 7C). At this time, a pn junction exposed portion A is formed on the surface of the semiconductor substrate.
- Impurities for example, arsenic ions
- the thickness of the insulating layer 218 is less than 5 nm, the effect of reducing the reverse current may not be obtained. On the other hand, if the thickness of the insulating layer 218 exceeds 60 nm, a layer made of a glass composition may not be formed by electrophoresis in the next glass layer forming step.
- the high breakdown voltage planar semiconductor device (semiconductor device according to the seventh embodiment) 202 can be manufactured.
- FIG. 9 is a chart showing the conditions and results of the examples.
- the raw materials were prepared so that the composition ratios shown in Examples 1 to 8 and Comparative Examples 1 and 2 (see FIG. 9) were obtained, and after thoroughly stirring with a mixer, the mixed raw materials were heated to a predetermined temperature ( It was placed in a platinum crucible raised to 1350 ° C. to 1550 ° C. and melted for 2 hours. Thereafter, the melt was poured into a water-cooled roll to obtain flaky glass flakes. The glass flakes were pulverized with a ball mill until the average particle size became 5 ⁇ m to obtain a powdery glass composition.
- raw materials used in the examples are SiO 2, H 3 BO 3, Al 2 O 3, ZnO, CaCO 3, MgO, BaCO 3, NiO, ZrO 2 and PbO.
- Evaluation item 1 (environmental impact)
- the object of the present invention is “to make it possible to manufacture a semiconductor device having a high withstand voltage using a glass material containing no lead as in the case of using a conventional“ glass material mainly composed of lead silicate ”. Therefore, when the lead component is not included, an evaluation of “ ⁇ ” is given, and when the lead component is included, an evaluation of “x” is given.
- Evaluation item 2 (firing temperature) If the firing temperature is too high, the influence on the semiconductor device being manufactured increases. Therefore, when the firing temperature is 900 ° C. or lower, an evaluation of “O” is given, and when the firing temperature exceeds 900 ° C., Evaluation was given.
- Evaluation item 4 (average linear expansion coefficient) A flaky glass plate is prepared from the melt obtained in the above-mentioned section “1. Preparation of sample”, and the average linear expansion of the glass composition at 50 ° C. to 550 ° C. using the flaky glass plate. The rate was measured. The average linear expansion coefficient is measured using a thermomechanical analyzer TMA-60 manufactured by Shimadzu Corporation using a silicon single crystal having a length of 20 mm as a standard sample by a total expansion measurement method (temperature increase rate: 10 ° C./min). It was.
- FIG. 10 is a diagram illustrating an example of a measurement result of the average linear expansion coefficient.
- FIG. 10A is a diagram showing a measurement result in the glass composition for protecting a semiconductor junction according to Example 3
- FIG. 10B is a diagram showing a measurement result in the glass composition for protecting a semiconductor junction according to Comparative Example 1.
- FIG. When the difference between the average linear expansion coefficient of the glass composition at 50 ° C. to 550 ° C. and the linear expansion coefficient of silicon (3.73 ⁇ 10 ⁇ 6 ) is “0.4 ⁇ 10 ⁇ 6 ” or less, An evaluation was given, and an evaluation of “x” was given when the difference exceeded “0.4 ⁇ 10 ⁇ 6 ”.
- the numbers in parentheses indicate the average linear expansion coefficient of glass composition at 50 ° C. to 550 ° C. ⁇ 10 + 6 .
- Evaluation item 5 A semiconductor device (pn diode) was manufactured by the same method as the method for manufacturing a semiconductor device according to Embodiment 4 or 6, and the reverse characteristics of the manufactured semiconductor device were measured.
- a semiconductor device is manufactured by the method for manufacturing a semiconductor device according to Embodiment 4, and in Examples 1 to 6, the semiconductor device according to Embodiment 6 is manufactured.
- a semiconductor device was manufactured by the method. As a result, an evaluation of “ ⁇ ” was given when the reverse direction characteristic of the semiconductor device was in the normal range, and an evaluation of “X” was given when the reverse direction characteristic of the semiconductor device was not in the normal range.
- Evaluation item 6 Presence / absence of crystallization
- a semiconductor device (pn diode) was manufactured by the same method as the method for manufacturing a semiconductor device according to Embodiment 4 or 6.
- a semiconductor device is manufactured by the method for manufacturing a semiconductor device according to Embodiment 4, and in Examples 1 to 6, the semiconductor device according to Embodiment 6 is manufactured.
- a semiconductor device was manufactured by the method. As a result, in the process of vitrifying a layer composed of a glass composition, an evaluation of “ ⁇ ” is given if it can be vitrified without crystallization, and an evaluation of “x” if it cannot be vitrified by crystallization. Gave.
- Evaluation item 7 (whether or not bubbles are generated)
- a semiconductor device (pn diode) is manufactured by a method similar to the method for manufacturing a semiconductor device according to the fourth or sixth embodiment, and bubbles are formed inside the glass layer 124 (particularly, near the interface with the silicon substrate) during the vitrification process. Was observed (preliminary evaluation).
- a glass composition for protecting a semiconductor junction according to Examples 1 to 6 and Comparative Examples 1 and 2 is applied on a 10 mm square silicon substrate to form a layer made of the glass composition for protecting a semiconductor junction and the semiconductor junction.
- a layer made of the protective glass composition was fired to form a glass layer, and it was observed whether bubbles were generated inside the glass layer (particularly, in the vicinity of the interface with the semiconductor substrate) (this evaluation).
- a semiconductor device is manufactured by the method for manufacturing a semiconductor device according to Embodiment 4, and in Examples 1 to 6, the semiconductor device according to Embodiment 6 is manufactured.
- a semiconductor device was manufactured by the method.
- FIG. 11 is a diagram for explaining the bubbles b generated in the glass layer 124 in the preliminary evaluation.
- FIG. 11A is a cross-sectional view of the semiconductor device when the bubble b is not generated
- FIG. 11B is a cross-sectional view of the semiconductor device when the bubble b is generated.
- FIG. 12 is a photograph shown for explaining the bubbles b generated in the glass layer 124 in this evaluation.
- FIG. 12A is an enlarged view showing a boundary surface between the silicon substrate and the glass layer when the bubble b is not generated
- FIG. 12B is a diagram illustrating the silicon substrate and the glass when the bubble b is generated. It is a figure which expands and shows the interface with a layer.
- the glass compositions according to Examples 1 to 8 were evaluated as “ ⁇ ” for all the evaluation items (evaluation items 1 to 7).
- the glass compositions according to Examples 1 to 8 are all glass materials that do not contain lead, but (a) can be fired at an appropriate temperature (for example, 900 ° C. or lower), and are used in step (b).
- Resists chemicals (c) has a linear expansion coefficient close to that of silicon (especially the average linear expansion coefficient at 50 ° C to 550 ° C is close to that of silicon), and (d) excellent insulation All the conditions of having the property, and (e) not crystallizing in the process of vitrification, and (f) may occur from the interface with the silicon substrate in the process of forming the glass layer It turned out that it is a glass composition which suppresses generation
- the semiconductor device according to Examples 1 to 6 has a low reverse current regardless of the composition of the glass layer and the baking conditions, even in the case of the semiconductor device according to Examples 7 to 8.
- the semiconductor devices according to Examples 1 to 6 were more easily processed in the process of forming the glass layer by firing the layer made of the glass composition than the semiconductor devices according to Examples 7 to 8. It has also been found that bubbles are less likely to be generated from the interface between the substrate and the glass layer.
- FIG. 13 is a chart showing 18 levels of composition and results. From FIG. 13, the following items (1) to (4) were found.
- ⁇ tends to decrease as the sum of the content of SiO 2 and the content of B 2 O 3 increases. It was found that ⁇ tends to be smaller as the content of Al 2 O 3 is larger. As for ZnO, it was found that ⁇ tends to be smaller as the ZnO content is larger. This is because ⁇ is smaller due to crystallization. A smaller content is considered better.
- Ts tends to be lower when the sum of the content of SiO 2 and the content of B 2 O 3 is smaller, and the content of SiO 2 It was found that the larger the ratio of the content of B 2 O 3 to the amount, the lower the Ts, and the larger the BaO content, the lower the Ts.
- a glass composition that is basically based on the same composition as the glass composition for protecting a semiconductor junction according to Embodiment 1 but does not contain nickel oxide is used.
- this invention demonstrated the glass composition for semiconductor junction protection, this invention is not limited to this.
- a glass composition that is basically based on the same composition as the glass composition for protecting a semiconductor junction according to Embodiment 2 but does not contain nickel oxide is also included in the present invention.
- At least one metal oxide selected from the group consisting of nickel oxide, copper oxide, manganese oxide and zirconium oxide (foaming in the process of vitrification)
- nickel oxide was used as the “metal oxide having the property of suppressing generation”
- the present invention is not limited to this.
- copper oxide, manganese oxide, or zirconium oxide may be used instead of nickel oxide.
- the present invention relates to “a glass composition for protecting a semiconductor junction which substantially does not contain Pb, As, Sb, Li, Na, and K”.
- a glass composition for protecting a semiconductor junction which does not substantially contain Pb, P, As, Sb, Li, Na, and K is also included.
- the glass layer is formed using the glass composition for protecting a semiconductor junction according to Embodiment 1, but the present invention is not limited to this.
- the glass layer may be formed using the glass composition for protecting a semiconductor junction according to Embodiment 2 or 3.
- you may form a glass layer using the glass composition for another semiconductor junction protection which falls in the range of Claim 1 or 3.
- the present invention has been described by taking a diode (mesa type pn diode, planar type pn diode) as an example, but the present invention is not limited to this.
- the present invention can also be applied to all semiconductor devices (for example, thyristors, power MOSFETs, IGBTs, etc.) in which the pn junction is exposed.
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Abstract
Description
従来の半導体装置の製造方法は、図14及び図15に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で含む。以下、従来の半導体装置の製造方法を工程順に説明する。
まず、n-型半導体基板(n-型シリコン基板)910の一方の表面からのp型不純物の拡散によりp+型拡散層912、他方の表面からのn型不純物の拡散によりn+型拡散層914を形成して、主面に平行なpn接合が形成された半導体基体を形成する。その後、熱酸化によりp+型拡散層912及びn+型拡散層914の表面に酸化膜916,918を形成する(図14(a)参照。)。
次に、フォトエッチング法によって、酸化膜916の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からpn接合を超える深さの溝920を形成する(図14(b)参照。)。
次に、溝920の表面に、電気泳動法により溝920の内面及びその近傍の半導体基体表面に半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層924を形成する(図14(c)参照。)。
次に、ガラス層924の表面を覆うようにフォトレジスト926を形成する(図14(d)参照。)。
次に、フォトレジスト926をマスクとして酸化膜916のエッチングを行い、Niめっき電極膜を形成する部位930における酸化膜916,918を除去する(図15(a)参照。)。
次に、Niめっき電極膜を形成する部位930における半導体基体表面の粗面化処理を行い、Niめっき電極と半導体基体との密着性を高くするための粗面化領域932を形成する(図15(b)参照。)。
次に、半導体基体にNiめっきを行い、粗面化領域932上にアノード電極934を形成するとともに、半導体基体の他方の表面にカソード電極936を形成する(図15(c)参照。)。
次に、ダイシング等により、ガラス層924の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置(pnダイオード)900を作製する(図15(d)参照。)。
実施形態1は、半導体接合保護用ガラス組成物に係る実施形態である。
実施形態2は、半導体接合保護用ガラス組成物に係る実施形態である。
実施形態3は、半導体接合保護用ガラス組成物に係る実施形態である。
実施形態4は、半導体装置の製造方法に係る実施形態である。
実施形態4に係る半導体装置の製造方法は、図1及び図2に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態4に係る半導体装置の製造方法を工程順に説明する。
まず、n-型半導体基板(n-型シリコン基板)110の一方の表面からのp型不純物の拡散によりp+型拡散層112、他方の表面からのn型不純物の拡散によりn+型拡散層114を形成して、主面に平行なpn接合が形成された半導体基体を形成する。その後、熱酸化によりp+型拡散層112及びn+型拡散層114の表面に酸化膜116,118を形成する(図1(a)参照。)。
次に、フォトエッチング法によって、酸化膜116の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からpn接合を超える深さの溝120を形成する(図1(b)参照。)。このとき、溝の内面にpn接合露出部Aが形成される。
次に、溝120の表面に、電気泳動法により溝120の内面及びその近傍の半導体基体表面に実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層124を形成する(図1(c)参照。)。従って、溝120の内部におけるpn接合露出部はガラス層124により直接覆われた状態となる。
次に、ガラス層124の表面を覆うようにフォトレジスト126を形成する(図1(d)参照。)。
次に、フォトレジスト126をマスクとして酸化膜116のエッチングを行い、Niめっき電極膜を形成する部位130における酸化膜116,118を除去する(図2(a)参照。)。
次に、Niめっき電極膜を形成する部位130における半導体基体表面の粗面化処理を行い、Niめっき電極と半導体基体との密着性を高くするための粗面化領域132を形成する(図2(b)参照。)。
次に、半導体基体にNiめっきを行い、粗面化領域132上にアノード電極134を形成するとともに、半導体基体の他方の表面にカソード電極136を形成する(図2(c)参照。)。
次に、ダイシング等により、ガラス層124の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置(pnダイオード)を作製する(図2(d)参照。)。
実施形態5は、半導体装置の製造方法に係る実施形態である。
実施形態5に係る半導体装置の製造方法は、図3及び図4に示すように、「半導体基体準備工程」、「p+型拡散層形成工程」、「n+型拡散層形成工程」、「ガラス層形成工程」、「ガラス層エッチング工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態5に係る半導体装置の製造方法を工程順に説明する。
まず、n+型シリコン基板210上にn-型エピタキシャル層212が積層された半導体基体を準備する(図3(a)参照。)。
次に、マスクM1を形成した後、当該マスクM1を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりp型不純物(例えばボロンイオン)を導入する。その後、熱拡散することにより、p+型拡散層214を形成する(図3(b参照。)。
次に、マスクM1を除去するとともにマスクM2を形成した後、当該マスクM2を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりn型不純物(例えばヒ素イオン)を導入する。その後、熱拡散することにより、n+型拡散層216を形成する(図3(c)参照。)。
次に、マスクM2を除去した後、n-型エピタキシャル層212の表面に、スピンコート法により、実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成し、その後、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層215を形成する(図4(a)参照。)。
次に、ガラス層215の表面にマスクM3を形成した後、ガラス層のエッチングを行う(図4(b)参照。)。これにより、n-型エピタキシャル層212の表面における所定領域にガラス層217が形成されることとなる。
次に、マスクM3を除去した後、半導体基体の表面におけるガラス層217で囲まれた領域にアノード電極218を形成するとともに、半導体基体の裏面にカソード電極220を形成する(図4(c)参照。)。
次に、ダイシング等により、半導体基体を切断して半導体基体をチップ化して、半導体装置(プレーナー型のpnダイオード)200を製造する(図示せず。)。
実施形態6に係る半導体装置の製造方法は、実施形態4に係る半導体装置の製造方法と同様に、pn接合が露出するpn接合露出部を有する半導体素子を準備する第1工程と、pn接合露出部を覆うようにガラス層を形成する第2工程とをこの順序で含む半導体装置の製造方法である。そして、当該第2工程においては、実施形態1に係る半導体接合保護用ガラス組成物を用いてガラス層を形成する。但し、実施形態6に係る半導体装置の製造方法においては、実施形態4に係る半導体装置の製造方法の場合とは異なり、第2工程が、溝の内部におけるpn接合露出部上に絶縁層を形成する工程と、当該絶縁層を介してpn接合露出部を覆うようにガラス層を形成する工程とを含む。実施形態6に係る半導体装置の製造方法においては、半導体装置としてメサ型のpnダイオードを製造する。
実施形態6に係る半導体装置の製造方法は、図5及び図6に示すように、「半導体基体形成工程」、「溝形成工程」、「絶縁層形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態6に係る半導体装置の製造方法を工程順に説明する。
まず、n-型半導体基板(n-型シリコン基板)110の一方の表面からのp型不純物の拡散によりp+型拡散層112、他方の表面からのn型不純物の拡散によりn+型拡散層114を形成して、主面に平行なpn接合が形成された半導体基体を形成する。その後、熱酸化によりp+型拡散層112及びn+型拡散層114の表面に酸化膜116,118を形成する(図5(a)参照。)。
次に、フォトエッチング法によって、酸化膜116の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からpn接合を超える深さの溝120を形成する(図5(b)参照。)。このとき、溝の内面にpn接合露出部Aが形成される。
次に、ドライ酸素(DryO2)を用いた熱酸化法によって、溝120の内面にシリコン酸化膜からなる絶縁層121を形成する(図5(c)参照。)。絶縁層121の厚さは、5nm~60nmの範囲内(例えば20nm)とする。絶縁層の形成は、半導体基体を拡散炉に入れた後、酸素ガスを流しながら900℃の温度で10分処理することにより行う。絶縁層121の厚さが5nm未満であると逆方向電流低減の効果が得られなくなる場合がある。一方、絶縁層121の厚さが60nmを超えると次のガラス層形成工程で電気泳動法によりガラス組成物からなる層を形成することができなくなる場合がある。
次に、電気泳動法により溝120の内面及びその近傍の半導体基体表面に実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成し、その後、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層124を形成する(図5(d)参照。)。なお、溝120の内面に半導体接合保護用ガラス組成物からなる層を形成する際には、溝120の内面を絶縁層121を介して被覆するように半導体接合保護用ガラス組成物からなる層を形成する。従って、溝120の内部におけるpn接合露出部Aは絶縁層121を介してガラス層124により覆われた状態となる。
次に、ガラス層124の表面を覆うようにフォトレジスト126を形成した後、当該フォトレジスト126をマスクとして酸化膜116のエッチングを行い、Niめっき電極膜を形成する部位130における酸化膜116を除去する(図6(a)参照。)。
次に、Niめっき電極膜を形成する部位130における半導体基体表面の粗面化処理を行い、Niめっき電極と半導体基体との密着性を高くするための粗面化領域132を形成する(図6(b)参照。)。
次に、半導体基体にNiめっきを行い、粗面化領域132上にアノード電極134を形成するとともに、半導体基体の他方の表面にカソード電極136を形成する(図6(c)参照。)。
次に、ダイシング等により、ガラス層124の中央部において半導体基体を切断して半導体基体をチップ化して、半導体装置(メサ型のpnダイオード)102を作製する(図6(d)参照。)。
実施形態7に係る半導体装置の製造方法は、実施形態5に係る半導体装置の製造方法と同様に、pn接合が露出するpn接合露出部を有する半導体素子を準備する第1工程と、pn接合露出部を覆うようにガラス層を形成する第2工程とをこの順序で含む半導体装置の製造方法である。そして、当該第2工程においては、実施形態1に係る半導体接合保護用ガラス組成物を用いてガラス層を形成する。但し、実施形態7に係る半導体装置の製造方法においては、実施形態5に係る半導体装置の製造方法の場合とは異なり、第2工程が、半導体基体の表面におけるpn接合露出部上に絶縁層を形成する工程と、当該絶縁層を介してpn接合露出部を覆うようにガラス層を形成する工程とを含む。実施形態7に係る半導体装置の製造方法においては、半導体装置としてプレーナー型のpnダイオードを製造する。
実施形態5に係る半導体装置の製造方法は、図7及び図8に示すように、「半導体基体準備工程」、「p+型拡散層形成工程」、「n+型拡散層形成工程」、「絶縁層形成工程」、「ガラス層形成工程」、「エッチング工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態7に係る半導体装置の製造方法を工程順に説明する。
まず、n+型シリコン基板210上にn-型エピタキシャル層212が積層された半導体基体を準備する(図7(a)参照。)。
次に、マスクM1を形成した後、当該マスクM1を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりp型不純物(例えばボロンイオン)を導入する。その後、熱拡散することにより、p+型拡散層214を形成する(図7(b)参照。)。
次に、マスクM1を除去するとともにマスクM2を形成した後、当該マスクM2を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりn型不純物(例えばヒ素イオン)を導入する。その後、熱拡散することにより、n+型拡散層216を形成する(図7(c)参照。)。このとき、半導体基体の表面にpn接合露出部Aが形成される。
次に、マスクM2を除去した後、ドライ酸素(DryO2)を用いた熱酸化法によって、n-型エピタキシャル層212の表面(及びn+型シリコン基板210の裏面)にシリコン酸化膜からなる絶縁層218を形成する(図7(d)参照。)。絶縁層218の厚さは、5nm~60nmの範囲内(例えば20nm)とする。絶縁層218の形成は、半導体基体を拡散炉に入れた後、酸素ガスを流しながら900℃の温度で10分処理することにより行う。絶縁層218の厚さが5nm未満であると逆方向電流低減の効果が得られなくなる場合がある。一方、絶縁層218の厚さが60nmを超えると次のガラス層形成工程で電気泳動法によりガラス組成物からなる層を形成することができなくなる場合がある。
次に、絶縁層218の表面に、電気泳動法により、実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成し、その後、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層220を形成する(図8(a)参照。)。
次に、ガラス層220の表面にマスクM3を形成した後、ガラス層220のエッチングを行い(図8(b)参照。)、引き続き、絶縁層218のエッチングを行う(図8(c)参照。)。これにより、n-型エピタキシャル層212の表面における所定領域に絶縁層218及びガラス層220が形成されることとなる。
次に、マスクM3を除去した後、半導体基体の表面におけるガラス層220で囲まれた領域にアノード電極222を形成するとともに、半導体基体の裏面にカソード電極224を形成する(図8(d)参照。)。
次に、ダイシング等により、半導体基体を切断して半導体基体をチップ化して、半導体装置(プレーナー型のpnダイオード)202を製造する(図示せず。)。
1.試料の調整
図9は、実施例の条件及び結果を示す図表である。実施例1~8及び比較例1~2に示す組成比(図9参照。)になるように原料を調合し、混合機でよく攪拌した後、その混合した原料を電気炉中で所定温度(1350℃~1550℃)まで上昇させた白金ルツボに入れ、2時間溶融させた。その後、融液を水冷ロールに流し出して薄片状のガラスフレークを得た。このガラスフレークをボールミルで平均粒径が5μmとなるまで粉砕して、粉末状のガラス組成物を得た。
上記方法により得た各ガラス組成物を用いて以下の評価項目により評価した。
本発明の目的が「鉛を含まないガラス材料を用いて、従来の『珪酸鉛を主成分としたガラス材料』を用いた場合と同様に高耐圧の半導体装置を製造することを可能とする」ことにあるため、鉛成分を含まない場合に「○」の評価を与え、鉛成分を含む場合に「×」の評価を与えた。
焼成温度が高すぎると製造中の半導体装置に与える影響が大きくなるため、焼成温度が900℃以下である場合に「○」の評価を与え、焼成温度が900℃を超える場合に「×」の評価を与えた。
ガラス組成物が王水及びめっき液の両方に対して難溶性を示す場合に「○」の評価を与え、王水及びめっき液の少なくとも一方に対して溶解性を示す場合に「×」の評価を与えた。
上記した「1.試料の調整」の欄で得られた融液から薄片状のガラス板を作製し、当該薄片状のガラス板を用いて、50℃~550℃におけるガラス組成物の平均線膨張率を測定した。平均線膨張率の測定は、島津製作所製の熱機械分析装置TMA-60を用いて、長さ20mmのシリコン単結晶を標準試料として、全膨張測定法(昇温速度10℃/分)により行った。
実施形態4又は6に係る半導体装置の製造方法と同様の方法によって半導体装置(pnダイオード)を作製し、作製した半導体装置の逆方向特性を測定した。なお、実施例7~8及び比較例1~2においては、実施形態4に係る半導体装置の製造方法によって半導体装置を作製し、実施例1~6においては、実施形態6に係る半導体装置の製造方法によって半導体装置を作製した。その結果、半導体装置の逆方向特性が正常範囲にある場合に「○」の評価を与え、半導体装置の逆方向特性が正常範囲にない場合に「×」の評価を与えた。
実施形態4又は6に係る半導体装置の製造方法と同様の方法によって半導体装置(pnダイオード)を作製した。なお、実施例7~8及び比較例1~2においては、実施形態4に係る半導体装置の製造方法によって半導体装置を作製し、実施例1~6においては、実施形態6に係る半導体装置の製造方法によって半導体装置を作製した。その結果、ガラス組成物からなる層をガラス化する過程で、結晶化することなくガラス化できた場合に「○」の評価を与え、結晶化によりガラス化できなかった場合に「×」の評価を与えた。
実施形態4又は6に係る半導体装置の製造方法と同様の方法によって半導体装置(pnダイオード)を作製し、ガラス化の過程でガラス層124の内部(特に、シリコン基板との境界面近傍)に泡が発生しているかどうかを観察した(予備評価)。また、10mm角のシリコン基板上に実施例1~6及び比較例1~2に係る半導体接合保護用ガラス組成物を塗布して半導体接合保護用ガラス組成物からなる層を形成するとともに当該半導体接合保護用ガラス組成物からなる層を焼成することによりガラス層を形成し、ガラス層の内部(特に、半導体基体との境界面近傍)に泡が発生しているかどうかを観察した(本評価)。なお、実施例7~8及び比較例1~2においては、実施形態4に係る半導体装置の製造方法によって半導体装置を作製し、実施例1~6においては、実施形態6に係る半導体装置の製造方法によって半導体装置を作製した。
上記した評価項目1~7についての各評価がすべて「○」の場合に「○」の評価を与え、各評価のうち1つでも「△」又は「×」がある場合に「×」の評価を与えた。
図9からも分かるように、比較例1~2に係るガラス組成物はいずれも、いずれかの評価項目で「×」の評価があり、「×」の総合評価が得られた。すなわち、比較例1に係るガラス組成物は、評価項目1及び4で「×」の評価が得られた。また、比較例2に係るガラス組成物は、評価項目3及び4で「×」の評価が得られた。
なお、上記の実施例1~8の組成を決定するにあたっては、18水準による予備実験を行い、この結果を参考にした。図13は、18水準の組成及び結果を示す図表である。図13から以下の(1)~(4)の事項が分かった。
Claims (20)
- 少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、
50℃~550℃の温度範囲における平均線膨張率が3.33×10-6~4.13×10-6の範囲内にあることを特徴とする半導体接合保護用ガラス組成物。 - 50℃~550℃の温度範囲における平均線膨張率が3.38×10-6~4.08×10-6の範囲内にあることを特徴とする請求項1に記載の半導体接合保護用ガラス組成物。
- 少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、
SiO2の含有量が49.5mol%~64.3mol%の範囲内にあり、
B2O3の含有量が8.4mol%~17.9mol%の範囲内にあり、
Al2O3の含有量が3.7mol%~14.8mol%の範囲内にあり、
ZnOの含有量が3.9mol%~14.2mol%の範囲内にあり、
アルカリ土類金属の酸化物の含有量が7.4mol%~12.9mol%の範囲内にあることを特徴とする半導体接合保護用ガラス組成物。 - SiO2の含有量とB2O3の含有量とを合計した値が、65mol%~75mol%の範囲内にあることを特徴とする請求項3に記載の半導体接合保護用ガラス組成物。
- 前記アルカリ土類金属の酸化物として、CaO、MgO及びBaOのすべてを含有することを特徴とする請求項1~4のいずれかに記載の半導体接合保護用ガラス組成物。
- CaO含有量が2.0mol%~5.3mol%の範囲内にあり、MgO含有量が1.0mol%~2.3mol%の範囲内にあり、BaO含有量が2.6mol%~5.3mol%の範囲内にあることを特徴とする請求項5に記載の半導体接合保護用ガラス組成物。
- 前記アルカリ土類金属の酸化物として、CaO及びBaOを含有することを特徴とする請求項1~4のいずれかに記載の半導体接合保護用ガラス組成物。
- 前記アルカリ土類金属の酸化物のうち、CaO含有量が2.0mol%~7.6mol%の範囲内にあり、BaO含有量が3.7mol%~5.9mol%の範囲内にあることを特徴とする請求項7に記載の半導体接合保護用ガラス組成物。
- ニッケル酸化物、銅酸化物、マンガン酸化物及びジルコニウム酸化物よりなる群から選択された少なくとも1つの金属酸化物をさらに含有することを特徴とする請求項1~8のいずれかに記載の半導体接合保護用ガラス組成物。
- ニッケル酸化物、銅酸化物、マンガン酸化物及びジルコニウム酸化物よりなる群から選択された少なくとも1つの金属酸化物の含有量が0.01mol%~2.0mol%の範囲内にあることを特徴とする請求項9に記載の半導体接合保護用ガラス組成物。
- pn接合が露出するpn接合露出部を有する半導体素子を準備する第1工程と、
前記pn接合露出部を覆うようにガラス層を形成する第2工程とをこの順序で含む半導体装置の製造方法であって、
前記第2工程においては、少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、50℃~550℃の温度範囲における平均線膨率が3.33×10-6~4.13×10-6の範囲内にある半導体接合保護用ガラス組成物を用いて前記ガラス層を形成することを特徴とする半導体装置の製造方法。 - pn接合が露出するpn接合露出部を有する半導体素子を準備する第1工程と、
前記pn接合露出部を覆うようにガラス層を形成する第2工程とをこの順序で含む半導体装置の製造方法であって、
前記第2工程においては、少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、SiO2の含有量が49.5mol%~64.3mol%の範囲内にあり、B2O3の含有量が8.4mol%~17.9mol%の範囲内にあり、Al2O3の含有量が3.7mol%~14.8mol%の範囲内にあり、ZnOの含有量が3.9mol%~14.2mol%の範囲内にあり、アルカリ土類金属の酸化物の含有量が7.4mol%~12.9mol%の範囲内にある半導体接合保護用ガラス組成物を用いて前記ガラス層を形成することを特徴とする半導体装置の製造方法。 - 前記第1工程は、主面に平行なpn接合を備える半導体基体を準備する工程と、前記半導体基体の一方の表面から前記pn接合を超える深さの溝を形成することにより、前記溝の内部に前記pn接合露出部を形成する工程とを含み、
前記第2工程は、前記溝の内部における前記pn接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項11又は12に記載の半導体装置の製造方法。 - 前記第2工程は、前記溝の内部における前記pn接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記第2工程は、前記溝の内部における前記pn接合露出部上に絶縁層を形成する工程と、前記絶縁層を介して前記pn接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記第1工程は、半導体基体の表面に前記pn接合露出部を形成する工程を含み、
前記第2工程は、前記半導体基体の表面における前記pn接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項11又は12に記載の半導体装置の製造方法。 - 前記第2工程は、前記半導体基体の表面における前記pn接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項16に記載の半導体装置の製造方法。
- 前記第2工程は、前記半導体基体の表面における前記pn接合露出部上に絶縁層を形成する工程と、前記絶縁層を介して前記pn接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項16に記載の半導体装置の製造方法。
- pn接合が露出するpn接合露出部を有する半導体素子と、
前記pn接合露出部を覆うように形成されたガラス層とを備える半導体装置であって、
前記ガラス層は、少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、50℃~550℃の温度範囲における平均線膨率が3.33×10-6~4.13×10-6の範囲内にある半導体接合保護用ガラス組成物を用いて形成されたものであることを特徴とする半導体装置。 - pn接合が露出するpn接合露出部を有する半導体素子と、
前記pn接合露出部を覆うように形成されたガラス層とを備える半導体装置であって、
前記ガラス層は、少なくともSiO2と、B2O3と、Al2O3と、ZnOと、CaO、MgO及びBaOのうち少なくとも2つのアルカリ土類金属の酸化物とを含有し、かつ、Pbと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物であって、SiO2の含有量が49.5mol%~64.3mol%の範囲内にあり、B2O3の含有量が8.4mol%~17.9mol%の範囲内にあり、Al2O3の含有量が3.7mol%~14.8mol%の範囲内にあり、ZnOの含有量が3.9mol%~14.2mol%の範囲内にあり、アルカリ土類金属の酸化物の含有量が7.4mol%~12.9mol%の範囲内にある半導体接合保護用ガラス組成物を用いて形成されたものであることを特徴とする半導体装置。
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