WO2013145545A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2013145545A1
WO2013145545A1 PCT/JP2013/001084 JP2013001084W WO2013145545A1 WO 2013145545 A1 WO2013145545 A1 WO 2013145545A1 JP 2013001084 W JP2013001084 W JP 2013001084W WO 2013145545 A1 WO2013145545 A1 WO 2013145545A1
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Prior art keywords
well region
semiconductor device
region
silicon carbide
diode
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PCT/JP2013/001084
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English (en)
French (fr)
Japanese (ja)
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梨菜 田中
古川　彰彦
昌之 今泉
阿部　雄次
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三菱電機株式会社
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Priority to US14/387,727 priority Critical patent/US9496344B2/en
Priority to DE112013003692.4T priority patent/DE112013003692T5/de
Priority to CN201380017760.7A priority patent/CN104205344A/zh
Priority to JP2014507365A priority patent/JP5774205B2/ja
Publication of WO2013145545A1 publication Critical patent/WO2013145545A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the present invention relates to an element structure and a manufacturing method of a semiconductor device which is a power semiconductor device.
  • JBS Joint Barrier Schottky
  • MPS Merged-Pi Schottky diode
  • Patent Document 1 In a JBS diode using a silicon semiconductor, a semiconductor device in which a P-type region includes a high impurity concentration portion (P +) covering an upper portion of a low impurity concentration portion (P ⁇ ) has been known (for example, Patent Document 1).
  • Patent Document 1 describes that a JBS diode can be obtained in which minority carrier accumulation in the pn diode portion is small and the reverse recovery time is short.
  • Patent Document 2 describes that in a JBS diode using a silicon carbide semiconductor not provided with an insulating region, the pn diode does not conduct when turned on.
  • Patent Document 1 when the structure of Patent Document 1 is applied to a wide bandgap semiconductor such as a silicon carbide semiconductor, the built-in potential of the pn diode becomes as large as about 3 V. Therefore, as described in Patent Document 2, Steady-state forward current mainly flows through the Schottky diode.
  • the present invention has been made to solve the above-described problems.
  • a JBS diode using a wide bandgap semiconductor such as silicon carbide the on-current is high, and the pn diode is easily turned on and is surge resistant.
  • An object of the present invention is to obtain a large semiconductor device.
  • a semiconductor device of the present invention includes a first conductivity type wide band gap semiconductor substrate, and a first conductivity type drift layer formed on the first main surface of the wide band gap semiconductor substrate and configured by a wide band gap semiconductor.
  • a plurality of second conductivity type first well regions formed adjacent to each other at a predetermined interval in a surface layer portion of the drift layer, and the first well on the semiconductor substrate side of the first well region
  • a second well region formed adjacent to the region and having a second conductivity type impurity concentration lower than that of the first well region and a width smaller than that of the first well region; and surfaces of the drift layer and the first impurity region
  • a Schottky electrode formed on the drift layer and Schottky connected to the drift layer; and an ohmic electrode formed in contact with a second main surface opposite to the first main surface of the semiconductor substrate.
  • the pn junction of the pn diode of the wide band gap JBS diode is formed at a location away from the Schottky electrode, and the width of the p-type region is narrowed away from the Schottky electrode. Therefore, a current can be passed through the pn diode with a lower bias voltage, and a current flowing through the Schottky diode can be increased. Therefore, even when a surge current is generated, the surge current can easily flow through the pn diode, the overcurrent can be suppressed from flowing through the Schottky diode, and a semiconductor device with a high switching speed and high surge resistance can be obtained.
  • FIG. 6 is a potential distribution diagram for illustrating the operation of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a potential distribution diagram for illustrating the operation of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a potential distribution diagram for illustrating the operation of the semiconductor device in the first embodiment of the present invention. It is a current ratio diagram for demonstrating operation
  • FIG. 7 is an on-current increase rate diagram for illustrating the operation of the semiconductor device in the first embodiment of the present invention. It is an on-current characteristic view of the semiconductor device in the first embodiment of the present invention. It is an off-current characteristic figure of the semiconductor device in Embodiment 1 of this invention.
  • 1 is a plan view schematically showing one form of a semiconductor device in Embodiment 1 of the present invention. It is a cross-sectional schematic diagram which represents typically the silicon carbide semiconductor device in Embodiment 2 of this invention. It is an on-current characteristic figure of the semiconductor device in Embodiment 2 of this invention. It is an off-current characteristic figure of the semiconductor device in Embodiment 2 of this invention.
  • Embodiment 1 the configuration of the semiconductor device according to the first embodiment of the present invention will be described.
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • FIG. 1 is a schematic cross-sectional view of a silicon carbide JBS diode which is a semiconductor device of the present embodiment.
  • an n-type drift layer 20 made of a 4H-type silicon carbide material is formed on a first main surface of a low-resistance n-type semiconductor substrate 10 made of a 4H-type silicon carbide material.
  • a plurality of p-type first well regions 30 formed adjacent to each other with a predetermined width and a predetermined interval are formed.
  • a second well region 40 having a lower p-type impurity concentration than the first well region 30 and a width smaller than the width of the first well region 30 is formed below the first well region 30 (on the semiconductor substrate 10 side).
  • An n-type drift layer 20 is formed between the second well region 40 and the semiconductor substrate 10.
  • a Schottky electrode 50 is formed on the surfaces of the first well region 30 and the drift layer 20.
  • an ohmic electrode 60 is formed on the second main surface opposite to the first main surface of the semiconductor substrate 10 so as to be in contact with the semiconductor substrate 10.
  • a p-type termination structure 70 is formed on the surface layer portion of the drift layer 20 at a location around the Schottky electrode 50.
  • FIG. 2 is a plan view of the silicon carbide JBS diode which is the semiconductor device of the present embodiment shown in FIG.
  • a Schottky electrode 50 is formed on the surface of the drift layer 20.
  • a termination structure 70 is formed in the surface layer portion of the drift layer 20 around the Schottky electrode 50.
  • a plurality of rectangular first well regions 30 as viewed from above are formed with a predetermined width and a predetermined interval.
  • a second well region 40 having a width smaller than the width of the first well region 30 is formed with the center of the first well region 30 being centered.
  • the semiconductor substrate 10 has a low resistance n-type
  • the (0001) plane has a polytype of 4H on the (0001) plane, and is in the c-axis direction.
  • 4H type silicon carbide semiconductor substrate inclined at 8 ° or less.
  • N-type silicon carbide semiconductor drift layer 20 contains nitrogen at a concentration of 1 ⁇ 10 13 cm ⁇ 3 to 1 ⁇ 10 16 cm ⁇ 3 as an n-type impurity, and has a thickness of about 10 to 100 ⁇ m.
  • the n-type impurity of the semiconductor substrate 10 and the drift layer 20 is nitrogen.
  • the p-type first well region 30 includes Al having a concentration of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 as a p-type impurity, and has a depth of 0.1 to 0.5 ⁇ m.
  • the p-type second well region 40 includes Al as a p-type impurity, the width thereof is smaller than the width of the first well region 30, and the depth is 0.5 to 6 ⁇ m.
  • the concentration of the p-type impurity in the second well region 40 is lower than the concentration of the p-type impurity in the first well region 30, for example, 1 to 2 digits lower.
  • the termination structure 70 is mainly a p-type region, and the shape may be appropriately selected from FLR (Field Limiting Ring) in which the cross-sectional shape is rectangular and the cross-sectional shape is discrete. What is necessary is just to also determine the density
  • the Schottky electrode 50 is Ti, and the ohmic electrode 60 is Ni.
  • FIG. 3 is a schematic cross-sectional view for illustrating a method for manufacturing a JBS diode using a silicon carbide semiconductor which is the semiconductor device of the present embodiment.
  • an n-type low-resistance silicon carbide semiconductor substrate 10 containing nitrogen at a concentration of about 1 ⁇ 10 18 cm ⁇ 3 or higher as an n-type impurity is chemically deposited.
  • a drift layer composed of silicon carbide having an n-type impurity concentration of 1 ⁇ 10 13 cm ⁇ 3 to 1 ⁇ 10 16 cm ⁇ 3 and a thickness of 1 to 5 ⁇ m is formed by a chemical vapor deposition (CVD) method.
  • One region 21 is epitaxially grown.
  • the second well region first region 41 is formed by ion-implanting the second conductivity type impurity Al at a predetermined position of the drift layer first region 21.
  • a drift layer second region 22 having a thickness of approximately 0.5 to 2 ⁇ m is epitaxially grown.
  • the second conductivity type impurity Al is ion-implanted into a position on the plane corresponding to the second well region first region 41 of the drift layer second region 22 to obtain the first.
  • a second well region second region 42 connected to the first well region first region 41 is formed.
  • the drift layer 20 having a predetermined thickness and the second well region 40 having a predetermined depth are formed.
  • the first well region 30 is formed by ion-implanting Al of the second conductivity type impurity at a predetermined position of the second well region 40 formed.
  • the termination structure 70 is formed by ion implantation of Al of the second conductivity type impurity, and activation annealing is performed on the ion implanted impurity.
  • the activation annealing may be performed under conditions such as a temperature range of 1500 to 2200 ° C. and a time range of 0.5 to 60 minutes.
  • a Schottky electrode 50 is formed on the surface of the drift layer 20 or the like by sputtering, and an ohmic electrode 60 is formed on the back surface (second main surface) side of the semiconductor substrate 10 by sputtering, so that the cross section shown in FIG.
  • a silicon carbide JBS diode that is a semiconductor device of the present embodiment can be manufactured.
  • the silicon carbide JBS diode that is the semiconductor device of the present embodiment, current flows from the Schottky electrode 50 toward the ohmic electrode 60 when turned on, but the potential of the ohmic electrode 60 is higher than the potential of the Schottky electrode 50 when turned off.
  • the reverse bias voltage is applied to the pn junction between the n-type drift layer 20 and the p-type first well region 30 or the second well region 40, and the n-type region and p A depletion layer is formed toward the mold region.
  • first well region 30 When a rated reverse bias voltage is applied to the silicon carbide JBS diode of the present embodiment, a depletion layer extending from first well region 30 is in contact with Schottky electrode 50 between adjacent first well regions when off. All the 20 surface layer portions are depleted, and the second well region is depleted from both sides in the cross-sectional lateral direction, so that the entire second well region 40 is completely depleted.
  • the first well region 30 has a second conductivity type impurity having a higher concentration than the second well region 40, and the width of the first well region 30 is larger than the width of the second well region 40. A region that is not fully depleted, i.e., not depleted, remains.
  • FIG. 4 is a schematic cross-sectional view showing a cross-sectional structure of a general silicon carbide JBS diode and a silicon carbide pn diode.
  • FIG. 4A is a cross-sectional view of the silicon carbide JBS diode, and FIG. It is a diode of a silicon pn diode.
  • the silicon carbide JBS diode corresponds to a silicon carbide JBS diode of the present embodiment in which the second well region 40 is omitted, that is, the second well region 40 remains the drift layer 20.
  • the silicon pn diode corresponds to the silicon carbide JBS diode of FIG. 4 and further having the first well region 30 formed on the entire surface.
  • n-type drift layers 21 and 22 are formed on semiconductor substrates 11 and 12.
  • p-type first well regions 31 and 32 are formed.
  • Schottky electrodes 51 and 52 are formed on the surface of the first well regions 31 and 32 or the drift layer 21.
  • ohmic electrodes 61 and 62 are formed on the second main surface opposite to the first main surface of the semiconductor substrates 11 and 12 in contact with the semiconductor substrates 11 and 12.
  • a plurality of p-type first well regions 31 are discretely formed.
  • the p-type first well region 32 is the drift layer 22. It is formed on the entire surface layer.
  • FIG. 5 shows a numerical calculation of the potential distribution in the current paths “A”, “B”, and “C” in FIG. 4.
  • the anode electrode Schottky electrodes 51, 52
  • the cathode electrode ohmic electrodes 61, 62.
  • the thickness of the drift layers 21 and 22 is 4 ⁇ m
  • the width of the first well region 31 in the cross-sectional lateral direction is 2 ⁇ m
  • the interval between the plurality of first well regions 31 is 2 ⁇ m (repetitive pitch is 4 ⁇ m).
  • the thickness of the first well regions 31 and 32 was 0.8 ⁇ m.
  • the potential distributions of the current paths “A”, “B”, and “C” in FIG. 5 Comparing the potential distributions of the current paths “A”, “B”, and “C” in FIG. 5, the potential distributions of the current paths “B” and “C” having the pn junction are substantially the same, This is different from the current path “A” having no pn junction.
  • the built-in potential of the pn junction is as high as about 3V, and the Schottky barrier between the Schottky electrode 51 and the drift layer 21 is large, so that no current flows at 0V bias.
  • FIG. 6 shows current paths “A”, “B”, and FIG. 4 when a bias voltage of 3 V is applied between the anode electrodes (Schottky electrodes 51, 52) and the cathode electrodes (ohmic electrodes 61, 62).
  • This is a numerical calculation of the potential distribution in “C”, and shows the potential depth distribution.
  • the thickness of the drift layers 21 and 22 and the width of the first well region 31 are the same as those in FIG. Comparing the potential distributions of the current paths “A”, “B”, and “C” in FIG. 6, there is a difference in potential distribution between the potential distributions of the current paths “B” and “C” having the pn junction. Has occurred.
  • FIG. 6 Comparing the potential distributions of the current paths “A”, “B”, and “C” in FIG. 6, there is a difference in potential distribution between the potential distributions of the current paths “B” and “C” having the pn junction. Has occurred.
  • the energy barrier is eliminated by applying a forward bias, and a current flows.
  • the energy barrier difference is substantially eliminated in the single silicon carbide pn diode of “C”, and current flows.
  • the potential of the n-type region is affected by the current flowing through the current path “A” of the Schottky diode portion of the adjacent silicon carbide JBS diode.
  • the potential difference between the p-type region and the n-type region is not reduced as much as “C”. For this reason, when a bias voltage of about 3 V is applied, the pn junction is not turned on and no current flows. In order to turn on the pn junction, it is necessary to apply a higher bias voltage.
  • the second well region 40 is provided below the first well region 30. Since the pn junction (the lower end of the second well region 40) is formed at a position away from the Schottky interface (the boundary between the Schottky electrode 50 and the drift layer 20), the potential of the pn junction is set as shown in FIG. The potential of the silicon carbide pn diode can be brought close to the potential difference between the p-type region and the n-type region of the pn junction. Therefore, the pn diode can be turned on by applying a lower bias voltage.
  • a great effect can be obtained by setting the depth (length in the longitudinal direction) of the second well region 40 to 3 to 6 ⁇ m. However, although it depends on the thickness of the drift layer 20, if it is 0.5 ⁇ m or more, the effect is obtained.
  • the current flowing through the Schottky diode portion is dominant in the on-current. Therefore, if the first well region 30 is formed deep as it is, the Schottky diode portion is turned on. The effect of the current spreading from the Schottky interface (boundary between the Schottky electrode 50 and the drift layer 20) toward the ohmic electrode 60 and the current flowing over the area equivalent to the area of the Schottky interface is suppressed, and the on-current is reduced.
  • FIG. 7 shows a general silicon carbide JBS diode whose cross-sectional view is shown in FIG. 4A.
  • a predetermined value is applied from the left and right end portions of the first well region 31.
  • FIG. It is a figure which showed the ratio which flows in the area
  • FIG. 7 shows numerical calculations for the case where the width of the first well region 31 is 4 ⁇ m, 10 ⁇ m, and 30 ⁇ m.
  • the first well region 31 is a region having a width of 25% with respect to the entire width of the first well region 31 from the end of the first well region 31, i. It can be seen that 50% or more of the current flowing under all the first well regions 31 flows where the area from the end is 25%. That is, only 50% or less of the current flowing under the first well region 31 flows in 75% of the area of the central portion of the first well region 31, and the on-current density is low here.
  • FIG. 8 is a diagram illustrating the on-state of the element when the ratio of the width of the second well region 40 to the width of the first well region 30 is changed in the silicon carbide JBS diode whose sectional view is shown in FIG. It is a figure showing how resistance, ie, resistance at the time of an element's ON, changes.
  • the horizontal axis indicates the ratio of the width of the second well region 40 to the width of the first well region 30, and the vertical axis indicates that the width of the second well region 40 is 0, that is, the second well region 40 is formed.
  • the rate of increase of the on-resistance of the element with respect to the on-resistance of the element in a non-existing state. .
  • the on-resistance increases as the ratio of the width of the second well region 40 to the first well region 30 increases, but when the ratio exceeds approximately 75%, the increase rate of the on-resistance increases. It can be seen that the slope with respect to the ratio is large.
  • the on-current flows from directly under the Schottky electrode 50 to the lower part of the first well region 30 and the second well region 40. As a result, the first well region 30 is directly under the first well region 30.
  • the width of the second well region 40 smaller than the width of the first well region 30 of the silicon carbide JBS diode having the structure of FIG. I understand.
  • the on-current can be increased as compared with the case where an insulating film is provided between the Schottky diode portion and the pn diode portion. More preferably, a portion having a width of 25% from the cross-sectional lateral end of the first well region 30 of the silicon carbide JBS diode having the structure of FIG.
  • the differential resistivity is 10 m ⁇ cm 2 or less
  • the drift layer 20 having a withstand voltage of 4 KV or more
  • the width of the first well region 30 is 4 ⁇ m
  • the depth is 0.3 ⁇ m
  • the impurity concentration is 2 ⁇ 10 18 cm. ⁇ 3
  • the width of the second well region 40 is 3 ⁇ m
  • the depth is 6 ⁇ m
  • the impurity concentration is 2 ⁇ 10 16 cm ⁇ 3 .
  • FIG. 9 compares the on-current characteristics of the silicon carbide JBS diode (conventional structure) having the structure of FIG. 4A and the silicon carbide JBS diode of the present embodiment.
  • the current density is higher than that of the conventional structure when the bias voltage is about 7 V or higher.
  • FIG. 10 is a comparison of off-current between the silicon carbide JBS diode having the structure of FIG. 4A and the silicon carbide JBS diode of the present embodiment.
  • the reverse current density is reduced compared to the conventional structure, the breakdown voltage is increased, and the breakdown voltage at the OFF time is improved.
  • first well region 30 containing a relatively high concentration of impurities is deepened as it is.
  • the withstand voltage at the time of off is not lowered as in the case of the time, and the withstand voltage at the time of off is improved.
  • the pn junction of the pn diode is formed at a location away from the Schottky electrode, and the width of the well region is increased at a location away from the Schottky electrode. Since it is formed narrowly, a current can flow with a low bias voltage by the pn diode, and the current flowing through the Schottky diode can be increased. Therefore, even when a surge current is generated, the surge current easily flows to the pn diode, and overcurrent can be suppressed from flowing to the Schottky diode. Therefore, the switching speed is high, and protection when a large current such as a surge is applied is protected. A semiconductor device with higher functions can be obtained.
  • the second well region 40 is completely depleted when the first well region 40 is off, so that the first well region 30 containing a relatively high concentration of impurities is deepened as it is.
  • the withstand voltage at the time of OFF does not decrease.
  • the silicon carbide JBS diode which is the semiconductor device of the present embodiment the first well region 30 is not completely depleted even when turned off, so that the depletion layer easily spreads in the drift layer 20 between the first well regions 30. A breakdown voltage can be secured.
  • a semiconductor device using a silicon carbide semiconductor has been described as an example.
  • a semiconductor device using a wide band gap semiconductor such as GaN or diamond has the same effect.
  • the silicon carbide semiconductor has the same effect regardless of whether it is a 4C silicon carbide semiconductor or a 3C silicon carbide semiconductor.
  • planar structure of the silicon carbide JBS diode of the present embodiment has been described with reference to an example in which the rectangular first well region 30 and the second well region 40 in FIG. 2 are arranged.
  • the present invention is not limited thereto, and as shown in a top view in FIG. 11, the first well region 30 and the second well region 40 having a square shape may be arranged vertically and horizontally. In such a case, the width is defined with respect to both the vertical direction and the horizontal direction in the plan view.
  • the planar structure is not limited to that shown in FIG. 2, but may be a polygonal shape or a circular shape as viewed from above.
  • n-type impurities and p-type impurities include nitrogen and aluminum, but the impurities may be other impurities, the n-type impurity may be phosphorus, and the p-type impurity may be boron.
  • Ti has been described as an example of the Schottky electrode 50 and the ohmic electrode 60 is Ni. However, the materials of the Schottky electrode 50 and the ohmic electrode 60 are not limited to these. What is necessary is just to select suitably from Mo, Ni, etc. which carry out Schottky connection with the drift layer 20 of this. In addition, as long as the ohmic electrode 60 is used, another metal may be used as long as the metal is in ohmic contact with the n-type semiconductor substrate 10.
  • the depletion layer extending from the first well region 30 depletes all the surface layer portions (Schottky interfaces) of the drift layer 20 in contact with the Schottky electrode 50 between the adjacent first well regions when off.
  • the Schottky interface does not need to be completely depleted when turned off, and the Schottky interface does not need to be completely depleted when turned off.
  • the second well region 40 is completely depleted when turned off.
  • the second well region 40 does not need to be completely depleted when turned off.
  • the second well region 40 may not be completely depleted when turned off.
  • FIG. FIG. 12 is a schematic cross-sectional view of a silicon carbide JBS diode which is a semiconductor device of the present embodiment.
  • the second well region 44 has a region of three levels of impurity concentration gradation in the vertical direction.
  • the second well region 44 is formed so that the impurity concentration becomes lower as the depth increases. That is, in the second well region 44, the p-type impurity concentration is lower at a position closest to the semiconductor substrate 10 than a region adjacent to the first well region 30. Since other points are the same as those in the first embodiment, detailed description thereof is omitted.
  • the impurity concentration of the first well region 30 is 2 ⁇ 10 18 cm ⁇ 3 and the impurity concentration of the second well region 44 is 2 ⁇ 10 18 cm ⁇ 3 , 2 ⁇ 10 in order from the shallowest.
  • the thicknesses of the three regions (44A, 44B, and 44C in order from the shallowest) are set to 2 ⁇ m at 17 cm ⁇ 3 and 2 ⁇ 10 16 cm ⁇ 3 will be described.
  • the average impurity concentration of the second well region 44 is lower than the impurity concentration of the first well region 30.
  • the silicon carbide JBS diode of FIG. 12 can be manufactured by changing the ion implantation concentration at each stage in the method described in FIG. 3 of the first embodiment.
  • FIG. 13 is a comparison of on-currents of the silicon carbide JBS diode having the structure of FIG. 4A, the silicon carbide JBS diode of the first embodiment of FIG. 1, and the silicon carbide JBS diode of the present embodiment (FIG. 1).
  • the current density increases from that of the conventional structure when the bias voltage is about 7 V or higher, and compared with the silicon carbide JBS diode of the first embodiment.
  • the on-current has increased.
  • FIG. 14 also compares the off currents of the silicon carbide JBS diode having the structure of FIG. 4A, the silicon carbide JBS diode of the first embodiment of FIG. 1, and the silicon carbide JBS diode of the present embodiment. Is.
  • the reverse current density is reduced, the breakdown voltage is increased, and the breakdown voltage at the time of OFF is improved as compared with the conventional structure. Further, in the silicon carbide JBS diode of the present embodiment, the reverse current density at the time of OFF is reduced as compared with the silicon carbide JBS diode of the first embodiment.
  • the on-current can be further increased as compared with the semiconductor device of the first embodiment, and the off characteristics can be improved.
  • FIG. 15 is a schematic cross-sectional view of a silicon carbide JBS diode which is a semiconductor device of the present embodiment.
  • the width of the second well region 40 of the first embodiment is constant, whereas the second well region 45 has a two-stage width in the vertical direction.
  • the second well region 45 is formed so that the width becomes smaller as the depth becomes deeper.
  • the width of the second well region 44 is narrower at the location closest to the semiconductor substrate 10 than the region adjacent to the first well region 30. Since other points are the same as those in the first embodiment, detailed description thereof is omitted.
  • the first well region 30 has an impurity concentration of 2 ⁇ 10 18 cm ⁇ 3 and the second well region 44 has a width of 3 ⁇ m and 1.5 ⁇ m in order from the shallowest two regions (shallow).
  • the thicknesses of 45A and 45B) are set to 3 ⁇ m in this order will be described.
  • the silicon carbide JBS diode of FIG. 15 can be manufactured by changing the opening width of the implantation mask at the time of ion implantation in the method described in FIG. 3 of the first embodiment.
  • FIG. 16 compares the on-currents of the silicon carbide JBS diode having the structure of FIG. 4A, the silicon carbide JBS diode of the first embodiment of FIG. 1, and the silicon carbide JBS diode of the present embodiment. is there.
  • the current density increases from that of the conventional structure when the bias voltage is around 7 V or higher, and is equal to or higher than that of the silicon carbide JBS diode of the first embodiment. Has on-current characteristics.
  • FIG. 17 also compares the off-current of the silicon carbide JBS diode having the structure of FIG. 4A, the silicon carbide JBS diode of the first embodiment of FIG. 1, and the silicon carbide JBS diode of the present embodiment. Is.
  • the reverse current density is reduced, the breakdown voltage is increased, and the breakdown voltage at the time of OFF is improved as compared with the conventional structure. Further, in the silicon carbide JBS diode of the present embodiment, the reverse current density at the time of OFF is reduced as compared with the silicon carbide JBS diode of the first embodiment.
  • the width of the well region is formed narrower at a location away from the Schottky electrode, so that the on-current characteristics can be further improved. it can.
  • FIG. 18 is a schematic cross-sectional view of a silicon carbide JBS diode which is a semiconductor device of the present embodiment.
  • the impurity concentration of n-type drift layer 20 in the first embodiment is made uniform, but in the surface layer portion of drift layer 20, drift layer 20 is in a region in contact with Schottky electrode 50 rather than drift layer 20.
  • An n-type high concentration drift region 80 having a high n-type impurity concentration is formed.
  • the high concentration drift region 80 is formed shallower than the second well region 40. Since other points are the same as those of the silicon carbide JBS diode described in the first embodiment, detailed description thereof is omitted.
  • the silicon carbide JBS diode shown in FIG. 18 is the surface of the drift layer 20 in the method described in FIG. 3 of the first embodiment, immediately after the final drift layer 20 (epitaxial layer) is formed or after the first well region 30 is formed.
  • the n-type high-concentration drift region 80 having an n-type impurity concentration higher than that of the drift layer 20 can be manufactured by ion implantation or the like in a region to be connected to the Schottky electrode 50 later.
  • the high concentration drift region 80 may be formed over the entire upper portion of the drift layer 20 as shown in the schematic cross-sectional view of FIG. In this case, the high concentration drift region 80 may be formed not by ion implantation but by epitaxial growth on the drift layer 20. Further, as shown in the schematic cross-sectional view of FIG. 20, the high concentration drift region 80 may be formed only in a part of the region where the first well region 30 is not formed.
  • the n-type impurity concentration of high concentration drift region 80 is increased in the region immediately below Schottky electrode 50 that becomes the current path of the on current, the on resistance can be reduced. it can. Further, since the high concentration drift region 80 is formed shallower than the second well region 40 in the surface layer portion of the drift layer 20, it is possible to avoid the bottom surface of the second well region 40 from becoming a high electric field, and the breakdown voltage is greatly deteriorated. Can be prevented.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the present invention is not limited to this, and the first conductivity type is p-type, Even if the conductivity type 2 is n-type, the same effect is obtained.
  • depletion indicates that the relationship between the voltage and the impurity concentration is designed so that depletion occurs.

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