WO2013124940A1 - Dispositif à semi-conducteur scellé par de la résine et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur scellé par de la résine et son procédé de fabrication Download PDF

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Publication number
WO2013124940A1
WO2013124940A1 PCT/JP2012/008023 JP2012008023W WO2013124940A1 WO 2013124940 A1 WO2013124940 A1 WO 2013124940A1 JP 2012008023 W JP2012008023 W JP 2012008023W WO 2013124940 A1 WO2013124940 A1 WO 2013124940A1
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Prior art keywords
resin
semiconductor device
filler
control element
power element
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PCT/JP2012/008023
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English (en)
Japanese (ja)
Inventor
南尾　匡紀
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パナソニック株式会社
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Priority to JP2013525060A priority Critical patent/JP5842109B2/ja
Publication of WO2013124940A1 publication Critical patent/WO2013124940A1/fr

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Definitions

  • the present invention relates to a resin-sealed semiconductor device and a method of manufacturing the same.
  • a sealed package is provided with a heat dissipation structure for cooling a semiconductor element by providing a gap between a metal cover and a refrigerant, and utilizing the heat of vaporization of the refrigerant absorbed by the porous member.
  • a heat dissipation structure for cooling a semiconductor element by providing a gap between a metal cover and a refrigerant, and utilizing the heat of vaporization of the refrigerant absorbed by the porous member.
  • FIG. 9 shows a cross-sectional configuration of the conventional sealed package disclosed in Patent Document 2. As shown in FIG.
  • the sealed package includes a substrate 102 on which the semiconductor element 101 is mounted, a metal cover 103 for covering the mounting surface of the substrate 102 and sealing the mounting surface, a flexible sheet 104, and a refrigerant. And the porous member 105 which adsorb
  • the semiconductor element 101 is in contact with the porous member 105 via the sheet 104. Therefore, when the temperature of the semiconductor element 101 rises, the refrigerant adsorbed by the porous member 105 is vaporized. As a result, the semiconductor element 101 is cooled by the heat of vaporization of the refrigerant.
  • the vaporized refrigerant vapor condenses in the form of water droplets on the inner wall surface of the metal cover 103 and is liquefied, and the liquefied refrigerant is adsorbed by the porous member 105.
  • JP 2008-004688 A Japanese Patent Application Publication No. 07-066575
  • the conventional hermetic package requires a porous member to be disposed inside the metal cover before joining the metal cover, which complicates the manufacturing process.
  • a resin-sealed semiconductor device includes: an exterior body; a lead frame which is sealed inside the exterior body and in which an end portion protrudes from the exterior body; A power element mounted on the lead frame and a control element sealed on the inside of the outer package and mounted on the lead frame, the power element and the control element in the outer package A sealing resin containing a filler is densely disposed in a region between the first and second regions in comparison with the other regions.
  • a lead frame on which a power element and a control element are mounted is disposed inside a mold to control the power element and control. Between the power element and the control element, the power element, the control element, and the lead frame are sealed with the second sealing resin after the first sealing resin containing the filler is injected into the region between the elements.
  • an outer package in which a sealing resin containing a filler is densely arranged is formed as compared with the other areas.
  • the long-term reliability of the semiconductor device can be secured.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a partial enlarged cross-sectional view showing the internal structure of the semiconductor device according to the embodiment of the present invention.
  • FIG. 3 is a plan view showing the internal structure of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4 is an enlarged plan view showing a porous filler used in a semiconductor device according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a step showing the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 6 is a plan view of a step showing the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a partial enlarged cross-sectional view showing the internal structure of the semiconductor device according to the embodiment of the present invention.
  • FIG. 3 is a plan view showing
  • FIG. 7 is a cross-sectional view of the next step showing the method of manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 8 is a plan view of the next process showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a conventional sealed package.
  • the present invention is not limited to the contents described below as long as it is based on the basic features described in the present specification.
  • FIG. 1 shows a cross-sectional configuration of a semiconductor device according to an embodiment.
  • FIG. 2 shows an enlarged sectional view of the region A of FIG.
  • the semiconductor device according to the present embodiment is a resin-sealed semiconductor device.
  • the semiconductor device according to the present embodiment is used by being incorporated into a photovoltaic power generation system or a built-in target device such as a home appliance motor or a motor for an electric vehicle (EV).
  • a photovoltaic power generation system or a built-in target device such as a home appliance motor or a motor for an electric vehicle (EV).
  • EV electric vehicle
  • the semiconductor device 10 at least includes a lead frame 11, a power device 12, a heat sink 30, a control device 14, and an exterior body 15. .
  • the lead frame 11 has a first die pad portion 16 on which the power element 12 is mounted, a second die pad portion 40 on which the control element 14 is mounted, and a plurality of leads.
  • the lead frame 11 is made of, for example, a material having high thermal conductivity, such as copper (Cu). A part of the lead frame 11 is sealed in the exterior body 15, and ends of a plurality of leads of the lead frame 11 project from the side surface of the exterior body 15 toward the outside of the exterior body 15.
  • the power element 12 is mounted on the upper surface 16 a of the first die pad portion 16 in the lead frame 11.
  • the power element 12 is mounted on the upper surface 16 a by, for example, a brazing material 26.
  • the control element 14 is mounted on the upper surface 40 a of the second die pad portion 40 in the lead frame 11.
  • the control element 14 is mounted on the upper surface 40 a by, for example, silver (Ag) paste.
  • the power element 12 is, for example, an IGBT (insulated gate bipolar transistor) or a power MOSFET (metal oxide film field effect transistor).
  • a bonding pad (not shown) of power element 12 and a plurality of leads of lead frame 11 are electrically connected by metal member 13.
  • the control element 14 is an element that controls the power element 12 and incorporates a drive circuit, an overcurrent prevention circuit, and the like.
  • the bonding pads (not shown) of the control element 14 and the plurality of leads of the lead frame 11 are electrically connected by the metal member 13.
  • a bonding pad (not shown) of power element 12 and a bonding pad (not shown) of control element 14 are electrically connected by metal member 13.
  • the control element 14 controls the power element 12 via the metal members 13.
  • a vertical power MOSFET to which a diode 50 is connected is taken as an example of the power element 12.
  • the diode 50 and the bonding pad (not shown) of the power element 12 are electrically connected by the metal member 13.
  • the metal member 13 for example, an aluminum (Al) wire or a gold (Au) wire will be described as an example.
  • an aluminum (Al) ribbon or a copper (Cu) clip may be used instead of the aluminum wire or the gold wire.
  • the aluminum ribbon or the copper clip has a large cross-sectional area and a small wiring resistance as compared with the aluminum wire or the gold wire, so that the power loss in the semiconductor device 10 can be reduced.
  • the heat sink 30 is formed of, for example, a metal having high thermal conductivity such as copper (Cu) or aluminum (Al).
  • the heat sink 30 is fixed to the lower surface 16 b of the first die pad portion 16 in the lead frame 11 via the insulating sheet 41.
  • the insulating sheet 41 is formed of a thermally conductive insulating material having a three-layer structure in which an insulating layer is sandwiched by adhesive layers. The insulating sheet 41 effectively transfers the heat generated from the power element 12 to the heat sink 30.
  • the heat dissipation plate 30 is sealed by the exterior body 15 so that the lower surface 30 b of the heat dissipation plate 30 is exposed from the lower surface 15 b of the exterior body 15.
  • the heat generated from the power element 12 is efficiently transferred from the exposed lower surface 30 b of the heat sink 30 to the outside through the insulating sheet 41. Further, in the semiconductor device 10, the side surface 30 c of the heat dissipation plate 30 is covered with the exterior body 15, so the heat dissipation plate 30 and the lead frame 11 are integrated.
  • the exterior body 15 is a sealing resin containing a porous filler 35 in a part thereof, and is made of, for example, a sealing resin made of a thermosetting resin such as epoxy.
  • region which contains the porous filler 35 which is a part of exterior body 15 is later mentioned using FIG.
  • the region containing the porous filler 35 is referred to as “heat sealing resin region”, and the other regions are referred to as “normal sealing resin region”.
  • the exterior body 15 encloses and seals a part of the lead frame 11 including the power element 12, the control element 14, the second die pad portion 40, and the side surface 30 c of the heat sink 30. By sealing in this manner, the lead frame 11 and the heat sink 30 can be integrated, and the power element 12 and the control element 14 can be protected.
  • FIG. 3 is an internal structure of the semiconductor device 10 according to the present embodiment, and shows a plan configuration thereof.
  • the end portions of the lead frames 11 respectively project from the side surfaces of the exterior body 15.
  • An end portion of the lead frame 11 is connected as a mounting terminal of the semiconductor device 10 to a circuit such as an inverter control device, for example.
  • the porous filler 35 is densely arranged as compared with the other regions to form a sealing resin region for heat insulation (a region including the porous filler 35 densely).
  • the heat insulating sealing resin region is formed between the power element 12 and the control element 14 (the porous filler 35 is disposed densely), the heat generated from the power element 12 is generally This is to prevent transfer to the heat weak control element 14.
  • the porous filler 35 is contained in a proportion of 70% by weight or more (more desirably 90% by weight or more) in the sealing resin region for heat insulation.
  • the porous filler 35 is disposed more unevenly on the power element 12 side than on the control element 14 side. Since the porous filler 35 is disposed on the side of the power element 12 more unevenly than the side of the control element 14, the heat generated from the power element 12 can be more reliably prevented from being transmitted to the control element 14. .
  • the porous filler 35 is disposed around the metal member 13 connecting the power element 12 and the control element 14.
  • the metal member 13 connecting the power element 12 and the control element 14 is an example of a first metal member.
  • the metal member 13 which connects the power element 12 and the control element 14 is arrange
  • power devices generate heat due to switching operation at high speed or large current.
  • the reliability with respect to the operation is significantly reduced, and the power element may malfunction. Therefore, high heat resistance elements such as GaN or SiC are beginning to be applied as constituent materials of power elements.
  • the control element is formed of silicon (Si), so its heat resistance is low. For example, when the temperature of the control element rises to 125 ° C. or more due to the heat conduction from the power element, the reliability of the operation of the control element may be significantly reduced and the control element may malfunction.
  • the semiconductor device 10 solves this problem, and the porous filler 35 is disposed more densely in the region between the power element 12 and the control element 14 than in the other regions, and sealing for heat insulation is performed. By forming the resin region, it is possible to realize the semiconductor device 10 with high long-term reliability.
  • FIG. 4 is an enlarged view of the porous filler 35 used for the semiconductor device 10 according to the present embodiment.
  • the porous filler 35 as shown in FIG. 4, includes a plurality of pore sites 35b, which are air layers, inside the porous filler site 35a.
  • the porous filler 35 examples include silicon dioxide (silica: SiO 2 ), magnesium oxide (MgO), aluminum oxide (alumina: Al 2 O 3 ) or boron nitride (BN).
  • the porous filler 35 is preferably, for example, a spherical filler having a specific surface area of 300 m 2 / g or more and an average particle diameter of about 1 ⁇ m to 10 ⁇ m. If the porous filler 35 is spherical, the porous filler 35 and the sealing resin of the outer package 15 are not in surface contact but in point contact, so the contact area between the porous filler 35 and the sealing resin of the outer package 15 is It can be as large as possible. By increasing the contact area between the porous filler 35 and the sealing resin of the outer package 15, the packing density of the sealing resin can be improved, and the adhesion of the porous filler 35 to the sealing resin can be improved. it can.
  • a biphenyl type epoxy resin is prepared by preparing a biphenyl type epoxy resin containing about 90% by weight of spherical porous filler 35 having an average particle diameter of 2.8 ⁇ m and a specific surface area of 380 m 2 / g.
  • a sealing resin for heat insulation was used as a sealing resin for heat insulation, and the region between the power element 12 and the control element 14 was sealed with this sealing resin for heat insulation to manufacture a semiconductor device 10.
  • the pore portion 35 b which is an air layer has a thermal conductivity of 0.0241 W / m ⁇ K, and 0.2 to 0.4 W / in the thermal conductivity of the epoxy resin. It is about one fifth to one tenth of the value of m ⁇ K.
  • the heat generation is transmitted to the heat sink 30 via the first die pad portion 16 and the insulating sheet 41, and the sheath covering the power element 12 It is transmitted to the body 15.
  • the transfer of heat is blocked (insulated) in the sealing resin region for heat insulation, and the heat influence on the control element 14 is reduced. It is considered that this is because the pore portion 35 b which is an air layer contained in the porous filler 35 has a thermal conductivity lower than that of the epoxy resin forming the exterior body 15.
  • the temperature of the control element 14 can be suppressed to less than 125 ° C. even when the power element 12 generates heat and the temperature rises to near 200 ° C.
  • the heat generation temperature of the control element 14 can be maintained at less than 125 ° C. by the porous filler 35 closely disposed in the region between the power element 12 and the control element 14 .
  • the porous filler 35 closely disposed in the region between the power element 12 and the control element 14 .
  • the heat sink 30 with the insulating sheet 41 temporarily attached to the upper surface is placed on the lower mold 62 with the heat sink 30 facing downward.
  • the lead frame 11 is mounted on the lower mold 62 so that the lower surface 16 b of the first die pad portion 16 in the lead frame 11 is in contact with the insulating sheet 41.
  • the upper mold 63 is lowered, and the lead frame 11 is clamped by the upper mold 63 and the lower mold 62. Thereby, a cavity 65 is formed between the upper mold 63 and the lower mold 62.
  • the interior of the cavity 65 is filled with the epoxy resin 75 containing the porous filler 35 from at least one gate 70 provided on the upper mold 63 by, for example, a transfer molding method.
  • the epoxy resin 75 is a sealing resin for forming a sealing resin region for heat insulation, and is an example of a first sealing resin.
  • the gate 70 is formed vertically above the space between the power element 12 disposed inside the cavity 65 and the control element 14. Thereby, the epoxy resin 75 containing the porous filler 35 is filled between the power element 12 and the control element 14.
  • the position of the gate 70 provided in the upper mold 63 is disposed closer to the power element 12 than the intermediate position between the power element 12 and the control element 14 as shown in FIGS. 5 and 6. Is preferred.
  • the ratio of containing the porous filler 35 is higher on the power element 12 side than on the control element 14 side. That is, in the semiconductor device 10 according to the present embodiment, the porous filler 35 is disposed more unevenly in the power element 12 side than in the control element 14 side.
  • the epoxy resin 75 containing the porous filler 35 can be filled more reliably.
  • the epoxy resin 66 is injected from the gate 64 provided on the side surface of the upper mold 63, and the epoxy resin 66 is filled into the inside of the cavity 65.
  • the epoxy resin 66 is usually a sealing resin for forming a sealing resin region, and is an example of a second sealing resin.
  • the epoxy resin 66 penetrates so as to completely fill the cavity 65 of the upper mold 63.
  • the epoxy resin 66 injected from the gate 64 has higher fluidity than the epoxy resin 75 injected from the gate 70. Therefore, as shown in FIG.
  • the epoxy resin 66 injected from the gate 64 is filled so as to fill the area except the epoxy resin 75 already filled from the gate 70. That is, the epoxy resin 75 filled in the sealing resin region for heat insulation is filled in with the epoxy resin 66 in the remaining region (usually the sealing resin region) as it is. As a result, the area between the power element 12 and the control element 14 (the heat insulating sealing resin area) is filled with the epoxy resin 75, and the other area (usually the sealing resin area) is filled with the epoxy resin 66. . Then, by curing these epoxy resins 75 and 66, the exterior body 15 shown in FIG. 1 can be configured, and the semiconductor device 10 can be manufactured.
  • the viscosity of the epoxy resin 66 not containing the porous filler 35 is about 0.01 Pa ⁇ s, and the viscosity of the epoxy resin 75 containing the porous filler 35 is about 2 Pa ⁇ s.
  • the volume of the epoxy resin 75 be equal to or less than one third of the volume of the epoxy resin 66.
  • the outer body 15 may be formed by filling the epoxy resin 66 so as to surround the periphery thereof.
  • the sealing resin region for heat insulation by the epoxy resin 75 can be formed more reliably between the power element 12 and the control element 14.
  • the porous filler 35 is densely disposed in the vicinity of the power element 12 and the control element 14 in the inside of the exterior body 15 and is unevenly distributed on the power element 12 side.
  • the semiconductor device 10 which raised the heat insulation effect between the power element 12 and the control element 14 is realizable.
  • the heat insulation effect between the power element 12 and the control element 14 is enhanced, and the heat dissipation characteristics from the power element 12 to the heat sink 30 can realize the semiconductor device 10 as in the related art. Therefore, even if the temperature of the power element 12 becomes high, the influence of heat on the control element 14 can be reduced, and the semiconductor device 10 with stable operation can be realized.
  • the one where the content rate of the porous filler 35 is as low as possible is desirable. This is because the heat generated by the drive of the power element 12 through the exterior body 5 is increased when the content ratio of the porous filler 35 becomes high also in the area excluding the space between the power element 12 and the control element 14 (usually the sealing resin area). This is because the heat can not be released, and the heat radiation path of the power element 12 is eliminated except through the heat radiation plate 30, and it is necessary to make the heat radiation plate 30 or the like larger.
  • the number of lead frames 11 is not limited as long as the object of the present invention is realized.
  • a lead frame in which two separate lead frames are integrated may be used.
  • the thermal conductivity of the heat sink 30 becomes unnecessary, and the epoxy resin 75 containing the porous filler 35 is applied to the entire inside of the cavity 65. It is also considered possible to fill. That is, it is considered possible not to use the epoxy resin 66 as the exterior body 15.
  • the resin-sealed semiconductor device and the method for manufacturing the same according to the present invention can be applied to semiconductor devices and the like used for devices for large power such as air conditioners.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention a trait à un dispositif à semi-conducteur (10) scellé par de la résine qui est doté : d'un logement extérieur (15) ; d'une grille de connexion (11), qui est scellée à l'intérieur du logement extérieur (15) et dont une des parties d'extrémité fait saillie à partir du logement extérieur (15) ; d'un élément d'alimentation électrique (12), qui est scellé à l'intérieur du logement extérieur (15) et qui est monté sur la grille de connexion (11) ; et d'un élément de commande (14), qui est scellé à l'intérieur du logement extérieur (15) et qui est monté sur la grille de connexion (11). Dans le logement extérieur (15), une résine d'étanchéité (résine époxy (75)) est disposée dans une région qui se trouve entre l'élément d'alimentation électrique (12) et l'élément de commande (14), ladite résine d'étanchéité contenant une charge (35) de façon plus dense par rapport à une résine d'étanchéité dans d'autres régions.
PCT/JP2012/008023 2012-02-23 2012-12-14 Dispositif à semi-conducteur scellé par de la résine et son procédé de fabrication WO2013124940A1 (fr)

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CN104901604A (zh) * 2014-03-06 2015-09-09 株式会社日立功率半导体 半导体装置以及采用它的马达和空调机
JP2018049894A (ja) * 2016-09-20 2018-03-29 株式会社Flosfia 半導体装置
JPWO2018142758A1 (ja) * 2017-01-31 2019-11-21 パナソニックＩｐマネジメント株式会社 電解コンデンサ
JP2020504451A (ja) * 2016-12-30 2020-02-06 日本テキサス・インスツルメンツ合同会社 表面が粗化された粒子を有するパッケージングされた半導体デバイス
US20210043604A1 (en) * 2019-08-06 2021-02-11 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same

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JP4381047B2 (ja) * 2003-07-09 2009-12-09 東芝三菱電機産業システム株式会社 半導体装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104901604A (zh) * 2014-03-06 2015-09-09 株式会社日立功率半导体 半导体装置以及采用它的马达和空调机
JP2018049894A (ja) * 2016-09-20 2018-03-29 株式会社Flosfia 半導体装置
JP2020504451A (ja) * 2016-12-30 2020-02-06 日本テキサス・インスツルメンツ合同会社 表面が粗化された粒子を有するパッケージングされた半導体デバイス
JP7206198B2 (ja) 2016-12-30 2023-01-17 テキサス インスツルメンツ インコーポレイテッド 表面が粗化された粒子を有するパッケージングされた半導体デバイス
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US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same

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