Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
  • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
  • H01L21/02005—Preparing bulk and homogeneous wafers
  • H01L21/02008—Multistep processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

• the invention relates to a manufacturing process of a 300mm silicon polishing sheet, in particular to a 300mm silicon polishing sheet manufacturing process using a high temperature heat treatment, wherein the high temperature refers to a temperature between 600-1 and 350 ° C, which is characterized by Subsequent high temperature heat treatment is used to replace the single-side grinding process in normal processing.
• a high temperature refers to a temperature between 600-1 and 350 ° C, which is characterized by Subsequent high temperature heat treatment is used to replace the single-side grinding process in normal processing.
• the manufacturing process of 300mm silicon polishing sheet is mainly divided into several main processes such as crystal pulling, slice lead angle, grinding, polishing and cleaning.
• the main purpose of the grinding and polishing process is to remove the damaged surface of the surface caused by the slicing and obtain a smooth, defect-free, well-formed surface.
• the conventional grinding process is replaced by a grinding process to obtain a better TTV and geometry, but also a surface damage layer.
• the grinding process uses a grinding wheel to thin the silicon wafer, but the impact of the grinding wheel on the surface of the silicon wafer will cause residual damage on the surface of the silicon wafer after grinding.
• the thickness of the damaged layer is about 5-1 Oum, which is determined by the processing technology and the grinding wheel. Particle size.
• the two-step grinding process generally adopts the method of double-side grinding and single-side grinding, that is, the surface of the silicon wafer is coarsely ground by double-side grinding, the damaged layer caused by the slicing process is removed, and then the single-sided grinding is performed. Grinding removes the damaged layer from double-sided grinding.
• the polished silicon wafer has a low degree of damage and damage to the surface and can be easily removed during the polishing process.
• Chemical corrosion is the chemical damage of the surface damage layer.
• the common corrosion process has two processes: acid corrosion and alkali corrosion. However, it is difficult to control the geometric parameters of the silicon wafer by the etching process. The excellent geometric parameters obtained after grinding are often damage.
• the concentration of the slurry, the flow rate, and the pressure during the polishing process all affect the removal efficiency of the micro-damage layer.
• the silicon wafer After the silicon wafer is polished, it can be judged whether there is any damage layer on the surface of the silicon wafer by Raman spectroscopy, transmission electron microscopy, wet oxidation and chemical etching.
• all the above characterization methods can be carried out after polishing, and it is a destructive test. Therefore, the micro-damage problem in the manufacturing process of the silicon wafer is controlled by these characterization methods, which not only brings waste of manufacturing cost, but also brings about Prolonged manufacturing time.
• Fig. 1 shows the surface micro-damage area characterized by transmission electron microscopy and wet oxidation plus chemical etching. Summary of the invention
• the process flow is simple, and the production efficiency can be improved, and the quality of the silicon wafer can be improved.
• the present invention adopts the following technical solutions:
• This 300mm silicon polishing pad manufacturing process using high temperature heat treatment includes: crystal pulling, sliced lead angle, double side grinding, double side polishing, final polishing, and high temperature heat treatment.
• the invention provides a new silicon polishing sheet processing flow, which preserves double-side grinding in a new process, directly polishing after grinding, and omits the single-side grinding process, and the surface micro-damage which is not eliminated by polishing is subjected to subsequent high-temperature heat treatment.
• the process is eliminated, and the micro defect distribution having internal gettering properties can also be formed in the silicon wafer by appropriately adjusting the high temperature heat treatment temperature.
• the high-temperature heat treatment process is introduced into the process of the present invention, and the high-temperature heat treatment (1 250-1 300 ° C) silicon polishing sheet is used to release the stress in the micro-damage region of the high-temperature surface layer, and the lattice energy at the surface layer is released at a high temperature. Self-healing of the lattice.
• the heat treatment process also combines the traditional internal gettering heat treatment process. After the high temperature treated silicon wafer, the surface micro-damage area disappears, and the defect distribution with the gettering performance is formed in the silicon wafer.
• the specific heat treatment process steps include: Wl, W2, W3, W4, W5, W0, W7, W8, and then, after cooling to room temperature under a pure nitrogen atmosphere, the slide is discharged, and the surface layer is free from micro stress and has internal suction.
• the structure of the oxygen precipitates the distribution of silicon wafers.
• the heat treatment process can quickly cool the silicon wafer to 050 ° C (W8) under the premise of no thermal slip at the end of the high temperature heat treatment constant temperature (ie, 1250-1 300 ° C), the flow rate of argon gas At 10 - 80 L / min; cooled to room temperature under a pure nitrogen atmosphere, the slide was released, and a silicon sheet having no micro-stress on the surface layer was obtained.
• the high temperature heat treatment process is suitable for all polished silicon wafers that have been qualified for surface and geometry. After the final mechanochemical polishing, as long as the micro-damage layer on the surface of the silicon wafer is in the range of 2 ⁇ m, the loss layer can be eliminated by the high-temperature heat treatment process of the patent. After high-temperature heat treatment, the silicon wafer can be directly shipped from the factory, or it can be packaged after normal cleaning process.
• the high temperature heat treatment process introduced in this patent aims to eliminate residual micro damage on the surface of the silicon wafer after grinding and polishing.
• This special The feature is a high-temperature heat treatment process, which introduces a high-temperature heat treatment process to replace the fine grinding process before polishing, and a high-temperature heat treatment to eliminate micro-damage after polishing.
• Table 1 shows the comparison between the normal wafer processing process and the patent processing process, and the thickness of the surface micro-damage layer after each step.
• the patent is characterized by direct polishing after double-side grinding and then introducing a high-temperature heat treatment process to eliminate the micro-damage layer. Compared to the current process, the single-side grinding process or the etching process before polishing is abandoned.
• the invention has the advantages that: through the change of the process flow, the production efficiency can be improved, and the surface quality of the silicon wafer can be improved, and the silicon wafer can have the gettering ability.
• This patent features a high temperature annealing process.
• the high temperature heat treatment of 1 250-1 350 °C can effectively remove residual micro-damage after polishing, and can also form micro-defect distribution of internal gettering results in the silicon wafer by subsequent heat treatment.
• Figure L1 Cross section of silicon wafer after grinding of 2000# grinding wheel TEM morphology 50000 ⁇
• Fig. 1. 2 After the grinding of the silicon wafer after 2000# grinding wheel, after the thermal oxidation of the polishing, the result of observation under the optical microscope after Secco corrosion is 200 X
• the heat treatment process is mainly divided into two processes of high-temperature heat treatment to eliminate micro-damage and oxygen precipitation nucleation, and the two heat treatment processes have different requirements on atmosphere, temperature rise and fall, and the like.
• the two processes of the high temperature heat treatment process include different temperature stages: Wl, W2, W3, W4, W5, W0, W7, W8, wherein the high temperature heat treatment eliminates the micro damage process including: 050° C loaded with silicon wafers, 050 ° C temperature rise, 1 250-1 300 ° C constant temperature repair micro-damage and other temperature stages.
• the oxygen precipitation nucleation process consists of 800 °C constant temperature and small hour (W5), slowly warming to 1 000 ° C (W0), 1 000 ° C constant temperature 12-1 0 hours (W7), the silicon wafer is quickly cooled to Several temperature stages such as 650V (W8).
• Wafer loading (W1) at 050 °C It is necessary to meet the conditions of clean surface of silicon wafer and pure nitrogen atmosphere. Because the heat treatment process of the present invention is set in the final stage of the wafer processing, the silicon wafer must pass the standard. The cleaning process to eliminate possible surface reactions at high temperatures on the surface of the wafer and in the body affects the quality of the wafer. At the same time, the loading of the silicon wafer must be carried out under a nitrogen atmosphere to avoid the reaction of oxygen and moisture in the environment with the surface of the wafer. The oxygen and moisture content of the environment in the slide should be less than 1 ppma.
• the cavity After the silicon wafer is loaded into the cavity, the cavity reaches a thermal equilibrium for a certain period of time, and argon gas is introduced to gradually replace the nitrogen in the heating chamber. If there is residual nitrogen in the cavity, a portion of the surface of the silicon wafer will occur under high temperature. For the nitridation reaction, the entire constant temperature and nitrogen replacement takes about 10-20 min.
• the argon used in the whole process is high purity argon with a purity greater than 99.99999% and the ratio of water to oxygen in the atmosphere does not exceed 10 ppb.
• the purity of the nitrogen used in the loading chamber is higher than 99.999%, and the ratio of water to oxygen in the atmosphere does not exceed 1 ppm.
• the chamber can be heated to 1250-1 300 °C (W2).
• the whole heating process needs to control the heating rate to avoid thermal slip on the surface of the silicon wafer, which can reduce the temperature rise. At the same time, the heat slip is avoided at the same time.
• argon gas is continuously charged, and the flow rate of argon gas is 10-50 L/min. 3.
• the silicon wafer is kept at a constant temperature (W3) at about 1 250-1 300 °C, and the constant temperature is 30-00 min. The flow rate of argon gas is maintained at 10-50 L/min.
• the interstitial oxygen content in the Czochralski single crystal is generally around 20-40 ppma (old-ASTM), at high temperature.
• the surface interstitial oxygen will diffuse to the surface, so that in the subsequent heat treatment of oxygen precipitation nucleation and growth, the concentration of interstitial oxygen cannot satisfy the condition of oxygen precipitation nucleation growth due to the out-diffusion of surface interstitial oxygen.
• 800 °C constant temperature ⁇ hour (W5), 800 °C constant temperature is to let the diffusion of oxygen in the silicon wafer to form a oxygen precipitation core, the flow rate of argon gas is 1 0-50L / min.
• the formation of the oxygen precipitation core is directly related to the constant temperature.
• the core diameter of the oxygen precipitate is larger than the critical diameter, it can be stably present, but if it is heated rapidly, it may cause the already existing oxygen precipitation core to be dissolved again.
• the core is precipitated by oxygen at a temperature of 800 ° C, and then slowly heated to ensure that the oxygen precipitation core gradually grows as the temperature increases. At a constant temperature of 1 000 ° C, these gradually growing oxygen-precipitating cores grow again, forming a stable oxygen precipitation. After the 1 000 °C constant temperature is over,
• the silicon wafer is rapidly cooled to 650V (W8), and the flow rate of argon gas is between 10 and 80L/min.
• Fig. 2 The specific temperature rise, constant temperature, and temperature drop curves are shown in Fig. 2.
• the ordinate is temperature ( °C) and the horizontal coordinate is constant temperature (hour).
• the metal content on the surface of the silicon wafer, the bending, warpage, and surface slip line of the silicon wafer are the main monitoring parameters.
• High-temperature annealing furnace The silicon wafer supporting structure is a necessary condition for ensuring the geometric parameters (bending and warping) of the silicon wafer.
• the proper silicon supporting structure can ensure that the geometric parameters of the silicon wafer do not deteriorate during the high temperature process.
• the high temperature heat treatment furnace has a controlled temperature rise and fall speed, the uniform stability of the heat field in the furnace chamber and the uniform force of the silicon wafer on the support structure.
• the selection and design of the high temperature heat treatment furnace is the premise guarantee of the high temperature heat treatment process.
• the loading zone of the silicon wafer and the heat treatment furnace tube were placed in a cavity, and the cavity was maintained in a nitrogen atmosphere.
• the support structure of the silicon wafer is shown in Fig. 3a and Fig. 3b.
• the silicon wafer is placed on the SiC support plate and then placed in the groove of the SiC boat.
• the SiC boat is composed of three columns, and the same position on each column. There are 100-150 grooves, and the number of grooves determines the number of wafers processed per batch in a high temperature annealing furnace. To ensure that no thermal slip occurs, the silicon wafer and the SiC support disk must be placed concentrically.
• the silicon wafer is placed on the SiC support plate by a robot and then placed entirely on the SiC boat.
• Figure 4 shows the placement of the silicon wafer.
• the SiC support disk is placed on a positioning table.
• the three vertical columns on the positioning table and the three small holes on the support plate are equilaterally triangular, and the three columns are just able to
• the support disk is secured by a small hole through the support disk.
• the SiC support disk is placed on the positioning table by the robot, and then the silicon wafer is placed on the three pillars of the fixed support plate.
• the robot holds the SiC support plate vertically, the silicon wafer falls on the SiC support. On the plate.
• By adjusting the position at which the robot places the silicon wafer on the column it is possible to ensure that the silicon wafer and the SiC support disk are concentric.
• Figure 5 shows a half-section of the SiC support disk.
• Embodiment 1 is a diagrammatic representation of Embodiment 1:
• a 300 mm single crystal silicon rod is subjected to barrel grinding, wire cutting, and edge chamfering to form a wire cutting piece having a thickness of about 900 ⁇ m. Then use the processing mode of this process to make a 300mm silicon polishing sheet:
• Double-sided grinding Double-sided grinding of silicon wafers with 2000# grinding wheel, single-sided removal of 45um. A grinding disc having a thickness of 810 um and a GBIR of 0.8 um was obtained. 2. Double-sided polishing: With a polishing cloth of Suba 800, the removal on one side is 20um. Obtained a double-sided polished sheet with a thickness of 790um and a GBIR of 0.4um
• Wafer cleaning removes the polishing solution introduced by the final polishing.
• High-temperature heat treatment the specific process of high-temperature heat treatment is shown in Table 2.
• the treatment time of the high-temperature heat treatment is relatively short, and the treatment purpose is only to eliminate the micro-damage of the surface layer of the silicon wafer, and basically no clean zone and oxygen precipitation distribution are formed in the silicon wafer.
• Embodiment 2 is a diagrammatic representation of Embodiment 1:
• a 300 mm single crystal silicon rod is subjected to barrel grinding, wire cutting, and edge chamfering to form a wire cutting piece having a thickness of about 900 ⁇ m. Then, a 300 mm silicon polishing sheet is manufactured by the processing mode of the present process, and a clean area distribution having internal gettering properties is introduced in one step of high temperature heat treatment:
• Double-sided grinding Double-sided grinding of silicon wafers with 2000# grinding wheel, with a single-sided removal of 45um. A grinding disc with a thickness of 810 um and a GBIR of 0.8 um was obtained.
• Double-sided polishing The polishing cloth with Suba 800 has a single-sided removal of 20um. Obtained a double-sided polished sheet with a thickness of 790um and a GBIR of 0.4um
• Wafer cleaning removes the polishing solution introduced by the final polishing.
• High temperature heat treatment the specific process of high temperature heat treatment is shown in Table 3.
• the treatment process takes a long time, and the heat treatment process includes the elimination of surface micro-damage and the increase of oxygen precipitation nucleation growth treatment.
• the cleavage surface was etched by Wright etching solution, and then the distribution of the clean area and the oxygen precipitate was observed under an optical microscope, and the cleanliness shown in Fig. 5 was obtained. Zone and oxygen precipitation distribution, this clean zone

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• 2011
  • 2011-12-06 CN CN201110401693.1A patent/CN103144024B/zh active Active
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