WO2012126334A1 - 直拉硅片的内吸杂工艺 - Google Patents

直拉硅片的内吸杂工艺 Download PDF

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WO2012126334A1
WO2012126334A1 PCT/CN2012/072453 CN2012072453W WO2012126334A1 WO 2012126334 A1 WO2012126334 A1 WO 2012126334A1 CN 2012072453 W CN2012072453 W CN 2012072453W WO 2012126334 A1 WO2012126334 A1 WO 2012126334A1
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silicon wafer
czochralski
czochralski silicon
rate
temperature
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PCT/CN2012/072453
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马向阳
徐泽
王彪
杨德仁
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浙江大学
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Priority to US13/695,517 priority Critical patent/US8466043B2/en
Publication of WO2012126334A1 publication Critical patent/WO2012126334A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Definitions

  • the invention relates to a silicon wafer gettering process, in particular to an internal gettering process of a Czochralski silicon wafer. Background technique
  • Czochralski wafers are the basic material of integrated circuits, and one of the root causes is that Czochralski silicon wafers have internal gettering capabilities associated with oxygen precipitation.
  • the integrated circuit will inevitably encounter metal contamination during the manufacturing process. If the metal contamination in the active area of the device cannot be eliminated, the manufacturing yield of the integrated circuit will be significantly reduced.
  • a high-density oxygen precipitate and its induced defects (this region is called a micro-defective region) are usually formed in the silicon wafer; and the near-surface region of the silicon wafer (ie, the active region of the device) is made. No oxygen precipitation is formed (this area is called a clean area).
  • the oxygen precipitation in the silicon wafer as described above and its induced defects act to absorb the metal contamination in the active region of the device, which is called internal gettering.
  • internal gettering a heat treatment process for forming a clean region and a body defect region in a Czochralski wafer is referred to as an internal gettering process.
  • the first type is a high-temperature-low temperature-high temperature three-step heat treatment method, that is, first, the silicon wafer is heat-treated at 1100 to 1200 °C for several hours to externally diffuse oxygen in the near surface region of the silicon wafer, thereby lowering the oxygen concentration in the region.
  • the purpose of this step of heat treatment is to form a clean area; then, The silicon wafer is heat treated at 600 ⁇ 800 °C for several hours to agglomerate the interstitial oxygen atoms in the silicon wafer to form an oxygen precipitation core.
  • the silicon wafer is Annealing at 1000-1100 °C for a long time (such as: 16 hours) causes the oxygen precipitation core in the silicon wafer to grow to form oxygen precipitation and its induced defects. At this time, oxygen precipitation does not form in the near surface region of the silicon wafer.
  • the second is the so-called "Magic Denuded Zone (MDZ)" process proposed by MEMC Corporation of the United States based on high-temperature rapid heat treatment.
  • the typical heat treatment steps are as follows: First, the silicon wafer is rapidly heat treated at 1250 ° C for 60 seconds under an argon atmosphere, and then Cool at a certain rate. This heat treatment step forms a high concentration of vacancies in the silicon wafer, and the hole concentration gradually decreases from the silicon wafer to the surface to a very low concentration due to the external diffusion of the vacancies. Then, the silicon wafer is heat treated at 800 ° C for 4 hours.
  • the silicon wafer is heat-treated at 1000 ° C for 16 hours. At this time, oxygen precipitation and its induced defects are formed in the silicon wafer, and no oxygen precipitate is formed in the near surface region of the silicon wafer.
  • MEMC's proposed thermal budget for the MDZ process has been much lower than the traditional high-temperature-high temperature three-step heat treatment process.
  • the thermal budget of the process of very large scale integrated circuits has been continuously decreasing, and the internal gettering process of the Czochralski silicon wafer needs to be further reduced. Since very large scale integrated circuits are fabricated using 200mm and 300mm silicon wafers, the low thermal budget internal gettering process is more important for 200mm and 300mm silicon wafers.
  • the present invention provides an internal gettering process for forming a Czochralski silicon wafer into a near surface clean region and a bulk micro defect region.
  • the process has a low thermal budget and is particularly suitable for 200 mm and 300 mm silicon wafers.
  • An internal gettering process for a Czochralski wafer comprising:
  • the Czochralski wafer processed by the step (1) is annealed at 800 to 900 ° C for 8 to 16 hours under an argon atmosphere.
  • the nitrogen concentration is greater than 99.99%.
  • the density of the micro-defects and the width of the clean area can be controlled by controlling the temperature, duration, and cooling rate of the rapid thermal processing (RTP).
  • RTP rapid thermal processing
  • the present invention has the following beneficial effects: (1) The thermal budget is significantly reduced, and only the two-step heat treatment process is included, and the required temperature and time are lower than those of the prior art.
  • DRAWINGS 1 is a cross-sectional optical micrograph of a Czochralski wafer containing a clean region and a bulk microdefect region obtained in Example 1 after preferential etching.
  • Fig. 2 is a cross-sectional optical micrograph of the Czochralski silicon wafer containing the clean region and the bulk microdefective region obtained in Example 3 after preferential etching.
  • Fig. 3 is a cross-sectional optical micrograph of the Czochralski wafer containing the clean region and the bulk microdefective region obtained in Example 4 after preferential etching.
  • a Czochralski wafer with a diameter of 300 mm, a crystal orientation of ⁇ 100> and an interstitial oxygen concentration of 8 ⁇ 10 17 cm- 3 is rapidly heat treated (RTP) under a high purity (purity greater than 99.99%) nitrogen atmosphere. : ramp up to 1250 ° C at 100 ° C / sec for 60 seconds, then cool to 800 ° C at 5 ° C / sec, then turn off the power to allow the silicon wafer to cool naturally;
  • Fig. 1 is an optical micrograph of a cross section of a silicon wafer obtained after the treatment of Example 1 after preferential etching. It can be seen from Fig. 1 that a defect-free clean zone is formed on the near surface of the silicon wafer, and a density micro-defective region is next to it, which plays a role of internal gettering.
  • the diameter is 200mm, the crystal orientation is ⁇ 100>, and the interstitial oxygen concentration is 8xl0 17 cm- 3
  • the Czochralski silicon wafer is rapidly heat treated (RTP) under a high purity nitrogen atmosphere at a temperature of 100 ° C / sec to 1200 ° C for 120 seconds, then cooled to 50 ° C / sec to 1000 ° C, after which the power is turned off to allow the silicon wafer to cool naturally;
  • Example 3 The effect after the implementation was similar to that of Example 1, in which the silicon wafer contained a clean area and a body micro defect area.
  • Example 3 The effect after the implementation was similar to that of Example 1, in which the silicon wafer contained a clean area and a body micro defect area.
  • a direct-drawing silicon wafer having a diameter of 300 mm, a crystal orientation of ⁇ 100> and a gap oxygen concentration of 9 ⁇ 10 17 cm- 3 is rapidly heat treated (RTP) under a nitrogen atmosphere, and the conditions are: 100 ° C / sec. The temperature is raised to 1200 ° C for 150 seconds, then cooled to 1000 ° C at a rate of 5 ° C / sec, after which the power is turned off to allow the silicon wafer to cool naturally;
  • Fig. 2 is an optical microscopy photograph of the cross section of the silicon wafer obtained after Example 3 after preferential etching. As can be seen from Fig. 2, a defect-free clean area is formed on the near surface of the silicon wafer, and a density micro-defective area is next to it, which plays a role of internal gettering.
  • Example 4
  • a Czochralski silicon wafer having a diameter of 200 mm, a crystal orientation of ⁇ 100> and an interstitial oxygen concentration of 7.5 ⁇ 10 17 cm- 3 is rapidly heat treated (RTP) under a high purity nitrogen atmosphere at a condition of: 100 °C. / sec speed up to 1250 ° C, for 30 seconds, then cool at 5 ° C / sec to 800 ° C, after which the power is turned off to allow the silicon wafer to cool naturally;
  • Fig. 3 is an optical micrograph of the cross section of the silicon wafer obtained after the treatment of Example 4 after preferential etching. As can be seen from Fig. 3, a defect-free clean area is formed on the near surface of the silicon wafer, and a density micro-defective area is next to it, which plays a role of internal gettering.

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Description

直拉硅片的内吸杂工艺 技术领域
本发明涉及一种硅片吸杂工艺，尤其涉及一种直拉硅片的内吸杂 工艺。 背景技术
直拉硅片是集成电路的基础材料，其根本原因之一在于直拉硅片 具有与氧沉淀相关的内吸杂能力。集成电路在制造过程中会不可避免 的遭遇金属沾污， 若器件有源区的金属沾污不能被消除， 集成电路的 制造成品率将显著下降。 为了解决这一问题， 通常使硅片体内形成高 密度的氧沉淀及其诱生缺陷 （这一区域称为体微缺陷区）； 而使硅片 近表面区（即：器件的有源区）不形成氧沉淀（这一区域称为洁净区）。 如上所述的硅片体内氧沉淀及其诱生缺陷起着吸收器件有源区中金 属沾污的作用， 这就是所谓的内吸杂。 通常， 把使直拉硅片中形成洁 净区和体 缺陷区的热处理工艺称为内吸杂工艺。
目前， 直拉硅片中的内吸杂工艺主要有两种。 第一种是高温-低 温-高温三步热处理法， 即： 首先， 将硅片在 1100 ~ 1200 °C热处理数 小时， 使硅片近表面区的氧发生外扩散， 使该区域的氧浓度降低， 从 而避免氧沉淀的形成， 这一步热处理的目的是形成洁净区； 然后， 将 硅片在 600 ~ 800°C热处理数小时， 使硅片体内的间隙氧原子发生团 聚而形成氧沉淀核心， 此时近表面区域氧浓度较低， 间隙氧原子不容 易团聚； 最后， 将硅片在 1000-1100°C长时间 (如: 16小时）退火， 使硅片体内的氧沉淀核心长大而形成氧沉淀及其诱生缺陷，此时硅片 近表面区域不会形成氧沉淀。
第二种是美国 MEMC公司提出的基于高温快速热处理的所谓 "Magic denuded zone (MDZ)"工艺， 其典型的热处理步骤如下： 首先， 将硅片在氩气氛下 1250°C快速热处理 60秒，然后以一定的速率冷却。 这一热处理步骤会在硅片体内形成高浓度的空位，而由于空位的外扩 散， 空穴浓度从硅片体内到表面逐渐降低到很低的浓度。 然后， 将硅 片在 800°C热处理 4小时， 此时， 在硅片体内较高浓度的空位可显著 促进氧沉淀的形核，而在硅片近表面区域则由于空位浓度较低而不会 发生氧沉淀的形核； 最后， 将硅片在 1000 °C热处理 16小时， 此时， 在硅片体内形成氧沉淀及其诱生缺陷，而在硅片近表面区不会形成氧 沉淀。
相比之下， MEMC公司提出的 MDZ工艺的热预算已经比传统的 高温-低温-高温三步热处理工艺降低了很多。 然而极大规模集成电路 的工艺的热预算有不断降低的趋势，因而直拉硅片的内吸杂工艺也需 要进一步降低。由于极大规模集成电路使用 200mm和 300mm硅片制 造， 因此，低热预算的内吸杂工艺对于 200mm和 300mm硅片而言更 为重要。 发明内容
本发明提供了一种使直拉硅片形成近表面洁净区和体微缺陷区 的内吸杂工艺， 该工艺具有热预算低的特点， 特别适合于 200mm和 300mm硅片。
一种直拉硅片的内吸杂工艺， 包括：
( 1 )在氮气氛下， 将直拉硅片以 50 ~ 100°C/秒的速率升温至 1200 - 1250 °C , 维持 30 ~ 150秒， 然后以 5 ~ 50°C/秒的速率冷却至 800 ~ 1000 °C , 接着自然冷却；
( 2 )将经步骤（ 1 )处理后的直拉硅片在氩气氛下于 800 ~ 900 °C 退火 8 ~ 16小时。
所述的氮气浓度大于 99.99%。
本发明中， 通过控制快速热处理 (RTP)的温度、 持续时间、 冷却 速率可以控制体微缺陷的密度和洁净区的宽度。快速热处理的温度越 高、 持续时间越长和冷却速度越高， 则体微缺陷的密度越高， 而洁净 区的宽度越小。 反之， 体微缺陷的密度越低， 而洁净区的宽度越大。
与现有的内吸杂工艺相比， 本发明具有以下有益的效果： ( 1 ) 热预算显著降低， 仅包含两步热处理工艺， 所需温度和时 间比现有工艺的要低。
( 2 )体微缺陷的浓度和洁净区宽度可以很方便地通过第一步快 速热处理的温度、 时间和冷却速率得到控制。 附图说明 图 1为实施例 1得到的包含洁净区和体微缺陷区的直拉硅片经择 优腐蚀后的截面光学显微镜照片。
图 2为实施例 3得到的包含洁净区和体微缺陷区的直拉硅片经择 优腐蚀后的截面光学显微镜照片。
图 3为实施例 4得到的包含洁净区和体微缺陷区的直拉硅片经择 优腐蚀后的截面光学显微镜照片。
具体实施方式
下面结合实施例和附图来详细说明本发明，但本发明并不仅限于 此。
实施例 1
( 1 )将直径为 300mm, 晶向为 <100>, 间隙氧浓度为 8xl017cm— 3 的直拉硅片在高纯 (纯度大于 99.99%)氮气氛下快速热处理（RTP ), 其条件为： 以 100°C/秒的速度升温至 1250°C , 维持 60秒， 然后以 5 °C/秒的速率冷却至 800°C , 其后切断电源， 使硅片自然冷却；
( 2 )将经步骤（ 1 )处理的硅片在氩气氛下于 900°C退火 8小时。 图 1为实施例 1处理后得到的硅片截面经择优腐蚀后的光学显微 镜照片。 从图 1可以看出， 在硅片近表面形成了无缺陷的洁净区， 在 其下方紧挨着一个密度的体微缺陷区， 它将起着内吸杂的作用。
实施例 2
( 1 )将直径为 200mm, 晶向为 <100>, 间隙氧浓度为 8xl017cm— 3 的直拉硅片在高纯氮气氛下快速热处理（RTP), 其条件为： 以 100 °C/秒的速度升温至 1200°C, 维持 120秒， 然后以 50°C/秒的速率冷却 至 1000°C, 其后切断电源， 使硅片自然冷却；
(2)将经步骤（1 )处理的硅片在氩气氛下于 900°C退火 16 小 时。
实施后的效果与例 1的相似， 硅片中包含洁净区和体微缺陷区。 实施例 3
( 1 )将直径为 300mm, 晶向为 <100>, 间隙氧浓度为 9xl017cm— 3 的直拉硅片在氮气氛下快速热处理（RTP), 其条件为： 以 100°C/秒 的速度升温至 1200°C ,维持 150秒，然后以 5°C/秒的速率冷却至 1000 °c, 其后切断电源， 使硅片自然冷却；
(2)将经步骤（1)处理的硅片在氩气氛下于 900°C退火 16 小 时。
图 2为实施例 3后得到的硅片截面经择优腐蚀后的光学显微镜照 片。 从图 2可以看出， 在硅片近表面形成了无缺陷的洁净区， 在其下 方紧挨着一个密度的体微缺陷区， 它将起着内吸杂的作用。 实施例 4
( 1 )将直径为 200mm,晶向为 <100>,间隙氧浓度为 7.5xl017cm— 3 的直拉硅片在高纯氮气氛下快速热处理（RTP), 其条件为： 以 100 °C/秒的速度升温至 1250°C, 维持 30秒， 然后以 5°C/秒的速率冷却至 800 °C , 其后切断电源， 使硅片自然冷却；
( 2 )将经步骤（1 )处理的硅片在氩气氛下于 800°C退火 16 小 时。
实施后的效果与例 1的相似， 硅片中包含洁净区和体微缺陷区。 图 3为实施例 4处理后得到的硅片截面经择优腐蚀后的光学显微 镜照片。 从图 3可以看出， 在硅片近表面形成了无缺陷的洁净区， 在 其下方紧挨着一个密度的体微缺陷区， 它将起着内吸杂的作用。

Claims

权 利 要 求 书
1、 一种直拉硅片的内吸杂工艺， 包括：
( 1 )在氮气氛下， 将直拉硅片以 50~ 100°C/秒的速率升温至 1200- 1250 °C, 维持 30 ~ 150秒， 然后以 5 ~ 50°C/秒的速率冷却至 800 ~ 1000 °C, 接着自然冷却；
( 2 )将经步骤（ 1 )处理后的直拉硅片在氩气氛下于 800 ~ 900 °C 退火 8 ~ 16小时。
2、 根据权利要求 1所述的内吸杂工艺， 其特征在于， 所述的氮 气浓度大于 99.99%。
3、 根据权利要求 1所述的内吸杂工艺， 其特征在于， 所述的直 拉硅片直径为 200 ~ 300mm。
PCT/CN2012/072453 2011-03-23 2012-03-16 直拉硅片的内吸杂工艺 WO2012126334A1 (zh)

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CN106087052A (zh) * 2016-08-10 2016-11-09 中联西北工程设计研究院有限公司 一种多晶硅铸锭的两步退火工艺
DE102017219255A1 (de) * 2017-10-26 2019-05-02 Siltronic Ag Halbleiterscheibe aus einkristallinem Silizium
CN114280072B (zh) * 2021-12-23 2023-06-20 宁夏中欣晶圆半导体科技有限公司 单晶硅体内bmd的检测方法
CN115224155B (zh) * 2022-06-09 2024-02-23 东莞南玻光伏科技有限公司 硅片内除杂的方法和系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1251206A (zh) * 1997-02-26 2000-04-19 Memc电子材料有限公司 理想的氧沉淀硅晶片及氧外扩散较小的工艺
CN1625802A (zh) * 2002-04-10 2005-06-08 Memc电子材料有限公司 用于控制理想氧沉淀硅片中洁净区深度的方法
CN1769549A (zh) * 2004-11-05 2006-05-10 北京有色金属研究总院 一种单晶硅抛光片热处理工艺
CN1838388A (zh) * 2005-03-21 2006-09-27 北京有色金属研究总院 一种获得洁净区的硅片快速热处理工艺方法及其产品
CN102168314A (zh) * 2011-03-23 2011-08-31 浙江大学 直拉硅片的内吸杂工艺

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US5401669A (en) * 1993-05-13 1995-03-28 Memc Electronic Materials, Spa Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
CN1155074C (zh) * 1998-09-02 2004-06-23 Memc电子材料有限公司 从低缺陷密度的单晶硅上制备硅-绝缘体结构
US6436846B1 (en) * 1998-09-03 2002-08-20 Siemens Aktiengesellscharft Combined preanneal/oxidation step using rapid thermal processing
KR100792773B1 (ko) * 2000-04-14 2008-01-11 신에쯔 한도타이 가부시키가이샤 실리콘웨이퍼, 실리콘에피텍셜웨이퍼, 어닐웨이퍼 및이들의 제조방법
JP2005340348A (ja) * 2004-05-25 2005-12-08 Sumco Corp Ｓｉｍｏｘ基板の製造方法及び該方法により得られるｓｉｍｏｘ基板
US7977216B2 (en) * 2008-09-29 2011-07-12 Magnachip Semiconductor, Ltd. Silicon wafer and fabrication method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1251206A (zh) * 1997-02-26 2000-04-19 Memc电子材料有限公司 理想的氧沉淀硅晶片及氧外扩散较小的工艺
CN1625802A (zh) * 2002-04-10 2005-06-08 Memc电子材料有限公司 用于控制理想氧沉淀硅片中洁净区深度的方法
CN1769549A (zh) * 2004-11-05 2006-05-10 北京有色金属研究总院 一种单晶硅抛光片热处理工艺
CN1838388A (zh) * 2005-03-21 2006-09-27 北京有色金属研究总院 一种获得洁净区的硅片快速热处理工艺方法及其产品
CN102168314A (zh) * 2011-03-23 2011-08-31 浙江大学 直拉硅片的内吸杂工艺

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