WO2013080942A1 - 電力変換制御装置 - Google Patents
電力変換制御装置 Download PDFInfo
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- WO2013080942A1 WO2013080942A1 PCT/JP2012/080549 JP2012080549W WO2013080942A1 WO 2013080942 A1 WO2013080942 A1 WO 2013080942A1 JP 2012080549 W JP2012080549 W JP 2012080549W WO 2013080942 A1 WO2013080942 A1 WO 2013080942A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
- H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
- H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
- H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M5/4585—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only having a rectifier with controlled elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
- H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
- H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
- H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
Definitions
- This invention relates to a power converter, and more particularly to a technique for improving the modulation factor of a voltage source inverter.
- an inverter has three current paths and outputs a three-phase AC voltage to a three-phase load.
- Each current path has a pair of switch elements on the high potential side and the low potential side of the DC voltage.
- the switch element performs switching based on a switching pattern determined based on a result of comparing the value of the carrier and the value of the signal wave. Based on this switching, the three-phase AC voltage is output.
- An example of a power converter is an indirect matrix converter having a current source converter, a voltage source inverter, and a DC link connecting both.
- the indirect matrix converter does not have a smoothing circuit although the DC voltage is applied to the DC link.
- the current source converter generates a so-called commutation that switches the current path by switching, and converts alternating current into the direct current voltage.
- so-called zero current switching has been proposed in which no current flows through the current source converter during the switching.
- the voltage source inverter In order to prevent current from flowing through the current source converter, insulate the DC link from the three-phase load in the voltage source inverter.
- the three-phase load is an electric motor
- the three-phase load is short-circuited in order to recirculate the current resulting from the counter electromotive force.
- the operation of the voltage source inverter is realized by adopting a switching pattern based on a voltage vector commonly called a zero voltage vector.
- the zero voltage vector when used in the control of the voltage source inverter in order to realize the zero current switching in the current source converter, the period during which the line voltage is supplied to the three-phase load is substantially reduced. Therefore, the magnitude of the line voltage output by the inverter, the so-called modulation factor, decreases with respect to the DC voltage output from the current source converter (this is also the DC voltage input to the voltage source inverter in the indirect matrix converter). .
- the nonlinear capacitor circuit introduced in Patent Document 3 receives the voltage output from the diode rectifier and reduces the voltage applied to the inverter.
- the charge / discharge circuit introduced in Patent Document 4 receives the voltage output from the diode rectifier and increases the voltage applied to the inverter.
- Such a non-linear capacitor circuit and charge / discharge circuit perform commutation operation inside the circuit, and therefore, zero current switching is desired as in the commutation of the current source converter.
- the voltage control rate here means the magnitude of the line voltage output by the inverter with respect to the DC voltage output by the diode bridge. Since this is a ratio based on the voltage output from the diode bridge and the voltage output from the inverter, for the sake of convenience, the present application treats it as the same as the above modulation rate.
- the present invention is a technique for improving the modulation factor in a voltage source inverter while realizing zero current switching in a stage before the inverter, for example, a current source converter, a nonlinear capacitor circuit described in Patent Document 3, and a charge / discharge circuit described in Patent Document 4.
- the purpose is to provide.
- a power conversion control device (9, 10) includes a carrier generation unit (35), a rectification unit control unit (20; 10), and an inverter control unit (30).
- the control target of the power converter is a power controller, and the power controller includes the following: a plurality of input terminals (Pr, Ps, Pt; 31, 32); first to third output terminals (Pu, Pv, Pw); first and second DC buses (LH, LL); rectifier (2; 2B; 2C); voltage source inverter (5).
- An alternating voltage (Vr, Vs, Vt; Vi) is applied to the plurality of input terminals.
- the rectifying unit rectifies the alternating voltage with commutation by switching, and makes the first DC bus (LH) have a higher potential than the second DC bus (LL), and the first DC A direct current (Idc) is passed from the bus (LH) to the second DC bus (LL).
- the voltage source inverter converts a DC voltage (Vdc) between the first DC bus (LH) and the second DC bus (LL) into a three-phase voltage (Vu, Vv, Vw), and Output to the first to third output terminals.
- the voltage source inverter includes three current paths connected in parallel between the first and second DC buses (LH, LL) to which the DC voltage is applied.
- Each of the current paths is connected between the first DC bus and each of the first to third output terminals.
- Each of the current paths includes an upper arm side switch (Qup, Qvp, Qwp), a lower arm side switch (Qun, Qvn, Qwn), an upper arm side diode (Dup, Dvp, Dwp), and a lower arm side diode. (Dun, Dvn, Dwn).
- the upper arm side switch is connected between the first to third output ends and the first DC bus, and each of the first to third output ends from the first DC bus when conducting. Current is passed through.
- the lower arm switch is connected between the first to third output terminals and the second DC bus, and when conducting, current flows from the first to third output terminals to the second DC bus. Shed.
- the upper arm side diode is connected in antiparallel to each of the upper arm side switches.
- the lower arm side diode is connected in antiparallel to each of the lower arm side switches.
- the carrier generation unit generates a carrier (C2) that exhibits a triangular wave reciprocating between a minimum value (0) and a maximum value (1) with a constant absolute value (tan ⁇ ) of the gradient with respect to time.
- the rectifying unit controller adds a predetermined time (tc) to the commutation reference time point (t00) at which the carrier takes the commutation reference value (drt; 1-dc) that is greater than or equal to the minimum value and less than or equal to the maximum value. Then, the commutation unit is caused to execute the commutation.
- the inverter control unit controls on / off of the upper arm side switch and the lower arm side switch of the voltage source inverter based on a comparison between the carrier and a signal wave with respect to the three-phase voltage.
- the inverter control unit starts with the first time point (t01, t03) and ends with the second time point (t02, t04) plus the dead time (td). All the upper arm switches are turned off.
- the first time point (t01; t03) is a time point when the carrier takes the value of the first signal wave (Vu1 *; Vu2 *), and the second time point (t02, t04) is the first time point. Is the time when the carrier takes the value of the second signal wave (Vu2 *; Vu1 *) for the first time after.
- the first signal wave and the second signal wave are the signal waves for the maximum phase of the three-phase voltage.
- the upper arm side switch (Qup) for passing a current corresponding to the voltage of the maximum phase transitions from the on state to the off state at the first time point, and from the off state to the on state after the dead time elapses from the second time point. Transition to.
- the predetermined time (tc) is greater than a value ( ⁇ 01) obtained by subtracting the commutation reference time from the first time, and a value ( ⁇ 02) obtained by subtracting the commutation reference time from the second time. It is set to a value shorter than the sum of time.
- a second mode of the power control apparatus is the first mode, wherein the plurality of input terminals are three input terminals (Pr, Ps, Pt).
- the rectifying unit is a current source converter (2), and includes three switch elements (Srp, Ssp,%) Connected between each of the first to third input terminals and the first DC power supply line. Stp) and a switch group including three switch elements (Srn, Ssn, Stn) connected between each of the first to third input terminals and the second DC power supply line.
- the rectifier commutates and outputs the three-phase current (ir, is, it) input to the first to third input terminals by opening and closing the switch group.
- a third aspect of the power control apparatus is the first aspect, wherein the plurality of input terminals are a pair of input terminals (31, 32).
- the rectifying unit (2B; 2C) includes a diode bridge (3) connected to the pair of input terminals, charge / discharge elements (C41, C42; C4), and first and second direct currents from the charge / discharge elements.
- the rectification unit commutates and outputs the current input to the pair of input terminals and the discharge current of the charge / discharge element by opening and closing the switch element.
- a fourth aspect of the power control apparatus is any one of the first to third aspects, wherein the predetermined time (tc) is obtained by subtracting the commutation reference time point from the first time point. Half of the sum of the value ( ⁇ 01), the value ( ⁇ 02) obtained by subtracting the commutation reference time point (t00) from the second time point (t02), and the dead time (td) ((1/2) ( ⁇ 02 ⁇ 01 + td))).
- a fifth aspect of the power control apparatus is any one of the first to fourth aspects, wherein a value (d0) obtained by subtracting the first signal wave from the second signal wave is , Greater than the value obtained by subtracting the product of the absolute value of the tilt of the carrier (tan ⁇ ) and the dead time (td) from zero ( ⁇ td ⁇ tan ⁇ ).
- a sixth aspect of the power control apparatus is any one of the first to third aspects, wherein the predetermined time (tc) is set to half of the dead time (td / 2). .
- the rectifier unit commutates during the zero voltage vector period eroded by the dead time and the dead time period.
- the dead time period as in the zero voltage vector period, no current flows through the rectifying unit, so that loss when the rectifying unit commutates can be reduced.
- the timing at which the rectifier commutates is located at the center of the isolation period, so even if the length of the zero voltage vector is shortened, An effect can be acquired and a modulation rate can be raised.
- the fifth aspect of the power control apparatus of the present invention it is possible to secure an isolation period that occurs due to dead time.
- the sixth aspect of the power control apparatus of the present invention even if the zero voltage vector period is not substantially provided, the first signal wave and the second signal wave are not affected by the magnitude. Since the rectifier commutates during the dead time, so-called zero current switching is possible.
- the circuit diagram which illustrates the composition of the power converter with which the 1st embodiment of the present invention is adopted.
- the timing chart which shows a mode that the switching signal when a dead time is provided is produced
- the timing chart which shows the behavior of the switching signal in the vicinity of the isolation period while the carrier is rising.
- the graph which shows the waveform of a three-phase voltage.
- the circuit diagram which shows the equivalent circuit of the voltage type inverter in an isolation
- separation period The circuit diagram which shows the equivalent circuit of the voltage type inverter in an isolation
- the circuit diagram which shows the equivalent circuit of the single phase / three phase direct conversion apparatus of FIG. 20 is a timing chart showing the operation of the equivalent circuit of FIG.
- FIG. 1 is a circuit diagram illustrating the configuration of a power conversion device in which an embodiment of the present invention is employed.
- the direct AC power converter illustrated here is an indirect matrix converter, and includes a current source converter 2 that performs AC / DC conversion and a voltage source inverter 5 that performs DC / AC conversion.
- Current source converter 2 and voltage source inverter 5 are connected by DC buses LH and LL.
- the DC bus LH has a higher potential than the DC bus LL.
- the voltage source inverter 5 includes three current paths connected in parallel between the DC buses LH and LL to which the link voltage Vdc, which is a DC voltage, is applied.
- the first current path has a connection point Pu, an upper arm side switch Qup, and a lower arm side switch Qun.
- the second current path has a connection point Pv, an upper arm side switch Qvp, and a lower arm side switch Qvn.
- the third current path has a connection point Pw, an upper arm side switch Qwp, and a lower arm side switch Qwn.
- the upper arm side switches Qup, Qvp, Qwp flow current from the DC bus LH to the connection points Pu, Pv, Pw, respectively, when conducting.
- the lower arm side switches Qun, Qvn, Qwn flow current from the connection points Pu, Pv, Pw to the DC bus LL when conducting.
- the voltage source inverter 5 switches the link voltage Vdc with a switching pattern based on pulse width modulation, and outputs the three-phase voltages Vu, Vv, Vw from the connection points Pu, Pv, Pw to the three-phase load 6.
- the connection points Pu, Pv, and Pw can also be grasped as output ends that output line currents iu, iv, and iw to the three-phase load 6, respectively.
- the line currents iu, iv, iw will be described with the direction from the output terminals Pu, Pv, Pw toward the three-phase load 6 as the positive direction.
- the upper arm side diodes Dup, Dvp, Dwp are connected in antiparallel to the upper arm side switches Qup, Qvp, Qwp, respectively.
- Lower arm side diodes Dun, Dvn, Dwn are connected in antiparallel to the lower arm side switches Qun, Qvn, Qwn, respectively.
- reverse parallel refers to a mode in which two elements are connected in parallel and the conduction directions of the two elements are opposite to each other.
- the current source converter 2 has three input terminals Pr, Ps, and Pt.
- the input terminals Pr, Ps, and Pt are connected to, for example, a three-phase AC power source 1a, and input three-phase voltages Vr, Vs, and Vt for each phase.
- the current source converter 2 commutates the three-phase line currents ir, is, and it supplied from the input terminals Pr, Ps, and Pt in a cycle divided into a first period and a second period, and generates a DC bus LH, A DC link current Idc is applied between LL.
- the line currents ir is, it will be described with the direction from the input terminals Pr, Ps, Pt toward the voltage source inverter 5 being the positive direction.
- a pair of currents to which the phase voltage exhibiting the maximum phase and the phase voltage exhibiting the minimum phase are applied is a link current Idc between the DC buses LH and LL. It is a period to be supplied.
- a pair of currents to which the phase voltage representing the intermediate phase and the phase voltage representing the minimum phase are applied among the input terminals Pr, Ps, and Pt are linked currents Idc between the DC buses LH and LL. It is a period supplied as.
- the current source converter 2 includes switch elements Sxp and Sxn (where x represents r, s, and t. The same applies hereinafter).
- the switch element Sxp is provided between the input terminal Px and the DC bus LH.
- the switch element Sxn is provided between the input terminal Px and the DC bus LL.
- the switch elements Sxp and Sxn can be realized by serial connection of an insulated gate bipolar transistor (IGBT) and a diode, or RB-IGBT (Reverse Blocking IGBT).
- IGBT insulated gate bipolar transistor
- RB-IGBT Reverse Blocking IGBT
- Switching signals Gxp and Gxn are input to the switch elements Sxp and Sxn, respectively.
- the switch element Sxp is turned on / off according to the activation / inactivation of the switching signal Gxp
- the switch element Sxn is turned on / off according to the activation / inactivation of the switching signal Gxn.
- Switching signals Gyp and Gyn are input to the switches Qyp and Qyn, respectively, where y represents u, v and w.
- the switch Qyp is turned on / off according to the activation / inactivation of the switching signal Gyp, and the switch Qyn is turned on / off according to the activation / inactivation of the switching signal Gyn.
- FIG. 2 is a graph for explaining the operation of the current source converter 2.
- the upper graph shows three-phase voltages Vr, Vs, and Vt, and the lower graph shows current ratios dr, ds, and dt.
- temporal regions R1 to R6 are appended above the upper graph. Regions R1 to R6 are temporally separated from each other at the timing of switching of the three-phase voltages Vr, Vs, and Vt having the largest absolute value. This switching timing is also a timing at which any of the three-phase voltages Vr, Vs, Vt takes zero. Since the regions R1 to R6 are divided in this way, each of them has a length of ⁇ / 3 obtained by dividing one period of the three-phase voltages Vr, Vs, and Vt into six equal parts.
- the region R1 is a region where the absolute value of the phase voltage Vt is larger than any of the absolute values of the phase voltages Vr and Vs, and starts from the time when the phase voltage Vs switches from negative to positive, and the phase voltage Vr changes from positive to negative. The time of switching will be the end.
- the three-phase voltages Vr, Vs, and Vt are expressed as a ratio with respect to the maximum value of the line voltage, and therefore the maximum value of the absolute values of the three-phase voltages Vr, Vs, and Vt is 1 / ⁇ 3.
- the time point at which the three-phase voltage Vr takes the maximum value is adopted as the reference (0 °) of the phase angle of the three-phase voltage.
- the conduction ratio dx indicates the ratio of the line current ix that flows due to the switching of the switch elements Sxp and Sxn. If the current ratio dx is positive, the switching element Sxp is turned on and the ratio of the current flowing into the current source converter 2 to the input terminal Px. If it is negative, the switching element Sxn is turned on and the three-phase from the input terminal Px.
- the switch elements Srp and Ssp are alternately turned on, and the ratio of the time when they are turned on is indicated by the flow ratios dr and ds.
- the switch elements Srp and Ssp are turned on alternately in a short cycle with respect to one cycle of the three-phase voltages Vr, Vs and Vt, and pulse width modulation is performed.
- the conduction ratio dr is larger than the conduction ratio ds
- the conduction ratio. dr is smaller than the flow ratio ds.
- the description will be continued by taking the region R1 as an example. Since the flow ratio dt is fixed to the value ⁇ 1 in the region R1, the flow ratios dr and ds in the region R1 are expressed as flow ratios drt and dst, respectively.
- the following explanation is appropriate by the phase order reading and the mutual reading of the switch elements Sxp and Sxn due to the symmetry of the phase voltage waveform.
- FIG. 3 is a graph for explaining the operation of the power conversion device in the prior art.
- the length of the period in which the carrier C1 is between the value 0 and the conduction ratio drt is drt ⁇ T0 (hereinafter, this period is referred to as “ It is also referred to as “period drt ⁇ T0”).
- the length of the period in which the carrier C1 is between the flow ratio drt and the value 1 is represented by dst ⁇ T0 (hereinafter, this period is also referred to as “period dst ⁇ T0”).
- dst> drt a case where the phase angle is large in the second half (phase angle 60 to 90 ° in FIG. 2) in the region R1 is illustrated.
- the phase voltages Vr, Vs, and Vt are the intermediate phase, the maximum phase, and the minimum phase, respectively.
- the periods dst ⁇ T0 and drt ⁇ T0 can be grasped as the first period and the second period, respectively.
- the pair of input terminals Ps and Pt to which the phase voltage Vs that exhibits the maximum phase and the phase voltage Vt that exhibits the minimum phase are applied.
- the flowing current is supplied to the DC bus LH.
- the current flowing through the pair of input terminals Pr and Pt to which the phase voltage Vr that exhibits the intermediate phase and the phase voltage Vt that exhibits the minimum phase are applied is DC. Supplied to bus LH.
- the generation of the switching signals Gxp and Gxn for realizing such commutation is well known in, for example, Patent Document 1 and will not be described.
- the carrier C2 is compared with the signal wave, and the switching signals Gyp and Gyn are generated based on the comparison result.
- a waveform having the same shape and the same phase as the carrier C1 is adopted as the carrier C2.
- the case where all the carriers have a minimum value of 0 and a maximum value of 1 is taken as an example.
- arbitrary values can be selected as the minimum value and the maximum value by appropriately performing linear conversion on the signal wave.
- the voltage vector to be adopted by the voltage source inverter 5 is expressed by d4 ⁇ V4 + d6 ⁇ V6 by using vector calculation (d4 + d6 ⁇ 1).
- unit voltage vector Vg was introduced.
- the value g is a value obtained by assigning the values 4, 2, and 1 to the U phase, V phase, and W phase, respectively, and adding up the assigned values when the corresponding upper arm is conductive. Then, an integer of 0 to 7 is taken.
- the unit voltage vector V4 represents a switching pattern in which the switches Qup, Qvn, and Qwn are turned on and the switches Qun, Qvp, and Qwp are turned off.
- the unit voltage vector V6 represents a switching pattern in which the switches Qup, Qvp, Qwn are turned on and the switches Qun, Qvn, Qwp are turned off.
- the W-phase phase voltage Vw is smaller than both the U-phase phase voltage Vu and the V-phase phase voltage Vv.
- the U-phase phase voltage Vu or the V-phase phase voltage Vv may be smaller than the other phase voltages in other periods of the carrier C2. It is clear that this explanation is valid.
- the unit voltage vectors V0, V4, V6, and V7 are employed with a length ratio of d0: d4: d6: (1-d0-d4-d6).
- switching is performed using unit voltage vectors V0, V4, V6, and V7 in a ratio of d0: d4: d6: (1-d0-d4-d6) within one period T0 of carrier C2. .
- the ratio of the length in which each unit voltage vector is employed to one carrier cycle is also referred to as a time ratio.
- d0 + d4 + d6 + d7 1.
- Zero current switching is desirable from the viewpoint of reducing the loss of the current source converter 2.
- the dead time refers to a period of time during which the switches Qyn and Qyp are simultaneously turned off to avoid the switches Qyn and Qyp from being turned on simultaneously. Therefore, conventionally, in the consideration for performing zero current switching, the switching signal Gyn and the switching signal Gyp were treated as being activated in a complementary manner.
- the activation / inactivation of the switching signals Gyp and Gyn is hereinafter expressed as “H” / “L”, respectively, and the switches Qyp and Qyn are turned on / off, respectively.
- the zero voltage vector (of FIG. 3) is always controlled by the control of the voltage source inverter at the timing when the current source converter switches.
- the zero voltage vector V0 is employed.
- the adoption of such a zero voltage vector has a problem that the modulation rate is small as described above.
- a technique for improving the modulation rate will be described.
- the duty ratio d0 does not have to be positive, and may be larger than a predetermined negative value. The negative value is specified later by the explanation using FIG.
- FIG. 4 is a timing chart showing how the switching signals Gyp and Gyn are generated when the dead time td is provided.
- the zero voltage vector V7 in the vicinity of the maximum value and the minimum value of the carrier C2 is not employed, which is not related to the zero current switch, is illustrated. That is, the duty ratio d7 is zero, and the W-phase signal waves Vw1 * and Vw2 * take the minimum and maximum values (here, values 0 and 1 respectively) of the carrier C2.
- the lower arm switch Qun belonging to the same current path as the upper arm switch Qup is transitioned from the off state to the on state after the elapse of the dead time td from the time point t01. That is, the switching signal Gun rises from time t01 when the switching signal Gup falls to time t06 after the dead time td has elapsed.
- the lower arm side switch Qun is on immediately before the second time point t02, and the lower arm side switch Qun is turned off at the second time point t02.
- the upper arm switch Qup belonging to the same current path as the lower arm switch Qun is changed from the off state to the on state after the elapse of the dead time td from the second time point t02. That is, the switching signal Gup falls after the elapse of the dead time td from the second time point t02 when the switching signal Gun rises.
- the switching signal Gvn rises after the elapse of the dead time td after the switching signal Gvp falls, and the switching signal Gvp rises after the elapse of the dead time td after the falling of the switching signal Gvn.
- the time points t01 and t03 can be grasped as the first time points when the carrier C2 takes the signal waves Vu1 * and Vu2 *, respectively. Further, when the time point t02 is grasped as the first time point, the time point t02 can be grasped as the second time point when the carrier C2 takes the signal wave Vu2 * for the first time after the first time point. If the time point t04 is grasped as the first time point, the time point t04 can be grasped as the second time point when the carrier C2 takes the signal wave Vu1 * for the first time after the first time point.
- the switching signal Gzn corresponding to the lower arm side switch falls at the timing (time t02, t04) when the carrier C2 takes one of the Z-phase signal waves, and the switching signal Gzp corresponding to the switching signal Gzn.
- the switching signal Gzp corresponding to the upper arm side switch falls at the timing (time t01, t03) when the carrier C2 takes the other of the Z-phase signal waves, and the switching signal Gzn corresponding to the switching signal Gzp is derived from the timing. It rises after the dead time td.
- the Z phase is a phase that becomes the maximum phase among the phase voltages Vu, Vv, and Vw, and the U phase corresponds to the description here.
- the U-phase signal waves Vu1 * and Vu2 * are signal waves for the maximum phase, and the value obtained by subtracting the signal wave Vu1 * from the signal wave Vu2 * is equal to the time ratio d0.
- the switching signals Gwp and Gwn are “L” and “H”, respectively, and both fall and rise do not occur.
- FIG. 4 shows a voltage vector (hereinafter referred to as “original voltage vector”) to be adopted if the dead time td is zero.
- the voltage vector actually employed (hereinafter also referred to as “actual voltage vector”) is eroded from the beginning of the period in which the original voltage vector is employed for the dead time td.
- the lower arm side switch Qun remains non-conductive, and all the upper arm side switches Qup, Qvp, and Qwp remain non-conductive.
- the original voltage vector V4 provided next to the original voltage vector V0 is also eroded by the dead time td from the beginning of the adopted period.
- the isolation period including a total of three periods of the period in which the actual voltage vector V0 is employed and the period Ud before and after the period, the actual voltage vector V4 is isolated in the vicinity where the current source converter 2 is switched. If the current source converter 2 switches during this isolation period, zero current switching is realized.
- the timing width at which the zero current switching is realized is increased by the dead time td as compared with the case where the existence of the dead time td is not considered.
- Such a shift can be realized by various methods.
- a case where the switching timing in the current source converter 2 is shifted by relatively shifting the phase of the carrier C1 from the phase of the carrier C2 will be described.
- the amount by which the phase of the carrier C1 is shifted from the phase of the carrier C2 will be described as the shift amount tc in the time dimension (the direction in which the carrier C1 can be sent is positive).
- the shift amount tc is 2 ⁇ (tc / T0) when converted into the phases of the carriers C1 and C2.
- FIG. 5 is a timing chart showing the behavior of the switching signals Gup and Gun near the isolation period while the carrier C2 is rising.
- FIG. 5 shows a period in which the actual voltage vectors V0 and V4 are employed and a period Ud.
- the commutation ratio drt is referred to as a commutation reference value drt.
- a time point at which the carrier C2 takes the commutation reference value drt is defined as a commutation reference time point t00.
- the actual switching timing of the current source converter 2 is delayed by the shift amount tc from the commutation reference time t00 if the shift amount tc is positive (however, if the shift amount tc is negative, the shift amount tc from the commutation reference time t00). Will advance by the absolute value of).
- the original voltage vector V0 exists at the time ⁇ 01 before the commutation reference time t00 and at the time ⁇ 02 after the commutation reference time t00 in the time ⁇ 0 in which the original voltage vector V0 is adopted.
- the commutation reference time t00 is included in the actual voltage vector V0, and therefore it is not necessary to shift the switching timing of the current source converter 2 from the commutation reference time t00. Therefore, it is assumed here that the time ⁇ 01 is smaller than the dead time td.
- Switching signals Gup and Gun fall at the above-mentioned times t01 and t02, respectively. If the time points t05 and t06 delayed from the time points t02 and t01 by the dead time td are introduced, it can be said that the switching signals Gup and Gun rise at the time points t05 and t06, respectively. Therefore, the actual voltage vector V0 is employed with a length of time ( ⁇ 0 ⁇ td).
- the current source converter 2 would have been switched at the time when the carrier C2 took the conduction ratio drt without providing the shift amount tc. Since it is assumed that there is a time when the carrier C2 takes the conduction ratio drt during the period in which the actual voltage vector V0 is adopted to realize zero current switching, the signal wave Vu1 * is set so that ⁇ 01> td. Had to set. Similarly, the signal wave Vu2 * must be set so that ⁇ 02> td while the carrier C2 is descending.
- the signal wave Vu1 * had to have the value drt ⁇ td ⁇ tan ⁇ as the upper limit, and the signal wave Vu2 * had to have the value drt + td ⁇ tan ⁇ as the lower limit (where tan ⁇ was the absolute value of the slope of the carrier C2 with respect to time). Therefore, if the shift amount tc is not provided as in the prior art, ⁇ 0> 2td is required. This requires a minimum time ratio d0 of 2td ⁇ tan ⁇ , which hinders an increase in the modulation rate.
- the link current Idc becomes zero not only in the period in which the actual voltage vector V0 is employed but also in the period Ud. Therefore, if the timing at which the current source converter 2 switches is within the isolation period defined between the time points t01 and t05, zero current switching is realized. That is, even when the duty ratio d0 is smaller than 2td ⁇ tan ⁇ , it is possible to obtain the timing at which the current source converter 2 switches to realize zero current switching. As a result, the upper limit of the signal wave Vu1 * increases and the lower limit of the signal wave Vu2 * decreases, thereby improving the modulation rate.
- the length of the isolation period is the sum of time ⁇ 0 and dead time td. Therefore, the shift amount tc only needs to satisfy the following relationship.
- the shift amount tc is preferably in the middle of the isolation period. From this point of view, the shift amount tc is preferably the following value tc0.
- the period Ud constituting the isolation period with the length of the dead time td contributes to the zero current switching. Therefore, even if the time ratio d0 employed in one cycle of the carrier C2 is zero, the isolation period is sandwiched between periods where the actual voltage vector V4 is employed.
- FIG. 6 is a timing chart showing the behavior of the switching signals Gup and Gun in the vicinity of the isolation period while the carrier C2 is rising, and illustrates the case where the time ratio d0 is zero.
- ⁇ 0 0, the time points t00, t01, and t02 coincide, and the signal waves Vu1 * and Vu2 * are both equal to the commutation reference value drt. Therefore, for convenience, the time point t06 can be considered to coincide with the time points t00, t01, and t02.
- the switching signal Gup occurs at time t01 and the rising occurs at time t05 while the carrier C2 is rising. Therefore, the switching signal Gup becomes “L” between the time points t01 and t05. The same applies to the lowering of the carrier C2.
- FIG. 7 is a timing chart showing the behavior of the switching signals Gup and Gun in the vicinity of the isolation period while the carrier C2 is rising, and illustrates the case where the time ratio d0 is negative.
- the duty ratio d0 is a ratio of the length in which the unit voltage vector V0 is adopted to one carrier period, and it is not appropriate for the explanation that the duty ratio d0 is negative.
- FIG. 7 also illustrates a case where such a relationship is satisfied.
- the commutation reference time point t00 is later than the time point t02, and the time points t01 and t05 are later than the commutation reference time point t00.
- the switching signal Gup corresponds to the logical sum of two switching original signals Gu1p and Gu2p. That is, the switching signal Gup is activated when either one of the switching original signals Gu1p and Gu2p is active, and the switching signal Gup is inactive when both the switching original signals Gu1p and Gu2p are inactive.
- the switching signal Gun corresponds to the logical product of the two switching original signals Gu1n and Gu2n. That is, if either one of the switching original signals Gu1n and Gu1p is inactive, the switching signal Gun is inactive. If both the switching original signals Gu1p and Gu2n are active, the switching signal Gun is active.
- the switching original signals Gu1p, Gu2p, Gu1p, Gu2n rise and activate according to the following rules, and fall and deactivate:
- the switching original signal Gu2p rises after the dead time td has elapsed after the carrier C2 takes the value of the signal wave Vu2 * from a value smaller than the signal wave Vu2 *;
- the switching original signal Gu2p falls when the carrier C2 takes the value of the signal wave Vu2 * from a value larger than the signal wave Vu2 *;
- the switching original signal Gu2n falls when the carrier C2 takes the value of the signal wave Vu2 * from a value smaller than the signal wave Vu2 *;
- the switching original signal Gu2n rises after the dead time td has elapsed after the carrier C2 takes the value of the signal wave Vu2 * from a value greater than the signal wave Vu2 *;
- the switching original signal Gu1p rises after the dead time td elapses after the carrier C2 takes the value of the signal
- the switching original signal Gu1p falls at time t01, and the switching original signal Gu2p rises at time t05 after the dead time td elapses from time t02. Since the time point t01 is later than the time point 02 by the time
- the switching original signal Gu2n falls at time t02.
- the dead time td has elapsed since the time t01 later than the time t02 when the switching original signal Gu1n rises. Therefore, the switching signal Gun corresponding to the logical product of the switching original signals Gu1n and Gu2n is not activated during the period in which the magnitude of the signal wave is maintained.
- FIG. 5 illustrates a case where the time ⁇ 0 included in the original voltage vector V 0 is larger than the dead time td for easy explanation.
- the time ⁇ 0 may be equal to or less than the dead time td.
- the time point t06 is later than the time point t02, it is not possible to accurately explain how the waveform of the switching signal Gun is based only on the description using FIG.
- the length of the isolation period is expressed as (td + d0 ⁇ cot ⁇ ) as described above, referring back to FIG. 5, if d0 ⁇ 0, the value td / 2 is adopted as the shift amount tc. It can be seen that zero current switching can be realized.
- the time points at which the signal waves Vu1 * and Vu2 * are taken while the carrier C2 is rising are grasped as the first time point t01 and the second time point t02, respectively.
- FIG. 8 is a graph showing waveforms of the three-phase voltages Vu, Vv, and Vw.
- the amplitude is normalized by the absolute value of the line voltage.
- the phase regions J1-J6 are defined as follows: Phase region J1 (0 ° ⁇ ⁇ ⁇ 60 °): phase voltages Vu, Vv, and Vw are maximum phase, intermediate phase, and minimum phase, respectively; Phase region J2 (60 ° ⁇ ⁇ ⁇ 120 °): phase voltages Vu, Vv, and Vw are respectively an intermediate phase, a maximum phase, and a minimum phase; Phase region J3 (120 ° ⁇ ⁇ ⁇ 180 °): phase voltages Vu, Vv, and Vw are minimum phase, maximum phase, and intermediate phase, respectively; Phase region J4 (180 ° ⁇ ⁇ ⁇ 240 °): phase voltages Vu, Vv, and Vw are minimum phase, intermediate phase, and maximum phase, respectively; Phase region J5 (240 ° ⁇ ⁇
- Each of the phase regions J1 to J6 has a section of 60 °, and the relationship of which phase voltage corresponds to the maximum phase, the intermediate phase, and the minimum phase in each of them is maintained.
- Table 1 shows the line in each phase region when the amount of delay relative to the phase voltage Vy of the line current iy is 0 ° to 30 °, and Table 2 shows the case where the amount of delay described above is 30 ° to 60 °. It is the table
- phase voltages Vu, Vv, and Vw correspond to the maximum phase, intermediate phase, and minimum phase, respectively, and the unit voltage vectors V4 and V6 or further the unit voltage vector V0 are adopted as the original voltage vector. Is done.
- the polarities of the line currents iu, iv and iw are positive, positive, negative or positive, positive and negative, respectively.
- Table 1 positive / negative of the polarity of such current is represented by +/ ⁇ , respectively.
- the line current iv corresponding to the phase voltage Vv corresponding to the intermediate phase takes either positive / negative in the phase region J1.
- the ratio between the period in which the line current iv is positive in one cycle of the carrier C2 and the period in which the line current iv is negative matches the ratio of the time ratio d6 and the time ratio d4.
- the notation of the upper arm side current iyp in Table 1 indicates whether or not this flows during the isolation period.
- unit voltage vectors V4 and V6 or further unit voltage vector V0 are adopted as the original voltage vector
- lower arm switches Qvn and Qwn are conductive during the isolation period. Accordingly, the line currents iv and iw flow through the lower arm side switches Qvn and Qwn or the diodes Dvn and Dwn.
- the line current iv is directed to the DC bus LL instead of the DC bus LH and does not flow to the upper arm side diode Dup even when it is negative. . Therefore, in Table 1, the upper arm side currents ivp and iwp are expressed as “0”, indicating that they do not flow.
- phase regions J2 to J6 The same applies to the other phase regions J2 to J6. That is, when the above-mentioned slow phase amount is 0 ° to 30 °, the upper arm side currents iup, ivp, iwp do not flow, and the voltage source inverter 5 performs a power running operation outside the isolation period and performs a reflux operation in the isolation period. It will be.
- phase voltages Vu, Vv, and Vw correspond to the maximum phase, intermediate phase, and minimum phase, respectively, and the unit voltage vectors V4 and V6 or further the unit voltage vector V0 are adopted as the original voltage vector. Is done. Since the delay amount is 30 ° to 60 °, the polarities of the line currents iu, iv, iw are positive, negative, positive or positive, negative, negative.
- the phase voltages Vu, Vv, and Vw correspond to the intermediate phase, the maximum phase, and the minimum phase, respectively, and the unit voltage vectors V6 and V2 or further the unit voltage vector V0 are adopted as the original voltage vector. Is done. Since the delay amount is 30 ° to 60 °, the polarities of the line currents iu, iv and iw are positive, negative, negative or positive, positive and negative, respectively.
- FIGS. 9 to 12 are circuit diagrams showing an equivalent circuit of the voltage source inverter 5 in the isolation period, particularly in a situation where the zero voltage vector V0 is not provided as the actual voltage vector ( ⁇ 0 ⁇ td), and the switch Qyn in the off state , Qyp is not described.
- FIG. 9 and 10 show an equivalent circuit of the voltage source inverter 5 in the isolation period in the phase region J1, and particularly show a case where the isolation period is constituted only by the period Ud (see FIG. 4 and the like).
- 11 and 12 show an equivalent circuit of the voltage source inverter 5 in the isolation period in the phase region J2, and particularly show a case where the isolation period is configured only by the dead time in the V phase.
- FIG. 9 shows the flow of the line currents iu, iv, and iw in the isolation period when the polarities of the line currents iu, iv, and iw are positive, negative, and positive, respectively, in the phase region J1 (Table 2, first row). .
- the upper arm side currents iup, ivp, and iwp do not flow because it is equivalent to the case where the V phase and the W phase in the case shown in the second row of Table 1 are switched.
- FIG. 10 shows the flow of the line currents iu, iv, and iw in the isolation period when the polarities of the line currents iu, iv, and iw are positive, negative, and negative (second row in Table 2) in the phase region J1, respectively.
- the upper arm side currents iup, ivp, and iwp do not flow because they are equivalent to the case shown in the first row of Table 1.
- FIG. 11 shows the flow of the line currents iu, iv, and iw in the isolation period when the polarities of the line currents iu, iv, and iw are positive, negative, and negative in the phase region J2 (Table 3, third row), respectively.
- FIG. 12 shows the flow of the line currents iu, iv, iw in the isolation period when the polarities of the line currents iu, iv, iw are positive, positive, and negative (the fourth row in Table 2) in the phase region J2. .
- the polarity of the line current iu is positive, and in the U phase, the upper arm side switch Qup is off. Therefore, the line current iu flows through the lower arm side diode Dun.
- the polarity of the line current iv is negative, and in the V phase, both the upper arm side switch Qvp and the lower arm side switch Qvn are off. Therefore, the line current iv flows through the upper arm side diode Dvp, and the upper arm side current ivp flows.
- the upper arm side switch Qyp is turned off in this way, but the upper arm side current iyp flows through the upper arm side diode Dyp connected in reverse parallel to the upper arm side switch Qyp by the symbol “-”. Yes.
- the polarity of the line current iv is positive, and the upper arm side switch Qvp and the lower arm side switch Qvn are off in the V phase. Therefore, the line current iv flows through the lower arm side diode Dvn, and the upper arm side current ivp does not flow (the column of ivp in the fourth row in Table 2 is expressed as “0”).
- the lower arm side switch Qwn is turned on, and the line current iw flows through either the lower arm side switch Qwn or the upper arm side diode Dwp. Since the current generally flows to the low potential side, the line current iw flows through the upper arm side diode Dwp in the case shown in FIG. 11 based on the direction of the line currents iu and iv. Therefore, the upper arm side current iwp flows (the iwp column in the third row of Table 2 is expressed as “ ⁇ ”). In the case shown in FIG. 12, the line current iw flows through the lower arm side diode Dwn. Therefore, the upper arm side current iwp does not flow (the column of iwp in the fourth row in Table 2 is expressed as “0”).
- the upper arm side currents iup, ivp, iwp may flow in the isolation period, particularly in the period when the actual voltage vector V0 is not provided.
- the voltage source inverter 5 performs a power running operation outside the isolation period, and performs a reflux operation or a regenerative operation during the isolation period.
- FIGS. 13 and 14 are graphs for explaining the operation of the power conversion apparatus when the flow ratio drt is relatively small.
- drt ⁇ T0 the vicinity of the period drt ⁇ T0 is shown enlarged. Since drt ⁇ dst, the phase voltage Vr is smaller than the phase voltage Vs and corresponds to the intermediate phase.
- FIG. 13 corresponds to the prior art, in which a carrier C2 for the voltage source inverter 5 is also used as a carrier for the current source converter 2, and zero current switching is performed in a period in which the actual voltage vector V0 is employed. The case of realizing is illustrated.
- the time t08 after the elapse of the dead time td from the above-mentioned time t03 is the time t08
- the start of the period in which the actual voltage vector V0 is adopted while the carrier C2 is falling is the time t03
- the end is the time t04 described above.
- the actual voltage vector V6 is employed in a period in which the switching signal Gup is activated between the time point t08 and the time point t02.
- the switching signal Gup is activated at the time point t07 after the elapse of the dead time td from the time point t04, and is not activated at the time point t01. Become active.
- time points t01 and t04 are the time points at which the carrier C2 takes the signal wave Vu1 *, in order that the period in which the actual voltage vector V6 is adopted is not eroded by the dead time td, Vu1 * ⁇ td ⁇ tan ⁇ must be satisfied. I must.
- the time t01 to t06 requires a dead time td at the minimum, and drt ⁇ Vu1 * + td ⁇ tan ⁇ ⁇ 2td ⁇ tan ⁇ . It becomes.
- the lower limit of the flow ratio drt is 2td ⁇ tan ⁇ .
- the length of the period drt ⁇ T0 needs to be four times the dead time td (4 ⁇ td) or more.
- FIG. 14 corresponds to the embodiment, and illustrates a case where zero current switching is realized by employing carriers C2 and C1 for the current source converter 2 and the voltage source inverter 5, respectively.
- the lower limit of the flow ratio drt is td ⁇ tan ⁇ .
- the length of the period drt ⁇ T0 is only required to be at least twice the dead time td (2 ⁇ td).
- the modulation factor is td / (4 ⁇ td) and 25% in the period in which the current source converter 2 outputs the phase voltage Vr as an intermediate phase.
- the modulation factor is td / (2 ⁇ td), which is improved to 50%. This is desirable from the viewpoint of improving the modulation rate in one carrier period.
- Extending the lower limit of the flow ratio in this way is desirable not only from the viewpoint of increasing the modulation rate but also suppressing the harmonic components of the line currents ir, is, and it.
- FIG. 15 is a graph for explaining the operation of the current source converter 2.
- the upper graph shows three-phase voltages Vr, Vs, Vt as input phase voltages
- the middle graph shows line current conduction ratios dr, ds, dt
- the lower graph shows line currents ir, is as input line currents. , It are shown respectively.
- FIG. 2 shows an ideal case in which the line current conduction ratios dr, ds, and dt continuously fluctuate.
- the line current conduction ratio corresponding to the intermediate phase has a lower limit as described above. Exists.
- the lower limit is drawn and the waveform indicating the line current flow ratio has a step in the vicinity where the line current flow ratio corresponding to the intermediate phase becomes zero. Due to this step difference in current flow ratio, the waveform of the line current ir, is, it also has a step with respect to the sine wave. This distortion of the line currents ir, is, and it causes harmonic components.
- the step of the conduction ratio is due to the lower limit of the conduction ratio of the line current corresponding to the intermediate phase. Therefore, it is obvious that the step is reduced by reducing the lower limit as described above. Therefore, by setting the shift amount tc to td / 2 as in the present embodiment, the lower limit of the current ratio of the line current corresponding to the intermediate phase is expanded, so that the line currents ir, Suppresses harmonic components of is and it.
- FIG. 16 is a block diagram illustrating a conceptual example of a specific internal configuration of the control unit 100 that performs the above-described control.
- the control unit 100 can be employed as the control device 9 in FIG.
- the control unit 100 includes a converter control unit 20, an inverter control unit 30, a modulation factor calculation unit 40, and a sensorless vector control unit 50.
- a three-phase motor is assumed as the three-phase load 6 (see FIG. 1).
- the converter control unit 20 includes a power supply phase detection unit 21, a conduction ratio generation unit 22, a comparator 23, a current source gate logic conversion unit 24, and a carrier generation unit 25.
- the power supply phase detector 21 detects, for example, the line voltage Vrs, detects the phase angle ⁇ of the three-phase voltage applied to the input terminals Pr, Ps, and Pt, and outputs it to the conduction ratio generator 22.
- the flow ratio generation unit 22 generates flow ratios dac and dbc based on the received phase angle ⁇ .
- the flow ratios dac and dbc correspond to the flow ratios dst and drt, respectively.
- the carrier generation unit 25 generates a carrier C1.
- the comparator 23 outputs the result of comparing the carrier C1 with the current ratios dac and dbc, and based on this, the current-type gate logic converter 24 generates the switching signals Grp, Gsp, Gtp, Grn, Gsn and Gtn. To do.
- the inverter control unit 30 includes a time ratio generation unit 32, a signal wave generation unit 34, a carrier generation unit 35, a comparator 36, and a logical operation unit 38.
- the time ratio generation unit 32 Based on the modulation rate ks received from the modulation rate calculation unit 40, the control phase angle ⁇ , and the command phase angle ⁇ ′ received from the sensorless vector control unit 50, the time ratio generation unit 32 The ratios dg1 and dg2 are generated. In the above example, the time ratios dg1 and dg2 correspond to the time ratios d4 and d6, respectively. The duty ratio d0 can be easily obtained as (1-d4-d6).
- the signal wave generator 34 generates a signal wave from the time ratios dg1 and dg2 and the flow ratios dac and dbc.
- signal waves Vu1 *, Vv1 *, Vw1 *, Vu2 *, Vv2 *, Vw2 * are generated. Since these generations can be realized with the same level of technology as the conventional technology for generating signal waves, the details are omitted.
- the carrier generation unit 35 generates a carrier C2.
- the signal wave is compared with the carrier C2 in the comparator 36, and the result and the dead time td are used for the calculation in the logic operation unit 38.
- the logic operation unit 38 generates the upper arm side switching signals Gup, Gvp, Gwp and the lower arm side switching signals Gun, Gvn, Gwn.
- the switching original signals Gy1p, Gy2p, Gy1n, and Gy2n are once generated. Since the logical operation unit 38 is easily configured by a well-known technique, its details are omitted here.
- the modulation factor calculation unit 40 receives the d-axis voltage command Vd * and the q-axis voltage command Vq * from the sensorless vector control unit 50, calculates the modulation factor ks and the control phase angle ⁇ , and outputs them as a time ratio generation unit. 32.
- the sensorless vector control unit 50 calculates the rotational angular velocity ⁇ and the command phase angle ⁇ ′ of the motor based on the line currents iu, iv, iw flowing from the connection points Pu, Pv, Pw to the three-phase load 6. Then, a d-axis voltage command Vd * and a q-axis voltage command Vq * are generated based on these and an externally input rotational angular velocity command ⁇ * and duty D.
- the carrier C1 is obtained by shifting the carrier C2 by a shift amount tc, with the time passing direction being positive. Therefore, the carrier generation unit 25 can be replaced with a phase shifter that delays the carrier C2 by a predetermined phase. Even if the shift amount tc is negative and the carrier C1 is advanced by a phase amount 2 ⁇ (
- FIG. 17 is a graph showing the operation of the current source converter 2 and the voltage source inverter 5.
- the vicinity of the commutation reference time point t00 when the carrier C2 is rising is shown enlarged.
- the case of ⁇ 01, ⁇ 02> 0 is illustrated as in FIG.
- the signal wave Vu1 * drt (1-d0) is taken at time t01 while the carrier C2 is rising.
- the switching signal Gup is deactivated between time points t01 and t05.
- the switching signal Grp falls and the switching signal Gsp rises.
- the time t09 at which the switching elements Srp and Ssp are switched is later than the commutation reference time t00 by the sum of the shift amount tc and the delay time ⁇ t1.
- time t09 In order to perform zero current switching as in the present embodiment, time t09 must be within a period in which the upper arm side switch Qup is turned off. Considering that the operation of turning on / off the upper arm side switch Qup is delayed with respect to activation / deactivation of the switching signal Gup, the most severe condition for setting the time point t09 is as follows. This is the case. That is, the delay time from the time t01 when the switching signal Gup falls to the time when the upper arm side switch Qup is turned off takes the maximum value ⁇ t2, and the delay from the time t05 when the switching signal Gup rises until the upper arm side switch Qup is turned on. This is a case where the time takes the minimum value ⁇ t3.
- the current source converter 2 supplies the link current Idc to the voltage source inverter 5 .
- the current source converter 2 rectifies the three-phase voltages Vr, Vs, Vt that are alternating voltages with commutation by switching of the switch elements Srn, Ssn, Stn, Srp, Ssp, Stp to link current Idc. It was functioning as a rectifier.
- FIG. 18 is a circuit diagram showing a simplified single-phase / three-phase direct conversion device (FIG. 1 of Patent Document 3) introduced in Patent Document 3. Moreover, the symbol added to the component is changed to the symbol corresponding to the present application.
- the single-phase diode rectifier 3 is connected to the single-phase AC power source 1b through a pair of input terminals 31 and 32, and includes diodes D31 to D34.
- the diodes D31 to D34 constitute a bridge circuit and rectifies the single-phase voltage Vi input from the single-phase AC power supply 1b.
- the nonlinear capacitor circuit 4 includes a plurality of capacitors C41 and C42, diodes D41 to D43, and switch elements S41 and S42. Opening and closing of the switch elements S41 and S42 is controlled by a signal SS.
- the signal SS and the switching signals Gxp, Gxn, Gyp, Gyn are output from the control unit 10.
- the capacitors C41 and C42 function as charge / discharge elements, and the switch elements S41 and S42 control discharge from the charge / discharge elements to the DC buses LH and LL. It can also be understood that the currents input to the input terminals 31 and 32 and the discharge currents of the capacitors C41 and C42 as charge / discharge elements are commutated and output by opening and closing the switch elements S41 and S42.
- the nonlinear capacitor circuit 4 can be grasped as a buffer unit interposed between the single-phase diode rectifier 3 as a diode bridge and the voltage source inverter 5. Further, the buffer unit functions as a rectification unit 2B that, in combination with the single-phase diode rectifier 3, rectifies the single-phase voltage Vi that is an alternating voltage with commutation due to switching of the switch elements S41 and S42 and flows the link current Idc. .
- the link current Idc is zero during the opening / closing operation of the switch elements S41 and S42, as in the first embodiment.
- the opening and closing of the switch elements S41 and S42 is determined as follows.
- FIG. 19 is an equivalent circuit of the single-phase / three-phase direct conversion device introduced in Patent Document 3 (FIG. 2 of Patent Document 3).
- FIG. 20 is a timing chart (FIG. 4 of Patent Document 3) showing the operation of the equivalent circuit (however, the carrier to which the symbol “C” is added in Patent Document 3 is considered in view of the first embodiment of the present application).
- the period tc in Patent Document 3 is different from the shift amount tc of the present application, and is shown as the period tc ′ in FIG.
- the link current Idc is generated during the period in which the current Ic flowing through the capacitors C41 and C42, the current Irec flowing through the single-phase diode rectifier 3, and the voltage source inverter 5 operates with a zero voltage vector. It is distributed to the flowing current Iz.
- the current Idc is treated as a current source, and the currents Ic, Irec, and Iz are treated as currents that flow due to conduction of the switches Sc, Srec, and Sz, respectively.
- Each switch Srec, Sc, Sz is controlled so that only one of them is always conducted.
- current distribution ratios for the currents Irec, Ic, and Iz are drec, dc, and dz, respectively.
- the current distribution ratios drec, dc, and dz can also be grasped as the ratios of conduction periods of the switches Srec, Sc, and Sz with respect to a predetermined period (for example, one cycle of the carrier C1 shown in the first embodiment), respectively.
- dc + drec + dz 1.
- the current distribution ratio drec of the current Irec flowing through this is determined by the current distribution ratio dc.
- the current distribution ratio dz is set depending on the operation of the voltage source inverter 5. Therefore, in this embodiment, the timing of the commutation operation of the rectification unit is determined only by the current distribution ratio dc.
- the commutation reference value drt is read as the commutation reference value (1-dc) in the first embodiment, the same operation as that of the rectifying unit and the voltage source inverter of the first embodiment is obtained in this embodiment.
- dst 1 ⁇ drt
- drt and dst are read as 1-dc and dc in FIGS. 4 to 7, 14 and 17, respectively.
- the link current Idc can be made zero at the timing when the switch Sc is turned on / off, so that the modulation factor in the voltage source inverter 5 is improved while realizing zero current switching. be able to.
- the carrier C1 obtained by shifting the carrier C employed for switching of the voltage source inverter 5 by the shift amount tc (detailed in the first embodiment) is used to obtain the signal SS.
- Adopt as a career.
- the timing at which the zero current is desired to be secured is not the timing at which the switch elements S41 and S42 open and close (this is also the timing at which the signal SS transitions), but the timing at which the switch Sc indicated by the equivalent circuit is turned on / off. Therefore, in executing this embodiment, it is not necessary to change the value drec compared with the carrier C1 to the value drec + dz in order to set the activation / deactivation of the signal SS.
- control unit 10 modified in this way can be grasped not only as the inverter control unit 30 in the first embodiment, but also as a rectification unit control unit that causes the rectification unit 2B to perform the above-described commutation. That is, the control unit 10 functions as a power conversion control device referred to in the present application.
- FIG. 21 is a circuit diagram showing a simplified single-phase / three-phase direct conversion device (FIG. 1 of Patent Document 4) introduced in Patent Document 4. Moreover, the symbol added to the component is changed to the symbol corresponding to the present application.
- the buffer circuit 4a includes a capacitor C4, and exchanges power with the DC buses LH and LL.
- the booster circuit 4b boosts the rectified voltage Vdc and charges the capacitor C4.
- the buffer circuit 4a further includes a switch Sc composed of a diode and a transistor connected in antiparallel.
- the switch Sc is connected in series between the DC buses LH and LL on the DC bus LH side with respect to the capacitor C4.
- the anti-parallel connection means that the forward directions are opposite to each other and are connected in parallel.
- the forward direction of the transistor is a direction from the DC bus LL to the DC bus LH
- the forward direction of the diode is a direction from the DC bus LH to the DC bus LL.
- Booster circuit 4b includes a diode D40, a reactor L4, and a switch Sl.
- the diode D40 includes a cathode and an anode, and the anode is connected between the switch Sc and the capacitor C4.
- Reactor L4 is connected between DC bus LH and the cathode.
- Switch Sl is connected between DC bus LL and the cathode.
- the switch S1 includes a transistor and a diode that are antiparallel to each other. Such a configuration is known as a so-called boost chopper.
- the capacitor C4 is charged by the booster circuit 4b.
- the opening and closing of the switches Sc and Sl are controlled by signals SSc and SSl, respectively.
- the signals SSc and SSl are output from the control unit 10.
- the capacitor C4 is charged from the DC bus LH through the reactor L4 and the diode D40 by opening and closing the switch Sl.
- the capacitor C4 is discharged to the DC buses LH and LL by the conduction of the switch Sc.
- the capacitor C4 functions as a charge / discharge element
- the switch Sc controls discharge from the charge / discharge element to the DC buses LH and LL. It can also be understood that the current input to the input terminals 31 and 32 and the discharge current of the capacitor C4 as a charge / discharge element are commutated and output by opening and closing the switch Sc.
- the buffer circuit 4a is a buffer unit interposed between the single-phase diode rectifier 3 serving as a diode bridge and the voltage source inverter 5.
- the buffer unit is coupled with the single-phase diode rectifier 3 and involves commutation due to switching of the switch Sc. It functions as a rectifier 2C that rectifies the single-phase voltage Vi, which is an alternating voltage, and flows the link current Idc.
- FIG. 22 is an equivalent circuit of the single-phase / three-phase direct conversion device introduced in Patent Document 4 (FIG. 2 of Patent Document 4).
- the link current Idc is a current Ic flowing through the capacitor C4, a current Irec flowing through the single-phase diode rectifier 3, and a current flowing during a period in which the voltage source inverter 5 operates with a zero voltage vector.
- Iz is an equivalent circuit of the single-phase / three-phase direct conversion device introduced in Patent Document 4 (FIG. 2 of Patent Document 4).
- the link current Idc is a current Ic flowing through the capacitor C4, a current Irec flowing through the single-phase diode rectifier 3, and a current flowing during a period in which the voltage source inverter 5 operates with a zero voltage vector.
- Iz Iz.
- the current Idc is treated as a current source, and the currents Ic, Irec, and Iz are treated as currents that flow due to conduction of the switches Sc, Srec, and Sz, respectively.
- Each switch Srec, Sc, Sz is controlled so that only one of them is always conducted.
- the rectification unit 2C is also read as 1-dc and dc in FIGS. 4 to 7, 14 and 17, respectively, in the same manner as the rectification unit 2B.
- the link current Idc can be made zero at the timing when the switch Sc is turned on / off, so that the modulation factor in the voltage source inverter 5 is improved while realizing zero current switching. be able to.
- the carrier C1 obtained by shifting the carrier C employed for switching of the voltage source inverter 5 by the shift amount tc is employed as a carrier for obtaining the signal SSc.
- the carrier for obtaining the signal SSc is shared with the carrier for obtaining the signal SS1. Specifically, it is not necessary to change the value compared with the shifted carrier C1.
- control unit 10 modified in this way can be grasped not only as the inverter control unit 30 in the first embodiment, but also as a rectification unit control unit that causes the rectification unit 2C to perform the above-described commutation. That is, the control unit 10 functions as a power conversion control device referred to in the present application.
- Non-Patent Document 2 has a configuration in which the booster circuit 4b is deleted from FIG. 21 of the present application (see FIG. 11 of Patent Document 4). Even in such a configuration, the configuration of the rectifying unit 2C is maintained, and the switching of the booster circuit 4b is not directly related to the commutation of the link current Idc as described above. Therefore, even in such a configuration, the carrier C1 obtained by shifting the carrier C employed for switching of the voltage source inverter 5 by the shift amount tc can be employed as the carrier for obtaining the signal SSc.
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Abstract
Description
{基本的な動作}
図1は本発明の実施の形態が採用される電力変換装置の構成を例示する回路図である。ここで例示される直接形交流電力変換装置はインダイレクトマトリックスコンバータであり、AC/DC変換を行う電流形コンバータ2と、DC/AC変換を行う電圧形インバータ5とを備えている。電流形コンバータ2と電圧形インバータ5とは、直流母線LH,LLによって接続される。直流母線LHは直流母線LLよりも高電位である。
さて、上述のように、デッドタイムtdの長さで隔離期間を構成する期間Udが零電流スイッチングに寄与する。よって原電圧ベクトルV0がキャリアC2の一周期において採用される時比率d0を零にしても、隔離期間は実電圧ベクトルV4が採用される期間に挟まれて存在する。
図7はキャリアC2が上昇中で隔離期間近傍におけるスイッチング信号Gup,Gunの振る舞いを示すタイミングチャートであり、時比率d0が負である場合を例示している。
スイッチング原信号Gu2pは、キャリアC2が信号波Vu2*より小さい値から信号波Vu2*の値を採った後デッドタイムtd経過して立ち上がる;
スイッチング原信号Gu2pは、キャリアC2が信号波Vu2*より大きい値から信号波Vu2*の値を採った時点で立ち下がる;
スイッチング原信号Gu2nは、キャリアC2が信号波Vu2*より小さい値から信号波Vu2*の値を採った時点で立ち下がる;
スイッチング原信号Gu2nは、キャリアC2が信号波Vu2*より大きい値から信号波Vu2*の値を採った後デッドタイムtd経過して立ち上がる;
スイッチング原信号Gu1pは、キャリアC2が信号波Vu1*より大きい値から信号波Vu1*の値を採った後デッドタイムtd経過して立ち上がる;
スイッチング原信号Gu1pは、キャリアC2が信号波Vu1*より小さい値から信号波Vu1*の値を採った時点で立ち下がる;
スイッチング原信号Gu1nは、キャリアC2が信号波Vu1*より大きい値から信号波Vu1*の値を採った時点で立ち下がる;
スイッチング原信号Gu1nは、キャリアC2が信号波Vu1*より小さい値から信号波Vu1*の値を採った後デッドタイムtd経過して立ち上がる。
上述の説明では上アーム側スイッチQypの全てがオフする隔離期間においてリンク電流Idcが零となり、電流形コンバータ2におけるスイッチングの際に、電流形コンバータ2に電流が流れないことを説明した。しかしながら、実電圧ベクトルV0が存在せず、かつ線電流iyが相電圧Vyに対して遅相量が大きくなる場合では、電圧形インバータ5内部での還流ではなく、直流母線LH,LLに回生電流としてリンク電流Idc(<0)が流れ得る。この場合には、直流母線LH,LL間にクランプ回路を設けることが望ましい。以下、そのような場合について説明する。
位相領域J1(0°≦Ψ≦60°):相電圧Vu,Vv,Vwがそれぞれ最大相、中間相、最小相;
位相領域J2(60°≦Ψ≦120°):相電圧Vu,Vv,Vwがそれぞれ中間相、最大相、最小相;
位相領域J3(120°≦Ψ≦180°):相電圧Vu,Vv,Vwがそれぞれ最小相、最大相、中間相;
位相領域J4(180°≦Ψ≦240°):相電圧Vu,Vv,Vwがそれぞれ最小相、中間相、最大相;
位相領域J5(240°≦Ψ≦300°):相電圧Vu,Vv,Vwがそれぞれ中間相、最小相、最大相;
位相領域J6(300°≦Ψ≦360°):相電圧Vu,Vv,Vwがそれぞれ最大相、最小相、中間相。
もしシフト量tcを設けることなく、電流形コンバータ2がスイッチングするタイミングが転流基準時点t00と一致し、かつ実電圧ベクトルV0が設けられる期間内に存在しなければならないのであれば、信号波Vu1*は値drt-td・cotαを上限とし、信号波Vu2*は値drt+td・cotαを下限としなければならなかった。これは電圧形インバータ5における変調率の制限であるばかりではなく、電流形コンバータ2における通流比の改善をも阻むことになる。
ここまでは、スイッチ素子Sxp、SxnやスイッチQyp,Qynが、それぞれスイッチング信号Gxp,Gxn,Gyp,Gynの活性/非活性に対して遅延せずに、導通/非導通するものとして説明してきた。以下では、スイッチ素子Sxp、SxnやスイッチQyp,Qynがスイッチング信号Gxp,Gxn,Gyp,Gynの活性/非活性に対して遅延することを考慮したシフト量tcの設定を説明する。
第1の実施の形態では、電圧形インバータ5に対して電流形コンバータ2がリンク電流Idcを供給する場合が説明された。簡単に言えば、電流形コンバータ2は、スイッチ素子Srn,Ssn,Stn,Srp,Ssp,Stpのスイッチングによる転流を伴って交番電圧たる三相電圧Vr,Vs,Vtを整流してリンク電流Idcを流す、整流部として機能していた。
電流形コンバータ2や非線形キャパシタ回路4,バッファ回路4aが転流するタイミングの、転流基準時点t00に対するずれであるシフト量tcは、常に非零である必要はなく、tc=0となるキャリア周期が存在してもよい。
Claims (7)
- 電力変換装置を制御する装置(9,10)であって、
前記電力変換装置は、
交番電圧(Vr,Vs,Vt;Vi)が印加される複数の入力端(Pr,Ps,Pt;31,32)と、
第1乃至第3の出力端(Pu,Pv,Pw)と、
第1及び第2の直流母線(LH,LL)と、
スイッチングによる転流を伴って前記交番電圧を整流し、前記第1の直流母線(LH)を前記第2の直流母線(LL)よりも高電位にしつつ、前記第1の直流母線(LH)から前記第2の直流母線(LL)へ直流電流(Idc)を流す整流部(2;2B;2C)と、
前記第1の直流母線(LH)と前記第2の直流母線(LL)との間の直流電圧(Vdc)を三相電圧(Vu,Vv,Vw)に変換して前記第1乃至第3の出力端に出力する電圧形インバータ(5)と
を備え、
前記電圧形インバータは、
前記直流電圧が印加される第1及び第2の直流母線(LH、LL)の間で相互に並列に接続される3つの電流経路を含み、
前記電流経路の各々が、
前記第1の直流母線と前記第1乃至第3の出力端の各々との間に接続され、導通時には前記第1の直流母線から前記第1乃至第3の出力端の各々に電流を流す上アーム側スイッチ(Qup,Qvp,Qwp)と、
前記第1乃至第3の出力端と前記第2の直流母線との間に接続され、導通時には前記第1乃至第3の出力端から前記第2の直流母線に電流を流す下アーム側スイッチ(Qun,Qvn,Qwn)と、
前記上アーム側スイッチの各々に対して逆並列に接続された上アーム側ダイオード(Dup,Dvp,Dwp)と、
前記下アーム側スイッチの各々に対して逆並列に接続された下アーム側ダイオード(Dun,Dvn,Dwn)と
を有し、
前記装置は、
時間に対する傾斜の絶対値(tanα)が一定であり、最小値(0)と最大値(1)との間で往復する三角波を呈するキャリア(C2)を生成するキャリア生成部(35)と、
前記最小値以上かつ前記最大値以下の転流基準値(drt;1-dc)を前記キャリアが採る転流基準時点(t00)から所定時間(tc)を加算した時点で、前記整流部に前記転流を実行させる整流部制御部(20;10)と、
前記電圧形インバータの前記上アーム側スイッチ及び前記下アーム側スイッチのオン/オフを、前記キャリアと前記三相電圧に対応する信号波との比較に基づいて制御するインバータ制御部(30)と
を備え、
前記インバータ制御部は、
第1時点(t01,t03)を始期とし、第2時点(t02,t04)にデッドタイム(td)を加えた時点を終期とする期間たる隔離期間(Ud,V0)において全ての前記上アーム側スイッチをオフ状態にし、
前記第1時点(t01;t03)は前記キャリアが第1の前記信号波(Vu1*;Vu2*)の値を採る時点であり、前記第2時点(t02,t04)は前記第1時点の後に初めて前記キャリアが前記第2の信号波(Vu2*;Vu1*)の値をとる時点であり、
前記第1の信号波及び前記第2の信号波は、前記三相電圧のうちの最大相についての前記信号波であり、
前記最大相の電圧に対応する電流を流す前記上アーム側スイッチ(Qup)は前記第1時点でオン状態からオフ状態へと遷移し、前記第2時点から前記デッドタイム経過後にオフ状態からオン状態へと遷移し、
前記所定時間(tc)は、前記第1時点から前記転流基準時点を差し引いた値(-τ01)よりも大きく、前記第2時点から前記転流基準時点を差し引いた値(τ02)と前記デッドタイムとの和よりも短い値に設定される、電力変換制御装置。 - 前記複数の入力端は三個の入力端(Pr,Ps,Pt)であり、
前記整流部は電流形コンバータ(2)であって、前記第1乃至第3の入力端の各々と前記第1の直流電源線との間に接続された3つのスイッチ素子(Srp,Ssp,Stp)と、前記第1乃至第3の入力端の各々と前記第2の直流電源線との間に接続された3つのスイッチ素子(Srn,Ssn,Stn)とを含むスイッチ群を有し、前記スイッチ群の開閉によって前記第1乃至第3の入力端に入力する三相電流(ir,is,it)を転流して出力する、請求項1記載の電力変換制御装置。 - 前記複数の入力端は一対の入力端(31,32)であり、
前記整流部(2B;2C)は、
前記一対の入力端に接続されたダイオードブリッジ(3)と、
充放電素子(C41,C42;C4)、及び前記充放電素子から第1及び第2の直流母線(LH、LL)への放電を制御するスイッチ素子(S41,S42;Sc)を含むバッファ部(4;4a)と
を有し、
前記整流部(2B;2C)は、前記スイッチ素子の開閉によって、前記一対の入力端に入力する電流と、前記充放電素子の放電電流とを転流して出力する、請求項1記載の電力変換制御装置。 - 前記所定時間(tc)は、前記第1時点(t01)から前記転流基準時点(t00)を差し引いた値(-τ01)と、前記第2時点(t02)から前記転流基準時点を差し引いた値(τ02)と、前記デッドタイム(td)との和の半分((1/2)(τ02-τ01+td)))に設定される、請求項1乃至請求項3のいずれか一つに記載の電力変換制御装置。
- 前記第2の信号波から前記第1の信号波を引いた値(d0)は、前記キャリアの前記傾斜の絶対値(tanα)と前記デッドタイム(td)との積を零から引いた値(-td・tanα)よりも大きい、請求項1乃至請求項3のいずれか一つに記載の電力変換制御装置。
- 前記第2の信号波から前記第1の信号波を引いた値(d0)は、前記キャリアの前記傾斜の絶対値(tanα)と前記デッドタイム(td)との積を零から引いた値(-td・tanα)よりも大きい、請求項4記載の電力変換制御装置。
- 前記所定時間(tc)は前記デッドタイムの半分(td/2)に設定される、請求項1乃至請求項3のいずれか一つに記載の電力変換制御装置。
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ES12853622.4T ES2630310T3 (es) | 2011-11-28 | 2012-11-27 | Dispositivo de control de conversión de potencia |
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JP2013138595A (ja) | 2013-07-11 |
US9178409B2 (en) | 2015-11-03 |
AU2012344863A1 (en) | 2014-07-17 |
CN103959630A (zh) | 2014-07-30 |
ES2630310T3 (es) | 2017-08-21 |
CN103959630B (zh) | 2015-07-08 |
US20140369089A1 (en) | 2014-12-18 |
JP5299555B2 (ja) | 2013-09-25 |
AU2012344863B2 (en) | 2015-05-14 |
AU2012344863C1 (en) | 2015-09-24 |
EP2787622A4 (en) | 2016-06-29 |
EP2787622A1 (en) | 2014-10-08 |
EP2787622B1 (en) | 2017-06-21 |
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