WO2013020309A1 - Carte de circuits imprimés à composant électronique intégré et procédé de fabrication de celle-ci - Google Patents

Carte de circuits imprimés à composant électronique intégré et procédé de fabrication de celle-ci Download PDF

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Publication number
WO2013020309A1
WO2013020309A1 PCT/CN2011/079032 CN2011079032W WO2013020309A1 WO 2013020309 A1 WO2013020309 A1 WO 2013020309A1 CN 2011079032 W CN2011079032 W CN 2011079032W WO 2013020309 A1 WO2013020309 A1 WO 2013020309A1
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Prior art keywords
electronic component
aluminum
aluminum electrode
circuit board
electrode
Prior art date
Application number
PCT/CN2011/079032
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English (en)
Chinese (zh)
Inventor
谷新
霍如肖
丁鲲鹏
杨之诚
孔令文
蔡坚
鲍平华
Original Assignee
深南电路有限公司
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Application filed by 深南电路有限公司 filed Critical 深南电路有限公司
Publication of WO2013020309A1 publication Critical patent/WO2013020309A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom

Definitions

  • the present invention relates to the field of circuit board manufacturing technology, and in particular to an electronic component embedded circuit board and a method of fabricating the same.
  • a power semiconductor chip such as a MOSFET or an IGBT chip
  • EMI electromagnetic interference
  • the switching frequency is getting higher and higher, the device volume is further reduced, the influence of parasitic parameters on power supply performance and reliability is becoming more and more significant, and the power consumption of the device is also increasing.
  • the above problem can be effectively solved by directly embedding the power chip inside the printed circuit board.
  • the power chip usually contains an aluminum electrode (hereinafter referred to as an aluminum electrode), and the chemical nature of the aluminum determines that the aluminum electrode cannot be compatible with the manufacturing process of the circuit board.
  • the surface of the aluminum electrode cannot be laser-processed, and the aluminum electrode is In the process of etching and the like, it may be corroded and damaged by chemical substances.
  • Embodiments of the present invention provide an electronic component embedded circuit board and a manufacturing method thereof, which can make an electronic component with an aluminum electrode compatible with a manufacturing process of a circuit board.
  • a manufacturing method of an electronic component embedded circuit board comprising:
  • the aluminum electrode was subjected to a rectification treatment, and nickel was plated on the surface of the aluminum electrode after the rectification treatment.
  • An electronic component embedded circuit board comprising:
  • a core layer having a through hole and electronic components buried in the through hole
  • One surface of the electronic component has an aluminum electrode having a nickel protective layer obtained by rectifying and nickel plating.
  • the technical solution of nickel treatment, the surface of the aluminum electrode after the rectification and nickel plating has increased the nickel protective layer, and in the subsequent circuit board manufacturing process, including laser blind hole processing, etching, etc., it will not be laser, various Acidic or alkaline chemical solution is damaged.
  • FIG. 1a is a flow chart showing a method of manufacturing an electronic component embedded circuit board according to an embodiment of the present invention
  • FIG. 1b is a flow chart showing a method of manufacturing an electronic component embedded circuit board according to another embodiment of the present invention
  • Embodiments of the present invention provide an electronic component embedded circuit board and a manufacturing method thereof, which adopt a technical scheme for performing a rectification process and a nickel plating process on an aluminum electrode of an electronic component embedded in a circuit board, and are processed by re-rendering and nickel plating. After the obtained nickel protective layer protects the aluminum electrode, the aluminum electrode is not damaged by laser, various acidic or alkaline chemical solutions in the process of manufacturing the circuit board including laser blind hole processing and etching. The details are described below separately. Referring to FIG. 1 , an embodiment of the present invention provides a method for manufacturing an electronic component embedded circuit board, including:
  • the electronic component is embedded in a through hole formed in a core layer of the circuit board, and one side of the electronic component has an aluminum electrode.
  • the opposite faces of the electronic component 400 have an aluminum electrode 401 and a non-aluminum electrode 402, respectively.
  • the electronic component 400 can be a power chip or any other type of component.
  • the non-aluminum electrode 402 is usually an electrode of silver-nickel or an electrode of other non-aluminum metal such as nickel or copper.
  • the core layer of the circuit board may be a single-sided copper clad laminate comprising an organic resin layer 501 and a metal layer 502 covering the surface of the organic resin layer 501.
  • the thickness of the organic resin layer 501 can be determined depending on the thickness of the electronic component 400, and is usually between 100 ⁇ m and 400 ⁇ m, and cannot be smaller than the thickness of the electronic component 400.
  • the thickness of the metal layer 502 is typically between 3 microns and 100 microns, as determined by the actual scenario.
  • the body can include: 111.
  • a through hole is formed in a core layer of the circuit board, and a first circuit pattern is formed on the first surface of the core layer.
  • a through hole 503 is formed in the core layer, and the size of the through hole 503 matches the size of the electronic component.
  • the number of the through holes 503 is equivalent to the number of electronic components to be buried, and may be one or plural.
  • the metal layer 502 of the first side of the core layer has been processed to form a first circuit pattern, and the first circuit pattern in the drawing is still indicated by 502.
  • a tape 504 is applied to the second side of the core layer.
  • the tape 504 may be an ultraviolet UV tape that loses its tackiness when exposed to ultraviolet light for easy removal; it may be other tapes, such as tapes that lose their tack when exposed to high temperatures such as 150 degrees Celsius.
  • the electronic component 400 is placed in the through hole 503, wherein the lower surface of the electronic component 400 having the aluminum electrode 401 is contacted and adhered to the tape 504 for temporary fixing.
  • the aluminum electrode 401 can be a plurality of independent aluminum electrodes.
  • the through hole 503 is slightly larger than the electronic component 400, and a gap is formed between the side surface of the electronic component 400 and the side surface of the through hole 503. As shown in FIG. 3e, in this step, the gap is filled with an insulating medium 505, wherein the insulating medium 505 is used to fix the electronic component in the core layer, and on the other hand, the insulating medium 505 is used to move the core layer up and down.
  • the insulating medium 505 is preferably a photosensitive resin.
  • the surface of the non-aluminum electrode 402 may be printed by the exposure and development process in the through hole 503, including the slit and the upper surface of the electronic component 400 having the non-aluminum electrode 402, all of which are printed with a photosensitive resin. The photosensitive resin is removed.
  • a conductive medium is filled on an upper surface of the electronic component having a non-aluminum electrode, and a non-aluminum electrode of the electronic component is electrically connected to the first circuit pattern.
  • the non-aluminum electrode 402 is electrically connected to the first circuit pattern 502 through the conductive medium 506.
  • a polishing and leveling step may also be included.
  • the conductive medium 506 is ground to be flush with the surface of the first circuit pattern.
  • Figure 3h is a schematic illustration of the removal of the tape 504.
  • the tape can be removed by hand, and the tape has been removed by chemical means or by ultraviolet light. After the tape is removed, the surface of the aluminum electrode 401 has no residual glue and is not contaminated by the tape.
  • the aluminum electrode is subjected to a rectification process, and nickel is plated on the surface of the aluminum electrode after the rectification process.
  • the surface of the aluminum electrode 401 is first subjected to a rectification process, as shown in FIG. 3i; and then nickel plating is performed, as shown in FIG. 3j.
  • a nickel protective layer 403 is formed on the surface of the aluminum electrode 401.
  • the rectification treatment comprises: immersing the aluminum electrode at a normal temperature of about 3 wt% to 5 wt ⁇ NaOH solution for about 10 to 30 seconds, and then immersing in a 20 wt% to 50 wt% nitric acid solution at room temperature for 10-30 seconds to ensure aluminum.
  • the aluminum electrode is immersed in a solution containing 500 g/L of NaOH and 100 g/L of ZnO, and immersed at room temperature for 10 to 30 seconds to form a layer of metal on the surface of the aluminum electrode.
  • wt% means weight percentage.
  • the nickel plating treatment is electroless nickel plating on the surface of the lexical layer after the rectification process, including: after the etched aluminum electrode is washed with deionized water, immediately placed in the electroless nickel plating solution for nickel plating 10 ⁇
  • the nickel plating solution is mainly composed of NiS0 4 and NaH 2 P0 2
  • the bath temperature is about 70-90 degrees Celsius
  • a Ni-P metal layer with a thickness of 7 microns or more is plated on the surface.
  • the main component of the electroless nickel plating coating is nickel, but other trace elements such as phosphorus and the like are not limited, and the phosphorus content may be between 4% by weight and 10% by weight, wherein ⁇ 1% means weight percentage.
  • subsequent processing can be performed according to a conventional process flow, and the aluminum electrode 401 under the protection of the nickel protective layer 403 will not It is then damaged by various chemical solutions in processes such as laser or etching.
  • subsequent steps can include:
  • the insulating dielectric layer 507 is laminated on the second side of the core layer, i.e., the side on which the aluminum electrode 401 is located.
  • the insulating dielectric layer 507 may be a prepreg resin.
  • a blind via 508 is formed on the insulating dielectric layer 507 corresponding to the position of the aluminum electrode 401, and the bottom of the blind via 508 reaches the aluminum electrode 401.
  • the blind hole 508 can be processed by laser drilling.
  • the blind via 508 is then metallized, i.e., a metal plating is formed on the inner wall of the blind via 508 by chemical copper plating, electroplating, or the like to make the blind via 508 a metallized blind via.
  • a second circuit pattern can be formed on the surface of the insulating dielectric layer 507 by using a conventional circuit board patterning process.
  • the second circuit pattern can be processed by the metallization blind via 508 and the electronic component 400 after being re-chemicalized and nickel-plated.
  • the aluminum electrode 401 is electrically connected.
  • the surface can be formed by electroless copper plating, pattern electroplating copper, etching, and the like.
  • the double-sided circuit board in which the electronic components are buried is completed. If other circuit layers are to be added, a conventional circuit board process can be used to add layers on both sides of the double-sided embedded electronic component.
  • an embodiment of the present invention provides a method for manufacturing an embedded circuit board for an electronic component, which adopts a technical solution for performing a rectification process and a nickel plating process on an aluminum electrode of an electronic component embedded in a circuit board,
  • the nickel-protected layer obtained after nickel plating protects the aluminum electrode, so that the aluminum electrode is not subjected to laser and various acidic or alkaline chemical solutions in the process of manufacturing the circuit board including laser drilling and etching. damage.
  • the connection of the portion of the electrode to an external circuit can be achieved by a conductive material filling method.
  • an embodiment of the present invention further provides an electronic component embedded circuit board, comprising: a core layer having a through hole 503 and an electronic component 400 embedded in the through hole 503;
  • One surface of the electronic component 400 has an aluminum electrode 401 having a nickel protective layer 403 obtained by rectifying and nickel plating.
  • a first circuit pattern of the core layer away from the aluminum electrode 401 is formed, and the first circuit pattern is electrically connected to the non-aluminum electrode 402 of the electronic component 400;
  • the second surface of the core layer where the aluminum electrode 401 is located is press-bonded with an insulating dielectric layer 507, and the second dielectric pattern is formed on the insulating dielectric layer 507, and the second circuit pattern is formed on the insulating dielectric layer 507.
  • the metallized blind vias 508 are electrically connected to the aluminum electrodes 401.
  • a gap between the side of the electronic component 400 and the side of the through hole 503 is filled with an insulating medium 505.
  • the insulating medium 505 is preferably a photosensitive resin.
  • the upper surface of the non-aluminum electrode 402 of the electronic component 400 in the via 503 is filled with a conductive medium 506 through which the non-aluminum electrode 402 of the electronic component is electrically connected to the first circuit pattern.
  • the electronic component embedded circuit board provided by the embodiment of the invention has a nickel protective layer obtained by rectifying and nickel plating on the surface of the aluminum electrode, which can prevent damage of laser drilling and various acidic or alkaline. Chemical solution corrosion.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention porte sur un procédé de fabrication pour une carte de circuits imprimés à composant électronique intégré (400), comprenant : l'intégration d'un composant électronique (400) dans un trou traversant d'une couche de cœur sur une carte de circuits imprimés, un côté du composant électronique (400) ayant une électrode d'aluminium (401); et le zingage de la couche de l'électrode d'aluminium (401) et le nickelage de la surface de l'électrode d'aluminium zinguée (401). L'invention porte également sur une carte de circuits imprimés intégrant un composant électronique correspondant (400). Étant donné qu'une couche de protection de zinc et de nickel (403) est formée sur la surface d'une électrode d'aluminium (401) par application d'un traitement de zingage et d'un traitement de nickelage dans la solution technique de la présente invention, l'électrode d'aluminium (401) ne sera pas endommagée par laser ou un quelconque genre de solutions chimiques acides ou alcalines durant le déroulement subséquent de la fabrication de la carte de circuits imprimés.
PCT/CN2011/079032 2011-08-10 2011-08-29 Carte de circuits imprimés à composant électronique intégré et procédé de fabrication de celle-ci WO2013020309A1 (fr)

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CN107124822A (zh) * 2017-05-30 2017-09-01 邹时月 一种裸芯片嵌入式电路板的制造方法
CN107046771A (zh) * 2017-05-30 2017-08-15 邹时月 一种埋入式电路板的制造方法
CN111199888A (zh) * 2018-11-20 2020-05-26 奥特斯奥地利科技与系统技术有限公司 包括pid的部件承载件以及制造部件承载件的方法
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