WO2013010352A1 - 一种低k芯片封装方法 - Google Patents

一种低k芯片封装方法 Download PDF

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Publication number
WO2013010352A1
WO2013010352A1 PCT/CN2011/081112 CN2011081112W WO2013010352A1 WO 2013010352 A1 WO2013010352 A1 WO 2013010352A1 CN 2011081112 W CN2011081112 W CN 2011081112W WO 2013010352 A1 WO2013010352 A1 WO 2013010352A1
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Prior art keywords
chip
wafer
metal
low
film layer
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PCT/CN2011/081112
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English (en)
French (fr)
Inventor
张黎
赖志明
陈栋
陈锦辉
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江阴长电先进封装有限公司
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Priority to US14/233,461 priority Critical patent/US8987055B2/en
Publication of WO2013010352A1 publication Critical patent/WO2013010352A1/zh

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    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the invention relates to a Low-k chip packaging method and belongs to the technical field of chip packaging.
  • the chip line width node is mainly divided into several stages: 0.18 ⁇ m stage, when the MOS tube starts to be popular, the chip is manufactured in the initial stage of the semiconductor process, and the size of the manufactured chip is relatively large; in the 0.13 ⁇ m stage, people are confident in the semiconductor process. It is hoped that the chip area and cost will be reduced by reducing the feature size; these two stages are what we often call the micron process stage.
  • the initial nanometer is 90nm support, but the number of cores per unit area increases according to the law of Moore's law.
  • Low-k low dielectric loss constant
  • the packaging process of the chip needs to be correspondingly upgraded to meet the needs of the product application.
  • the package for the low-k product is still in the usual flip-chip structure or wire bonding mode, resulting in package yield.
  • the loss is more, and the structure of the failure analysis points to the dielectric layer fragmentation under the bonding electrodes (wire bonding and flip bonding).
  • the usual solution is to use a flip-chip bonding package for the wire bonding package, and to place a non-flowing underfill adhesive on the substrate before flip-chip bonding.
  • the package structure and flow are as shown in FIG. 1 and FIG.
  • the underfill adhesive has both the properties of a common underfill adhesive and the nature of reflow solder, so that wetting can be formed between the solder balls and the substrate pads.
  • the advantage of this method is that the soldering of the conventional flip chip process is improved.
  • the ball stress causes the damage of the dielectric layer inside the chip.
  • the stress of the reflow is redistributed by the non-flowing underfill adhesive, and the inner dielectric layer of the chip is not damaged due to stress concentration.
  • the biggest disadvantage of this method is that the wettability of the solder is not strong due to the presence of the underfill adhesive, and it cannot be ensured that each solder ball is well bonded to the pad, and the underfill filler is easily cured due to the presence of the flux and the reflow process. A void occurs in the process, and the packaging process is complicated and costly.
  • the object of the present invention is to overcome the above-mentioned deficiencies, and to provide a Low-k chip packaging method and a package structure, which can solve the problem of low-k chip failure caused by stress concentration in the chip packaging process, and provide a low-cost package solution for the Low-K chip package. Program.
  • the object of the present invention is achieved by a Low-k chip packaging method, the method comprising the following processes:
  • Step 1 taking a Low-k wafer, and cutting the Low-k wafer into a single chip
  • Step 2 preparing a carrier wafer, forming a registration mark on the carrier wafer by photolithography, and completing the graphic layout on the carrier wafer;
  • Step 3 attaching a temporary peeling film on the carrier disc, and flipping the single chip cut in the first step one by one onto the carrier disc with the temporary peeling film attached to complete the chip flipping;
  • Step 4 attaching a film layer I to the carrier wafer on which the chip is flipped, and encapsulating the support wafer, and bonding the support wafer to the film layer I during the encapsulation process, and then curing the film layer I to form a chip and a film layer.
  • Step 5 stripping the reconstructed wafer and the carrier wafer, and cleaning the surface of the chip of the reconstructed wafer to expose the chip electrode;
  • Step 6 performing single-layer or multi-layer rewiring metal traces on the film layer I and the surface of the chip by means of photolithography, sputtering or electroplating, and guiding the chip electrodes to the peripheral area of the chip by rewiring the metal traces;
  • Step 7 forming a metal pillar by photolithography or electroplating at the terminal of the completed rewiring metal trace
  • Step 8 Apply a film layer II on the surface of the reconstructed wafer on which the metal pillar is formed for encapsulation and solidification, and then etch away the film material at the top of the metal pillar by laser ablation to form a complete or partial opening of the metal pillar. , the top of the metal column is exposed to the film layer II;
  • Step IX plating a metal layer on the top of the metal pillar exposing the film layer II;
  • Step 10 forming a BGA solder ball on the metal layer by printing or ball-planting, and finally cutting the reconstructed wafer forming the BGA solder ball into a single BGA package.
  • the metal column is made of a conductive metal such as copper or nickel, and has a height of between 50 ⁇ m and 100 ⁇ m.
  • the metal layer is a multilayer metal having a structure of Ni/Au or Ni/Pd/Au, and the thickness of the metal layer is not more than 5 ⁇ m.
  • the film layer I and the film layer II are made of a non-photosensitive material.
  • the support wafer is a silicon wafer or a metal sheet.
  • the carrier wafer is a silicon substrate or a glass substrate.
  • the chip is directly flipped on the carrier wafer, does not undergo the reflow process, and has no stress concentration experience, and solves the problem that the stress concentration of the flip-chip process in the current Low-k chip BGA package causes the chip to fail;
  • the chip electrodes are epitaxially extended to the non-chip area by rewiring, and the stress generated by the BGA structure mounting process is transferred, and the chip area is in an unstressed state;
  • the low-reliability of the package can be realized while realizing the high-reliability packaging of the Low-k chip;
  • FIG. 1 is a schematic diagram of a current Low-k chip package structure.
  • FIG 3 is a schematic view of a Low-k chip package structure of the present invention.
  • FIG. 4 is a flow chart showing the packaging process of the Low-k chip package structure of the present invention.
  • a Low-k chip package structure of the present invention includes a chip body 2-1, a chip electrode 2-2, and a chip surface passivation layer 2-3, and the chip body 2-1 is overcoated.
  • a film layer I2-4 There is a film layer I2-4, the film layer I2-4 is back-bonded with a support wafer 2-5, and the chip electrode 2-2 is transferred to a film layer outside the periphery of the chip via the rewiring metal trace 2-6.
  • a metal post 2-7 is provided, and the metal post 2-7 is covered with a thin film layer II2-8, and the top end of the metal post 2-7 is exposed to the thin film layer. II2-8, a metal layer 2-9 is disposed at the top end of the exposed metal pillar 2-7, and the solder ball 2-10 is disposed on the metal layer 2-9.
  • the implementation process of the Low-k chip package structure of the present invention is as follows:
  • Step 1 Take a Low-k wafer and cut the Low-k wafer into a single chip.
  • Step 2 Prepare a carrier wafer, form a registration mark on the carrier wafer by photolithography, and complete the graphic layout on the carrier wafer.
  • the carrier wafer can be selected from a silicon substrate or a glass substrate, and the purpose of forming the alignment mark is convenient for subsequent chip flipping, so that the chip can be guaranteed in an ideal position.
  • Step 3 attach a temporary release film to the carrier wafer, and flip the single chip cut in step one onto the carrier wafer with the temporary release film.
  • the temporary release film has adhesiveness on both sides, and can form a good connection with the carrier wafer and the subsequently flip chip.
  • the release film is a thermal peeling property or a UV light peeling property, and if it is a UV light peeling property, it needs to be used.
  • the carrier wafer of the glass substrate or the quartz substrate needs to be irradiated with UV due to UV light peeling, so that a transparent substrate is required to achieve transmission of UV light.
  • the chip is selected for two purposes. On the one hand, it is to ensure that the chips of different thicknesses are on the same plane in the subsequent process, and on the other hand, the front side of the chip is covered with no glue on the reconstructed wafer to facilitate subsequent Process.
  • Step 4 attaching a film layer I2-4 to the carrier wafer on which the chip is flipped, and encapsulating the support wafer 2-5 to the film layer I2-4 during the encapsulation process, and then curing the film layer I2. -4, forming a reconstituted wafer consisting of a chip, a thin film layer I2-4, and a support wafer 2-5.
  • the supporting wafer 2-5 is a silicon wafer or a metal sheet, and the film layer I2-4 is used for good fluidity under heating, thereby ensuring the flatness of the surface of the wafer.
  • Step 5 The reconstituted wafer and the carrier wafer are peeled off by UV irradiation or thermal peeling, and the surface of the chip of the reconstructed wafer is cleaned to expose the chip electrode 2-2.
  • Step 6 Complete single-layer or multi-layer rewiring metal traces 2-6 on the film layer I2-4 and the surface of the chip by photolithography, sputtering or electroplating of the wafer level process, and rewire the metal traces 2 - 6 Lead the chip electrode 2-2 to the peripheral area of the chip (without the chip area).
  • Step 7 Form the metal posts 2-7 by photolithography or electroplating at the terminals of the completed rewiring metal traces 2-6.
  • the metal pillars 2-7 are conductive metals such as copper and nickel, and the height of the metal pillars 2-7 can be adjusted according to the structural requirements, and the height should be not less than 50 ⁇ m, usually between 50 ⁇ m and 100 ⁇ m.
  • the metal column 2-7 has two functions here. First, the current crowding effect is reduced, and the current can be evenly distributed to reduce the occurrence of electromigration. On the other hand, the height of the metal column 2-7 is buffered. The stress from the solder balls 2-10 protects the Low-k chip.
  • Step 8 coating and solidifying the surface of the reconstituted wafer on which the metal pillars 2-7 are formed by coating the film layer II2-8, and then etching the film material at the top of the metal pillar by laser ablation to form a metal pillar
  • the complete or partial opening of 2-7 causes the top of the metal post to expose the film layer II2-8.
  • the film layer I2-4 and the film layer II2-8 are non-photosensitive resin insulating materials.
  • Step 9 A metal layer 2-9 is plated on the top of the metal pillar 2-7 exposing the film layer II2-8.
  • the metal layer 2-9 is a single layer or a plurality of layers of metal, and the general structure is Ni/Au or Ni/Pd/Au, and the thickness of the metal layer 2-9 is not more than 5 ⁇ m, and the purpose is to block tin and copper in the solder. The mutual diffusion between the two increases the reliability of the product.
  • Step 10 Form BGA solder balls 2-10 on the metal layers 2-9 by printing or ball-planting, and finally cut the reconstructed wafers forming the BGA solder balls into a single BGA package.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

提供一种低k芯片封装方法，包括：在载体圆片上贴一层临时剥离膜，将芯片（2-1）经由临时剥离膜倒装在载体圆片上，在载体圆片上贴上薄膜层I（2-4）进行包封，支撑圆片（2-5）键合到薄膜层I（2-4）上并固化，形成芯片（2-1）、薄膜层I（2-4）和支撑圆片组成的重构晶圆，将重构晶圆和载体圆片剥离，在薄膜层I（2-4）上完成再布线金属走线（2-6），在再布线金属走线（2-6）的终端形成金属柱（2-7），在金属柱（2-7）表面贴附薄膜层II（2-8）进行包封并固化，在金属柱（2-7）顶端镀上金属层（2-9），通过印刷或植球方式在金属层（2-9）上形成BGA焊球（2-10），最后将形成BGA焊球（2-10）的重构晶圆切割成单颗BGA封装体。

Description

[根据细则37.2由ISA制定的发明名称]　一种低K芯片封装方法 技术领域
本发明涉及一种Low-k芯片封装方法，属于芯片封装技术领域。
 背景技术
在半导体制造行业，摩尔定律一直是鞭策行业向前发展的动力，其中Intel在此方面功不可没。芯片线宽节点主要分为几个阶段：0.18µm阶段，为MOS管开始风靡的时候，为半导体制程的初级阶段，制造的芯片的尺寸相对较大；0.13µm阶段，人们对半导体制程信心十足，寄希望通过减小特征尺寸来缩小芯片面积和成本；这两个阶段为我们常说的微米制程阶段。随着纳米技术的发展，人们的目光远不止于微米技术，开始将半导体制程向纳米尺度进阶，最初出现的纳米是90nm的支撑，但随着单位面积上管芯数量按照摩尔定律的指数增长，相继出现了65纳米、45纳米、32纳米和目前的22纳米技术，这种特征尺寸的急剧缩减，导致介电材料追求低介电损耗常数（通常称为Low-k），以减小电路结构的寄生电阻、电容和电感，同时保证线路具有良好的绝缘性能。通常，低k材料的选择为多孔材料，这导致材料相对较脆，在外加应力的情况下容易碎裂，造成线路失效。
由于低K材料易碎裂的特性，芯片的封装工艺需要做相应的提升以适应产品应用的需求，目前针对低k产品的封装采用还是通常的倒装结构或引线键合方式，造成封装良率损失较多，失效分析的结构都指向键合电极（引线键合和倒装键合）下的介电层碎裂。目前通常的解决方式是将引线键合封装用倒装键合封装，同时在倒装键合前在基板上点上非流动性的底填料胶，该封装结构和流程如图1、图2所示，该底填料胶既有普通底填料胶的性质，也有回流焊剂的性质，因而焊球和基板焊垫之间能形成润湿，该方法的好处是改良了通常的倒装工艺回流时焊球应力导致芯片内部介电层损伤的问题，通过非流动性底填料胶将回流的应力重新分配，不会因为应力集中而导致芯片内层介电层受到损伤。但该方式的最大缺点是因底填料胶的存在导致焊剂的润湿作用不强，而无法保证每个焊球与焊盘结合良好，且因焊剂的存在和回流工艺容易导致底填料胶在固化过程中出现空洞，并且封装工艺过程复杂，成本较高。
综上所述，在Low-k芯片的封装过程中，目前存在的主要有两个方面的问题：
1、采用引线键合和常规倒装工艺，因为工艺过程应力导致芯片电极处应力集中，进而破会易碎裂的Low-K介电层，导致芯片失效；
2、采用非流动性底填料方式倒装工艺存在焊接不良和固化后胶体空洞缺陷，导致产品可靠性低。
 技术问题
本发明的目的在于克服上述不足，提供一种Low-k芯片封装方法和封装结构，能够解决芯片封装过程应力集中导致Low-k芯片失效问题，为Low-K芯片的封装提供低成本的封装解决方案。
 技术解决方案
本发明的目的是这样实现的：一种Low-k芯片封装方法，所述方法包括以下工艺过程：
步骤一、取一Low-k圆片，将该Low-k圆片切割成单颗芯片；
步骤二、准备一片载体圆片，在载体圆片上通过光刻方式形成对位标志，完成载体圆片上的图形布局；
步骤三、在载体圆片上贴上一层临时剥离膜，将步骤一切割成的单颗芯片一一倒装在贴有临时剥离膜的载体圆片上，完成芯片倒装；
步骤四、在完成芯片倒装的载体圆片上贴上薄膜层I进行包封，在包封过程中将支撑圆片键合到薄膜层I上，然后固化薄膜层I，形成由芯片、薄膜层I和支撑圆片组成的重构晶圆；
步骤五、将上述重构晶圆与载体圆片进行剥离，并将重构晶圆的芯片表面清洗干净，露出芯片电极；
步骤六、通过光刻、溅射或电镀等方式在薄膜层I和芯片表面完成单层或多层再布线金属走线，通过再布线金属走线将芯片电极引导至芯片周边区域；
步骤七、在完成的再布线金属走线的终端通过光刻或电镀的方式形成金属柱；
步骤八、在形成金属柱的重构晶圆表面贴上薄膜层II进行包封并固化，然后利用激光烧蚀的方式将金属柱顶端的薄膜材料刻蚀掉，形成金属柱的完整或部分开口，使金属柱顶端露出薄膜层II；
步骤九、在露出薄膜层II的金属柱顶端镀上金属层；
步骤十、通过印刷或者植球的方式在所述金属层上形成BGA焊球，最后将形成BGA焊球的重构晶圆切割成单颗BGA封装体。
所述金属柱采用铜、镍等导电金属，其高度在50µm~100µm之间。
所述金属层为多层金属，其结构为Ni/Au或者Ni/Pd/Au，金属层的厚度不超过5µm。
所述薄膜层I和薄膜层II采用非光敏性材料。
所述支撑圆片为硅片或金属片。
所述载体圆片采用硅基材或者玻璃基材。
 有益效果
与现有技术相比，本发明的有益效果是：
1、将芯片直接倒装在载体圆片上，不经历回流过程，无应力集中经历，解决了目前Low-k芯片BGA封装中倒装工艺过程应力集中导致芯片失效的问题；
2、利用了圆片级的工艺将芯片电极通过再布线外延至非芯片区，将BGA结构贴装过程产生的应力转移，芯片区域处于不受力状态；
3、利用金属柱技术和结构，实现高功率的载流和电流均匀分配，同时利用铜柱的高度，缓冲来自BGA焊球的应力，使其不到达再布线层。
4、结合圆片级封装工艺和金属柱工艺，在实现Low-k芯片高可靠性封装的同时，还可以实现封装的低成本化；
5、利用薄膜贴膜技术代替现有的包封技术，降低了封装工艺对设备的要求；
6、整合了凸点工艺、倒装工艺和基板工艺，实现了BGA封装的晶圆制造工艺。
 附图说明
图1为目前Low-k芯片封装结构的示意图。
图2为目前Low-k芯片封装结构的封装工艺流程图。
图3为本发明Low-k芯片封装结构的示意图。
图4为本发明Low-k芯片封装结构的封装工艺流程图。
其中：
芯片本体1-1
芯片电极1-2
表面钝化层1-3
凸点下金属层1-4
焊球凸点1-5
基板1-6
基板焊盘I1-7
低填料胶1-8
基板焊盘II1-9
BGA焊球1-10
芯片本体2-1
芯片电极2-2
芯片表面钝化层2-3
薄膜层I2-4
支撑圆片2-5
再布线金属走线2-6
金属柱2-7
薄膜层II2-8
金属层2-9
焊球2-10。
 本发明的实施方式
参见图3~4，本发明一种Low-k芯片封装结构，它包括芯片本体2-1、芯片电极2-2和芯片表面钝化层2-3，所述芯片本体2-1外包覆有薄膜层I2-4，所述薄膜层I2-4背面键合设置有支撑圆片2-5，所述芯片电极2-2经由再布线金属走线2-6转移至芯片周边外的薄膜层I2-4上，在再布线金属走线2-6的终端设置有金属柱2-7，所述金属柱2-7外包覆有薄膜层II2-8，金属柱2-7顶端露出薄膜层II2-8，在露出的金属柱2-7顶端设置有金属层2-9，所述金属层2-9上设置有焊球2-10。
本发明Low-k芯片封装结构的实现过程如下：
步骤一、取一Low-k圆片，将该Low-k圆片切割成单颗芯片。
步骤二、准备一片载体圆片，在载体圆片上通过光刻方式形成对位标志，完成载体圆片上的图形布局。
所述载体圆片可选用硅基材或者玻璃基材，形成对位标志的目的时方便后续芯片倒装，使芯片能保证在理想的位置。
步骤三、在载体圆片上贴上一层临时剥离膜，将步骤一切割成的单颗芯片一一倒装在贴有临时剥离膜的载体圆片上。
所述临时剥离膜双面都具有粘性，可以与载体圆片和后续倒装的芯片形成较好的连接，该剥离膜是热剥离属性或者UV光剥离属性，如果为UV光剥离属性，需要使用玻璃基材或石英基材的载体圆片，因UV光剥离需要使用UV进行照射，因此需选用透明基材以实现UV光的透过。
芯片选用倒装有两个目的，一方面是为了保证不同厚度芯片在后续的工艺中芯片正面在同一平面上，另一方面是芯片正面在重构晶圆上无胶覆盖，以方便进行后续的工艺。
步骤四、在完成芯片倒装的载体圆片上贴上薄膜层I2-4进行包封，在包封过程中将支撑圆片2-5键合到薄膜层I2-4上，然后固化薄膜层I2-4，形成由芯片、薄膜层I2-4和支撑圆片2-5组成的重构晶圆。
所述支撑圆片2-5为硅片或金属片，包封时利用薄膜层I2-4在加热情况下良好的流动性，保证了圆片表面的平整性。
步骤五、利用UV照射或者热剥离的方式将上述重构晶圆与载体圆片进行剥离，并将重构晶圆的芯片表面清洗干净，露出芯片电极2-2。
步骤六、通过圆片级工艺的光刻、溅射或电镀等方式在薄膜层I2-4和芯片表面完成单层或多层再布线金属走线2-6，通过再布线金属走线2-6将芯片电极2-2引导至芯片周边区域（不含芯片区域）。
步骤七、在完成的再布线金属走线2-6的终端通过光刻或电镀的方式形成金属柱2-7。
所述金属柱2-7为铜、镍等导电金属，金属柱2-7的高度可按照结构需求进行调节，高度应不低于50µm，通常在50µm~100µm之间。金属柱2-7在此有两方面的作用，一是减小电流拥挤效应，即可将电流均匀分布，从而减小电迁移现象的发生；另一方面，利用金属柱2-7的高度缓冲来自焊球2-10的应力，从而保护Low-k芯片。
步骤八：在形成金属柱2-7的重构晶圆表面贴上薄膜层II2-8进行包封并固化，然后利用激光烧蚀的方式将金属柱顶端的薄膜材料刻蚀掉，形成金属柱2-7的完整或部分开口，使金属柱顶端露出薄膜层II2-8。
所述薄膜层I2-4和薄膜层II2-8为非光敏性树脂绝缘类材料。
步骤九、在露出薄膜层II2-8的金属柱2-7顶端镀上金属层2-9。
所述金属层2-9为单层或多层金属，通常的结构为Ni/Au或者Ni/Pd/Au，金属层2-9的厚度不宜超过5µm，其目的时阻挡焊料中的锡和铜之间的相互扩散，提升产品的可靠性。
步骤十、通过印刷或者植球的方式在所述金属层2-9上形成BGA焊球2-10，最后将形成BGA焊球的重构晶圆切割成单颗BGA封装体。

Claims (8)

  1. 一种Low-k芯片封装方法，其特征在于：所述方法包括以下工艺过程：
    步骤一、取一Low-k圆片，将该Low-k圆片切割成单颗芯片；
    步骤二、准备一片载体圆片，在载体圆片上通过光刻方式形成对位标志，完成载体圆片上的图形布局；
    步骤三、在载体圆片上贴上一层临时剥离膜，将步骤一切割成的单颗芯片一一倒装在贴有临时剥离膜的载体圆片上，完成芯片倒装；
    步骤四、在完成芯片倒装的载体圆片上贴上薄膜层I（2-4）进行包封，在包封过程中将支撑圆片（2-5）键合到薄膜层I（2-4）上，然后固化薄膜层I（2-4），形成由芯片、薄膜层I（2-4）和支撑圆片（2-5）组成的重构晶圆；
    步骤五、将上述重构晶圆与载体圆片进行剥离，并将重构晶圆的芯片表面清洗干净，露出芯片电极（2-2）；
    步骤六、通过光刻、溅射和电镀方式在薄膜层I（2-4）和芯片表面完成单层或多层再布线金属走线（2-6），通过再布线金属走线（2-6）将芯片电极（2-2）引导至芯片周边区域；
    步骤七、在完成的再布线金属走线（2-6）的终端通过光刻和电镀的方式形成金属柱（2-7）；
    步骤八、在形成金属柱（2-7）的重构晶圆表面贴上薄膜层II（2-8）进行包封并固化，然后利用激光烧蚀的方式将金属柱顶端的薄膜材料刻蚀掉，形成金属柱（2-7）的完整或部分开口，使金属柱（2-7）顶端薄膜层露出开口II（2-8）；
    步骤九、在露出薄膜层开口II（2-8）的金属柱（2-7）表面镀上金属层（2-9）；
    步骤十、通过印刷或者植球的方式在所述金属层（2-9）上形成BGA焊球（2-10），最后将形成BGA焊球的重构晶圆切割成单颗BGA封装体。
  2. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：芯片本体（2-1）在倒装至载体圆片上时并不带有凸点。
  3. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：芯片电极（2-2）通过晶圆级再布线工艺的方式被引至封装体的周边。
  4. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：所述薄膜层（2-4）和（2-8）采用贴膜的方式粘连到圆片上。
  5. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：所述薄膜层（2-4）和（2-8）采用激光刻蚀的方式开口；
  6. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：所述金属柱（2-7）是通过光刻、溅射、电镀的方式形成。
  7. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：所述金属层（2-9）是通过化学镀的方式形成。
  8. 根据权利要求1所述的一种Low-k芯片封装方法，其特征在于：载体圆片与重构晶圆的玻璃可采用热剥离法或UV照射剥离法。
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