WO2013004041A1 - 一种适用于psva与阵列的测试电路 - Google Patents

一种适用于psva与阵列的测试电路 Download PDF

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WO2013004041A1
WO2013004041A1 PCT/CN2011/078957 CN2011078957W WO2013004041A1 WO 2013004041 A1 WO2013004041 A1 WO 2013004041A1 CN 2011078957 W CN2011078957 W CN 2011078957W WO 2013004041 A1 WO2013004041 A1 WO 2013004041A1
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pad
thin film
substrate
line signal
psva
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French (fr)
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陈政鸿
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

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  • the present invention relates to the field of LCD technology, and in particular, to a test circuit suitable for a PSVA and an array.
  • Adjacent data Line or adjacent gate line short-circuit with each other, so each chip (chip) will have corresponding G1, G2, ..., Gn and D1, D2, ..., Dm and several common communication numbers pad C1, C2, ..., Cx (collectively referred to as com) as an array
  • the test input plus the input point of the signal can also be used in the PSVA process, the traditional way is to G1, G2, ..., Gn and D1, D2, ..., Dm corresponding to each chip on the glass and several common communication numbers C1, C2.
  • the present invention is implemented as follows:
  • a test circuit suitable for a PSVA and an array comprising a gate line signal line, a data line signal line, a first pad, a second pad, and a thin film transistor, the gate line signal line and the data line signal line
  • the extension lines are respectively connected to the drains of the corresponding thin film transistors, the sources of the thin film transistors corresponding to the data line signal lines are connected to each other, and are connected to the first pads, and the thin film transistors corresponding to the data line signal lines
  • the gate is connected to the coating structure on the substrate; the source and the gate of the thin film transistor corresponding to the gate line signal line are connected to each other and connected to the coating structure on the substrate; the second pad is located The first pad is connected to the coating structure on the substrate, and the first pad and the second pad are independent of each other.
  • a common communication number line pad is further included, and the common communication number line pads are connected to each other and to the coating structure on the substrate.
  • the coating structure on the substrate is coated with a conductive material and is connected to the conductive layer of the upper substrate of the substrate.
  • the number of the gate line signal lines and the data line signal lines is at least one.
  • the invention also provides a test circuit suitable for a PSVA and an array, comprising a gate line signal line, a data line signal line, a first pad and a thin film transistor, the gate line signal line and the data line signal line
  • the extension lines are respectively connected to the drains of the corresponding thin film transistors, the sources of the thin film transistors corresponding to the data line signal lines are connected to each other, and are connected to the first pads, and the thin film transistors corresponding to the data line signal lines
  • the gate is connected to the coating structure on the substrate; the source and the gate of the thin film transistor corresponding to the gate line signal line are connected to each other and connected to the coating structure on the substrate.
  • a second pad is further included, the second pad being located on a side of the first pad and connected to the coating structure on the substrate.
  • a common communication number line pad is further included, and the common communication number line pads are connected to each other and to the coating structure on the substrate.
  • the common communication line pad is connected to the first pad.
  • the coating structure on the substrate is coated with a conductive material and is connected to the conductive layer of the upper substrate of the substrate.
  • the number of the gate line signal lines and the data line signal lines is at least one.
  • the invention also provides a test circuit suitable for a PSVA and an array, comprising a gate line signal line, a data line signal line, a first pad and a thin film transistor, the gate line signal line and the data line signal line
  • the extension lines are respectively connected to the drains of the corresponding thin film transistors, and the gates of the corresponding thin film transistors of the gate line signal line and the data line signal line are respectively connected to the coating structure on the substrate, the data line
  • the sources of the thin film transistors corresponding to the signal lines are connected to each other and connected to the first pads; the sources of the thin film transistors corresponding to the gate line signal lines are connected to each other and connected to the first pads.
  • the second pad and the common communication number line pad are further connected to the coating structure on the substrate, and the common communication number line pads are connected to each other, and Connect to the coated structure on the substrate.
  • the coating structure on the substrate is coated with a conductive material and is connected to the conductive layer of the upper substrate of the substrate.
  • the number of the gate line signal lines and the data line signal lines is at least one.
  • the technical solution provided by the present invention connects the extension lines of the gate lines and the data line signal lines to the drains of the corresponding thin film transistors, and the data line signal lines correspond to
  • the source of the thin film transistor is connected to each other and extends to the first pad.
  • the gate of the thin film transistor is connected to the coating structure on the substrate, and the source and the gate of the thin film transistor corresponding to the gate line signal line are connected to each other and connected together.
  • the coating structure on the substrate the coating structure on the substrate is coated with a conductive material to be connected with the conductive layer of the upper plate, which effectively reduces the number of glass edge pads and simplifies the complexity of the overall circuit.
  • the technical solution provided by the present invention connects the extension lines of the gate lines and the data line signal lines to the drains of the corresponding thin film transistors, and the data line signal lines correspond to
  • the source of the thin film transistor is connected to each other and extends to the first pad.
  • the gate of the thin film transistor is connected to the coating structure on the substrate, and the source and the gate of the thin film transistor corresponding to the gate line signal line are connected to each other and connected together.
  • the coating structure on the substrate the coating structure on the substrate is coated with a conductive material to be connected with the conductive layer of the upper plate, which effectively reduces the number of glass edge pads and simplifies the complexity of the overall circuit.
  • FIG. 1 is a schematic structural view of a prior art test circuit suitable for a PSVA and an array
  • FIG. 2 is a schematic structural view of a test circuit suitable for a PSVA and an array according to a first preferred embodiment of the present invention
  • FIG. 3 is a schematic structural view of a test circuit suitable for a PSVA and an array according to a second preferred embodiment of the present invention
  • FIG. 4 is a schematic structural view of a test circuit suitable for a PSVA and an array according to a third preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a test circuit suitable for a PSVA and an array according to a first preferred embodiment of the present invention.
  • each of the gate lines G1, G2, ..., Gn and the data line The extension lines of the D1, D2, ..., Dm signal lines are connected to the drains of the corresponding thin film transistors, and the sources of the thin film transistors corresponding to the data lines D1, D2, ..., Dm are connected to each other.
  • the gate of the thin film transistor is connected to a coating structure on the substrate; the source and the gate of the thin film transistor corresponding to the gate lines G1, G2, ..., Gn are connected to each other And the coating structure attached to the substrate together, the second pad (Pad2) of the glass edge is directly connected to the coating structure on the substrate; the common communication line pad pad C1, C2, ..., Cx (collectively referred to as com) are attached to each other and are attached to a coating structure on a substrate; wherein the coating is coated with a conductive substance to connect to the upper plate during the cell-to-group process Conductive layer.
  • the gates (gates) of all TFTs are floating. Potential (suspended potential), TFT off, high impedance between source (Source) and drain, all gate lines G1, G2, ..., Gn and data lines D1, D2, ..., Dm
  • the corresponding Pad is equivalent to being in an independent state, so different Pads can apply different signals to detect the array.
  • the conductive material in the transfer conducts the conductive layer of the upper plate, all the lines connected to the transfer are equivalent to the signals added by Pad2, and the Pad2 is applied higher than the Pad1 in the PSVA process.
  • the signal of the potential which causes all the transfer and the conductive layer of the opposite side glass to be high, and the gate of the thin film transistor is high, so the resistance between the source and the drain is lowered. It can be regarded as the conduction state, and the signal applied by the source of the transistor can enter all the G1, G2, ..., Gn and D1, D2, ..., Dm lines, and smoothly supply the picture curing.
  • FIG. 3 is a schematic structural diagram of a test circuit suitable for a PSVA and an array according to a second preferred embodiment of the present invention.
  • each of the gate lines G1, G2, . . . , Gn and the data line The extension lines of the D1, D2, ..., Dm signal lines are connected to the drains of the respective thin film transistors,
  • the gates of the gate lines G1, G2, ..., Gn and the data lines D1, D2, ..., Dm signal lines of the corresponding thin film transistors are respectively connected to the coating structure (Transfer) on the substrate, the data lines D1, D2, ...
  • the source of the thin film transistor corresponding to Dm is connected to each other and extended to the first pad of the glass edge through a signal line (Pad1); the source of the thin film transistor corresponding to the gate lines G1, G2, ..., Gn is connected to each other, and the source of the thin film transistor corresponding to D1, D2, ..., Dm is connected to the first pad through a signal line
  • the signal line is connected and extends to the first pad on the edge of the glass (Pad1), the second pad (Pad2) of the glass edge is directly connected to the coating structure on the substrate;
  • the common communication line pad pad a coating structure in which C1, C2, ..., Cx are connected to each other and connected together on a substrate; wherein a transfer structure is coated with a conductive substance to connect to a conductive layer of the upper plate during the cell-to-group process .
  • FIG. 4 is a schematic structural diagram of a test circuit suitable for a PSVA and an array according to a third preferred embodiment of the present invention.
  • each of the gate lines G1, G2, ..., Gn and the data line The extension lines of the D1, D2, ..., Dm signal lines are connected to the drains of the corresponding thin film transistors, and the sources of the thin film transistors corresponding to the data lines D1, D2, ..., Dm are connected to each other.
  • the gate of the thin film transistor is connected to the coating structure on the substrate; the source and the gate of the thin film transistor corresponding to the gate lines G1, G2, ..., Gn are mutually a coating structure that is connected and connected together on the substrate, a second pad (Pad2) of the glass edge is directly connected to the coating structure on the substrate; a common communication line pad pad C1, C2, ..., Cx (collectively referred to as Cx) are connected to the signal line of the first pad through a signal line and the source of the thin film transistor corresponding to D1, D2, ..., Dm and extend to the first pad of the glass edge (Pad1); wherein the transfer structure is coated with a conductive substance to connect to the conductive layer of the upper plate during the cell-to-group process.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及LCD技术领域，尤其涉及一种适用于PSVA与阵列的测试电路。本发明适用于PSVA与阵列的测试电路，包括栅极线讯号线路、数据线讯号线路、第一焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连，所述数据线讯号线路所对应的薄膜晶体管的栅极连接至基板上的涂布结构；所述栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接，并连接至基板上的涂布结构。相较于现有的适用于PSVA与阵列的测试电路，本发明提供的技术方案能有效的减少玻璃边缘焊盘的数目，简化整体线路的复杂度。

Description

一种适用于PSVA与阵列的测试电路 技术领域
本发明涉及LCD技术领域，尤其涉及一种适用于PSVA与阵列的测试电路。
 背景技术
目前的PSVA（ Polymer Stabilized Vertical Alignment, 聚合物稳定型垂直配向技术）制程中，为了在array（阵列）段制程之中进行电路测试，一般会使用所谓的shorting bar（短路棒）将所有的gate line（栅极线）与data line（数据线）并联成G1、G2、…、Gn以及D1、D2、…、Dm讯号，具体如图1所示，其中n与m值的设计必须要大于等于2，在测试之时才能拦截相邻data line或是相邻gate line互相短路的状况，所以每个chip（芯片）会有相对应的G1、G2、…、Gn及D1、D2、…、Dm与数个共通讯号pad C1、C2、…、Cx（统称为com）以作为阵列 test时外加讯号之输入点。为了使这些线路也能够在PSVA制程中加电压使用，传统的方式是把玻璃上每个chip所对应的G1、G2、…、Gn以及D1、D2、…、Dm与数个共通讯号C1、C2、…、Cx皆连接至玻璃边上的Pad（焊盘），后续cell（晶元）段PSVA制程前会移除对向侧的边缘部分玻璃，使这些Pad裸露而得以顺利加上电压。但若是整片玻璃的chip数目较多，就会导致玻璃边缘的pad数目太多，将会增加PSVA 制程加电压probe（探针）的数目以及整体周边线路的复杂度。
故，有必要提供一种更加优化的适用于PSVA与阵列的测试电路，以解决上述问题。
 技术问题
本发明的目的在于提供一种适用于PSVA与阵列的测试电路，以解决现有阵列测试电路中probe的数目太多以及整体周边线路复杂的问题。
 技术解决方案
本发明是这样实现的：
一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路、数据线讯号线路、第一焊盘、第二焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连，所述数据线讯号线路所对应的薄膜晶体管的栅极连接至基板上的涂布结构；所述栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接，并连接至基板上的涂布结构；所述第二焊盘位于第一焊盘一侧，且与基板上的涂布结构连接，所述第一焊盘与第二焊盘相互独立。
在本发明的一较佳实施例中，还包括共通讯号线焊盘，所述共通讯号线焊盘彼此连接，并与基板上的涂布结构相连。
在本发明的一较佳实施例中，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
在本发明的一较佳实施例中，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
本发明还提供了一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路、数据线讯号线路、第一焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连，所述数据线讯号线路所对应的薄膜晶体管的栅极连接至基板上的涂布结构；所述栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接，并连接至基板上的涂布结构。
在本发明的一较佳实施例中，还包括第二焊盘，所述第二焊盘位于第一焊盘一侧，且与基板上的涂布结构连接。
在本发明的一较佳实施例中，还包括共通讯号线焊盘，所述共通讯号线焊盘彼此连接，并与基板上的涂布结构相连。
在本发明的一较佳实施例中，所述共通讯号线焊盘与第一焊盘相连。
在本发明的一较佳实施例中，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
在本发明的一较佳实施例中，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
本发明还提供了一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路、数据线讯号线路、第一焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述栅极线讯号线路及所述数据线讯号线路各自对应的薄膜晶体管的栅极分别连接至基板上的涂布结构，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连；所述栅极线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连。
在本发明的一较佳实施例中，还包括第二焊盘和共通讯号线焊盘，所述第二焊盘与基板上的涂布结构相连，所述共通讯号线焊盘彼此连接，并接至基板上的涂布结构。
在本发明的一较佳实施例中，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
在本发明的一较佳实施例中，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
相较于现有的适用于PSVA与阵列的测试电路，本发明提供的技术方案，将栅极线和数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，数据线讯号线路对应的薄膜晶体管的源极彼此连接并延伸连接第一焊盘，薄膜晶体管的栅极连接基板上的涂布结构，栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接并一起连接在基板上的涂布结构，基板上的涂布结构涂有导电物质使其与上板的导电层连接，有效的减少玻璃边缘焊盘的数目，简化整体线路的复杂度。
 有益效果
相较于现有的适用于PSVA与阵列的测试电路，本发明提供的技术方案，将栅极线和数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，数据线讯号线路对应的薄膜晶体管的源极彼此连接并延伸连接第一焊盘，薄膜晶体管的栅极连接基板上的涂布结构，栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接并一起连接在基板上的涂布结构，基板上的涂布结构涂有导电物质使其与上板的导电层连接，有效的减少玻璃边缘焊盘的数目，简化整体线路的复杂度。
 附图说明
图1为现有技术的适用于PSVA与阵列的测试电路的结构示意图；
图2为本发明的第一较佳实施例的适用于PSVA与阵列的测试电路的结构示意图；
图3为本发明的第二较佳实施例的适用于PSVA与阵列的测试电路的结构示意图；
图4为本发明的第三较佳实施例的适用于PSVA与阵列的测试电路的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图2所示，为本发明提供的第一较佳实施例的适用于PSVA与阵列的测试电路的结构示意图，在图2中，每个栅极线G1、G2、…、Gn以及数据线D1、D2、…、Dm讯号线路的延伸线连接到各自所对应的薄膜晶体管之漏极(drain)，数据线D1、D2、…、Dm所对应的薄膜晶体管的源极(Source)彼此连接在一起，并通过一条讯号线延伸至玻璃边缘的第一焊盘 (Pad1)，薄膜晶体管的栅极连接至基板上的涂布结构（Transfer）；栅极线G1、G2、…、Gn所对应的薄膜晶体管的源极(Source)与栅极(Gate)彼此连接并一起连接在基板上的涂布结构，玻璃边缘的第二焊盘(Pad2)直接连接在基板上的涂布结构；共通讯号线焊盘Pad C1、C2、…、Cx（统称为com）彼此连接并一起连接在基板上的涂布结构；其中，涂布结构（Transfer）在cell对组制程时涂上导电的物质使其连接至上板的导电层。
因此在阵列测试时，由于不具有对向侧玻璃，所有TFT之闸极（栅极）为floating 电位（悬浮电位），TFT关闭，源极(Source)与漏极(drain)间存在高阻抗，所有的栅极线G1、G2、…、Gn以及数据线D1、D2、…、Dm 对应的Pad等同于处于独立状态，因此不同的Pad可施加不同的讯号以检测阵列。在Cell 上下玻璃对组的制程中，由于transfer中的导电物质导通上板的导电层，因此所有连接至transfer的线路皆相当于Pad2所加之讯号，于PSVA制程时Pad2相较于Pad1会施加较高电位的讯号，这样一来会导致所有transfer与对向侧玻璃的导电层为高电位，薄膜晶体管之闸极皆为高电位，因此源极(Source)与漏极(drain)间的阻值降低可视为导通状态，电晶体之源极(Source)所施加的讯号便可进入所有的G1、G2、…、Gn以及D1、D2、…、Dm线路，顺利供给画素固化（curing）时所需的电位。
如图3所示，为本发明提供的第二较佳实施例的适用于PSVA与阵列的测试电路的结构示意图，在图3中，每个栅极线G1、G2、…、Gn以及数据线D1、D2、…、Dm讯号线路的延伸线连接到各自所对应的薄膜晶体管之漏极(drain)， 栅极线G1、G2、…、Gn以及数据线D1、D2、…、Dm讯号线路各自对应的薄膜晶体管的栅极分别连接至基板上的涂布结构（Transfer），数据线D1、D2、…、Dm所对应的薄膜晶体管的源极(Source)彼此连接在一起，并通过一条讯号线延伸至玻璃边缘的第一焊盘 (Pad1)；栅极线G1、G2、…、Gn所对应的薄膜晶体管的源极彼此连接，并通过一条讯号线与D1、D2、…、Dm对应的薄膜晶体管源极连接第一焊盘的讯号线连接并延伸至玻璃边缘的第一焊盘 (Pad1)，玻璃边缘的第二焊盘(Pad2)直接连接至基板上的涂布结构；共通讯号线焊盘Pad C1、C2、…、Cx彼此连接并一起连接在基板上的涂布结构（Transfer）；其中，涂布结构（Transfer）在cell对组制程时涂上导电的物质使其连接至上板的导电层。
如图4所示，为本发明提供的第三较佳实施例的适用于PSVA与阵列的测试电路的结构示意图，在图4中，每个栅极线G1、G2、…、Gn以及数据线D1、D2、…、Dm讯号线路的延伸线连接到各自所对应的薄膜晶体管之漏极(drain)，数据线D1、D2、…、Dm所对应的薄膜晶体管的源极(Source)彼此连接在一起，并通过一条讯号线延伸至玻璃边缘的第一焊盘 (Pad1)，薄膜晶体管的栅极皆连接至基板上的涂布结构（Transfer）；栅极线G1、G2、…、Gn所对应的薄膜晶体管的源极(Source)与栅极(Gate)彼此连接并一起连接在基板上的涂布结构（Transfer），玻璃边缘的第二焊盘(Pad2)直接连接至基板上的涂布结构；共通讯号线焊盘Pad C1、C2、…、Cx（统称为Cx）通过一条讯号线与D1、D2、…、Dm对应的薄膜晶体管源极连接第一焊盘的讯号线连接并延伸至玻璃边缘的第一焊盘 (Pad1)；其中，涂布结构（Transfer）在cell对组制程时涂上导电的物质使其连接至上板的导电层。
综上所述，虽然本发明已以较佳实施例揭露如上，但上述较佳实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
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Claims (14)

  1. 一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路和数据线讯号线路，其特征在于，还包括第一焊盘、第二焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连，所述数据线讯号线路所对应的薄膜晶体管的栅极连接至基板上的涂布结构；所述栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接，并连接至基板上的涂布结构；所述第二焊盘位于第一焊盘一侧，且与基板上的涂布结构连接，所述第一焊盘与第二焊盘相互独立。
  2. 根据权利要求1所述的适用于PSVA与阵列的测试电路，其特征在于，还包括共通讯号线焊盘，所述共通讯号线焊盘彼此连接，并与基板上的涂布结构相连。
  3. 根据权利要求1或2所述的适用于PSVA与阵列的测试电路，其特征在于，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
  4. 根据权利要求1或2所述的适用于PSVA与阵列的测试电路，其特征在于，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
  5. 一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路和数据线讯号线路，其特征在于，还包括第一焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连，所述数据线讯号线路所对应的薄膜晶体管的栅极连接至基板上的涂布结构；所述栅极线讯号线路所对应的薄膜晶体管的源极与栅极彼此连接，并连接至基板上的涂布结构。
  6. 根据权利要求5所述的适用于PSVA与阵列的测试电路，其特征在于，还包括第二焊盘，所述第二焊盘位于第一焊盘一侧，且与基板上的涂布结构连接。
  7. 根据权利要求5或6所述的适用于PSVA与阵列的测试电路，其特征在于，还包括共通讯号线焊盘，所述共通讯号线焊盘彼此连接，并与基板上的涂布结构相连。
  8. 根据权利要求5或6所述的适用于PSVA与阵列的测试电路，其特征在于，所述共通讯号线焊盘与第一焊盘相连。
  9. 根据权利要求5或6所述的适用于PSVA与阵列的测试电路，其特征在于，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
  10. 根据权利要求5所述的适用于PSVA与阵列的测试电路，其特征在于，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
  11. 一种适用于PSVA与阵列的测试电路，包括栅极线讯号线路和数据线讯号线路，其特征在于，还包括第一焊盘和薄膜晶体管，所述栅极线讯号线路和所述数据线讯号线路的延伸线分别连接各自对应的薄膜晶体管的漏极，所述栅极线讯号线路及所述数据线讯号线路各自对应的薄膜晶体管的栅极分别连接至基板上的涂布结构，所述数据线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连；所述栅极线讯号线路所对应的薄膜晶体管的源极彼此连接，并与第一焊盘相连。
  12. 根据权利要求11所述的适用于PSVA与阵列的测试电路，其特征在于，还包括第二焊盘和共通讯号线焊盘，所述第二焊盘与基板上的涂布结构相连，所述共通讯号线焊盘彼此连接，并接至基板上的涂布结构。
  13. 根据权利要求11或12所述的适用于PSVA与阵列的测试电路，其特征在于，所述基板上的涂布结构涂有导电物质，并与基板上板的导电层连接。
  14. 根据权利要求11或12所述的适用于PSVA与阵列的测试电路，其特征在于，所述栅极线讯号线路与数据线讯号线路的数量至少为一个。
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