WO2012142781A1 - 隧穿电流放大晶体管 - Google Patents

隧穿电流放大晶体管 Download PDF

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Publication number
WO2012142781A1
WO2012142781A1 PCT/CN2011/074686 CN2011074686W WO2012142781A1 WO 2012142781 A1 WO2012142781 A1 WO 2012142781A1 CN 2011074686 W CN2011074686 W CN 2011074686W WO 2012142781 A1 WO2012142781 A1 WO 2012142781A1
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Prior art keywords
tunneling
floating
base
emitter
amplifying transistor
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English (en)
French (fr)
Inventor
黄如
詹瞻
黄芊芊
王阳元
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Peking University
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Peking University
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Priority to US13/255,087 priority Critical patent/US8895980B2/en
Priority to DE112011103129T priority patent/DE112011103129T5/de
Publication of WO2012142781A1 publication Critical patent/WO2012142781A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species

Definitions

  • the invention belongs to the field of field effect transistor logic devices in CMOS Very Large Scale Integrated Circuit (ULSI), and particularly relates to a field effect transistor-tunneling current amplifying transistor which utilizes a PN junction to amplify a banded tunneling current.
  • ULSI Very Large Scale Integrated Circuit
  • the development of integrated circuits for more than 50 years can be described by the law of the summary of the moles, and the driving force for the future development of the integrated circuit industry and systems should be to reduce power consumption, that is, not to improve integration as a technology node, but to improve performance /
  • the power consumption ratio is the scale.
  • the traditional MOSFET is limited by the thermoelectric potential.
  • the theoretical threshold of the subthreshold slope is 60mV/dec, and as the device size decreases, the threshold voltage decreases, and the static leakage current of the device inevitably deteriorates, causing the static power consumption to increase. Can not meet the needs of future low-power design.
  • the TFET Timl ing FET
  • This carrier generation mechanism different from the MOSFET overcomes the subthreshold characteristic of the source carrier Fermi distribution, which can further reduce the subthreshold slope of the device and reduce the static leakage current of the device and thus reduce the static power consumption of the device.
  • the tunneling current amplifying transistor comprises a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein: the drain, the floating tunneling base and the control
  • the gate forms a conventional TFET structure with the emitter doping type opposite to the floating tunneling base.
  • Such an emitter can provide another carrier to amplify the current flowing through the base of the tunnel.
  • the emitter position is generally on the other side of the floating tunneling base with respect to the drain.
  • the type of semiconductor between the emitter and the floating tunneling base needs to be the same as the floating tunneling base. This can be achieved by selecting a suitable semiconductor substrate type or by well implantation. Not more than lel9cm- 3 .
  • the floating tunneling base is generally heavily doped to provide high tunneling efficiency, and the emitter is also heavily doped to provide high Current amplification capability.
  • the gate dielectric layer material is silicon dioxide or other insulating material.
  • the invention can be applied to silicon-based semiconductor materials as well as other semiconductor materials such as germanium, gallium arsenide, and indium phosphide. It is also possible to use other semiconductor materials in one piece of the device to form a heterojunction.
  • the tunneling current amplifying transistor of the present invention utilizes a PN junction to amplify a band-band tunneling current.
  • a PN junction to amplify a band-band tunneling current.
  • the gate voltage increases, the electric field between the floating tunneling base and the channel increases, and a strong field acts. Then, the electrons in the valence band of the floating tunneling begin to tunnel to the channel conduction band.
  • This tunneling process injects a hole current into the floating tunneling base while injecting an electron current into the channel.
  • the tunneling current is relatively small, the hole current injected into the floating tunneling base is recombined at the emitter, and the hole current is again converted into an electron current.
  • the tunneling current When the tunneling current is relatively large, the holes injected into the base of the floating tunnel will introduce a certain amplification of the electron current at the emitter.
  • the magnification is approximately equal to the ratio of the doping concentrations across the emitter junction.
  • the incoming electron current drifts to the drain and is collected by the drain, increasing the amount of conduction current.
  • the tunneling current When the gate voltage is reset to zero, the tunneling current is suppressed, so that the floating tunneling base injects the hole current to be cut off, and the device immediately enters the off state.
  • FIG. 1 is a schematic structural view of a tunneling current amplifying transistor according to the present invention.
  • 2a to 2f are main process steps for preparing a tunneling current amplifying transistor of the present invention, wherein:
  • Figure 2a shows the process of implanting and propelling the active region well
  • Figure 2b shows the process of emitter and drain implants
  • Figure 2c shows the lithography floating tunneling base implant window process
  • Figure 2d shows etching polysilicon and performing a floating tunneling base implant
  • Figure 2e shows the knot activation process
  • Fig. 2f is a schematic view showing the structure of a tunneling current amplifying transistor which is finally formed.
  • FIG. 2a The specific implementation steps are shown in Figure 2a to Figure 2f: 1. Grating a gate oxide layer (ie, a gate dielectric layer) on the semiconductor substrate 5, depositing a silicon nitride lithography active region, then performing a well implant, and then performing a well push to form a well 6, as shown in FIG. 2a.
  • the purpose of the well is to provide the semiconductor material required between the emitter and the floating tunneling base. If the semiconductor substrate itself meets the needs, then the process step of well implantation can be omitted).
  • a silicon dioxide layer is deposited on the entire film.
  • the contact hole is lithographically patterned, and then the metal is sputtered, and the emitter, drain, and gate contact electrodes are photolithographically patterned to form a tunneling current amplifying transistor, as shown in FIG. 2f.

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  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)

Description

隧穿电流放大晶体管 技术领域
本发明属于 CMOS超大规模集成电路 (ULSI)中场效应晶体管逻辑器件领域， 具体涉及一 种利用 PN结放大带带隧穿电流的场效应晶体管——隧穿电流放大晶体管。 背景技术 集成电路 50多年来的发展可以以摩尔总结的规律来描述， 而未来集成电路产业与系统发 展的驱动力应当是降低功耗， 即不以提高集成度为技术节点， 而以提高性能 /功耗比为标尺。 当集成电路的功耗成为不可忽视的问题的时候， 以低功耗设计为宗旨的绿色纳米器件便应运 而生。 传统 M0SFET, 因为受到热电势的限制， 亚阈值斜率理论极限是 60mV/dec， 而且随着器 件尺寸的降低， 阈值电压降低， 器件的静态漏泄电流不可避免地恶化， 引起静态功耗增加， 因此已经不能满足以后低功耗设计的需要。 TFET (Timnel ing FET)通过栅电极控制沟道能带 位置， 利用带带隧穿为 TFET提供导通电流。 这种不同于 M0SFET的载流子产生机制克服了源端 载流子费米分布对亚阈值特性的限制， 可以进一步降低器件亚阈值斜率， 降低器件静态漏泄 电流进而降低器件静态功耗。 但是由于存在隧穿势垒， 隧穿效率的低下始终是一个难以克服 的难题。 窄禁带半导体的应用虽然克服了隧穿电流大小的问题， 但是随之而来的漏泄电流， 以及新材料带来的成本的提高都是其大规模应用的屏障。
发明内容
本发明的目的在于提供一种隧穿电流放大晶体管， 该器件同时具备低漏泄电流、 陡直亚 阈斜率、 高导通电流等优点。 本发明提供的隧穿电流放大晶体管， 包括半导体衬底、 栅介质层、 发射极、 漏极、 浮空 隧穿基极以及控制栅， 其中： 所述漏极、 浮空隧穿基极和控制栅构成一个常规的 TFET结构， 而发射极的掺杂类型与浮空隧穿基极相反。 这样发射极可以提供另一种载流子来放大浮空隧 穿基极的电流。
所述发射极位置一般相对于漏极在浮空隧穿基极的另一侧。 一般来说发射极与浮空隧穿 基极之间的半导体类型需要与浮空隧穿基极相同， 这可以通过选择合适的半导体衬底类型， 也可以通过阱注入来实现， 掺杂浓度一般不超过 lel9cm— 3。
所述浮空隧穿基极一般采用重掺杂以提供高的隧穿效率， 发射极也采用重掺杂以提供高 的电流放大能力。
所述栅介质层材料为二氧化硅或其他绝缘材料。
本发明可以应用于硅基半导体材料， 也可以应用于其他半导体材料， 比如锗、 砷化镓、 磷化铟。 也可以在器件的某一块采用其他半导体材料来形成异质结。
本发明隧穿电流放大晶体管是利用 PN结放大带带隧穿电流， 以 N型器件为例， 随着栅 电压的增加， 浮空隧穿基极与沟道之间电场增加， 在强场作用下， 浮空隧穿基极价带中的电 子开始向沟道导带隧穿。 这种隧穿过程向浮空隧穿基极注入空穴电流， 同时向沟道注入电子 电流。 在隧穿电流比较小的时候， 向浮空隧穿基极注入的空穴电流在发射极被复合， 空穴电 流再次被转换成电子电流。 当隧穿电流比较大的时候， 浮空隧穿基极注入的空穴会在发射极 引入一定放大倍数的电子电流。 放大倍数大致等于发射结两端的掺杂浓度之比。 引入的电子 电流会漂移到漏极被漏极收集， 从而增加了导通电流大小。 当栅电压归零的时候， 隧穿电流 被抑制， 从而浮空隧穿基极注入空穴电流被截断， 器件立即进入关态。
与现有的 TFET相比， 本发明隧穿电流放大晶体管可以有效的提高器件导通电流， 提高器 件的驱动能力。 附图说明 图 1为本发明提出的隧穿电流放大晶体管结构示意图。
图 2a〜图 2f为制备本发明隧穿电流放大晶体管的主要工艺步骤， 其中：
图 2a显示了有源区阱注入并推进的工艺过程；
图 2b显示了发射极与漏极注入的工艺过程；
图 2c显示了光刻浮空隧穿基极注入窗口工艺过程；
图 2d显示了刻蚀多晶硅并且进行浮空隧穿基极注入；
图 2e显示了结激活过程；
图 2f为最终形成的隧穿电流放大晶体管结构示意图。
图中， 1——多晶硅栅； 2——栅氧化层； 3——浮空隧穿基极； 4——发射极； 5——半导 体衬底； 6——阱； 7——漏极； 8——二氧化硅层； 9——金属接触电极； 10——光刻胶。 具体实施方式
以下结合附图， 通过具体的实施例对本发明所述的隧穿电流放大晶体管的实施方法做进 一步的说明
具体实施步骤如图 2a〜图 2f 所示： 1， 在半导体衬底 5上生长栅氧化层 （即栅介质层） 2， 淀积氮化硅光刻有源区， 然后进 行阱注入， 接着进行阱推进， 形成阱 6， 如图 2a所示（阱的目的是提供发射极与浮空 隧穿基极之间所需要的半导体材料， 如果半导体衬底本身满足需要， 那么可以省略阱 注入这一工艺步骤） 。
2， 淀积多晶硅， 多晶硅注入， 然后光刻并刻蚀多晶硅， 形成发射极与漏注入窗口， 以 多晶硅栅 1为硬掩膜进行发射极 4与漏极 7的注入， 如图 2b所示。
3， 涂光刻胶 10， 然后光刻出浮空隧穿基极的注入窗口， 如图 2c所示。
4， 刻蚀多晶硅栅 1， 然后进行浮空隧穿基极 3注入， 如图 2d所示。
5， 去胶， 然后高温激活发射极 4、 漏极 7以及浮空隧穿基极 3掺杂的杂质， 如图 2e所 示。
6， 全片淀积二氧化硅层 8， 光刻接触孔， 然后溅射金属， 光刻出发射极、 漏极、 栅接 触电极 9， 最终形成隧穿电流放大晶体管， 如图 2f所示。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。 任何熟悉本领域的技 术人员， 在不脱离本发明技术方案范围情况下， 都可利用上述揭示的方法和技术内容对本发 明技术方案作出许多可能的变动和修饰， 或修改为等同变化的等效实施例。 因此， 凡是未脱 离本发明技术方案的内容， 依据本发明的技术实质对以上实施例所做的任何简单修改、 等同 变化及修饰， 均仍属于本发明技术方案保护的范围内。

Claims

权利 要求 书
1、一种隧穿电流放大晶体管， 其特征在于， 包括半导体衬底、栅介质层、发射极、漏极、 浮空隧穿基极和控制栅， 所述漏极、浮空隧穿基极和控制栅构成一个 TFET结构， 而发射极的 掺杂类型与浮空隧穿基极相反。
2、 如权利要求 1所述的隧穿电流放大晶体管， 其特征在于， 发射极的位置相对于漏极在 浮空隧穿基极的另一侧。
3、 如权利要求 2所述的隧穿电流放大晶体管， 其特征在于， 发射极与浮空隧穿基极之间 的半导体类型与浮空隧穿基极相同， 该发射极与浮空隧穿基极之间的半导体的掺杂浓度不高 于 lel9cm— 3。
4、 如权利要求 1所述的隧穿电流放大晶体管， 其特征在于， 该器件采用硅基、 锗基、 砷 化镓基或磷化铟基半导体材料实现。
5、如权利要求 1所述的隧穿电流放大晶体管，其特征在于，所述栅介质层采用二氧化硅。
PCT/CN2011/074686 2011-04-20 2011-05-26 隧穿电流放大晶体管 Ceased WO2012142781A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/255,087 US8895980B2 (en) 2011-04-20 2011-05-26 Tunneling current amplification transistor
DE112011103129T DE112011103129T5 (de) 2011-04-20 2011-05-26 Verstärkungstransistor vom Typ Tunnelstrom

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CN201110098730.6 2011-04-20
CN2011100987306A CN102208446B (zh) 2011-04-20 2011-04-20 隧穿电流放大晶体管

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CN103456636A (zh) * 2012-06-05 2013-12-18 上海华虹Nec电子有限公司 解决晶体管的IdVg曲线双峰现象的方法
CN103996713B (zh) * 2014-04-22 2017-02-15 北京大学 垂直沟道双机制导通纳米线隧穿晶体管及制备方法
CN104465737B (zh) * 2014-12-08 2017-07-21 沈阳工业大学 体硅双栅绝缘隧穿基极双极晶体管及其制造方法
CN104409490B (zh) * 2014-12-08 2017-10-20 沈阳工业大学 Soi衬底双栅绝缘隧穿基极双极晶体管及其制造方法
CN104485354B (zh) * 2014-12-08 2017-10-27 沈阳工业大学 Soi衬底折叠栅绝缘隧穿增强晶体管及其制造方法
CN104465775B (zh) * 2014-12-12 2018-01-05 西安邮电大学 基于陷阱产生机制的双漏区半导体器件其制造方法及应用
CN104485358B (zh) * 2014-12-12 2018-01-05 西安邮电大学 一种基于陷阱产生机制的半导体器件其制造方法及应用
CN104465776B (zh) * 2014-12-12 2017-09-15 西安邮电大学 一种双栅电极的半导体器件其制造方法及应用

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