WO2012137728A1 - 走査信号線駆動回路およびそれを備えた表示装置 - Google Patents
走査信号線駆動回路およびそれを備えた表示装置 Download PDFInfo
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- WO2012137728A1 WO2012137728A1 PCT/JP2012/058918 JP2012058918W WO2012137728A1 WO 2012137728 A1 WO2012137728 A1 WO 2012137728A1 JP 2012058918 W JP2012058918 W JP 2012058918W WO 2012137728 A1 WO2012137728 A1 WO 2012137728A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0224—Details of interlacing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
Definitions
- the present invention relates to a display device and a driving circuit thereof, and more particularly to a scanning signal line driving circuit (gate driver) for driving a scanning signal line disposed in a display unit of the display device.
- a scanning signal line driving circuit gate driver
- an active matrix type liquid crystal display device including a TFT (thin film transistor) as a switching element.
- This liquid crystal display device includes a liquid crystal panel composed of two insulating substrates facing each other. On one substrate of the liquid crystal panel, gate bus lines (scanning signal lines) and source bus lines (video signal lines) are provided in a lattice pattern, and TFTs are provided in the vicinity of the intersection between the gate bus lines and the source bus lines. It has been.
- the TFT includes a gate terminal connected to the gate bus line, a source terminal connected to the source bus line, and a drain terminal. The drain terminal is connected to pixel electrodes arranged in a matrix on the substrate in order to form an image.
- the other substrate of the liquid crystal panel is provided with a common electrode (also referred to as a “counter electrode”) for applying a voltage to the pixel electrode through the liquid crystal.
- a common electrode also referred to as a “counter electrode” for applying a voltage to the pixel electrode through the liquid crystal.
- the liquid crystal has a property of deteriorating when a DC voltage is continuously applied. For this reason, in the liquid crystal display device, an alternating voltage is applied to the liquid crystal.
- the application of such an AC voltage is caused by the polarity of the pixel voltage (the potential of the pixel electrode with reference to the potential of the common electrode) in each pixel forming portion (the region where one pixel that is the minimum unit constituting the image is formed) Is inverted every frame period.
- a driving system called line inversion driving and a driving system called dot inversion driving are known.
- the line inversion driving is a driving method in which the polarity of the pixel voltage is inverted every frame period and every gate bus line (every row).
- the polarity of the pixel voltage in two consecutive frame periods is, for example, as shown in FIG.
- the dot inversion drive inverts the polarity of the pixel voltage for each frame period and for each gate bus line, and further has the polarity between pixel forming portions adjacent in the horizontal (horizontal) direction within one frame period. This is a driving method to be reversed.
- the polarity of the pixel voltage in two consecutive frame periods is, for example, as shown in FIG. 12 and 13, (16 ⁇ 8) pixel forming portions provided corresponding to the intersections of the 16 gate bus lines GL1 to GL16 and the eight source bus lines SL1 to SL8. The polarity of the pixel voltage is shown.
- Japanese Laid-Open Patent Publication No. 11-352938 proposes a driving method for reducing power consumption for a display device employing line inversion driving or dot inversion driving.
- the gate bus line is divided into a plurality of blocks, and the plurality of blocks are sequentially selected one by one, and a plurality of gates included in each block are also selected. Interlaced scanning is performed on the bus line. For example, when eight gate bus lines GL1 to GL8 are divided into two blocks, as shown in FIG. 14, the gates are arranged in the order of “GL1, GL3, GL2, GL4, GL5, GL7, GL6, GL8”. A bus line is selected.
- FIG. 12 or FIG. 13 it is sufficient to invert the polarity of the video signal every two horizontal scanning periods instead of every one horizontal scanning period. As a result, power consumption is reduced.
- a driving method that satisfies the following (1) to (4) as in the driving method disclosed in Japanese Patent Laid-Open No. 11-352938 is referred to as “block inversion driving”.
- the gate bus line is divided into a plurality of blocks, the plurality of blocks are sequentially selected one by one.
- Interlaced scanning is performed on a plurality of gate bus lines included in each block.
- two vertical scans scan for selecting the odd-numbered row and scan for selecting the even-numbered row
- the polarity of the video signal applied to each source bus line is inverted between the first vertical scan and the second vertical scan.
- the polarity of the pixel voltage is inverted every frame period.
- Japanese Unexamined Patent Publication No. 2006-154810 discloses a scan driver (gate driver) invention that can selectively perform sequential scanning and interlaced scanning.
- Japanese Laid-Open Patent Publication No. 8-320674 discloses that a good image quality can be obtained by reversing the polarity of a display signal (video signal) supplied to a data line (source bus line) every predetermined period in addition to interlaced scanning. It is described that low power consumption can be achieved.
- an object of the present invention is to provide a monolithic gate driver capable of performing block inversion driving without causing deterioration in display quality or increase in power consumption.
- a first aspect of the present invention is a scanning signal line driving circuit that is monolithically formed on a substrate constituting a display panel and drives a plurality of scanning signal lines disposed on the substrate, A plurality of odd line scanning circuits for driving the odd numbered scanning signal lines of the plurality of scanning signal lines; A plurality of even line scanning circuits for driving even numbered scanning signal lines of the plurality of scanning signal lines; A selection circuit that selects a circuit to be activated from the plurality of odd line scanning circuits and the plurality of even line scanning circuits; The plurality of scanning signal lines are divided into z (z is an integer of 2 or more) blocks so that k continuous (k is an integer of 4 or more) scanning signal lines are included in each block.
- the odd line scanning circuit and the even line scanning circuit are provided for each block,
- the selection circuit sequentially selects the odd-numbered line scanning circuit and the even-numbered line scanning circuit while sequentially selecting the first to zth blocks one by one,
- Each odd line scanning circuit selectively drives the odd-numbered scanning signal lines included in the corresponding block sequentially,
- Each even-line scanning circuit selectively drives the even-numbered scanning signal lines included in the corresponding block sequentially.
- the selection circuit, the odd line scanning circuit, and the even line scanning circuit output a plurality of status signals indicating either the first state or the second state based on a clock signal input from the outside.
- Each stage constituting the shift register is An output node for outputting the state signal;
- a switching element for output control wherein the clock signal is applied to a second electrode, and a third electrode is connected to the output node;
- a first node connected to the first electrode of the output control switching element;
- a capacitive element provided between the output node and the first node;
- a first node charging unit for charging the first node based on a start instruction signal or a state signal output from a preceding output node;
- a first node discharging unit for discharging the first node based on a state signal output from an output node of the next stage;
- an output node discharge unit for discharging the output node based on a state signal output from the output node of the next stage.
- the output control is performed after the first node is charged by the first node charging unit and before the first node is discharged by the first node discharging unit.
- the clock signal applied to the second electrode of the switching element for use changes from a low level to a high level.
- a state signal output from the odd-numbered stage of the shift register constituting the selection circuit is given to the first stage of the shift register constituting the odd-line scanning circuit as the start instruction signal.
- a state signal output from the even-numbered stage of the shift register constituting the selection circuit is given as the start instruction signal to the first stage of the shift register constituting the even-line scanning circuit,
- a state signal output from each stage of the shift register constituting the odd line scanning circuit is given as a scanning signal to the odd number scanning signal lines of the plurality of scanning signal lines.
- the even numbered scanning signal line among the plurality of scanning signal lines is supplied with a status signal output from each stage of the shift register constituting the even line scanning circuit as a scanning signal.
- the selection circuit, the odd line scanning circuit, and the even line scanning circuit output a plurality of status signals indicating either the first state or the second state based on a clock signal input from the outside.
- the first stage of the shift register that constitutes the odd line scanning circuit is provided with a status signal output from the odd stage of the shift register that constitutes the selection circuit as a start instruction signal
- a state signal output from the even-numbered stage of the shift register constituting the selection circuit is given as the start instruction signal to the first stage of the shift register constituting the even-line scanning circuit
- a state signal output from each stage of the shift register constituting the odd line scanning circuit is given as a scanning signal to the odd number scanning signal lines of the plurality of scanning signal lines.
- the even numbered scanning signal line among the plurality of scanning signal lines is supplied with a status signal output from each stage of the shift register constituting the even line scanning circuit as a scanning signal.
- the first node charging unit includes a first switching element in which a state signal output from a previous output node is applied to a first electrode and a second electrode, and a third electrode is connected to the first node; In the first node discharge unit, a state signal output from the output node of the next stage is applied to the first electrode, the second electrode is connected to the first node, and a low level potential is applied to the third electrode.
- a second switching element is included.
- a state signal output from a previous output node is applied to the first electrode, a second electrode is connected to the output node, and a low level potential is applied to the third electrode.
- a switching element is included.
- a clear signal input from the outside is applied to the first electrode, a second electrode is connected to the output node, and a low level potential is applied to the third electrode. It further has a switching element.
- a clear signal input from the outside is applied to the first electrode, a second electrode is connected to the first node, and a low level potential is applied to the third electrode.
- the switching element is further provided.
- the switching element included in each stage constituting the shift register is a thin film transistor made of amorphous silicon.
- the switching element included in each stage constituting the shift register is a thin film transistor made of an N-type oxide semiconductor containing indium, gallium, zinc, and oxygen as main components.
- the selection circuit, the odd line scanning circuit, and the even line scanning circuit output a plurality of status signals indicating either the first state or the second state based on a clock signal input from the outside.
- Each stage constituting the shift register includes a master flip-flop that captures input data based on the clock signal, and a slave flip-flop that outputs data captured by the master flip-flop as the status signal based on the clock signal;
- a master-slave flip-flop realized using a CMOS logic circuit The first stage of the shift register constituting the odd line scanning circuit is given as the input data the status signal output from the odd stage of the shift register constituting the selection circuit, A state signal output from the previous stage is given as the input data to each stage after the second stage of the shift register constituting the odd line scanning circuit,
- a status signal output from the even stage of the shift register constituting the selection circuit is given as the input data,
- a state signal output from the previous stage is given as the input data to each stage after the second stage of the shift register constituting the even line scanning circuit,
- a state signal output from each stage of the shift register constituting the odd line scanning circuit is given as a scanning
- a thirteenth aspect of the present invention is the twelfth aspect of the present invention, A thin film transistor made of polycrystalline silicon is used for a CMOS logic circuit included in each stage constituting the shift register.
- a fourteenth aspect of the present invention is a display device, A scanning signal line driving circuit according to any one of the first to thirteenth aspects of the present invention; A video signal line driving circuit for driving a plurality of video signal lines disposed on the substrate, When the video signal line driving circuit focuses on the video signal applied to each video signal line, the polarity of the video signal and the even line scanning when the odd line scanning circuit is selected by the selection circuit The polarity of the video signal when the circuit is selected by the selection circuit is different from that of the video signal.
- a fifteenth aspect of the present invention is the fourteenth aspect of the present invention.
- the video signal line driving circuit is characterized in that the polarities of video signals applied to two adjacent video signal lines are different from each other.
- the plurality of scanning signal lines are divided into z blocks so that four or more gate bus lines continuous to one block are included. Since the selection circuit alternately selects the odd line scanning circuit and the even line scanning circuit, the odd-numbered scanning signal lines are sequentially selected one by one in the first vertical scanning for each block, and then 2 The even-numbered scanning signal lines are sequentially selected one by one in the vertical scanning of the first time.
- block inversion is performed by inverting the polarity of each video signal during the first vertical scanning and during the second vertical scanning, and by inverting the polarity of each video signal every frame period. Driving is realized.
- the block inversion driving can be performed in the monolithic scanning signal line driving circuit without causing deterioration in display quality and increase in power consumption.
- block inversion driving is performed in a monolithic scanning signal line drive circuit including a shift register using bootstrap without causing deterioration in display quality or increase in power consumption. It becomes possible.
- the first node is bootstrapped at a suitable timing in each stage of the shift register.
- the same effect as that of the second or third aspect of the present invention can be obtained without complicating the circuit configuration in the scanning signal line driving circuit.
- the same effect as in the first aspect of the present invention can be obtained without complicating the circuit configuration in the scanning signal line driving circuit.
- the same effect as in the second aspect of the present invention can be obtained without complicating the circuit configuration of the shift register.
- the same effect as in the second aspect of the present invention can be obtained without complicating the circuit configuration of the shift register.
- the potential of the output node is set to the low level (initial state) based on the clear signal. For this reason, the occurrence of malfunction is suppressed by setting the clear signal to the ON level at an appropriate timing.
- the potential of the first node is set to a low level (initial state) based on the clear signal. For this reason, the occurrence of malfunction is suppressed by setting the clear signal to the ON level at an appropriate timing.
- a monolithic scanning signal line driving circuit for a display device for example, a large liquid crystal panel
- a display device for example, a large liquid crystal panel
- an amorphous silicon TFT as a driving element
- a monolithic scanning signal line drive circuit for a display device that employs an IGZO-TFT as a drive element block inversion is performed without causing deterioration in display quality or increase in power consumption. It becomes possible to drive. Further, since the mobility of IGZO is high, it is possible to improve the driving capability of the scanning signal line driving circuit and narrow the frame by reducing the TFT size. Furthermore, since load capacity is reduced, power consumption is significantly reduced. Furthermore, since the IGZO-TFT has less leakage, for example, in a circuit using a bootstrap, it is possible to suppress the occurrence of malfunction due to the leakage of the charge of the floating node and to increase the operation margin. Become.
- a monolithic scanning signal line drive circuit including a shift register using a master-slave type flip-flop
- block inversion is performed without causing deterioration in display quality or increase in power consumption. It becomes possible to drive. Further, since the shift register is configured using a CMOS logic circuit, power consumption is effectively reduced.
- the block without causing deterioration in display quality and increase in power consumption is achieved. Inversion driving can be performed.
- a display device including a monolithic scanning signal line driving circuit capable of performing block inversion driving without causing deterioration in display quality or increase in power consumption is realized. .
- the pixel voltages have different polarities (inverted states) between pixels adjacent in the horizontal (horizontal) direction and between pixels adjacent in the vertical (vertical) direction. As a result, higher quality display can be performed.
- FIG. 3 is a block diagram showing a detailed configuration of a gate driver in the liquid crystal display device according to one embodiment of the present invention.
- it is a block diagram which shows the whole structure of a liquid crystal display device.
- it is a block diagram which shows schematic structure of a gate driver.
- FIG. 5 is a diagram for describing input / output signals of an n-th stage configuration circuit of each shift register included in an odd line scanning circuit and an even line scanning circuit in the embodiment.
- it is a circuit diagram which shows the structure (structure for one stage of a shift register) of a stage structure circuit.
- it is a signal waveform diagram for demonstrating operation
- FIG. 11 is a circuit diagram showing a configuration of a stage constituent circuit (a configuration for one stage of a shift register) in a second modification of the embodiment.
- FIG. 10 is a circuit diagram showing a configuration for generating clock signals clk and clkb from a clock signal CK in the second modification of the embodiment. It is a figure which shows the polarity of the pixel voltage in the continuous 2 frame period when line inversion drive is employ
- the gate terminal (gate electrode) of the thin film transistor corresponds to the first electrode
- the drain terminal (drain electrode) corresponds to the second electrode
- the source terminal (source electrode) corresponds to the third electrode.
- FIG. 2 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention.
- the liquid crystal display device includes a display unit 100, a display control circuit 200, a source driver (video signal line drive circuit) 300, and a gate driver (scanning signal line drive circuit) 400.
- the display unit 100 includes a plurality (j) of source bus lines (video signal lines) SL1 to SLj, a plurality (i) of gate bus lines (scanning signal lines) GL1 to GLi, and a source bus line SL1.
- a plurality of (i ⁇ j) pixel forming portions provided corresponding to the intersections of .about.SLj and the gate bus lines GL1 to GLi are formed.
- the plurality of pixel forming portions are arranged in a matrix to form a pixel array.
- Each pixel forming portion includes a thin film transistor (TFT) 11 which is a switching element having a gate terminal connected to a gate bus line passing through a corresponding intersection and a source terminal connected to a source bus line passing through the intersection.
- TFT thin film transistor
- the liquid crystal layer is sandwiched between the electrode and the common electrode Ec.
- a pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec.
- an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to hold the electric charge in the pixel capacitor Cp with certainty.
- the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
- the display control circuit 200 receives a data signal DAT and a timing control signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG sent from the outside, and controls the digital video signal DV and the operation of the source driver 300.
- a control signal SCTL and a gate control signal GCTL for controlling the operation of the gate driver 400 are output.
- the source control signal SCTL and the gate control signal GCTL are composed of a plurality of signals.
- the source control signal SCTL includes, for example, a start pulse signal and a clock signal for controlling the operation of the shift register in the source driver 300. A detailed description of the gate control signal GCTL will be given later.
- the source driver 300 receives the digital video signal DV and the source control signal SCTL output from the display control circuit 200, and applies driving video signals to the source bus lines SL1 to SLj.
- the gate driver 400 Based on the gate control signal GCTL output from the display control circuit 200, the gate driver 400 applies an active scan signal (output of a scan pulse) to each of the gate bus lines GL1 to GLi with one vertical scan period as a cycle. repeat. A detailed description of the gate driver 400 will be given later.
- the gate driver 400 is formed on one of the two substrates (glass substrates) constituting the liquid crystal panel including the display unit 100. That is, the gate driver 400 in this embodiment is a monolithic gate driver.
- an amorphous silicon TFT is employed as a drive element.
- the driving video signals are applied to the source bus lines SL1 to SLj, and the scanning signals are applied to the gate bus lines GL1 to GLi, so that they are based on the image signal DAT sent from the outside.
- An image is displayed on the display unit 100.
- FIG. 3 is a block diagram showing a schematic configuration of the gate driver 400 in the present embodiment.
- the gate bus lines GL1 to GLi are divided into a plurality of blocks (groups) such that k continuous (k is an integer of 4 or more) gate bus lines are included in one block.
- k is an integer of 4 or more
- the gate driver 400 is provided with an odd line scanning circuit 42 for driving odd-numbered gate bus lines and an even-number line scanning circuit 44 for driving even-numbered gate bus lines for each block. It has been.
- the gate driver 400 also has a block scanning circuit (selection circuit) 40 composed of a plurality of stages of shift registers for sequentially selecting the odd line scanning circuit 42 and the even line scanning circuit 44. Is provided. Note that each stage of the shift register is indicated by a symbol SR (the same applies to FIG. 1). In the following, the stage corresponding to the odd line scanning circuit 42 is referred to as “odd line driving stage”, and the stage corresponding to the even line scanning circuit 44 is referred to as “even line driving”. It is called “stage”.
- the blocks from the first block BLK1 to the z-th block BLKz are sequentially selected one by one. Focusing on each block, first, the odd-numbered gate bus lines are sequentially scanned one by one by the odd-line scanning circuit 42, and then the even-numbered gate bus lines are scanned by the even-numbered line scanning circuit 44. One by one is scanned sequentially.
- FIG. 1 is a block diagram showing a detailed configuration of the gate driver 400 in the present embodiment.
- FIG. 1 shows only portions corresponding to the gate bus lines GL1 to GL16 from the first row to the sixteenth row.
- the gate driver 400 includes the block scanning circuit 40 and the odd line scanning circuit 42 and the even line scanning circuit 44 provided for each block.
- Each of the block scanning circuit 40, each odd line scanning circuit 42, and each even line scanning circuit 44 is composed of a plurality of stages of shift registers.
- each odd line scanning circuit 42 and each even line scanning circuit 44 is constituted by a shift register having four stages.
- Each stage of the shift register is in one of two states (first state and second state) at each time point, and a signal indicating the state (hereinafter referred to as a “state signal”) .) Is output.
- a circuit constituting each stage of the shift register is also referred to as a “stage constituent circuit”.
- the gate driver 400 includes a start pulse signal GSP including a pulse for starting the operation of the shift register in the block scanning circuit 40 and a shift in the block scanning circuit 40 as the gate control signal GCTL.
- a start pulse signal GSP including a pulse for starting the operation of the shift register in the block scanning circuit 40 and a shift in the block scanning circuit 40 as the gate control signal GCTL.
- Two clock signals BCK1 and BCK2 for controlling the shift operation of the register
- two clock signals GCK1 and GCK2 for controlling the shift operation of the shift register in the odd line scanning circuit 42, and an odd line scanning circuit
- a clear signal GCLR1 including a pulse for completely clearing the state of the shift register in 42
- two clock signals GCK3 and GCK4 for controlling the shift operation of the shift register in the even line scanning circuit 44, and an even number
- the state of the shift register in the line scanning circuit 44 is completely cleared.
- a clear signal GCLR2 including a pulse for given.
- the odd line scanning circuit 42 When the odd line scanning circuit 42 receives the pulse of the start pulse signal GSPOp, the odd line scanning circuit 42 sequentially shifts the pulse from the first stage to the last stage (fourth stage) of the shift register based on the two clock signals GCK1 and GCK2. Forward to. Along with such a shift operation, scan pulses for selectively driving the odd-numbered gate bus lines sequentially are sequentially output from the shift register constituting the odd-number line scanning circuit 42.
- the even line scanning circuit 44 receives the pulse of the start pulse signal GSPEq, the pulse is sequentially transferred from the first stage to the last stage (fourth stage) of the shift register based on the two clock signals GCK3 and GCK4. Forward to. Along with such a shift operation, scan pulses for selectively driving the even-numbered gate bus lines sequentially are sequentially output from the shift register constituting the even-line scanning circuit 44.
- FIG. 4 is a diagram for explaining input / output signals of the n-th stage configuration circuit SRn of the shift register included in the odd line scanning circuit 42 and the even line scanning circuit 44.
- a clock signal CK, a clear signal CLR, a set signal SET, and a reset signal RESET are given to each stage constituent circuit.
- Each stage constituent circuit outputs a state signal Z indicating the state at each time point.
- the clock signal CK is one of the four clock signals GCK1 to GCK4.
- the clear signal CLR is one of the two clear signals GCLR1 and GCLR2.
- the state signal Zn-1 output from the (n-1) th stage configuration circuit SRn-1 is given to the nth stage configuration circuit SRn as the set signal SET, and the (n + 1) th stage configuration circuit SRn-1 is supplied.
- the state signal Zn + 1 output from the circuit SRn + 1 is given as the reset signal RESET.
- the state signal Zn output from the n-th stage constituent circuit SRn is applied as a scanning signal to the gate bus line GL corresponding to the stage constituent circuit SRn, and in addition, the (n ⁇ 1) -th stage Is provided as a reset signal RESET to the second stage configuration circuit SRn ⁇ 1, and is provided as a set signal SET to the (n + 1) th stage configuration circuit SRn + 1.
- FIG. 5 is a circuit diagram showing the configuration of the stage configuration circuit (configuration of one stage of the shift register) in the present embodiment.
- this stage configuration circuit includes six thin film transistors TS and T1 to T5, and one capacitor (capacitance element) Cap. These six thin film transistors TS and T1 to T5 are all N-channel type.
- This stage configuration circuit has four input terminals 51 to 54 and one output terminal (output node) 59 in addition to the input terminal for the low-level DC power supply potential VSS.
- the input terminal that receives the set signal SET is denoted by reference numeral 51
- the input terminal that receives the reset signal RESET is denoted by reference numeral 52
- the input terminal that receives the clock signal CK is denoted by reference numeral 53
- the clear signal An input terminal for receiving CLR is denoted by reference numeral 54.
- An output terminal for outputting the status signal Z is denoted by reference numeral 59.
- the gate terminal of the thin film transistor TS, the source terminal of the thin film transistor T1, the drain terminal of the thin film transistor T2, the drain terminal of the thin film transistor T5, and one end of the capacitor Cap are connected to each other.
- a region (wiring) in which these are connected to each other is referred to as “netA” (first node) for convenience.
- the gate terminal is connected to netA, the drain terminal is connected to the input terminal 53, and the source terminal is connected to the output terminal 59.
- the gate terminal and the drain terminal are connected to the input terminal 51 (that is, diode connection), and the source terminal is connected to netA.
- the gate terminal is connected to the input terminal 52, the drain terminal is connected to netA, and the source terminal is connected to the input terminal for the DC power supply potential VSS.
- the gate terminal is connected to the input terminal 52, the drain terminal is connected to the output terminal 59, and the source terminal is connected to the input terminal for the DC power supply potential VSS.
- the gate terminal is connected to the input terminal 54, the drain terminal is connected to the output terminal 59, and the source terminal is connected to the input terminal for the DC power supply potential VSS.
- the gate terminal is connected to the input terminal 54, the drain terminal is connected to netA, and the source terminal is connected to the input terminal for the DC power supply potential VSS.
- the capacitor Cap has one end connected to the netA and the other end connected to the output terminal 59.
- the output control switching element is realized by the thin film transistor TS
- the first switching element is realized by the thin film transistor T1
- the second switching element is realized by the thin film transistor T2
- the third switching element is realized by the thin film transistor T3.
- a switching element is realized
- a fourth switching element is realized by the thin film transistor T4
- a fifth switching element is realized by the thin film transistor T5.
- the first node charging unit is realized by the portion denoted by reference numeral 57 in FIG. 5
- the first node discharging portion is realized by the portion denoted by reference numeral 58a in FIG. 5
- An output node discharge unit is realized by the portion shown.
- the potential of netA and the potential of the state signal Z are at a low level.
- a pulse of the set signal SET is given to the input terminal 51. Since the thin film transistor T1 is diode-connected as shown in FIG. 5, the thin film transistor T1 is turned on by the pulse of the set signal SET, and the capacitor Cap is charged. As a result, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on.
- the clock signal CK is at a low level. Therefore, during this period, the state signal Z is maintained at a low level.
- the clock signal CK changes from low level to high level.
- the potential of the output terminal 59 increases as the potential of the input terminal 53 increases.
- the capacitor Cap is provided between the netA-output terminal 59, the potential of the netA rises as the potential of the output terminal 59 rises (netA is bootstrapped).
- a large voltage is applied to the thin film transistor TS, and the potential of the state signal Z rises to the high level potential of the clock signal CK.
- the gate bus line connected to the output terminal 59 of this stage constituent circuit is selected.
- the clock signal CK changes from high level to low level.
- the potential of the output terminal 59 decreases as the potential of the input terminal 53 decreases, and the potential of netA also decreases via the capacitor Cap.
- the potential of netA is lowered by the amount of decrease in the potential of the output terminal 59, it is not lowered to the low level but is maintained at the high level.
- a pulse of the reset signal RESET is given to the input terminal 52.
- the thin film transistor T2 and the thin film transistor T3 are turned on.
- the potential of the netA changes from the high level to the low level
- the thin film transistor T3 is turned on, the potential of the output terminal 59 is pulled to the DC power supply potential VSS at the low level.
- a pulse of the clear signal CLR is given to the input terminal 54.
- the thin film transistor T4 and the thin film transistor T5 are turned on.
- the potential of the output terminal 59 is pulled to the low level DC power supply potential VSS
- the thin film transistor T5 is turned on, the potential of netA is pulled to the low level DC power supply potential VSS. It is.
- a pulse of the start pulse signal GSP is given to the odd line drive stage.
- the odd line driving stage outputs a pulse of the start pulse signal GSPO1 at a timing (time t11) when the pulse of the clock signal BCK1 is first received after time t10.
- the pulse of the start pulse signal GSPO1 output from the odd line driving stage is supplied to the even line driving stage and to the first stage of the shift register in the odd line scanning circuit 42.
- the even line drive stage receives the pulse of the start pulse signal GSPE1 at the timing (time t12) when the pulse of the clock signal BCK2 is first received after receiving the pulse of the start pulse signal GSPO1 output from the odd line drive stage. Output.
- the pulse of the start pulse signal GSPE1 output from the even line driving stage is supplied to the odd line driving stage and to the first stage of the shift register in the even line scanning circuit 44.
- the odd line scanning circuit 42 receives the pulse of the start pulse signal GSPO1 in the first stage of the shift register (after time t11), and based on the two clock signals GCK1 and GCK2, the odd-numbered gate bus line Scan pulses are sequentially output to GL1, GL3, GL5, and GL7.
- the even-number line scanning circuit 44 receives the pulse of the start pulse signal GSPE1 in the first stage of the shift register (after time t12), and based on the two clock signals GCK3 and GCK4, the even-numbered gate bus line Scan pulses are sequentially output to GL2, GL4, GL6, and GL8.
- the pulse of the clear signal GCLR1 rises at time t13. As a result, all the stage constituent circuits constituting the shift register in the odd line scanning circuit 42 are completely cleared. At time t15, the clear signal GCLR2 pulse rises. As a result, all the stage constituent circuits constituting the shift register in the even line scanning circuit 44 are completely cleared.
- the gate bus lines GL1 to GLi are divided into a plurality of blocks so that eight gate bus lines are included in one block. Focusing on each block, interlaced scanning is performed on the eight gate bus lines. Specifically, first, four gate bus lines in odd rows are sequentially selected one by one in the first vertical scanning, and then four gate bus lines in even rows are sequentially selected in the second vertical scanning. Selected sequentially. For this reason, the polarity of each video signal is inverted during the first vertical scanning and the second vertical scanning, and the polarity of each video signal is inverted every frame period. The polarity of the pixel voltage in the two frame period is as shown in FIG. Further, by reversing the polarity of the video signal applied to the adjacent source bus line, the polarity of the pixel voltage in two consecutive frame periods is as shown in FIG. As described above, in this embodiment, block inversion driving is performed.
- a monolithic gate driver capable of performing block inversion driving without causing deterioration in display quality or increase in power consumption is realized.
- the switching element is configured using only N-channel TFTs.
- a monolithic gate driver capable of block inversion driving is also realized in a display device that employs an amorphous silicon TFT as a driving element, such as a large liquid crystal panel.
- the shift register in the gate driver 400 can be realized by using a circuit having the same configuration at all stages, and can be realized by a circuit having a relatively simple configuration. It becomes.
- IGZO-TFT a TFT using IGZO which is a kind of amorphous oxide semiconductor (hereinafter referred to as “IGZO-TFT”) is employed as a driving element.
- IGZO is an N-type oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components. Since it is an N-type oxide semiconductor, the configuration of each stage (stage configuration circuit) of the shift register in the gate driver can be the same as that of the above embodiment (see FIG. 5).
- IGZO is characterized by high mobility. For this reason, by adopting the IGZO-TFT as a drive element, it becomes possible to improve the drive capability of the gate driver 400 and to narrow the frame by reducing the TFT size. In addition, by reducing the load capacity, it is possible to further reduce power consumption compared to the above embodiment. Further, the IGZO-TFT has a feature that there is little leakage. Therefore, for example, in a circuit using bootstrap (see FIG. 5), the charge of the floating node (node in an electrically floating state, netA in FIG. 5 in the period from time t1 to time t2 in FIG. 6) Occurrence of operation failure due to the leakage is suppressed, and the operation margin can be expanded.
- each stage (stage configuration circuit) of the shift register in the gate driver 400 has a configuration using a CMOS logic circuit.
- FIG. 10 is a circuit diagram showing the configuration of the stage configuration circuit (configuration of one stage of the shift register) in this modification.
- this stage configuration circuit includes four clocked inverters 61 to 64 and two NOR circuits 65 and 66. These four clocked inverters 61 to 64 and the two NOR circuits 65 and 66 all have a circuit configuration using CMOS.
- CMOS complementary metal-oxide-semiconductor
- the clocked inverters 61 and 64 function as inverters when the clock signal clk is at a low level and the clock signal clkb is at a high level, and between the input terminal and the output terminal when the clock signal clk is at a high level and the clock signal clkb is at a low level. Is electrically disconnected.
- the clocked inverters 62 and 63 function as inverters when the clock signal clk is at a high level and the clock signal clkb is at a low level, and between the input terminal and the output terminal when the clock signal clk is at a low level and the clock signal clkb is at a high level. Electrically disconnected.
- NOR circuits 65 and 66 output a signal indicating a negative logical sum of signals given to two input terminals.
- the NOR circuit 65 an output signal from the clocked inverters 61 and 62 is given to one input terminal, and a clear signal CLR is given to the other input terminal.
- the output signal from the NOR circuit 65 is given to the clocked inverters 62 and 63.
- the NOR circuit 66 an output signal from the clocked inverters 63 and 64 is given to one input terminal, and a clear signal CLR is given to the other input terminal.
- the output signal from the NOR circuit 66 is supplied to the clocked inverter 64 and is output as a state signal Z from this stage constituent circuit.
- the logical value of the signal (input data) Din is temporarily held at the node N1.
- the logical value of the data temporarily held at the node N1 is changed to the state signal Z. It appears as a waveform.
- this stage configuration circuit operates as a master-slave type D flip-flop including a master flip-flop (portion indicated by reference numeral 601 in FIG. 10) and a slave flip-flop (portion indicated by reference numeral 602 in FIG. 10). .
- the two clock signals clk and clkb supplied to the clocked inverters 61 to 64 are generated from the clock signal CK by the circuit shown in FIG. 11 configured using the two inverters 71 and 72.
- the clock signal CK is one of the four clock signals GCK1 to GCK4 as in the above embodiment. With the configuration shown in FIG. 11, when the clock signal CK is at a high level, the clock signal clk is at a high level and the clock signal clkb is at a low level. On the other hand, when the clock signal CK is at a low level, the clock signal clk is at a low level, and the clock signal clkb is at a high level.
- the start pulse signal or the state signal Zn-1 output from the previous stage is supplied to the clocked inverter 61 as the input signal Din.
- the logic value “1” is set in the stage configuration circuit corresponding to the gate bus line GL3 in the third row based on the scanning pulse and the clock signal GCK2.
- the indicated data is temporarily held at the node N1.
- the stage configuration corresponding to the gate bus line GL3 of the third row is made by the clock signal GCK2 changing from the low level to the high level after one horizontal scanning period from the rising edge of the scanning pulse of the gate bus line GL1 of the first row.
- the state signal Z output from the circuit becomes high level. In this manner, the scan pulse for the third row gate bus line GL3 rises one horizontal scan period after the scan pulse for the first row gate bus line GL1 rises.
- the gate driver 400 can operate in the same manner as in the above embodiment. Since the stage configuration circuit is configured using a CMOS logic circuit, power consumption is reduced compared to the above embodiment. Also in this modified example, regarding the shift register in the gate driver 400, all the stages can be realized by a circuit having the same configuration, and can be realized by a circuit having a relatively simple configuration. Become.
- liquid crystal display device has been described as an example in the above embodiment, the present invention is not limited to this.
- the present invention can also be applied to other display devices such as an organic EL (Electro Luminescence).
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Abstract
Description
(1)ゲートバスラインが複数個のブロックに区分された上で、当該複数個のブロックに対しては1つずつ順次に選択が行われる。
(2)各ブロックに含まれる複数本のゲートバスラインに対しては飛び越し走査が行われる。これにより、各ブロックに関し、1フレーム期間中に2回の垂直走査(奇数行目を選択するための走査と偶数行目を選択するための走査)が行われる。
(3)1フレーム期間中における2回の垂直走査に関し、1回目の垂直走査の際と2回目の垂直走査の際とで、各ソースバスラインに印加される映像信号の極性が反転する。
(4)個々の画素形成部において、画素電圧の極性は1フレーム期間毎に反転する。
前記複数本の走査信号線のうちの奇数行目の走査信号線を駆動するための複数個の奇数ライン走査用回路と、
前記複数本の走査信号線のうちの偶数行目の走査信号線を駆動するための複数個の偶数ライン走査用回路と、
前記複数個の奇数ライン走査用回路および前記複数個の偶数ライン走査用回路の中からアクティブにすべき回路を選択する選択回路と
を備え、
前記複数本の走査信号線は、連続するk本(kは4以上の整数)の走査信号線が各ブロックに含まれるように、z個(zは2以上の整数)のブロックに区分され、
前記奇数ライン走査用回路および前記偶数ライン走査用回路は、ブロック毎に設けられ、
前記選択回路は、1個目からz個目までのブロックを1つずつ順次に選択しつつ、前記奇数ライン走査用回路と前記偶数ライン走査用回路とを交互に選択し、
各奇数ライン走査用回路は、対応するブロックに含まれる奇数行目の走査信号線を順次に選択的に駆動し、
各偶数ライン走査用回路は、対応するブロックに含まれる偶数行目の走査信号線を順次に選択的に駆動することを特徴とする。
前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記シフトレジスタを構成する各段は、
前記状態信号を出力するための出力ノードと、
第2電極に前記クロック信号が与えられ、前記出力ノードに第3電極が接続された出力制御用スイッチング素子と、
前記出力制御用スイッチング素子の第1電極に接続された第1ノードと、
前記出力ノードと前記第1ノードとの間に設けられた容量素子と、
開始指示信号または前段の出力ノードから出力される状態信号に基づいて前記第1ノードを充電するための第1ノード充電部と、
次段の出力ノードから出力される状態信号に基づいて前記第1ノードを放電するための第1ノード放電部と、
次段の出力ノードから出力される状態信号に基づいて前記出力ノードを放電するための出力ノード放電部と
を有することを特徴とする。
前記シフトレジスタを構成する各段において、前記第1ノード充電部によって前記第1ノードが充電された後であって前記第1ノード放電部によって前記第1ノードが放電される前に、前記出力制御用スイッチング素子の第2電極に与えられているクロック信号がローレベルからハイレベルに変化することを特徴とする。
前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が前記開始指示信号として与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記開始指示信号として与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする。
前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が開始指示信号として与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記開始指示信号として与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする。
前記シフトレジスタを構成する各段において、
前記第1ノード充電部は、前段の出力ノードから出力される状態信号が第1電極および第2電極に与えられ、前記第1ノードに第3電極が接続された第1のスイッチング素子を含み、
前記第1ノード放電部は、次段の出力ノードから出力される状態信号が第1電極に与えられ、前記第1ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第2のスイッチング素子を含むことを特徴とする。
前記シフトレジスタを構成する各段において、
前記出力ノード放電部は、前段の出力ノードから出力される状態信号が第1電極に与えられ、前記出力ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第3のスイッチング素子を含むことを特徴とする。
前記シフトレジスタを構成する各段は、外部から入力されるクリア信号が第1電極に与えられ、前記出力ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第4のスイッチング素子を更に有することを特徴とする。
前記シフトレジスタを構成する各段は、外部から入力されるクリア信号が第1電極に与えられ、前記第1ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第5のスイッチング素子を更に有することを特徴とする。
前記シフトレジスタを構成する各段に含まれるスイッチング素子は、アモルファスシリコンからなる薄膜トランジスタであることを特徴とする。
前記シフトレジスタを構成する各段に含まれるスイッチング素子は、インジウム,ガリウム,亜鉛,および酸素を主成分とするN型の酸化物半導体からなる薄膜トランジスタであることを特徴とする。
前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記シフトレジスタを構成する各段は、入力データを前記クロック信号に基づいて取り込むマスターフリップフロップと該マスターフリップフロップに取り込まれたデータを前記クロック信号に基づいて前記状態信号として出力するスレーブフリップフロップとからなる、CMOS論理回路を用いて実現されたマスタースレーブ型フリップフロップであって、
前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が前記入力データとして与えられ、
前記奇数ライン走査用回路を構成するシフトレジスタの二段目以降の各段には、前段から出力される状態信号が前記入力データとして与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記入力データとして与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの二段目以降の各段には、前段から出力される状態信号が前記入力データとして与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする。
前記シフトレジスタを構成する各段に含まれるCMOS論理回路には、多結晶シリコンからなる薄膜トランジスタが用いられていることを特徴とする。
本発明の第1から第13までのいずれかの局面に係る走査信号線駆動回路と、
前記基板上に配設された複数本の映像信号線を駆動する映像信号線駆動回路と
を備え、
前記映像信号線駆動回路は、各映像信号線に印加される映像信号に着目したとき、前記奇数ライン走査用回路が前記選択回路によって選択されている時の前記映像信号の極性と前記偶数ライン走査用回路が前記選択回路によって選択されている時の前記映像信号の極性とを異なる極性にすることを特徴とする。
前記映像信号線駆動回路は、隣接する2本の映像信号線に印加される映像信号の極性を互いに異なる極性にすることを特徴とする。
図2は、本発明の一実施形態に係るアクティブマトリクス型の液晶表示装置の全体構成を示すブロック図である。図2に示すように、この液晶表示装置は、表示部100と、表示制御回路200と、ソースドライバ(映像信号線駆動回路)300と、ゲートドライバ(走査信号線駆動回路)400とを備えている。表示部100には、複数本(j本)のソースバスライン(映像信号線)SL1~SLjと、複数本(i本)のゲートバスライン(走査信号線)GL1~GLiと、ソースバスラインSL1~SLjとゲートバスラインGL1~GLiとの交差点にそれぞれ対応して設けられた複数個(i×j個)の画素形成部とが形成されている。上記複数個の画素形成部はマトリクス状に配置されて画素アレイを構成している。各画素形成部は、対応する交差点を通過するゲートバスラインにゲート端子が接続されると共に当該交差点を通過するソースバスラインにソース端子が接続されたスイッチング素子である薄膜トランジスタ(TFT)11と、その薄膜トランジスタ11のドレイン端子に接続された画素電極と、上記複数個の画素形成部に共通的に設けられた対向電極である共通電極Ecと、上記複数個の画素形成部に共通的に設けられ画素電極と共通電極Ecとの間に挟持された液晶層とからなる。そして、画素電極と共通電極Ecとにより形成される液晶容量により、画素容量Cpが構成される。なお、通常、画素容量Cpに確実に電荷を保持すべく、液晶容量に並列に補助容量が設けられるが、補助容量は本発明には直接に関係しないのでその説明および図示を省略する。
<2.1 ゲートドライバの概略構成>
図3は、本実施形態におけるゲートドライバ400の概略構成を示すブロック図である。本実施形態においては、ゲートバスラインGL1~GLiは、連続するk本(kは4以上の整数)のゲートバスラインが1つのブロックに含まれるように、複数個のブロック(グループ)に区分される。なお、本説明においては、各ブロックに8本のゲートバスラインが含まれるようゲートバスラインGL1~GLiはz個(z=i/8)のブロックBLK1~BLKzに区分されていると仮定する。
図1は、本実施形態におけるゲートドライバ400の詳細な構成を示すブロック図である。なお、図1には、1行目から16行目までのゲートバスラインGL1~GL16に対応する部分のみを示している。上述したように、ゲートドライバ400には、ブロック走査用回路40と、ブロック毎に設けられた奇数ライン走査用回路42および偶数ライン走査用回路44とが含まれている。ブロック走査用回路40,各奇数ライン走査用回路42,および各偶数ライン走査用回路44はそれぞれ複数段からなるシフトレジスタで構成されている。なお、本説明の例では、各奇数ライン走査用回路42および各偶数ライン走査用回路44は、4段からなるシフトレジスタで構成されている。シフトレジスタの各段は、各時点において2つの状態(第1の状態および第2の状態)のうちのいずれか一方の状態となっていて、当該状態を示す信号(以下、「状態信号」という。)を出力する。また、以下においては、シフトレジスタの各段を構成する回路のことを「段構成回路」ともいう。
図4は、奇数ライン走査用回路42および偶数ライン走査用回路44に含まれるシフトレジスタのn段目の段構成回路SRnの入出力信号について説明するための図である。各段構成回路には、クロック信号CKとクリア信号CLRとセット信号SETとリセット信号RESETとが与えられる。また、各段構成回路からは、各時点における状態を示す状態信号Zが出力される。クロック信号CKは、上記4つのクロック信号GCK1~GCK4のうちのいずれかである。クリア信号CLRは、上記2つのクリア信号GCLR1,GCLR2のうちのいずれかである。n段目の段構成回路SRnには、(n-1)段目の段構成回路SRn-1から出力される状態信号Zn-1がセット信号SETとして与えられ、(n+1)段目の段構成回路SRn+1から出力される状態信号Zn+1がリセット信号RESETとして与えられる。また、n段目の段構成回路SRnから出力される状態信号Znは、当該段構成回路SRnに対応するゲートバスラインGLに走査信号として印加されるのに加えて、(n-1)段目の段構成回路SRn-1にリセット信号RESETとして与えられ、(n+1)段目の段構成回路SRn+1にセット信号SETとして与えられる。
<3.1 段構成回路の動作>
図5および図6を参照しつつ、本実施形態における段構成回路の動作について説明する。この液晶表示装置の動作中、図6に示すように所定の周期で所定の期間ハイレベルとなるクロック信号CKが入力端子53に与えられる。
次に、上述した段構成回路の動作を踏まえ、図7を参照しつつ、本実施形態におけるゲートドライバ400全体の動作について説明する。なお、ここでは、ブロックBLK1(図3参照)に着目するが、その他のブロックBLK2~BLKzについても同様の動作が行われる。
本実施形態によれば、ゲートバスラインGL1~GLiは、1つのブロックに8本のゲートバスラインが含まれるように複数個のブロックに区分される。各ブロックに着目すると、8本のゲートバスラインに対して飛び越し走査が行われる。詳しくは、まず1回目の垂直走査で奇数行目の4本のゲートバスラインが1本ずつ順次に選択され、その後2回目の垂直走査で偶数行目の4本のゲートバスラインが1本ずつ順次に選択される。このため、1回目の垂直走査の際と2回目の垂直走査の際とで各映像信号の極性を反転させ、かつ、1フレーム期間毎にも各映像信号の極性を反転させることによって、連続する2フレーム期間における画素電圧の極性は図12に示したようなものとなる。さらに、隣接するソースバスラインに印加される映像信号の極性をも反転させることによって、連続する2フレーム期間における画素電圧の極性は図13に示したようなものとなる。以上のように、本実施形態においては、ブロック反転駆動が行われる。
上記実施形態においては、駆動素子としてアモルファスシリコンTFTが採用されている例を挙げて説明したが、本発明はこれに限定されない。以下、駆動素子として採用されるTFTについての変形例を説明する。
まず、駆動素子としてアモルファス酸化物半導体の一種であるIGZOを用いたTFT(以下、「IGZO-TFT」という。)が採用される例について説明する。IGZOは、インジウム(In),ガリウム(Ga),亜鉛(Zn),および酸素(O)を主成分とするN型の酸化物半導体である。N型の酸化物半導体であるので、ゲートドライバ内のシフトレジスタの各段(段構成回路)の構成を上記実施形態と同様の構成(図5参照)にすることができる。
次に、駆動素子として多結晶シリコンTFT(p-Si TFT)が採用される例について説明する。多結晶シリコンTFTについては、アモルファスシリコンTFTとは異なり、CMOS構成を採用することができる。そこで、本変形例においては、ゲートドライバ400内のシフトレジスタの各段(段構成回路)は、CMOS論理回路を用いた構成となっている。
上記実施形態においては液晶表示装置を例に挙げて説明したが、本発明はこれに限定されない。有機EL(Electro Luminescence)等の他の表示装置にも本発明を適用することができる。
42…奇数ライン走査用回路
44…偶数ライン走査用回路
51~54…(段構成回路の)入力端子
59…(段構成回路の)出力端子
100…表示部
200…表示制御回路
300…ソースドライバ(映像信号線駆動回路)
400…ゲートドライバ(走査信号線駆動回路)
BLK1~BLKz…ブロック
SR…段構成回路(シフトレジスタの段)
Cap…キャパシタ(容量素子)
TS,T1~T5…薄膜トランジスタ(TFT)
GL1~GLi…ゲートバスライン
SL1~SLj…ソースバスライン
Claims (15)
- 表示パネルを構成する基板上にモノリシックに形成され、前記基板上に配設された複数本の走査信号線を駆動する走査信号線駆動回路であって、
前記複数本の走査信号線のうちの奇数行目の走査信号線を駆動するための複数個の奇数ライン走査用回路と、
前記複数本の走査信号線のうちの偶数行目の走査信号線を駆動するための複数個の偶数ライン走査用回路と、
前記複数個の奇数ライン走査用回路および前記複数個の偶数ライン走査用回路の中からアクティブにすべき回路を選択する選択回路と
を備え、
前記複数本の走査信号線は、連続するk本(kは4以上の整数)の走査信号線が各ブロックに含まれるように、z個(zは2以上の整数)のブロックに区分され、
前記奇数ライン走査用回路および前記偶数ライン走査用回路は、ブロック毎に設けられ、
前記選択回路は、1個目からz個目までのブロックを1つずつ順次に選択しつつ、前記奇数ライン走査用回路と前記偶数ライン走査用回路とを交互に選択し、
各奇数ライン走査用回路は、対応するブロックに含まれる奇数行目の走査信号線を順次に選択的に駆動し、
各偶数ライン走査用回路は、対応するブロックに含まれる偶数行目の走査信号線を順次に選択的に駆動することを特徴とする、走査信号線駆動回路。 - 前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記シフトレジスタを構成する各段は、
前記状態信号を出力するための出力ノードと、
第2電極に前記クロック信号が与えられ、前記出力ノードに第3電極が接続された出力制御用スイッチング素子と、
前記出力制御用スイッチング素子の第1電極に接続された第1ノードと、
前記出力ノードと前記第1ノードとの間に設けられた容量素子と、
開始指示信号または前段の出力ノードから出力される状態信号に基づいて前記第1ノードを充電するための第1ノード充電部と、
次段の出力ノードから出力される状態信号に基づいて前記第1ノードを放電するための第1ノード放電部と、
次段の出力ノードから出力される状態信号に基づいて前記出力ノードを放電するための出力ノード放電部と
を有することを特徴とする、請求項1に記載の走査信号線駆動回路。 - 前記シフトレジスタを構成する各段において、前記第1ノード充電部によって前記第1ノードが充電された後であって前記第1ノード放電部によって前記第1ノードが放電される前に、前記出力制御用スイッチング素子の第2電極に与えられているクロック信号がローレベルからハイレベルに変化することを特徴とする、請求項2に記載の走査信号線駆動回路。
- 前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が前記開始指示信号として与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記開始指示信号として与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする、請求項2または3に記載の走査信号線駆動回路。 - 前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が開始指示信号として与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記開始指示信号として与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする、請求項1に記載の走査信号線駆動回路。 - 前記シフトレジスタを構成する各段において、
前記第1ノード充電部は、前段の出力ノードから出力される状態信号が第1電極および第2電極に与えられ、前記第1ノードに第3電極が接続された第1のスイッチング素子を含み、
前記第1ノード放電部は、次段の出力ノードから出力される状態信号が第1電極に与えられ、前記第1ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第2のスイッチング素子を含むことを特徴とする、請求項2に記載の走査信号線駆動回路。 - 前記シフトレジスタを構成する各段において、
前記出力ノード放電部は、前段の出力ノードから出力される状態信号が第1電極に与えられ、前記出力ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第3のスイッチング素子を含むことを特徴とする、請求項2に記載の走査信号線駆動回路。 - 前記シフトレジスタを構成する各段は、外部から入力されるクリア信号が第1電極に与えられ、前記出力ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第4のスイッチング素子を更に有することを特徴とする、請求項2に記載の走査信号線駆動回路。
- 前記シフトレジスタを構成する各段は、外部から入力されるクリア信号が第1電極に与えられ、前記第1ノードに第2電極が接続され、ローレベルの電位が第3電極に与えられる第5のスイッチング素子を更に有することを特徴とする、請求項2に記載の走査信号線駆動回路。
- 前記シフトレジスタを構成する各段に含まれるスイッチング素子は、アモルファスシリコンからなる薄膜トランジスタであることを特徴とする、請求項2から9までのいずれか1項に記載の走査信号線駆動回路。
- 前記シフトレジスタを構成する各段に含まれるスイッチング素子は、インジウム,ガリウム,亜鉛,および酸素を主成分とするN型の酸化物半導体からなる薄膜トランジスタであることを特徴とする、請求項2から9までのいずれか1項に記載の走査信号線駆動回路。
- 前記選択回路,前記奇数ライン走査用回路,および前記偶数ライン走査用回路は、外部から入力されるクロック信号に基づき第1の状態または第2の状態のいずれかを示す状態信号を出力する複数の段からなるシフトレジスタで構成され、
前記シフトレジスタを構成する各段は、入力データを前記クロック信号に基づいて取り込むマスターフリップフロップと該マスターフリップフロップに取り込まれたデータを前記クロック信号に基づいて前記状態信号として出力するスレーブフリップフロップとからなる、CMOS論理回路を用いて実現されたマスタースレーブ型フリップフロップであって、
前記奇数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの奇数段目から出力される状態信号が前記入力データとして与えられ、
前記奇数ライン走査用回路を構成するシフトレジスタの二段目以降の各段には、前段から出力される状態信号が前記入力データとして与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの一段目には、前記選択回路を構成するシフトレジスタの偶数段目から出力される状態信号が前記入力データとして与えられ、
前記偶数ライン走査用回路を構成するシフトレジスタの二段目以降の各段には、前段から出力される状態信号が前記入力データとして与えられ、
前記複数本の走査信号線のうちの奇数行目の走査信号線には、前記奇数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられ、
前記複数本の走査信号線のうちの偶数行目の走査信号線には、前記偶数ライン走査用回路を構成するシフトレジスタの各段から出力される状態信号が走査信号として与えられることを特徴とする、請求項1に記載の走査信号線駆動回路。 - 前記シフトレジスタを構成する各段に含まれるCMOS論理回路には、多結晶シリコンからなる薄膜トランジスタが用いられていることを特徴とする、請求項12に記載の走査信号線駆動回路。
- 表示装置であって、
請求項1から13までのいずれか1項に記載の走査信号線駆動回路と、
前記基板上に配設された複数本の映像信号線を駆動する映像信号線駆動回路と
を備え、
前記映像信号線駆動回路は、各映像信号線に印加される映像信号に着目したとき、前記奇数ライン走査用回路が前記選択回路によって選択されている時の前記映像信号の極性と前記偶数ライン走査用回路が前記選択回路によって選択されている時の前記映像信号の極性とを異なる極性にすることを特徴とする、表示装置。 - 前記映像信号線駆動回路は、隣接する2本の映像信号線に印加される映像信号の極性を互いに異なる極性にすることを特徴とする、請求項14に記載の表示装置。
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US8686990B2 (en) | 2014-04-01 |
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