WO2012131878A1 - 縦型半導体装置 - Google Patents
縦型半導体装置 Download PDFInfo
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- WO2012131878A1 WO2012131878A1 PCT/JP2011/057670 JP2011057670W WO2012131878A1 WO 2012131878 A1 WO2012131878 A1 WO 2012131878A1 JP 2011057670 W JP2011057670 W JP 2011057670W WO 2012131878 A1 WO2012131878 A1 WO 2012131878A1
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- semiconductor device
- surface density
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- resurf
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 177
- 239000012535 impurity Substances 0.000 claims abstract description 143
- 238000009792 diffusion process Methods 0.000 claims abstract description 53
- 238000009826 distribution Methods 0.000 claims description 51
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 37
- 230000007423 decrease Effects 0.000 abstract description 20
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 133
- 230000002093 peripheral effect Effects 0.000 description 76
- 230000015556 catabolic process Effects 0.000 description 40
- 230000005684 electric field Effects 0.000 description 13
- 239000002344 surface layer Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005204 segregation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Definitions
- the present invention relates to a vertical semiconductor device.
- Patent Documents 1-4 disclose a RESURF structure in a semiconductor device.
- a RESURF structure is realized by disposing a diffusion layer in at least a part of the non-cell region.
- a depletion layer spreading from the interface of the diffusion layer shares the voltage and relaxes the concentration of the electric field, thereby realizing a high breakdown voltage.
- the present specification provides a technique for solving the above problems.
- the present specification provides a technique for suppressing a decrease in breakdown voltage when external charges adhere to a vertical semiconductor device having a RESURF structure.
- the vertical semiconductor device disclosed in the present specification includes a cell region and a non-cell region disposed outside the cell region.
- the vertical semiconductor device has a diffusion layer in at least a part of the non-cell region.
- the impurity surface density at the end near the cell region is higher than the impurity surface density satisfying the RESURF condition, and the end on the side far from the cell region.
- the impurity surface density in the portion is lower than the impurity surface density satisfying the RESURF condition.
- the impurity surface density when the vertical semiconductor device is viewed in plan, compared to the average gradient of the impurity surface density in the region of the impurity surface density lower than the impurity surface density that satisfies the resurf condition, the impurity surface density satisfies the resurf condition.
- the average gradient of the impurity surface density in the high impurity surface density region is large.
- the impurity surface density referred to here is a value obtained by integrating the impurity concentration in the diffusion layer in the depth direction of the diffusion layer, and corresponds to the impurity implantation amount per unit area when the vertical semiconductor device is viewed in plan view. To do.
- the impurity surface density that satisfies the RESURF condition is about 1 ⁇ 10 12 [cm ⁇ 2 ].
- the impurity surface density in the diffusion layer is preferably 5 ⁇ 10 13 [cm ⁇ 2 ] or less at the maximum.
- the depletion layer spreading from the interface of the diffusion layer shares the voltage, and the electric field concentration is reduced.
- the diffusion layer is formed such that the impurity surface density at the end near the cell region is higher than the impurity surface density satisfying the resurf condition, and the impurity surface density at the end far from the cell region is lower than the impurity surface density satisfying the resurf condition.
- the impurity surface density of the diffusion layer decreases from the end near the cell region toward the end far from the cell region, and there is a portion where the impurity surface density satisfies the RESURF condition during that time. .
- the formed depletion layer does not change greatly. According to the vertical semiconductor device, it is possible to suppress a decrease in breakdown voltage due to adhesion of external charges. Further, in the above vertical semiconductor device, the impurity concentration of the diffusion layer and the semiconductor layer below it varies during manufacturing, and the carrier distribution of the diffusion layer and the semiconductor layer below it is disturbed due to the variation of the impurity concentration. Even in this case, a large change does not occur in the formed depletion layer.
- the vertical semiconductor device described above has less variation in breakdown voltage with respect to variations in impurity concentration during manufacturing.
- a region having an impurity surface density lower than the impurity surface density satisfying the resurf condition is a gentle gradient region having a small average gradient of the impurity surface density, and is higher than the impurity surface density satisfying the resurf condition.
- the region of impurity surface density is a steep region where the average gradient of impurity surface density is large. In the steep region, there are many surplus carriers that are not involved in the formation of the depletion layer. Therefore, even when external charges adhere to the surface of the diffusion layer and carriers in the diffusion layer decrease due to the influence of the external charges, the decrease in carriers in the diffusion layer is compensated by the surplus carriers existing in the steep slope region. be able to. A decrease in breakdown voltage due to the adhesion of external charges can be suppressed.
- Another vertical semiconductor device disclosed in the present specification includes a cell region and a non-cell region disposed outside the cell region.
- the vertical semiconductor device has a diffusion layer in at least a part of the non-cell region.
- the distribution in the depth direction of the carrier concentration at the end portion on the side away from the cell region has a maximum value at a position deeper than the surface.
- the depth at which the carrier concentration reaches a maximum value is preferably 0.5 [ ⁇ m] or more from the surface.
- the depletion layer spreading from the interface of the diffusion layer shares the voltage and relaxes the concentration of the electric field.
- the spread of the depletion layer changes according to the carrier concentration at the end of the diffusion layer on the side away from the cell region, and the breakdown voltage of the vertical semiconductor device is at the end of the diffusion layer on the side away from the cell region. This depends on the maximum value of the carrier concentration in the part.
- the maximum value of the carrier concentration at the end of the diffusion layer on the side away from the cell region exists at a position deeper than the surface, and even when external charges adhere to the surface, the carrier concentration The maximum value of is difficult to change. According to the vertical semiconductor device, it is possible to suppress a decrease in breakdown voltage due to adhesion of external charges.
- Another vertical semiconductor device disclosed in the present specification includes a cell region and a non-cell region disposed outside the cell region.
- the vertical semiconductor device has a diffusion layer in at least a part of the non-cell region.
- a polysilicon layer is stacked above the end of the diffusion layer on the side away from the cell region.
- the impurity concentration of the same conductivity type as that of the diffusion layer in the polysilicon layer is lower than the maximum value of the impurity concentration in the diffusion layer below the polysilicon layer.
- the depletion layer spreading from the interface of the diffusion layer shares the voltage and relaxes the concentration of the electric field.
- the spread of the depletion layer changes according to the carrier concentration at the end of the diffusion layer on the side away from the cell region, and the breakdown voltage of the vertical semiconductor device is at the end of the diffusion layer on the side away from the cell region.
- the polysilicon layer is stacked above the end of the diffusion layer on the side away from the cell region, and the carrier concentration is the maximum value at the end of the diffusion layer on the side away from the cell region.
- the vertical semiconductor device it is possible to suppress a decrease in breakdown voltage due to adhesion of external charges.
- FIG. 3 is a plan view of semiconductor devices 10, 300, and 400 according to Examples 1, 2, and 3.
- FIG. 2 is a cross-sectional view of the semiconductor device 10 according to the first embodiment at a position indicated by line II-II in FIG.
- the distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 of Example 1 is shown.
- the electric field strength distribution in the depletion layer of the semiconductor device 10 of Example 1 is shown.
- the relationship between the withstand voltage at the time of positive charge adhesion and the withstand voltage at the time of negative charge adhesion of the semiconductor device 10 of Example 1 is shown.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- 7 shows another distribution of the p-type impurity surface density in the RESURF region 34 of the semiconductor device 10 according to the first embodiment.
- FIG. 2 The hole direction depth distribution in the outer peripheral side edge part C of the resurf area
- the semiconductor device 10 of this embodiment includes a semiconductor element region 100 (corresponding to a cell region) in which a semiconductor element is formed, and a peripheral withstand voltage region 200 (non-null) surrounding the semiconductor element region 100.
- the vertical semiconductor device includes a cell region.
- an IGBT is formed in the semiconductor element region 100.
- another power semiconductor element such as a MOSFET or a diode may be formed in the semiconductor element region 100, for example.
- the semiconductor element region 100 is formed at a substantially central portion of the semiconductor layer 20, and the peripheral breakdown voltage region 200 is formed along the outer peripheral edge 22 of the semiconductor layer 20.
- the peripheral breakdown voltage region 200 is a region for ensuring a breakdown voltage between the outer peripheral edge 22 of the semiconductor layer 20 and the semiconductor element region 100.
- the semiconductor device 10 mainly includes a semiconductor layer 20, an insulating layer 40, a central electrode 50, an outer peripheral electrode 60, and a back electrode 80.
- the semiconductor layer 20 is made of silicon.
- the central electrode 50 is formed on the upper surface 24 of the semiconductor layer 20 in the semiconductor element region 100.
- the center electrode 50 is an IGBT emitter electrode.
- the outer peripheral electrode 60 is formed on the upper surface 24 of the semiconductor layer 20 and extends along the outer peripheral end 22 of the semiconductor layer 20.
- the outer peripheral electrode 60 is a channel stop electrode.
- the insulating layer 40 is formed on the upper surface 24 of the semiconductor layer 20 between the central electrode 50 and the outer peripheral electrode 60.
- the back electrode 80 is formed on the lower surface 26 of the semiconductor layer 20.
- the back electrode 80 is an IGBT collector electrode.
- the back electrode contact region 38 is made of a p-type semiconductor having a high p-type impurity concentration.
- the back electrode contact region 38 is formed over the entire surface layer region (region in the vicinity of the lower surface 26 including the lower surface 26) on the lower surface 26 side of the semiconductor layer 20.
- the back electrode contact region 38 is ohmically connected to the back electrode 80.
- the back electrode contact region 38 is an IGBT collector region in the semiconductor element region 100.
- the center electrode contact region 32 is made of a p-type semiconductor having a high p-type impurity concentration.
- the central electrode contact region 32 is a surface layer region (region in the vicinity of the upper surface 24 including the upper surface 24) on the upper surface 24 side of the semiconductor layer 20, and is formed in the semiconductor element region 100.
- the center electrode contact region 32 is ohmically connected to the center electrode 50.
- the center electrode contact region 32 is an IGBT body region in the semiconductor element region 100.
- An isolation region that separates the two may be formed between the central electrode contact region 32 and the RESURF region 34.
- the low-concentration n-type region 30 is composed of an n-type semiconductor having a low n-type impurity concentration.
- the low-concentration n-type region 30 is mainly formed in an intermediate portion in the depth direction of the semiconductor layer 20.
- the low concentration n-type region 30 is formed between the back electrode contact region 38 and the center electrode contact region 32.
- the low concentration n-type region 30 in the semiconductor element region 100 functions as a drift region of the IGBT.
- the semiconductor layer 20 in the semiconductor element region 100 includes various n-type or p-type in addition to the central electrode contact region 32, the low concentration n-type region 30, and the back electrode contact region 38.
- a mold region (for example, an emitter region) is formed.
- a gate electrode is formed in the semiconductor element region 100.
- the IGBT in the semiconductor element region 100 is formed by the central electrode 50, the back electrode 80, the gate electrode, and various n-type or p-type semiconductor regions in the semiconductor element region 100.
- the outer peripheral electrode contact region 36 is composed of an n-type semiconductor having a high n-type impurity concentration.
- the peripheral electrode contact region 36 is a surface layer region on the upper surface 24 side of the semiconductor layer 20 and is formed on the outermost peripheral side of the peripheral withstand voltage region 200. That is, the outer peripheral electrode contact region 36 is formed at a position exposed at the outer peripheral end 22 of the semiconductor layer 20.
- the outer peripheral electrode contact region 36 is ohmically connected to the outer peripheral electrode 60.
- the outer peripheral electrode contact region 36 is a channel stop region.
- the RESURF region 34 (corresponding to a diffusion layer) is composed of a p-type semiconductor having a low p-type impurity concentration.
- the RESURF region 34 is a surface layer region on the upper surface 24 side of the semiconductor layer 20 and is formed in the peripheral withstand voltage region 200. One end of the RESURF region 34 is in contact with the central electrode contact region 32. Between the outer peripheral electrode contact region 36 and the RESURF region 34, the above-described low concentration n-type region 30 exists.
- the peripheral electrode contact region 36 is separated from the RESURF region 34 by the low concentration n-type region 30.
- the function of the peripheral withstand voltage region 200 of the semiconductor device 10 will be described.
- the IGBT in the semiconductor element region 100 is on, a high potential difference does not occur between the electrodes of the semiconductor device 10.
- the IGBT is turned off, the potentials of the outer peripheral electrode 60 and the back electrode 80 rise with respect to the potential of the central electrode 50.
- a depletion layer extends from the central electrode contact region 32 into the low concentration n-type region 30.
- the depletion layer extends from the central electrode contact region 32 toward the outer peripheral side in the surface layer region on the upper surface 24 side of the semiconductor layer 20.
- the RESURF region 34 promotes the depletion layer to extend toward the outer peripheral side.
- the depletion layer in the peripheral withstand voltage region 200 reaches the outer peripheral electrode contact region 36. Since the peripheral electrode contact region 36 has a high n-type impurity concentration, the depletion layer does not extend into the peripheral electrode contact region 36. That is, the depletion layer stops at the boundary between the peripheral electrode contact region 36 and the low concentration n-type region 30 as indicated by a dotted line 90 in FIG. Therefore, the depletion layer does not extend to the outer peripheral side from the outer peripheral electrode contact region 36. This prevents the depletion layer from extending to the outer peripheral edge 22 of the semiconductor layer 20.
- a depletion layer is formed in a region between the central electrode contact region 32 and the outer peripheral electrode contact region 36 (that is, the low concentration n-type region 30 and the RESURF region 34). . Most of the voltage between the central electrode 50 and the outer peripheral electrode 60 is shared by this depleted region.
- FIG. 3 shows the surface density distribution of the p-type impurity in the RESURF region 34.
- the p-type impurity in the RESURF region 34 gradually decreases in surface density from the end B on the central side (side closer to the semiconductor element region 100) toward the end A on the outer peripheral side (side far from the semiconductor element region 100).
- the p-type impurity surface density of the RESURF region 34 becomes the reference surface density at a position slightly closer to the center side end portion B than an intermediate position between the center side end portion B and the outer peripheral side end portion A.
- the reference surface density is a surface density that satisfies a so-called RESURF condition.
- a position where the p-type impurity surface density becomes the reference surface density is defined as a reference position P.
- the average gradient of the p-type impurity surface density at the center side from the reference position P is set steeper than the average gradient of the p-type impurity surface density at the outer peripheral side from the reference position P.
- the average gradient of the p-type impurity surface density at the center side from the reference position P is set to 1.3 times the average gradient of the p-type impurity surface density at the outer peripheral side from the reference position P.
- the surface density of the p-type impurity in the RESURF region 34 is 5 ⁇ 10 13 [cm ⁇ 2 ] or less at the maximum.
- FIG. 4 shows the electric field strength distribution in the depletion layer when a voltage is applied between the center electrode 50 and the outer peripheral electrode 60 with the IGBT turned off.
- the solid line shows the case where the p-type impurity surface density in the resurf region 34 has the distribution shown in FIG. 3, and the broken line shows the p-type impurity surface density in the resurf region 34 constant at the reference surface density N 0. The case where it has distribution is shown.
- the breakdown voltage of the semiconductor device 10 can be maximized under an ideal situation where there is no variation in the p-type impurity concentration.
- the p-type impurity concentration varies, the p-type impurity surface density of the RESURF region 34 deviates from the RESURF condition throughout, and the electric field strength distribution in the depletion layer greatly fluctuates. This greatly affects the breakdown voltage of the semiconductor device 10.
- the p-type impurity surface density in the resurf region 34 has the distribution shown in FIG. 3, and the electric field intensity distribution in the depletion layer is the maximum value in the vicinity of the reference position P. Distribution. Therefore, in an ideal situation where there is no variation in p-type impurity concentration, the breakdown voltage of the semiconductor device 10 is lower than when the p-type impurity surface density is constant at the reference surface density N 0 .
- the semiconductor device 10 of this embodiment even when the p-type impurity concentration varies, the position where the p-type impurity surface density becomes the reference surface density N 0 , that is, the reference position P moves to the center side or the outer periphery side. However, the electric field strength distribution in the depletion layer does not vary so much, and the breakdown voltage of the semiconductor device 10 is hardly affected.
- a semiconductor device 10 having high robustness against variations in p-type impurity concentration can be realized.
- a steep slope region is formed in a range closer to the center than the reference position P of the RESURF region 34.
- this steep region there are many surplus holes that are not involved in the formation of the depletion layer.
- the movement of the holes in the steep region compensates for the decrease in holes due to the adhesion of positive charges. Therefore, according to the semiconductor device 10 of the present embodiment, it is possible to suppress the influence on the breakdown voltage when a positive charge is attached as an external charge.
- FIG. 5 shows a semiconductor device when the p-type impurity surface density of the RESURF region 34 has the distribution shown in FIG. 3 (A) and when the gradient of the p-type impurity surface density of the RESURF region 34 is constant (B).
- 10 shows the relationship between the withstand voltage when a positive charge is attached and the withstand voltage when a negative charge is attached.
- the withstand voltage when a positive charge is attached and the withstand voltage when a negative charge is attached are in a trade-off relationship.
- the breakdown voltage at the time of positive charge adhesion can be improved without lowering the breakdown voltage at the time of negative charge adhesion.
- the breakdown voltage at the time of positive charge adhesion and the breakdown voltage at the time of negative charge adhesion can be improved beyond the trade-off limit when the gradient of the p-type impurity surface density of the RESURF region 34 is constant.
- the RESURF region 34 having the p-type impurity surface density distribution as described above can be formed by various methods.
- the RESURF region 34 having the p-type impurity surface density distribution as described above is formed by gradually decreasing the resist opening diameter at the time of p-type impurity implantation from the center side toward the outer peripheral side. Can do.
- the RESURF region 34 having the p-type impurity surface density distribution as described above can also be formed by gradually increasing the distance between the openings of the resist from the central side toward the outer peripheral side.
- the RESURF region 34 having the p-type impurity surface density distribution as described above can be formed by gradually reducing the thickness of the resist from the central side toward the outer peripheral side.
- the average slope in the range exceeding the reference areal density N 0 is, if the average steep than the slope in the range of less than the reference surface density N 0, as what distribution Also good.
- a distribution in which a steep slope region and a gentle slope region are switched may be used in a p-type impurity surface density higher than the reference surface density N 0 .
- the distribution may be such that the steep slope region and the gentle slope region are switched at a p-type impurity surface density lower than 0 .
- the distribution may be such that the p-type impurity surface density decreases stepwise, or as shown in FIG.
- the p-type impurity surface density decreases in a curved line. Also good. Furthermore, as shown in FIG. 10, although the p-type impurity surface density repeatedly increases and decreases locally, a distribution in which the p-type impurity surface density gradually decreases may be adopted. Moreover, as shown in FIG. 11, it is good also as distribution which switches to the steep slope area
- the corner portion 210 is more likely to concentrate an electric field than the straight portion 220, and the withstand voltage of the semiconductor device 10 is often determined according to the electric field strength distribution of the corner portion 210. Therefore, only the resurf region 34 in the corner portion 210 may have a p-type impurity surface density distribution as shown in FIG. 3, and the p-type impurity surface density in the resurf region 34 in the straight portion 220 may be constant. Alternatively, only the resurf region 34 in the corner portion 210 may have a p-type impurity surface density distribution as shown in FIG. 3 and the resurf region 34 in the straight portion 220 may have a constant gradient of p-type impurity surface density.
- the semiconductor device 300 according to the present embodiment has substantially the same configuration as the semiconductor device 10 according to the first embodiment.
- the same components as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the semiconductor device 300 according to the present embodiment includes a resurf region 310 instead of the resurf region 34 according to the first embodiment.
- the RESURF region 310 is composed of a p-type semiconductor having a low p-type impurity concentration.
- the RESURF region 310 is a surface layer region on the upper surface 24 side of the semiconductor layer 20 and is formed in the peripheral withstand voltage region 200. One end of the RESURF region 310 is in contact with the center electrode contact region 32.
- a low-concentration n-type region 30 exists between the outer peripheral electrode contact region 36 and the RESURF region 310.
- the peripheral electrode contact region 36 is separated from the RESURF region 310 by the low concentration n-type region 30.
- the RESURF region 310 has a hole concentration distribution shown in FIG. 13 in the depth direction from the surface at the end C on the outer peripheral side.
- the hole concentration at the end C on the outer peripheral side increases from the surface in the depth direction, then reaches a maximum value at the depth D 0 , and then decreases in the depth direction.
- the depth D 0 at which the hole concentration reaches the maximum value is 0.5 [ ⁇ m] from the surface.
- the depth D 0 at which the hole concentration becomes the maximum value is preferably 0.5 [ ⁇ m] or more from the surface.
- the semiconductor device 300 of this embodiment by forming the resurf region 310 as described above, it is possible to suppress the influence on the breakdown voltage of the semiconductor device 300 when external charges are attached.
- the carrier distribution in the resurf region 310 is disturbed, which affects the formation of the depletion layer, and reduces the breakdown voltage of the semiconductor device 300. End up.
- the breakdown voltage of the semiconductor device 300 depends on the maximum value of the hole concentration at the end C on the outer peripheral side of the RESURF region 310. If the maximum value of the hole concentration at the outer end C of the RESURF region 310 is reduced due to adhesion of external charges, the breakdown voltage of the semiconductor device 300 is reduced.
- the hole concentration has a maximum value at the depth D 0 at the outer peripheral end C of the RESURF region 310. Therefore, even when external charges are attached, The maximum value of does not change so much. With such a configuration, it is possible to suppress a decrease in breakdown voltage of the semiconductor device 300 due to adhesion of external charges.
- the semiconductor device 300 of the present embodiment is characterized in that the peak is arranged at a position deeper than the movement of the peak due to such segregation.
- the ion implantation amount is 1 ⁇ at an acceleration energy of 1 [MeV] to 5 [MeV] at the outer peripheral end C. It can be formed by setting it to 10 12 [cm ⁇ 2 ] to 5 ⁇ 10 13 [cm ⁇ 2 ].
- the surface concentration ratio ratio of the carrier concentration on the surface to the maximum value of the carrier concentration
- the hole concentration in the RESURF region 310 only needs to have a depth direction distribution as shown in FIG.
- the depth at which the hole concentration becomes maximum may be constant from the center side to the outer periphery side of the RESURF region 310.
- the depth at which the hole concentration becomes maximum may be gradually increased from the center side to the outer periphery side of the RESURF region 310.
- the depth at which the hole concentration becomes maximum may be irregularly increased or decreased from the center side to the outer periphery side of the RESURF region 310.
- the RESURF region 310 itself may be formed at a deep position as a whole away from the surface of the semiconductor layer 20. In the end portion C on the outer peripheral side of the RESURF region 310, it is only necessary that the depth direction distribution of the hole concentration has a maximum value at a position deeper than the surface.
- the upper end of the outer peripheral end C of the RESURF region 310 is formed. Further, a low concentration n-type region 312 may be further formed. Also in this case, in the end portion C on the outer peripheral side of the RESURF region 310, the hole concentration depth direction distribution can have a maximum value at a position deeper than the surface.
- the semiconductor device is configured such that the n-type impurity concentration in the low concentration n-type region 312 is higher than the p-type impurity concentration in the RESURF region 310 There is a possibility that the breakdown voltage of 300 is reduced.
- the n-type impurity concentration in the low-concentration n-type region 312 needs to be lower than the p-type impurity concentration in the RESURF region 310.
- the semiconductor device 400 according to the present embodiment has substantially the same configuration as the semiconductor device 10 according to the first embodiment.
- the same components as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the semiconductor device 400 according to the present embodiment includes a resurf region 410 instead of the resurf region 34 according to the first embodiment.
- the RESURF region 410 is composed of a p-type semiconductor having a low p-type impurity concentration.
- the RESURF region 410 is a surface layer region on the upper surface 24 side of the semiconductor layer 20 and is formed in the peripheral withstand voltage region 200.
- One end of the RESURF region 410 is in contact with the central electrode contact region 32.
- a low-concentration n-type region 30 exists between the outer peripheral electrode contact region 36 and the RESURF region 410.
- the peripheral electrode contact region 36 is separated from the RESURF region 310 by the low concentration n-type region 30.
- a polysilicon layer 412 is laminated above the end D on the outer peripheral side of the RESURF region 410.
- a p-type impurity of the same element as the p-type impurity in the RESURF region 410 is added to the polysilicon layer 412.
- the p-type impurity concentration in the polysilicon layer 412 is set lower than the p-type impurity concentration in the RESURF region 410 below the polysilicon layer 412.
- the polysilicon layer 412 is arranged as described above, and the semiconductor device 400 in the case where an external load is attached to the surface of the insulating layer 40 as in the semiconductor device 300 of the second embodiment. It is possible to suppress the influence on the withstand voltage. Since the polysilicon layer 412 is laminated above the end D on the outer peripheral side of the RESURF region 410, the depth at which the hole concentration reaches the maximum value in the RESURF region 410 is set to the thickness of the polysilicon layer 412. It can be a deep position. Thereby, even when an external load adheres to the surface of the insulating layer 40, the maximum value of the hole concentration at the end D on the outer peripheral side of the RESURF region 410 does not change so much. With such a configuration, it is possible to suppress a decrease in breakdown voltage of the semiconductor device 400 due to adhesion of external charges.
- the semiconductor device 400 according to the present embodiment does not need to implant impurities with high energy when forming the resurf region 410 and the polysilicon layer 412. For this reason, the damage which silicon receives at the time of impurity implantation can be reduced.
- carriers that pass through the low-concentration n-type region 30 from the back electrode contact region 38 and flow into the vicinity of the outer peripheral end D of the resurf region 410 are caused by the polysilicon layer 412. Be trapped. Carrier concentration in the vicinity of the outer peripheral end D of the RESURF region 410 can be suppressed, and the breakdown tolerance of the semiconductor device 400 can be improved.
- the polysilicon layer 412 may have any configuration as long as the p-type impurity concentration is lower than the p-type impurity concentration in the RESURF region 410 below the polysilicon layer 412.
- the polysilicon layer 412 may be p-type as a whole by adding only p-type impurities of the same element as the p-type impurity included in the RESURF region 410.
- the polysilicon layer 412 may be an n-type as a whole by adding more n-type impurities together with a p-type impurity of the same element as the p-type impurities included in the RESURF region 410.
- the n-type impurity of the polysilicon layer 412 is counter-doped, and the depth at which the hole concentration becomes the maximum value in the resurf region 410 is further increased. Can be deep.
- the polysilicon layer 412 may be stacked at least above the outer end D of the RESURF region 410.
- the polysilicon layer 412 is stacked only above the outer end D of the RESURF region 410.
- the p-type impurity concentration in the polysilicon layer 412 may be lower than the p-type impurity concentration in the resurf region 410 below the upper end D of the resurf region 410.
- the p-type impurity concentration in the polysilicon layer 412 may be higher than the p-type impurity concentration in the RESURF region 410 below it.
- the polysilicon layer 412 may be laminated on the upper surface 24 of the semiconductor layer 20, or a trench is formed in the upper surface 24 of the semiconductor layer 20, and the trench is filled with polysilicon. You may form by doing.
- the RESURF region 34 of the semiconductor device 10 of the first embodiment shown in FIG. 2 is formed so as to have the hole concentration distribution shown in FIG.
- FIG. That is, the polysilicon layer 412 shown in FIG. 15 may be stacked above the end A on the outer peripheral side of the resurf region 34 of the semiconductor device 10 of the first embodiment shown in FIG. Or it can also be set as the structure which combined all the characteristics of Example 1, 2, and 3.
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Abstract
Description
図1に示すように、本実施例の半導体装置10は、半導体素子が形成されている半導体素子領域100(セル領域に相当する)と、半導体素子領域100の周囲を取り囲む周辺耐圧領域200(非セル領域に相当する)を備える縦型半導体装置である。本実施例では、半導体素子領域100内に、IGBTが形成されている。なお、他の例においては、半導体素子領域100内に、例えば、MOSFETやダイオード等の他のパワー半導体素子が形成されていてもよい。半導体素子領域100は、半導体層20の略中央部に形成されており、周辺耐圧領域200は、半導体層20の外周端22に沿って形成されている。周辺耐圧領域200は、半導体層20の外周端22と半導体素子領域100との間の耐圧を確保するための領域である。
本実施例の半導体装置300は、実施例1の半導体装置10とほぼ同様の構成を備えている。以下では実施例1の半導体装置10と同様の構成については、同一の参照符号を付して詳細な説明を省略する。図12に示すように、本実施例の半導体装置300は、実施例1のリサーフ領域34の代わりに、リサーフ領域310を備えている。
本実施例の半導体装置400は、実施例1の半導体装置10とほぼ同様の構成を備えている。以下では実施例1の半導体装置10と同様の構成については、同一の参照符号を付して詳細な説明を省略する。図15に示すように、本実施例の半導体装置400は、実施例1のリサーフ領域34の代わりに、リサーフ領域410を備えている。
Claims (5)
- 縦型半導体装置であって、
セル領域と、前記セル領域の外側に配置された非セル領域を備えており、
前記非セル領域の少なくとも一部に拡散層を有しており、
前記拡散層では、前記縦型半導体装置を平面視したときに、前記セル領域に近い側の端部における不純物面密度が、リサーフ条件を満たす不純物面密度より高く、前記セル領域から遠い側の端部における不純物面密度が、リサーフ条件を満たす不純物面密度より低く、
前記拡散層では、前記縦型半導体装置を平面視したときに、リサーフ条件を満たす不純物面密度より低い不純物面密度の領域における不純物面密度の平均勾配に比べて、リサーフ条件を満たす不純物面密度より高い不純物面密度の領域における不純物面密度の平均勾配が大きいことを特徴とする縦型半導体装置。 - 前記拡散層では、前記セル領域から離れた側の端部におけるキャリア濃度の深さ方向分布が、表面よりも深い位置で極大値を有することを特徴とする請求項1の縦型半導体装置。
- 前記拡散層の前記セル領域から離れた側の端部の上方にポリシリコン層が積層されており、
前記ポリシリコン層の前記拡散層と同一導電型の不純物濃度が、その下方の前記拡散層における不純物濃度の最大値より低いことを特徴とする請求項1の縦型半導体装置。 - 縦型半導体装置であって、
セル領域と、前記セル領域の外側に配置された非セル領域を備えており、
前記非セル領域の少なくとも一部に拡散層を有しており、
前記拡散層では、前記セル領域から離れた側の端部におけるキャリア濃度の深さ方向分布が、表面よりも深い位置で極大値を有することを特徴とする縦型半導体装置。 - 縦型半導体装置であって、
セル領域と、前記セル領域の外側に配置された非セル領域を備えており、
前記非セル領域の少なくとも一部に拡散層を有しており、
前記拡散層の前記セル領域から離れた側の端部の上方にポリシリコン層が積層されており、
前記ポリシリコン層の前記拡散層と同一導電型の不純物濃度が、その下方の前記拡散層における不純物濃度の最大値より低いことを特徴とする縦型半導体装置。
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US13/640,447 US9035415B2 (en) | 2011-03-28 | 2011-03-28 | Vertical semiconductor device comprising a resurf structure |
EP11862776.9A EP2693483B1 (en) | 2011-03-28 | 2011-03-28 | Vertical-type semiconductor device |
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- 2011-03-28 JP JP2012524024A patent/JP5459403B2/ja active Active
- 2011-03-28 CN CN201180049802.6A patent/CN103155152B/zh active Active
- 2011-03-28 US US13/640,447 patent/US9035415B2/en active Active
- 2011-03-28 EP EP11862776.9A patent/EP2693483B1/en active Active
- 2011-03-28 WO PCT/JP2011/057670 patent/WO2012131878A1/ja active Application Filing
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Cited By (5)
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US9100000B2 (en) | 2011-09-21 | 2015-08-04 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
WO2014054319A1 (ja) * | 2012-10-02 | 2014-04-10 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2017028263A (ja) * | 2015-06-30 | 2017-02-02 | インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト | 半導体装置および半導体装置形成方法 |
US9768291B2 (en) | 2015-06-30 | 2017-09-19 | Infineon Technologies Austria Ag | Semiconductor device having a non-depletable doping region |
US10096704B2 (en) | 2015-06-30 | 2018-10-09 | Infineon Technologies Austria Ag | Semiconductor device having a non-depletable doping region |
Also Published As
Publication number | Publication date |
---|---|
CN103155152B (zh) | 2015-07-01 |
EP2693483A4 (en) | 2014-08-06 |
JP5459403B2 (ja) | 2014-04-02 |
JPWO2012131878A1 (ja) | 2014-07-24 |
CN103155152A (zh) | 2013-06-12 |
EP2693483B1 (en) | 2016-11-16 |
US20130037805A1 (en) | 2013-02-14 |
EP2693483A1 (en) | 2014-02-05 |
US9035415B2 (en) | 2015-05-19 |
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