WO2012124314A1 - 不揮発性記憶素子の駆動方法及び不揮発性記憶装置 - Google Patents
不揮発性記憶素子の駆動方法及び不揮発性記憶装置 Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H10N70/20—Multistable switching devices, e.g. memristors
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- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0073—Write using bi-directional cell biasing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
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- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Definitions
- the present invention relates to a method for driving a nonvolatile memory element and a nonvolatile memory device that implements the method.
- FIG. 22 is a cross-sectional view showing a configuration of a conventional example of such a nonvolatile memory element (see, for example, Patent Document 1 and Non-Patent Document 1).
- a transistor 1020 and a nonvolatile memory portion 1010 are formed on the main surface of a semiconductor substrate 1024.
- the transistor 1020 constitutes a circuit that controls conduction of the nonvolatile memory portion 1010 to the bit line, and includes a source region 1025b, a drain region 1025a, a gate insulating film 1026, and a gate electrode 1027.
- the nonvolatile memory unit 1010 includes a lower electrode 1002 connected to the drain region 1025a, a resistance change layer 1003 whose resistance is reversibly changed by a voltage pulse or a current pulse, and an upper electrode 1004. Further, the transistor 1020 and the nonvolatile memory portion 1010 formed over the semiconductor substrate 1024 are covered with an interlayer insulating film 1028, and the upper electrode 1004 is connected to the electrode wiring 1029.
- Patent Document 1 as a material constituting the resistance change layer 1003, nickel oxide (NiO), vanadium oxide (V 2 O 5 ), zinc oxide (ZnO), niobium oxide (Nb 2 O 5 ), titanium An oxide (TiO 2 ), tungsten oxide (WO 3 ), cobalt oxide (CoO), or the like is used. Such a transition metal oxide exhibits a specific resistance value when a voltage or current exceeding a threshold value is applied, and the resistance value maintains the resistance value until a new voltage or current is applied. It is known.
- PCMO Pr 1-x Ca x MnO 3
- Perovskite-type metal oxides are also known to exhibit the above resistance change characteristics.
- endurance characteristics may be a problem.
- the change in the resistance value of the variable resistance layer becomes unstable, so that a writing error is likely to occur.
- the present invention has been made in view of such circumstances, and a main object thereof is to provide a driving method of a nonvolatile memory element capable of improving endurance characteristics and a nonvolatile memory device that implements the method. It is in.
- a method for driving a nonvolatile memory element includes: a first terminal; a second terminal; and the first terminal.
- a variable resistance layer provided between the second terminal and a resistance value that reversibly changes in response to a voltage pulse applied between the first terminal and the second terminal.
- the resistance change element, the first input / output terminal connected to the second terminal, the second input / output terminal, and the conduction between the first input / output terminal and the second input / output terminal are controlled.
- a field effect transistor having a gate terminal, wherein the nonvolatile memory element is driven by applying a write voltage pulse having a first polarity between the first terminal and the second input / output terminal.
- An erase step for changing to a high resistance state wherein in the write step, the first input / output terminal is a source terminal, the write voltage pulse has a pulse width of PWLR, and the erase voltage pulse has a pulse width of In the case of PWHR, PWLR and PWHR satisfy the relationship of PWLR ⁇ PWHR.
- a stable memory operation can be realized. Further, according to the nonvolatile memory device according to the present invention that implements this driving method, a memory device having good endurance characteristics can be realized.
- FIG. 1 is a cross-sectional view showing a configuration of a variable resistance element included in the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 2 is a diagram showing current-voltage characteristics of the resistance change element included in the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 3 is a circuit diagram illustrating an example of the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention, where (a) is an equivalent circuit diagram of the nonvolatile memory element, and (b) is a diagram of the nonvolatile memory element.
- FIG. 4C is a circuit diagram of a variable resistance element provided, and FIG.
- FIG. 5C is a circuit diagram of a field effect transistor provided in a nonvolatile memory element.
- FIG. 4 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 5 is a diagram showing current-voltage characteristics of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 6 is a circuit diagram showing a configuration example of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 7 is a cross-sectional view showing a configuration example of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 4 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 5 is a diagram showing current-voltage characteristics of the nonvolatile memory element according to Embodiment 1 of the present invention.
- FIG. 6 is a circuit diagram showing a
- FIG. 8 shows the endurance of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 50 ns, the voltage value VHR of the erase voltage pulse is +2.0 V, and the pulse width PWHR is 300 ns. It is a graph which shows a characteristic.
- FIG. 9 shows the endurance of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 300 ns, the voltage value VHR of the erase voltage pulse is +2.0 V, and the pulse width PWHR is 50 ns. It is a graph which shows a characteristic.
- FIG. 10 shows the endurance of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 100 ns, the voltage value VHR of the erase voltage pulse is +1.8 V, and the pulse width PWHR is 100 ns. It is a graph which shows a characteristic.
- FIG. 11 is a graph showing the results of examining the endurance characteristics of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4V and the voltage value VHR of the erase voltage pulse is + 2.4V.
- FIG. 12 is a graph showing the results of examining the endurance characteristics of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +2.2 V. .
- FIG. 13 is a graph showing the results of examining the endurance characteristics of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +2.0 V.
- FIG. 14 is a graph showing the results of examining the endurance characteristics of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +1.8 V.
- FIG. 15 is a graph showing the endurance characteristics of the variable resistance element when the voltage value VLR of the write voltage pulse is ⁇ 2.2V and the voltage value VHR of the erase voltage pulse is + 2.2V.
- FIG. 16 is a graph showing the endurance characteristics of the resistance change element when the voltage value VLR of the write voltage pulse is ⁇ 2.2V and the voltage value VHR of the erase voltage pulse is + 1.7V.
- FIG. 17 is a graph showing the endurance characteristics of the variable resistance element when the voltage value VLR of the write voltage pulse is ⁇ 2.2V and the voltage value VHR of the erase voltage pulse is + 2.0V.
- FIG. 18 is a graph showing the endurance characteristics of the variable resistance element when the voltage value VLR of the write voltage pulse is ⁇ 2.2V and the voltage value VHR of the erase voltage pulse is + 2.3V.
- FIG. 19 is a graph showing the results of examining the quality of endurance characteristics.
- FIG. 20 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 21 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 22 is a cross-sectional view showing a configuration of a conventional nonvolatile memory element.
- the nonvolatile memory element includes a first terminal, a second terminal, and the first terminal and the second terminal.
- a resistance change element comprising: a resistance change layer that is reversibly changed in response to a voltage pulse applied between the first terminal and the second terminal; and An electric field comprising: a first input / output terminal connected to the terminal; a second input / output terminal; and a gate terminal for controlling conduction between the first input / output terminal and the second input / output terminal.
- the nonvolatile memory element is driven by applying a write voltage pulse having a first polarity between the first terminal and the second input / output terminal.
- the first input / output terminal is a source terminal
- the pulse width of the write voltage pulse is PWLR
- the pulse width of the erase voltage pulse is PWHR.
- PWHR satisfies the relationship PWLR ⁇ PWHR.
- the high resistance state of the variable resistance layer at the time of erasing can be changed to a dense high resistance state with less leakage current. Therefore, even when the write current value is limited by the substrate bias effect at the time of writing, an effective voltage for reducing the resistance can be sufficiently applied to the variable resistance layer. As a result, good endurance characteristics can be realized. In other words, the resistance value in the low resistance change state can be kept constant by the substrate bias effect, and a sufficient effective voltage can be applied for the resistance change.
- the absolute values of VLR and VHR may satisfy the relationship of
- the absolute values of VLR and VHR may satisfy the relationship of
- the current value when changing the variable resistance layer from the high resistance state to the low resistance state can be increased.
- good endurance characteristics can be realized.
- the resistance value in the low resistance change state can be kept constant by the substrate bias effect, and the current value limited by the substrate bias effect can be increased to a level sufficient to reduce the resistance.
- the resistance change layer may include tantalum oxide, and the absolute values of VLR and VHR may further satisfy a relationship of
- the field effect transistor may be an N-type MISFET, and the first polarity may be such that the potential of the second input / output terminal is higher than the potential of the first terminal.
- the N-type MISFET is the P-type.
- Current drive capability is larger than MISFET. Therefore, according to this aspect, when manufacturing MISFETs having the same current drive capability, the element size of the N-type MISFET can be reduced.
- the field effect transistor may be a P-type MISFET, and the first polarity may be such that the potential of the second input / output terminal is lower than the potential of the first terminal.
- variable resistance layer may include tantalum oxide.
- the variable resistance layer includes a first region containing an oxygen-deficient tantalum oxide having a composition represented by TaO x , and a second region having a composition represented by TaO y (where x ⁇ y). And a second region containing tantalum oxide.
- the resistance change phenomenon can be stably generated in the second region. it can.
- the nonvolatile memory device includes a first terminal, a second terminal, the first terminal provided between the first terminal and the second terminal, A resistance change element including a resistance change layer whose resistance value reversibly changes in response to a voltage pulse applied between the second terminal and a first input connected to the second terminal; A non-volatile memory element comprising: an output terminal; a second input / output terminal; and a field effect transistor including a gate terminal for controlling conduction between the first input / output terminal and the second input / output terminal.
- the first pole is between the first terminal and the second input / output terminal.
- the input / output terminal is a source terminal in the writing step, and the voltage application unit is configured such that PWLR and PWHR are PWLR when the pulse width of the write voltage pulse is PWLR and the pulse width of the erase voltage pulse is PWHR. ⁇ The write voltage and the erase voltage are applied to the nonvolatile memory element so as to satisfy the relationship of PWHR.
- the high resistance state of the variable resistance layer at the time of erasing can be changed to a dense high resistance state with less leakage current. Therefore, even when the write current value is limited by the substrate bias effect at the time of writing, an effective voltage for reducing the resistance can be sufficiently applied to the variable resistance layer. As a result, good endurance characteristics can be realized. In other words, the resistance value in the low resistance change state can be kept constant by the substrate bias effect, and a sufficient effective voltage can be applied for the resistance change.
- the voltage application unit has the relationship that the absolute values of VLR and VHR are
- the write voltage and the erase voltage may be applied to the nonvolatile memory element so as to satisfy the condition.
- the voltage application unit has a relationship in which the absolute values of VLR and VHR are
- the write voltage and the erase voltage may be applied to the nonvolatile memory element so as to satisfy the condition.
- the current value when changing the variable resistance layer from the high resistance state to the low resistance state can be increased.
- good endurance characteristics can be realized.
- the resistance value in the low resistance change state can be kept constant by the substrate bias effect, and the current value limited by the substrate bias effect can be increased to a level sufficient to reduce the resistance.
- variable resistance layer includes tantalum oxide
- the voltage application unit includes the nonvolatile memory so that the absolute values of VLR and VHR satisfy a relationship of
- the write voltage and the erase voltage may be applied to the memory element.
- the field effect transistor is an N-type MISFET, and the voltage application unit applies a voltage having a polarity such that the potential of the second input / output terminal is higher than the potential of the first terminal in the writing step. May be.
- the N-type MISFET is the P-type.
- Current drive capability is larger than MISFET. Therefore, according to this aspect, when manufacturing MISFETs having the same current drive capability, the element size of the N-type MISFET can be reduced.
- the field effect transistor is a P-type MISFET, and the voltage application unit applies a voltage having a polarity such that the potential of the second input / output terminal is lower than the potential of the first terminal in the erasing step. May be.
- variable resistance layer may include a transition metal oxide.
- the transition metal oxide may be selected from the group consisting of tantalum oxide, zirconium oxide, and hafnium oxide.
- the transition metal oxide has a first region including an oxygen-deficient transition metal oxide having a composition represented by MO x and a composition represented by MO y (where x ⁇ y). And a second region containing a transition metal oxide.
- the resistance change phenomenon can be stably generated in the second region. it can.
- the transition metal element M of the transition metal oxide may be selected from the group consisting of tantalum, zirconium, and hafnium.
- the transition metal oxide includes a first region including an oxygen-deficient transition metal oxide having a composition represented by MO x when the first transition metal is represented by M; the transition metal different from the second transition metal when expressed as N, and a second region including a transition metal oxide having a composition represented by NO y, the degree of oxygen deficiency of the NO y is The oxygen deficiency of MO x may be smaller.
- the standard electrode potential of the second transition metal N may be lower than the standard electrode potential of the first transition metal M.
- the resistance change phenomenon can be caused more stably.
- FIG. 1 is a cross-sectional view illustrating a configuration of a resistance change element 10 included in the nonvolatile memory element according to the present embodiment.
- a resistance change element 10 according to the present embodiment includes a substrate 1, a lower electrode 2 formed on the substrate 1, a resistance change layer 3 formed on the lower electrode 2, and And an upper electrode 4 formed on the resistance change layer 3.
- the lower electrode 2 and the upper electrode 4 are electrically connected to the resistance change layer 3.
- the substrate 1 is composed of, for example, a silicon substrate.
- the lower electrode 2 and the upper electrode 4 are, for example, one of Au (gold), Pt (platinum), Ir (iridium), Cu (copper), TiN (titanium nitride), and TaN (tantalum nitride) or Consists of a plurality of materials.
- the resistance change layer 3 includes a metal oxide.
- the resistance change layer 3 preferably includes an oxygen-deficient transition metal oxide. Thereby, a stable resistance change can be realized. More preferably, the resistance change layer 3 includes a first transition metal oxide layer 3a and a second transition metal oxide layer 3b having a higher oxygen content than the first transition metal oxide layer 3a. Configured. At this time, the second transition metal oxide layer 3b has a higher oxygen content than the first transition metal oxide layer 3a. That is, the second transition metal oxide layer 3b has a lower oxygen deficiency than the first transition metal oxide layer 3a. Moreover, the transition metal contained in the first transition metal oxide layer 3a and the transition metal contained in the second transition metal oxide layer 3b may be the same or different.
- variable resistance layer 3 corresponds to the first transition metal oxide layer 3a by a forming process (for example, a process of alternately applying a high resistance voltage pulse and a low resistance pulse).
- a forming process for example, a process of alternately applying a high resistance voltage pulse and a low resistance pulse.
- the first region and the second region corresponding to the second transition metal oxide layer 3b may be electrically formed.
- the resistance change phenomenon is considered to occur when a metal oxide having a plurality of oxidation states undergoes a state change due to a redox reaction.
- the oxidation-reduction reaction is generated by a voltage (or current) applied to the resistance change layer 3.
- a voltage equal to or higher than a predetermined threshold voltage or current equal to or higher than a predetermined threshold current
- the resistance change layer 3 has a stacked structure of the first transition metal oxide layer 3a and the second transition metal oxide layer 3b, the voltage applied to the resistance change layer 3 has a relatively high resistance value.
- the second transition metal oxide layer 3b is distributed more and the resistance change phenomenon is stably generated in the second transition metal oxide layer 3b. In this case, it is considered that the resistance of the entire second transition metal oxide layer 3b does not change, but a part of the second transition metal oxide layer 3b changes in resistance.
- the resistance change layer 3 illustrates a case where the first tantalum oxide layer 3a and the second tantalum oxide layer 3b are stacked. That is, the first tantalum oxide layer 3a is composed of an oxygen-deficient tantalum oxide. At this time, the oxygen content of the second tantalum oxide layer 3b is higher than the oxygen content of the first tantalum oxide layer 3a. In other words, the oxygen deficiency of the second tantalum oxide layer 3b is smaller than the oxygen deficiency of the first tantalum oxide layer 3a.
- the “oxygen deficiency” refers to the ratio of oxygen deficiency with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in each transition metal.
- the transition metal is tantalum (Ta)
- the stoichiometric oxide composition is Ta 2 O 5 , and thus can be expressed as TaO 2.5 .
- the degree of oxygen deficiency of TaO 2.5 is 0%.
- An oxide having a small oxygen deficiency has a high resistance because it is closer to an oxide having a stoichiometric composition.
- an oxide having a large oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.
- the oxygen content of Ta 2 O 5 is the ratio of oxygen to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.
- x is 0.8 or more and 1.9 or less
- y is It is desirable that it is 2.1 or more and 2.5 or less.
- x and y are within the above ranges, the resistance value of the resistance change layer 3 can be stably changed at high speed. Therefore, x and y are preferably within the above range.
- the thickness of the resistance change layer 3 is preferably 1 ⁇ m or less in order to obtain a change in resistance value. Furthermore, when the thickness of the resistance change layer 3 is 200 nm or less, the formation of the resistance change layer 3 by the patterning process can be simplified. Further, when the thickness of the resistance change layer 3 is 200 nm or less, the voltage value of the voltage pulse necessary for changing the resistance value of the resistance change layer 3 can be lowered. On the other hand, the thickness of the resistance change layer 3 is preferably at least 5 nm or more from the viewpoint of more reliably avoiding breakdown (dielectric breakdown) during voltage pulse application.
- the thickness of the second tantalum oxide layer 3b is disadvantageous in that the initial resistance value becomes too high if it is too large, and if it is too small, there is a disadvantage that a stable resistance change cannot be obtained. 8 nm or less is preferable.
- the resistance change layer 3 may be configured to include an oxygen-deficient transition metal oxide.
- hafnium oxide, zirconium oxide, or the like can be used.
- the oxygen content of the second transition metal oxide layer 3b (HfO y ) is 64.3 atm% or more and 66.7 atm. % Or less (1.8 ⁇ y ⁇ 2.0)
- the oxygen content of the first transition metal oxide layer 3a (HfO x ) which is a low-concentration oxygen-containing layer, is 47.4 atm% or more and 61 0.5 atm% or less (0.9 ⁇ x ⁇ 1.6) is preferable.
- the oxygen content of the second transition metal oxide layer 3b (ZrO y ), which is a high-concentration oxygen-containing layer, is 65.5 atm% or more and 66.7 atm. % Or less (1.9 ⁇ y ⁇ 2.0)
- the oxygen content of the first transition metal oxide layer 3a (ZrO x ) which is a low-concentration oxygen-containing layer is 47.4 atm% or more and 58 .3 atm% or less (0.9 ⁇ x ⁇ 1.4) is preferable.
- the transition metal constituting the first transition metal oxide layer 3a may be different from the transition metal constituting the second transition metal oxide layer 3b.
- the transition metal oxide constituting the resistance change layer 3 has a first region including an oxygen-deficient transition metal oxide having a composition represented by MO x and a composition represented by NO y. And a second region containing a transition metal oxide.
- the first transition metal is represented as M
- the second transition metal different from the first transition metal is represented as N.
- tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), or the like can be used.
- the standard electrode potential of the second transition metal constituting the second transition metal oxide layer 3b is smaller than the standard electrode potential of the first transition metal constituting the first transition metal oxide layer 3a.
- the standard electrode potential shows a characteristic that it is less likely to be oxidized as its value increases. That is, the standard electrode potential of the second transition metal constituting the second transition metal oxide layer 3b is made smaller than the standard electrode potential of the first transition metal constituting the first transition metal oxide layer 3a. Thus, the redox reaction in the second transition metal oxide layer 3b is more likely to occur.
- TiO 2 is used for the second transition metal oxide layer 3b, and oxygen-deficient tantalum oxide (TaO x , 0.8 ⁇ x ⁇ 1.9) is used for the first transition metal oxide layer 3a.
- oxygen-deficient tantalum oxide TaO x , 0.8 ⁇ x ⁇ 1.9
- the lower electrode 2 (TaN) is formed on the substrate 1 by sputtering. Thereafter, a first tantalum oxide layer 3a is formed on the lower electrode 2 by a so-called reactive sputtering method in which a Ta target is sputtered in argon gas and oxygen gas.
- the oxygen content in the first tantalum oxide layer 3a can be easily adjusted by changing the flow ratio of the oxygen gas to the argon gas.
- the substrate temperature can be set to room temperature without any particular heating.
- the outermost surface of the first tantalum oxide layer 3a is oxidized.
- a region having a high oxygen content (second tantalum oxide layer 3b) is formed on the surface of the tantalum oxide layer.
- a region where the oxidation has not progressed by the oxidation step that is, a region other than the second tantalum oxide layer 3b in the tantalum oxide layer is a region having a low oxygen content (first tantalum oxide layer 3a).
- the variable resistance layer 3 is constituted by the first tantalum oxide layer 3a and the second tantalum oxide layer 3b.
- the composition of the first tantalum oxide layer 3a (TaO x ) and the composition of the second tantalum oxide layer 3b (TaO y ) are within the range where the value of x is 0.8 or more and 1.9 or less ( 0.8 ⁇ x ⁇ 1.9), and when the value of y is adjusted within the range of 2.1 or more (2.1 ⁇ y), stable resistance change can be realized.
- the upper electrode 4 (Ir) is formed on the resistance change layer 3 by sputtering.
- size and shape of the lower electrode 2, the upper electrode 4, and the resistance change layer 3 can be adjusted with patterning process conditions.
- the resistance change element 10 is obtained through the above steps.
- the size of the upper electrode 4 and the resistance change layer 3 is 0.5 ⁇ m ⁇ 0.5 ⁇ m (area 0.25 ⁇ m 2 ), and the size of the portion where the lower electrode 2 and the resistance change layer 3 are in contact is also 0. 0.5 ⁇ m ⁇ 0.5 ⁇ m (area 0.25 ⁇ m 2 ).
- the thicknesses of the upper electrode 4 and the lower electrode 2 were both 50 nm.
- the thickness of the resistance change layer 3 was 50 nm, the thickness of the first tantalum oxide layer 3a was 44 nm, and the thickness of the second tantalum oxide layer 3b was 6 nm.
- the second tantalum oxide layer 3b may be formed by sputtering in an argon gas and an oxygen gas using a tantalum oxide target, or may be formed using a CVD method or an ALD method.
- FIG. 2 is a diagram showing current-voltage characteristics of the resistance change element 10 included in the nonvolatile memory element 30 according to the present embodiment.
- the horizontal axis indicates the voltage value of the upper electrode 4 with respect to the lower electrode 2
- the vertical axis indicates the current value flowing from the upper electrode 4 to the lower electrode 2.
- the mechanism of this resistance change is estimated as follows. First, in the second tantalum oxide layer 3b, a filament path that is a minute region that causes a resistance change is formed. When a voltage pulse in which the upper electrode 4 has a positive polarity is applied to the lower electrode 2, the filament path in the second tantalum oxide layer 3b receives oxygen ions from the first tantalum oxide layer 3a, and the second The tantalum oxide layer 3b is considered to have a high resistance. On the contrary, when a voltage pulse in which the upper electrode 4 has a negative polarity with respect to the lower electrode 2 is applied, the filament path in the second tantalum oxide layer 3b causes the received oxygen ions to pass through the first tantalum oxide layer 3a. It is considered that the resistance of the second tantalum oxide layer 3b is reduced.
- FIG. 3A is a circuit diagram showing a configuration of the nonvolatile memory element 30 including one transistor / 1 resistance change element (1T1R) according to the present embodiment.
- the nonvolatile memory element 30 includes a resistance change element 10 and a switching element (field effect transistor) 20.
- WL indicates a word line
- SL indicates a source line
- BL indicates a bit line.
- FIG. 3B is a circuit diagram showing a configuration of the variable resistance element 10 that constitutes the nonvolatile memory element 30.
- FIG. 3C is a circuit diagram illustrating a configuration of the field effect transistor 20 included in the nonvolatile memory element 30. In other words, when the variable resistance element 10 shown in FIG. 3B and the field effect transistor 20 shown in FIG. 3C are connected, the nonvolatile memory element 30 shown in FIG. 3A is obtained. .
- the resistance change element 10 is an element having a two-terminal structure in which the upper electrode 4 and the lower electrode 2 have terminals.
- One terminal 12 of the variable resistance element 10 is connected to one terminal 21 of the field effect transistor 20.
- one terminal 12 connected to the field effect transistor 20 is referred to as a second terminal 12, and the other terminal not connected to the field effect transistor 20.
- the terminal 11 is called the first terminal 11.
- the circuit diagram symbol of the resistance change element 10 shown in FIG. 3B is lower in resistance when a voltage pulse in which the first terminal 11 has a negative polarity with respect to the second terminal 12 is applied to the resistance change element 10.
- the resistance change layer 3 is increased in resistance.
- the field effect transistor 20 is an element having at least three terminals of a source terminal, a drain terminal, and a gate terminal.
- one terminal 21 connected to the resistance change element 10 is referred to as a first input / output terminal 21 and can be electrically connected to the first input / output terminal 21 by transistor operation.
- the other terminal 22 is referred to as a second input / output terminal 22.
- a terminal 23 that controls conduction between the first input / output terminal 21 and the second input / output terminal 22 is referred to as a gate terminal 23.
- the field effect transistor 20 has one of the first input / output terminal 21 and the second input / output terminal 22 serving as a source terminal and the other serving as a drain terminal.
- the source terminal or drain terminal
- the source terminal is determined by the direction of current flow and the polarity of carriers.
- the field-effect transistor 20 is, for example, a MISFET (metal-insulator-semiconductor field-effect transistor) or a MOSFET (metal-oxide-semiconductor field-effect transistor: Metal that is a kind of MISFET). -Oxide-Semiconductor (Field-Effect Transistor).
- the field effect transistor 20 may be simply referred to as the transistor 20.
- the field effect transistor 20 may be specifically referred to as a MISFET 20, an N-type MISFET 20, or a P-type MISFET 20 in accordance with the embodiment.
- variable resistance element 10 and the field effect transistor 20 have been described separately and independently, but this is an expression on the circuit diagram for simple explanation. Therefore, for example, the resistance change element 10 and the field effect transistor 20 may be integrated as a device.
- the first input / output terminal 21 of the field effect transistor 20 may also serve as the lower electrode 2 of the resistance change element 10.
- the second terminal 12 of the resistance change element 10 and the first input / output terminal 21 of the field effect transistor 20 may be electrically connected.
- another conductive member may be interposed between the variable resistance element 10 and the field effect transistor 20.
- FIG. 4 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element 30 according to the present embodiment.
- the nonvolatile memory element 30 includes a resistance change element 10 and a field effect transistor 20.
- FIG. 4 shows a case where the field effect transistor 20 is a MISFET 20 as an example.
- the resistance change element 10 includes the lower electrode 2, the resistance change layer 3, and the upper electrode 4 in the same manner as the resistance change element 10 illustrated in FIG. 1, and the resistance change layer 3 includes the first tantalum oxide layer 3a. And a second tantalum oxide layer 3b. Therefore, when a voltage pulse in which the upper electrode 4 has a negative polarity with respect to the lower electrode 2 is applied to the resistance change layer 3, the resistance change layer 3 is reduced in resistance. On the contrary, when a positive polarity voltage pulse is applied, the resistance change layer 3 is increased in resistance.
- the MISFET 20 includes a semiconductor substrate 24, a first diffusion layer 25a and a second diffusion layer 25b disposed on the semiconductor substrate 24, and a first diffusion layer 25a and a second diffusion layer 25b on the semiconductor substrate 24.
- a gate insulating film 26 disposed so as to straddle and a gate electrode 27 disposed on the gate insulating film 26 are provided.
- the MISFET 20 is also called a MOSFET.
- the MISFET 20 can be formed by various known methods.
- An interlayer insulating film 28 is formed on the MISFET 20, and a conductive via 29 is formed through the interlayer insulating film 28 to connect the lower electrode 2 of the resistance change element 10 and the first diffusion layer 25 a of the MISFET 20. Has been.
- the resistance change layer 3 increases in resistance.
- a positive polarity voltage pulse is applied, the resistance change layer 3 is lowered in resistance.
- the semiconductor substrate 24 and the first diffusion layer 25a and the second diffusion layer 25b are of the opposite conductivity type.
- the semiconductor substrate 24 is P-type
- the first diffusion layer 25a and the second diffusion layer 25b are N-type.
- the MISFET 20 is an N-type MISFET.
- the semiconductor substrate 24 is N-type
- the first diffusion layer 25a and the second diffusion layer 25b are P-type.
- the MISFET 20 is a P-type MISFET.
- FIG. 3A and FIG. 4 show connection relationships when the MISFET 20 is an N-type MISFET 20.
- the vertical arrangement of the resistance change layer 3 is opposite to the vertical arrangement of the resistance change layer 3 when the MISFET 20 is an N-type MISFET 20. Connected.
- the MISFET 20 when the MISFET 20 is N-type, majority carriers are electrons. On the other hand, when the MISFET 20 is P-type, the majority carriers are holes. In general, since the mobility of electrons is larger than the mobility of holes, when the MISFET 20 having the same gate insulating film 26 structure (material and film thickness) and the same size is formed, the N-type MISFET is more P Current drive capability is larger than type MISFET. Therefore, when manufacturing the MISFET 20 having the same current drive capability, the element size of the N-type MISFET can be reduced.
- the cross-sectional structure of the nonvolatile memory element 30 shown in FIG. 4 is an example, and the nonvolatile memory element 30 according to the present embodiment includes the structure of the resistance change element 10, the structure of the field effect transistor 20, and the resistance change element.
- the structure of the connection part between 10 and the field effect transistor is not limited to this.
- the field effect transistor 20 shown in FIGS. 3 and 4 will be described as an N-type MISFET 20 unless otherwise specified.
- the resistance state of the resistance change layer 3 can be changed as follows by applying a voltage to the nonvolatile memory element 30 using a power source or the like.
- a voltage pulse having a first polarity, a voltage value of VLR, and a pulse width of PWLR is applied between the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20 to thereby generate resistance.
- the change layer 3 is changed from the high resistance state to the low resistance state.
- this is called a write step
- a voltage pulse applied at this time is called a write voltage pulse
- a current flowing at this time is called a write current.
- the first polarity means the polarity of a voltage pulse required to change the resistance change layer 3 from the high resistance state to the low resistance state. For example, in the connection relationship shown in FIGS.
- the potential of the upper electrode 4 in the resistance change element 10 is relatively relative to the potential of the second diffusion layer 25 b of the N-type MISFET 20.
- the polarity of the voltage that decreases is the first polarity.
- the voltage applied to the resistance change element 10 is such that the upper electrode 4 has a negative polarity with respect to the lower electrode 2, so that the resistance change layer 3 changes from the high resistance state to the low resistance state.
- a voltage pulse having a second polarity different from the first polarity and a voltage value of VHR and a pulse width of PWHR is applied to the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20. Apply between. Thereby, the resistance change layer 3 is changed from the low resistance state to the high resistance state.
- this is called an erasing step
- a voltage pulse applied at this time is called an erasing voltage pulse
- a current flowing at this time is called an erasing current.
- the second polarity means the polarity of a voltage pulse required to change the resistance change layer 3 from the low resistance state to the high resistance state. For example, in the connection relationship shown in FIGS.
- the potential of the upper electrode 4 in the resistance change element 10 is relatively relative to the potential of the second diffusion layer 25 b of the N-type MISFET 20.
- the polarity of the voltage that becomes higher is the second polarity.
- the voltage applied to the resistance change element 10 is such that the upper electrode 4 has a positive polarity with respect to the lower electrode 2, so that the resistance change layer 3 changes from the low resistance state to the high resistance state.
- the nonvolatile memory element 30 operates by repeating the above writing step and erasing step.
- Whether the resistance change layer 3 is in a low resistance state or a high resistance state is determined by applying a voltage pulse for reading with a predetermined value (hereinafter referred to as a reading voltage pulse). Specifically, by applying a read voltage pulse between the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20, a current flowing through the resistance change layer 3 at this time (hereinafter referred to as the following) Whether the resistance change element 10 is in the high resistance state or the low resistance state is determined according to the current value of the read current).
- the magnitude (absolute value) of the voltage value applied to the resistance change element 10 by the read voltage pulse is smaller than the threshold voltage that causes a resistance change in the resistance change layer 3. Therefore, the read voltage pulse does not affect the resistance state of the resistance change element 10. For example, when the resistance change layer 3 is in a low resistance state, even if a read voltage pulse having the first polarity is applied between the resistance change element 10 and the transistor 20, the resistance state of the resistance change layer 3 does not change. , Maintained in a low resistance state. Similarly, when the resistance change layer 3 is in a high resistance state, even if a read voltage pulse having the second polarity is applied between the resistance change element 10 and the transistor 20, the resistance state of the resistance change layer 3 changes. Without being maintained in a high resistance state.
- the nonvolatile memory element 30 can be used as one memory cell. For example, a case where the resistance change layer 3 is in a low resistance state is associated with “1”, and a case where the resistance change layer 3 is in a high resistance state is associated with “0”, thereby forming a 1-bit memory cell.
- Non-volatile memory element connection and substrate bias effect The nonvolatile memory element 30 according to the present embodiment is connected so that the first input / output terminal 21 becomes a source terminal in the writing step.
- the terminal on the side connected to the resistance change element 10 among the terminals of the field effect transistor 20 is the source terminal.
- the “source” means a supply source of majority carriers in the field effect transistor 20.
- the “drain” means an inlet for majority carriers in the field effect transistor 20.
- the field effect transistor 20 is N-type, the majority carriers are electrons.
- the field effect transistor 20 is P-type, the majority carriers are holes.
- the source and the drain are switched depending on the direction in which the current flows.
- the source and the drain are reversed accordingly. That is, the source or drain in the writing step becomes the drain or source in the erasing step.
- the field effect transistor 20 is an N-type MISFET 20
- the first input / output terminal 21 is a drain terminal
- the input / output terminal 22 is a source terminal.
- the second input / output terminal 22 is a drain terminal.
- the field effect transistor 20 is a P-type MISFET 20
- the first input / output terminal 21 is a source terminal
- the input / output terminal 22 is a drain terminal.
- the on-current flows from the second input / output terminal 22 to the first input / output terminal 21
- the first input / output terminal 21 is a drain terminal
- the second input / output terminal 22 is a source terminal.
- the write voltage pulse applied to the nonvolatile memory element 30 in FIGS. 3A and 4 in the write step is the upper part in the resistance change element 10 as described above.
- the potential of the electrode 4 (the potential of the first terminal 11) is a voltage pulse relatively lower than the potential of the second diffusion layer 25b of the N-type MISFET 20 (the potential of the second input / output terminal 22).
- the current flows from the second input / output terminal 22 to the first input / output terminal 21, the second terminal 12, and the first terminal 11 in this order. That is, in the writing step, the first input / output terminal 21 of the N-type MISFET 20 becomes the source terminal.
- the erase voltage pulse applied to the nonvolatile memory element 30 in FIGS. 3A and 4 in the erase step has the opposite polarity to that in the write step.
- the second input / output terminal 22 of the MISFET 20 becomes a source terminal.
- the write voltage pulse applied to the nonvolatile memory element 30 is such that the potential of the upper electrode 4 in the resistance change element 10 (the potential of the first terminal 11) is the second diffusion of the P-type MISFET 20.
- the voltage pulse is relatively high with respect to the potential of the layer 25b (the potential of the second input / output terminal 22).
- the current flows in the order from the first terminal 11 to the second terminal 12, the first input / output terminal 21, and the second input / output terminal 22.
- the majority carriers flowing through the P-type MISFET 20 are holes. Therefore, in the write step, the first input / output terminal 21 of the P-type MISFET 20 becomes the source terminal.
- the erase voltage pulse applied to the nonvolatile memory element 30 in the erase step has a voltage polarity opposite to that in the write step, and therefore the second input / output terminal 22 of the P-type MISFET 20. Becomes the source terminal.
- the connection relationship of the nonvolatile memory element 30 of the present embodiment and the relationship between the substrate bias effect (body effect) will be described with reference to the nonvolatile memory element 30 of FIG. 3A and FIG.
- the influence of the substrate bias effect described below will be described by taking the case where the field effect transistor 20 is an N-type MISFET 20 as an example, but is not limited to the case where the field effect transistor 20 is an N-type MISFET 20 as will be described later.
- the write voltage applies a relatively low potential to the first terminal 11 of the resistance change element 10 and a relatively high potential to the second input / output terminal 22 of the N-type MISFET 20.
- the source potential of the N-type MISFET 20 (the potential of the first input / output terminal 21) is determined by the voltage dividing relationship between the on-resistance value of the N-type MISFET 20 and the resistance value of the resistance change element 10. Specifically, the source potential is higher than the first terminal 11 of the resistance change element 10 by the amount of voltage increase due to the resistance change element 10.
- the source potential of the N-type MISFET 20 (the potential of the second input / output terminal 22) is not affected by the voltage drop caused by the resistance change element 10, and is the potential applied to the second input / output terminal 22. It depends on. This is because the source terminal (second input / output terminal 22) of the N-type MISFET 20 is one end of the nonvolatile memory element 30.
- the source potential of the N-type MISFET 20 (the potential of the second input / output terminal 22) is maintained substantially the same as the potential of the semiconductor substrate 24. Therefore, the influence of the substrate bias effect generated in the MISFET 20 is small, and the on-current value of the N-type MISFET 20 can be relatively large. As a result, the value of the current flowing through the resistance change element 10 connected thereto can be relatively large.
- connection relation and the driving method are such that the write current is limited in the write step and a larger erase current is passed in the erase step. Thereby, the resistance change of the resistance change element 10 can be obtained stably. The reason will be described below.
- the resistance value of the resistance change layer 3 rapidly decreases.
- the increase in the current value of the write current flowing through the variable resistance element 10 proceeds rapidly.
- the current value is limited by using the substrate bias effect, these progresses can be kept in an appropriate state.
- the resistance value in the low resistance state can be kept at a constant low resistance value.
- the absolute value of the erase current is larger than the write current (current restricted when the resistance is lowered), and the write current is written.
- the current needs to have a polarity opposite to that of the current. Therefore, the high resistance state can be stably exhibited by reducing the substrate bias effect of the transistor and increasing the value of the current flowing through the transistor.
- FIG. 5 shows current-voltage characteristics of the nonvolatile memory element 30 according to the present embodiment.
- the nonvolatile memory element 30 according to the present embodiment has a voltage pulse having a voltage value larger than a certain value when the resistance change element 10 is reduced in resistance (in FIG. 5, ⁇ 1. Even if a voltage having an absolute value greater than 8V is applied, the value of the current flowing through the resistance change element 10 is limited, so that the resistance change element 10 remains in a substantially constant low resistance state (the current value is about ⁇ 170 ⁇ A). Around). The reason why the current flowing through the nonvolatile memory element 30 is almost constant even when the voltage applied to the nonvolatile memory element 30 is increased is that the transistor functions as a constant current source.
- the resistance change element 10 when the resistance change element 10 is increased in resistance, if a current (about 210 ⁇ A) equal to or higher than the current value that has flowed through the resistance change element 10 when the resistance change is reduced is passed through the resistance change element 10, a more stable high Shows resistance state.
- the nonvolatile memory element 30 When it is desired to develop a stable resistance change using the above-described substrate bias effect, the nonvolatile memory element 30 is connected so that the first input / output terminal 21 becomes the source terminal (so-called source follower) in the writing step. Connection) and is not limited to the configuration shown in FIGS. Hereinafter, other connection examples will be described.
- 6A to 6F include the nonvolatile memory element 30 including the nonvolatile memory element 30 described in FIG. 3, and the nonvolatile memory element 30 connected so that the first input / output terminal 21 becomes a source terminal.
- FIG. 3 the nonvolatile memory element 30 including the nonvolatile memory element 30 described in FIG. 3, and the nonvolatile memory element 30 connected so that the first input / output terminal 21 becomes a source terminal.
- 6A to 6C show a nonvolatile memory element 30 including an N-type MISFET 20 as the field effect transistor 20.
- the polarity of the write voltage pulse applied to the nonvolatile memory element 30 is such that the potential of the second input / output terminal 22 of the N-type MISFET 20 is higher than the potential of the first terminal 11 of the resistance change element 10.
- Polarity. 6A to 6C when a voltage pulse in which the first terminal 11 has a negative polarity with respect to the second terminal 12 is applied to the resistance change element 10. Any element may be used as long as it satisfies the condition that the resistance change layer 3 is increased in resistance when the resistance is lowered and a positive polarity voltage pulse is applied.
- the resistance change element 10 is desirably an element whose resistance value in a low resistance state is determined depending on the value of the current flowing through the resistance change element 10 in the writing step (reducing the resistance of the resistance change element 10). This is to make use of the current limiting effect due to the substrate bias effect.
- FIG. 6A shows a configuration of the resistance change element 10 and a connection example of the resistance change element 10 and the N-type MISFET when the field effect transistor 20 is an N-type MISFET in the configuration of FIG. 6B
- the resistance change element 10 has the same configuration as that in FIG. 6A, and the connection between the bit line and the source line is opposite to that in FIG. 6A.
- a connection example of an N-type MISFET is shown.
- the variable resistance element 10 has the same configuration as that of FIG. 6A, and the variable resistance element 10 and the N type when the source line is connected to a reference power source that supplies a fixed reference voltage.
- a connection example of MISFET is shown. In this case, the write state is controlled by increasing or decreasing the bit line voltage with respect to the reference voltage.
- FIGS. 6 (a) to 6 (c) show a nonvolatile memory element 30 including a P-type MISFET 20 as the field effect transistor 20.
- the resistance change element 10 is connected in the opposite direction to the resistance change element 10 shown in FIGS. 6 (a) to 6 (c). This is because the definition of the source and drain in the direction of current flow in the P-type MISFET 20 is opposite to the definition of source and drain in the direction of current flow in the N-type MISFET 20.
- the polarity of the write voltage pulse applied to the nonvolatile memory element 30 is such that the potential of the second input / output terminal 22 of the P-type MISFET 20 is the first of the resistance change element 10.
- the polarity is lower than the potential of the terminal 11.
- the resistance change element 10 shown in FIGS. 6D to 6F is obtained when a voltage pulse in which the first terminal 11 has a positive polarity with respect to the second terminal 12 is applied to the resistance change element 10. It is sufficient if the element satisfies the condition that the resistance change layer 3 is increased in resistance when the resistance is decreased and the negative polarity voltage pulse is applied.
- the resistance change element 10 is desirably an element whose resistance value in a low resistance state is determined depending on the value of the current flowing through the resistance change element 10 in the writing step (reducing the resistance of the resistance change element 10). This is to make use of the current limiting effect due to the substrate bias effect.
- the polarity of voltage and the direction of current flow in the write step and the erase step are opposite to those of the resistance change element 10 shown in FIG.
- the substrate voltage of the P-type MISFET is supplied with a high potential such as the power supply voltage VDD, for example.
- the nonvolatile memory element 30 in FIG. 6D is used as a memory cell
- the word line is selected when the memory cell is selected as compared with the case where the nonvolatile memory element 30 in FIG. 6A is used as a memory cell.
- the polarity of the applied voltage is reversed.
- Other control methods are the same as in the case of the N-type MISFET shown in FIG. FIG.
- 6E shows the variable resistance element 10 in the case where the variable resistance element 10 has the same configuration as in FIG. 6D and the connection relationship between the bit line and the source line is opposite to that in FIG.
- a connection example of the P-type MISFET 20 is shown.
- 6 (f) the variable resistance element 10 has the same configuration as that of FIG. 6 (e)
- a connection example of the MISFET 20 is shown. In this case, the write state is controlled by increasing or decreasing the bit line voltage with respect to the reference voltage.
- the nonvolatile memory element 30 shown in FIGS. 6A to 6F is merely an example, and the present embodiment can be applied to other connection examples.
- the reference power supply can be connected to the second input / output terminal 22 of the field effect transistor 20 by reversing the bit line and the reference potential.
- 7 (a) to 7 (f) are cross-sectional views showing examples of the configuration of the resistance change element 10 for realizing the circuits of FIGS. 6 (a) to 6 (f), respectively.
- 7A to 7C show, for example, the second tantalum oxide layer 3b having a high oxygen content on the upper electrode 4 side in the variable resistance layer 3, as in the configuration shown in FIG.
- the first tantalum oxide layer 3a having a low oxygen content is provided on the lower electrode 2 side.
- 7D to 7F for example, the first tantalum oxide layer 3a having a low oxygen content is formed on the upper electrode 4 side of the resistance change layer 3 contrary to the configuration shown in FIG.
- the second tantalum oxide layer 3b having a high oxygen content is provided on the lower electrode 2 side.
- the configuration of the variable resistance element 10 is not limited to this. As described above, it is only necessary that the first input / output terminal 21 is connected to be the source terminal. This connection relationship is determined by the polarity (current direction) of the voltage pulse applied to the resistance change element 10 and the direction of resistance change (low resistance or high resistance) of the resistance change element 10. In other words, the variable resistance element 10 may have any configuration, and the bipolar connection variable resistance element 10 can be applied by appropriately selecting the connection relationship. Therefore, the resistance change layer 3 may be a single layer or a laminated structure of two or more layers. In addition to tantalum oxide, a perovskite metal oxide such as PCMO can be used as the material of the resistance change layer 3. When the resistance change layer 3 is a single layer, the high resistance layer may be electrically formed by forming processing (for example, processing for alternately applying a high resistance voltage pulse and a low resistance pulse).
- zirconium (Zr) oxide, hafnium (Hf) oxidation is a material whose resistance value in the low resistance state of the resistance change layer 3 depends on the current value flowing through the resistance change layer 3.
- An oxygen-deficient transition metal oxide such as a product can be used.
- the oxygen-deficient transition metal oxide refers to a transition metal oxide having a lower oxygen content than the composition of a transition metal oxide (usually an insulator) having a stoichiometric composition.
- These materials can also have a laminated structure. In the laminated structure, a favorable resistance change can be realized by appropriately setting the oxygen content. Further, the direction of resistance change (low resistance or high resistance) of the resistance change layer 3 can be defined in advance.
- x is about 0.9 or more and 1.4 or less.
- y is preferably about 1.8 or more and 2.0 or less.
- x is 0.9 or more and 1.6 or less. It is preferable that y is about 1.89 or more and 1.97 or less.
- Non-volatile memory element drive voltage when the pulse width of the write voltage pulse is PWLR and the pulse width of the erase voltage pulse is PWHR, these pulse widths satisfy PWLR ⁇ PWHR.
- the pulse width is PWLR> PWHR
- the high resistance state of the resistance change layer 3 is a relatively high resistance state with a relatively large leakage current, and therefore the resistance change layer 3 is set to a low resistance at the time of writing.
- the effective voltage necessary for resistance cannot be sufficiently applied, and as a result, there is a problem that a phenomenon (hereinafter referred to as “HR sticking error”) that the resistance change layer 3 remains high and does not decrease in resistance is caused. is there.
- the resistance change layer 3 is made of tantalum oxide, it is desirable that the absolute values of the write voltage pulse and the erase voltage pulse satisfy
- FIG. 8 shows the endurance characteristic results of the resistance change layer 3 when the voltage value VLR and pulse width PWLR of the write voltage pulse and the voltage value VHR and pulse width PWHR of the erase voltage pulse are changed.
- FIG. 8 shows the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 50 ns, the voltage value VHR of the erase voltage pulse is +2.0 V, and the pulse width PWHR is 300 ns. It is a graph which shows an endurance characteristic.
- FIG. 9 shows the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 300 ns, the voltage value VHR of the erase voltage pulse is +2.0 V, and the pulse width PWHR is 50 ns. It is a graph which shows an endurance characteristic.
- FIG. 10 shows the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V, the pulse width PWLR is 100 ns, the voltage value VHR of the erase voltage pulse is +1.8 V, and the pulse width PWHR is 100 ns. It is a graph which shows an endurance characteristic. The number of repetitions on the horizontal axis is displayed in logarithm.
- E + 02 means 100, 1.
- E + 03 is 1000;
- E + 04 means 10,000.
- the nonvolatile memory element 30 shown in FIGS. 6A and 7A was used. That is, the field effect transistor 20 is an N-type MISFET 20. In this embodiment, the gate voltage Vg of the N-type MISFET 20 is 2.4V.
- the vertical axis indicates the current value of the read current that flows when the read voltage (0.4 V) is applied to the nonvolatile memory element 30, and the horizontal axis indicates the write step and the erase step. The number of repetitions when these are alternately repeated is shown. As for the number of repetitions, one cycle of the writing step and the erasing step is counted as one time.
- each point of the graph represents a distribution of read current values for a plurality of times for each point for convenience. Specifically, when the number of repetitions is 100 to 1000, the current value distribution of the read current when the writing step and the erasing step are repeated 34 times is shown for each point, and the number of repetitions is 1000 times. From 1 to 10,000 times, the current value distribution of the read current when the write step and the erase step are repeated 490 times is shown for each point. In the following, 10000 times as a reference for the number of repetitions in this embodiment is referred to as “reference endurance number”.
- the bar at each point indicates the distribution of the current value of the read current
- the circle at each point indicates the median value of the current value.
- the black circles indicate the median value of the read current after the write step
- the white circles indicate the median value of the read current after the erase step. .
- FIG. 8 is a graph showing the endurance characteristics of the resistance change layer 3 when PWLR is 50 ns and PWHR is 300 ns (PWLR ⁇ PWHR). As shown in FIG. 8, the HR sticking error did not occur up to the reference endurance number of 10,000 times, and the window was maintained. This indicates that good endurance characteristics can be realized when PWLR ⁇ PWHR.
- FIG. 9 is a graph showing the endurance characteristics of the resistance change layer 3 when PWLR is 300 ns and PWHR is 50 ns (PWLR> PWHR).
- the HR sticking error did not occur until the number of repetitions was 10,000, which is the reference endurance number.
- the reference endurance number of 10,000 there is a state in which the bar extending from the black circle to the bar extending from the white circle is close or overlapped. It was seen (see the part added as “no window” in FIG. 10).
- the fact that both bars are close or overlapped is referred to as “no window”, and the fact that both bars are sufficiently separated is referred to as “the window is present”.
- FIG. 10 shows that the stability of the storage operation is lowered due to a read error or the like.
- FIG. 11 to FIG. 14 are graphs showing the quality of endurance characteristics in which the results obtained by changing the combination of PWLR and PWHR are summarized with the PWHR on the vertical axis and the PWLR on the horizontal axis.
- the case where the HR sticking error does not occur until the reference endurance number reaches 10,000 times and the window is driven is indicated by a white circle symbol, and the HR until the reference endurance number reaches 10,000 times.
- a sticking error does not occur, a windowless state is indicated by a black triangle symbol, and a case where an HR sticking error occurs at a reference endurance of less than 10,000 times is indicated by a cross symbol. Yes.
- 11 to 14 show the case where the voltage value VLR of the write voltage pulse is ⁇ 2.4V and the voltage value of the erase voltage pulse is + 2.4V, + 2.2V, + 2.0V, and + 1.8V, respectively.
- 3 is a graph showing endurance characteristics of a resistance change layer 3. Further, the gate voltage Vg of the field effect transistor 20 was set to 2.4 V in all cases.
- FIG. 11 shows the endurance characteristics of the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +2.4 V (
- PWLR ⁇ PWHR the HR sticking error did not occur until the reference endurance number was reached, and the driving was performed with a window (white circle symbol).
- FIG. 12 shows the endurance characteristics of the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +2.2 V (
- the HR sticking error occurs when the HR sticking error occurs less than the reference endurance count (the symbol of the cross in FIG. 12), and the HR sticking error occurs until the reference endurance count is reached. Although there was no window, the result was a mixture of those without a window (black triangle symbol).
- FIG. 13 shows the endurance characteristics of the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +2.0 V (
- FIG. 14 shows the endurance characteristics of the resistance change layer 3 when the voltage value VLR of the write voltage pulse is ⁇ 2.4 V and the voltage value VHR of the erase voltage pulse is +1.8 V (
- PWLR> PWHR the HR sticking error did not occur until the reference number of endurances was reached, but a windowless state occurred (a black triangle symbol in FIG. 14).
- PWHR PWLR
- an HR sticking error does not occur until the reference endurance count is reached, and the drive is performed with a window (white circle symbol), and an HR sticking error occurs less than the reference endurance count (X The result was a mixture of symbols with a sign.
- PWLR ⁇ PWHR the HR sticking error did not occur until the reference endurance number was reached, and the driving was performed with a window (white circle symbol).
- the effect by having made PWLR ⁇ PWHR confirmed by the above-mentioned Example implement achieves a favorable endurance characteristic by applying sufficient effective voltage for resistance reduction to the resistance change layer 3. It is. Therefore, it is estimated that the same effect can be obtained not only in the resistance change material of the present embodiment but also in the case of using another resistance change material.
- FIG. 12 to 14 show results when the voltage value VLR of the write voltage pulse and the voltage value VHR of the erase voltage pulse satisfy
- FIG. 11 shows the result when the voltage value VLR of the write voltage pulse and the voltage value VHR of the erase voltage pulse satisfy
- the nonvolatile memory element 30 shown in FIGS. 6A and 7A is used. That is, the field effect transistor 20 is an N-type MISFET 20.
- the gate voltage Vg of the N-type MISFET 20 is 2.4 V
- the pulse width PWLR of the write voltage pulse and the pulse width PWHR of the erase voltage pulse are both 100 ns.
- the vertical axis indicates the current value of the read current that flows when the read voltage (0.4 V) is applied to the nonvolatile memory element 30, and the horizontal axis indicates the write step and the erase step. The number of repetitions when these are alternately repeated is shown. As for the number of repetitions, one cycle of the writing step and the erasing step is counted as one time.
- each point of the graph shows a distribution of read current values for a plurality of times for each point for convenience. Specifically, when the number of repetitions is 100 to 1000, the distribution of read current values when the writing step and the erasing step are repeated 34 times is shown for each point, and the number of repetitions is 1000 to 10,000. Shows the current value distribution of the read current when the write step and the erase step are repeated 490 times for each point. In the following, 1000 times and 10000 times that are used as the reference for the number of repetitions in this embodiment are referred to as “first reference endurance number” and “second reference endurance number”, respectively.
- the bar at each point indicates the distribution of the current value of the read current
- the circle at each point indicates the median value of the current value.
- the black circles indicate the median value of the read current after the write step
- the white circles indicate the median value of the read current after the erase step. .
- FIG. 15 is a graph showing the endurance characteristics of the resistance change layer 3 when VLR is ⁇ 2.2 V and VHR is +2.2 V (
- the high resistance state does not change from the high resistance state to the low resistance state even after the writing step is performed before the number of repetitions reaches 1000 which is the first reference endurance number. (See the part marked “HR sticking error” in FIG. 15). As described above, this indicates that, when
- FIG. 16 is a graph showing the endurance characteristics of the resistance change layer 3 when VLR is ⁇ 2.2 V and VHR is +1.7 V (
- FIG. 17 is a graph showing the endurance characteristics of the resistance change layer 3 when VLR is ⁇ 2.2 V and VHR is +2.0 V (
- FIG. 18 is a graph showing the endurance characteristics of the resistance change layer 3 when VLR is ⁇ 2.2 V and VHR is +2.3 V (
- FIG. 19 shows the endurance characteristics evaluated by changing the VLR in 0.2 V steps and the VHR values in 0.1 V steps, and the obtained results are shown with the vertical axis representing the absolute value of the VLR and the horizontal axis representing the VHR. It is the graph put together as an absolute value.
- a case where the HR sticking error does not occur until the second reference endurance number reaches 10,000 times is indicated by a white circle symbol, and the first reference endurance number from 1000 times to the second reference endurance number.
- the case where an HR sticking error occurs between 10,000 times is indicated by a white triangle symbol, and the case where an HR sticking error occurs when the HR sticking error occurs less than the first reference endurance number of 1000 times Is shown.
- the VLR step is 0.2 V and the VHR step is 0.1 V here, the voltage values of other steps may be used depending on the characteristics of the resistance change element 10.
- VLR and VHR are to suppress the sticking error by increasing the current value limited by the substrate bias effect. Therefore, it is presumed that the same effect can be obtained not only in the variable resistance material of the present embodiment but also when another variable resistance material is used.
- the value of 0.3 V is a value when the resistance change layer 3 includes tantalum oxide, and other resistance change materials may take different values. .
- + 0.3V is more desirable when PWLR PWHR.
- the voltage value for stabilizing the endurance characteristic is more preferably
- + 0.3V in the case of PWLR PWHR.
- the nonvolatile property causes a substrate bias effect in the transistor 20.
- the nonvolatile memory element 30 having good endurance characteristics can be realized by driving the pulse width PWLR of the write voltage pulse and the pulse width PWHR of the erase voltage pulse to satisfy PWLR ⁇ PWHR.
- the second embodiment is a non-volatile memory device including the one-transistor / 1 resistance change element (1T1R) including the non-volatile memory element 30 described in the first embodiment.
- the configuration and operation of this nonvolatile memory device will be described below.
- FIG. 20 is a block diagram showing an example of the configuration of the nonvolatile memory device 100 according to this embodiment.
- the nonvolatile memory device 100 includes a memory array 101 and a voltage application unit 102.
- the memory array 101 a plurality of nonvolatile memory elements described in Embodiment 1 are arranged in an array, and each nonvolatile memory element constitutes a memory cell.
- the voltage application unit 102 includes an address input circuit 103, a control circuit 104, a write power supply unit 105, and a memory drive circuit 106.
- the nonvolatile memory device 100 includes the memory main body 107, the address An input circuit 103, a control circuit 104, and a writing power supply unit 105 are provided.
- the memory driving circuit 106 selects a predetermined memory cell of the memory array 101 based on an address signal and a data signal input from the external circuit to the address input circuit 103 and the data input / output circuit 110, and from the write power supply unit 105 and the like. Predetermined data is programmed (that is, written) to the selected memory cell using the inputted write voltage and erase voltage, or information on the memory cell is read from the data input / output circuit 110 by applying a read voltage to the selected memory. , Output data to the outside.
- the memory drive circuit 106 includes, for example, a row selection circuit 108, a row driver 109, a data input / output circuit 110, a write circuit 111, a column selection circuit 112, a column driver 113, and a read circuit 114.
- the write power supply unit 105 sets a write voltage pulse and an erase voltage pulse.
- the write power supply unit 105 includes, for example, a pulse width setting circuit 115, an LR power supply 116, and an HR power supply 117.
- the pulse width setting circuit 115 functions as one block different from the LR power supply 116 and the HR power supply 117 will be described, but the present invention is not limited to this.
- the pulse width may be set for the power supply voltages output from the LR power supply 116 and the HR power supply 117, respectively.
- the memory array 101 includes two word lines W1 and W2 extending in the horizontal direction, two bit lines B1 and B2 extending in the vertical direction across the word lines W1 and W2, A matrix corresponding to each of the intersections of the two source lines S1, S2 extending in the vertical direction and corresponding to the bit lines B1, B2 and the word lines W1, W2 and the bit lines B1, B2.
- a matrix corresponding to each of the intersections of the two source lines S1, S2 extending in the vertical direction and corresponding to the bit lines B1, B2 and the word lines W1, W2 and the bit lines B1, B2. are provided with four memory cells MC111, MC112, MC121, MC122.
- each of these components is not limited to the above.
- four memory cells are described in the memory array 101 of FIG. 20 as described above, this is an example, and a configuration including five or more memory cells may be employed. In the following, a case where there are four memory cells will be described for the sake of simplicity.
- the above-described memory cells MC111, MC112, MC121, and MC122 include the nonvolatile memory element 30 in the first embodiment.
- the configuration of the memory array 101 will be further described with reference to FIG.
- a memory cell MC111 is provided between the bit line B1 and the source line S1, and the memory cell MC111 is formed of a nonvolatile memory element in which a transistor T111 and a resistance change element R111 are connected in series. More specifically, the transistor T111 is connected to the bit line B1 and the resistance change element R111 between the bit line B1 and the resistance change element R111.
- the resistance change element R111 is connected to the transistor T111 and the source line S1. In the meantime, the transistor T111 and the source line S1 are connected.
- the gate terminal of the transistor T111 is connected to the word line W1.
- connection states of the transistors T112, T121, T122 and the resistance change elements R112, R121, R122 that constitute the other three memory cells MC112, MC121, MC122 are the same as those of the transistor T111 and the resistance change element that constitute the memory cell MC111. Since it is the same as that of R111, description is abbreviate
- the address input circuit 103 receives an address signal from an external device (not shown), outputs a row address signal to the row selection circuit 108 based on the address signal, and outputs a column address signal to the column selection circuit 112.
- the address signal is a signal indicating the address of the selected memory cell among the memory cells MC111, MC112, MC121, and MC122.
- the row address signal is a signal indicating a row address among the addresses indicated by the address signal
- the column address signal is also a signal indicating a column address.
- the row selection circuit 108 receives the row address signal supplied from the address input circuit 103, and determines a word line (for example, word line W1) of a row to be selected based on the row address signal. Specifically, the row driver 109 is controlled to apply a predetermined voltage (gate voltage) for turning on the transistors (transistors T111 and T112). On the other hand, the row driver 109 applies a predetermined voltage for turning off the transistors constituting the memory cell to the word line (for example, the word line W2) of the non-selected row, or does not apply the voltage. To control.
- the row driver 109 includes a word line driver WLD connected to each word line, and a voltage is applied to the word line by the word line driver WLD.
- the column selection circuit 112 receives the column address signal supplied from the address input circuit 103, and determines the source line (for example, source line S1) and bit line (for example, bit line B1) of the column to be selected based on the column address signal. To do. Specifically, the column driver 113 is controlled so that a writing voltage, an erasing voltage, or a reading voltage is applied between the source line and the bit line, and a transistor connected between the source line and the bit line ( For example, a predetermined voltage (for example, source voltage / drain voltage) is applied to the transistors T111 and T121).
- a predetermined voltage for example, source voltage / drain voltage
- the column driver 113 is controlled to apply a non-selection voltage to the source line (for example, the source line S2) and the non-selected bit line (for example, the bit line B2) of the non-selected column.
- the column driver 113 includes a source line driver SLD connected to each source line, and a voltage is applied to the source line by the source line driver SLD.
- a memory cell for example, memory cell MC111 connected to a position where the selected row and column intersect is selected.
- the read circuit 114 determines whether the selected memory cell is in a low resistance state or a high resistance state, outputs this as a logical result, and determines the state of data stored in the memory cell. .
- the output data obtained here is output to an external device via the data input / output circuit 110.
- the read circuit 114 can also determine the level of the high resistance state (high resistance value). In this case, it is determined whether or not the high resistance value of the nonvolatile memory element exceeds a predetermined threshold value causing low resistance sticking, and information on the determination result is supplied to the control circuit 104.
- the write circuit 111 applies a write voltage corresponding to the input data input from the external device to the source line and the bit line selected by the column selection circuit 112 via the data input / output circuit 110.
- the control circuit 104 selects one of a write mode (corresponding to the above “write step” and “erase step”) and a read mode in accordance with a control signal received from the external device or the read circuit 114. select. Specifically, the control circuit 104 controls the write power supply unit 105 and the write circuit 111 so that data is written to the selected memory cell. Here, the control circuit 104 supplies a voltage / pulse width setting signal indicating the voltage level of the voltage pulse at the time of writing to the power supply unit 105 for writing.
- control circuit 104 In the write mode, the control circuit 104 outputs a control signal instructing “write voltage pulse application” to the write circuit 111 and the column driver 113 in accordance with the input data received from the external circuit.
- the control circuit 104 In the read mode, the control circuit 104 outputs a control signal instructing “read voltage pulse application” to the column driver 113. In this read mode, the control circuit 104 further receives a signal indicating the value of the current flowing through the source lines S1 and S2 from the column driver 113. This current value is measured by a sense amplifier or the like (not shown). The control circuit 104 converts the received signal into output data indicating a bit value and outputs it to an external device. This output data corresponds to the value of the write voltage pulse applied to the selected / unselected source line.
- the “write step” and “erase step” described in the first embodiment are executed in the write mode. Control is performed so that the pulse width PWLR of the write voltage pulse applied to each memory cell in the “write step” and the pulse width PWHR of the erase voltage pulse applied in the “erase step” satisfy PWLR ⁇ PWHR. Is done. Thereby, the non-volatile storage device 100 can realize good endurance characteristics.
- FIG. 21 is a block diagram showing a modified example of the configuration of the nonvolatile memory device according to the present embodiment.
- the nonvolatile memory device 200 in FIG. 21 is partially different in structure from the above-described nonvolatile memory device 100 and the memory main body 207.
- the configuration of the memory array 201 is different, and accordingly, the voltage application unit 202 including the memory drive circuit 206 is different.
- portions having the same configuration as the nonvolatile storage device 100 are denoted by the same reference numerals, and description thereof is omitted.
- adjacent two rows of memory cells are connected to a common source line extending in the horizontal direction.
- the memory cell MC211 and the memory cell MC221 adjacent to the memory cell MC211 are connected to the common source line S1.
- the source line driver SLD is disposed on the row driver 209 side.
- the row selection circuit 108 receives the row address signal supplied from the address input circuit 103, and determines a word line (for example, word line W1) and a source line (for example, source line S1) of a row to be selected based on the row address signal. To do. Specifically, a predetermined voltage (gate voltage) for turning on the transistors (transistors T211, T212, T213) is applied to a word line (for example, the word line W1), and a write voltage and an erase voltage are applied. The row driver 209 is controlled to apply a voltage or a read voltage to the source line (for example, the source line S1).
- a predetermined voltage gate voltage
- the row driver 209 is controlled to apply a voltage or a read voltage to the source line (for example, the source line S1).
- a predetermined voltage for turning off the transistors constituting the memory cell is applied to the word lines (for example, word lines W2, W3, W4) of the non-selected rows, or no voltage is applied.
- the row driver 209 is controlled. Further, the row driver 209 is controlled so that a non-selection voltage is applied to the source lines (for example, the source lines S1 and S2) of the non-selected rows.
- the column selection circuit 112 receives the column address signal supplied from the address input circuit 103, and selects a bit line of a column to be selected based on the column address signal. Specifically, a write voltage, an erase voltage, or a read voltage is applied to a bit line (for example, bit line B1) of a selected column, and a non-selected bit line (for example, bit lines B2 and B3) is applied. Apply a non-selection voltage.
- a memory cell for example, memory cell MC211 connected to a position where the selected row and column intersect is selected.
- the pulse width PWLR of the write voltage pulse and the pulse width PWHR of the erase voltage pulse can be controlled to satisfy PWLR ⁇ PWHR. Thereby, good endurance characteristics can be realized also in the nonvolatile memory device 200.
- the configuration and circuit configuration of the memory array in the second embodiment are examples, and are not limited to the above.
- a known circuit can be used as the circuit in each block diagram.
- a new embodiment can be realized by appropriately combining the above-described embodiment and a known configuration.
- the method for driving the nonvolatile memory element and the nonvolatile memory device according to the present invention have been described based on the embodiment.
- the present invention is not limited to this embodiment. Unless it deviates from the meaning of this invention, the form which carried out the various deformation
- nonvolatile memory element driving method and nonvolatile memory device are useful as a nonvolatile memory element driving method and memory device used in various electronic devices such as personal computers and portable telephones, respectively. .
Abstract
Description
[抵抗変化素子の構成]
まず、実施の形態1に係る不揮発性記憶素子が具備する抵抗変化素子の構成について説明する。
次に、抵抗変化素子10の製造方法の一例について説明する。
次に、上述したように構成された本実施の形態に係る抵抗変化素子10の特性について説明する。
図3(a)は、本実施の形態に係る1トランジスタ/1抵抗変化素子(1T1R)で構成される不揮発性記憶素子30の構成を示す回路図である。不揮発性記憶素子30は、抵抗変化素子10とスイッチング素子(電界効果トランジスタ)20を備える。なお、WLがワード線を、SLがソース線を、BLがビット線をそれぞれ示している。
次に、上述したように構成された不揮発性記憶素子30の駆動方法について説明する。なお、以下では、抵抗変化素子10の抵抗値が所定の高い値(例えば、20000Ω)にある場合を高抵抗状態といい、同じく所定の低い値(例えば、700Ω)にある場合を低抵抗状態という。また、本明細書中では、抵抗変化素子10(または抵抗変化層3)が高抵抗状態から低抵抗状態へ変化することを低抵抗化と呼び、低抵抗状態から高抵抗状態へ変化することを高抵抗化と呼ぶことがある。
本実施の形態に係る不揮発性記憶素子30は、書き込みステップにおいて、第1の入出力端子21がソース端子となるように接続されている。言い換えると、書き込みステップにおいて、電界効果トランジスタ20の端子のうち、抵抗変化素子10と接続されている側の端子が、ソース端子となっている。
上述の基板バイアス効果を利用して安定的な抵抗変化を発現させたい場合、不揮発性記憶素子30は、書き込みステップにおいて、第1の入出力端子21がソース端子となるように接続(いわゆるソースフォロワ接続)されていればよく、図3及び図4の構成に限らない。以下に、その他の接続例について説明する。
本実施の形態では、書き込み電圧パルスのパルス幅をPWLRとし、消去電圧パルスのパルス幅をPWHRとした場合に、それらパルス幅がPWLR<PWHRを満たすようにする。これにより、消去時における抵抗変化層3の高抵抗状態を、よりリーク電流の少ない緻密な高抵抗状態にすることができるため、書き込み時に、基板バイアス効果によって書き込み電流値が制限されたとしても、抵抗変化層3には低抵抗化のための実効電圧を十分印加することができる。その結果、良好なエンデュランス特性を実現できる。言い換えると、基板バイアス効果によって低抵抗変化状態の抵抗値を一定値に留め、かつ、抵抗変化のために十分な実効電圧を印加することができる。
実施の形態2は、実施の形態1において説明した不揮発性記憶素子30を備える、1トランジスタ/1抵抗変化素子(1T1R)で構成される不揮発性記憶装置である。以下、この不揮発性記憶装置の構成及び動作について説明する。
図20は、本実施の形態に係る不揮発性記憶装置100の構成の一例を示すブロック図である。図20に破線で示すように、不揮発性記憶装置100は、メモリアレイ101と、電圧印加ユニット102とを備える。メモリアレイ101は、実施の形態1で示した不揮発性記憶素子がアレイ状に複数配置されており、各不揮発性記憶素子がそれぞれメモリセルを構成する。電圧印加ユニット102は、アドレス入力回路103と、制御回路104と、書き込み用電源部105と、メモリ駆動回路106とを備える。
上記のとおり、本実施の形態に係る不揮発性記憶装置の場合、書き込みモードにおいて、実施の形態1において説明した「書き込みステップ」及び「消去ステップ」を実行する。そして、「書き込みステップ」において各メモリセルに対して印加する書き込み電圧パルスのパルス幅PWLRと、「消去ステップ」において同じく印加する消去電圧パルスのパルス幅PWHRとが、PWLR<PWHRを満たすように制御される。これにより、不揮発性記憶装置100は、良好なエンデュランス特性を実現できる。
図21は、本実施の形態に係る不揮発性記憶装置の構成の変形例を示すブロック図である。図21の不揮発性記憶装置200は、上述の不揮発性記憶装置100とメモリ本体部207の構造が一部異なる。具体的には、メモリアレイ201の構成が異なり、それに伴って、メモリ駆動回路206を含む電圧印加ユニット202が異なる。なお、不揮発性記憶装置100と構成が同じ部分については、同じ参照番号を付して、説明を省略する。
2,1002 下部電極
3,1003 抵抗変化層
3a 第1の遷移金属酸化物層(第1タンタル酸化物層)
3b 第2の遷移金属酸化物層(第2タンタル酸化物層)
4,1004 上部電極
10 抵抗変化素子
20,1020 電界効果トランジスタ(トランジスタ、MISFET)
24,1024 半導体基板
30,1030 不揮発性記憶素子
100,200 不揮発性記憶装置
101,201 メモリアレイ
102,202 電圧印加ユニット
103 アドレス入力回路
104 制御回路
105 書き込み用電源部
106,206 メモリ駆動回路
107,207 メモリ本体部
108 行選択回路
109,209 行ドライバ
110 データ入出力回路
111 書き込み回路
112 列選択回路
113 列ドライバ
114 読み出し回路
115 パルス幅設定回路
116 LR化用電源
117 HR化用電源
1010 不揮発性記憶部
1029 電極配線
Claims (20)
- 不揮発性記憶素子の駆動方法であって、
前記不揮発性記憶素子は、
第1の端子と、第2の端子と、前記第1の端子と前記第2の端子との間に設けられ前記第1の端子と前記第2の端子との間に印加される電圧パルスに応じて可逆的に抵抗値が変化する抵抗変化層と、を具備する抵抗変化素子と、
前記第2の端子に接続された第1の入出力端子と、第2の入出力端子と、前記第1の入出力端子と前記第2の入出力端子間の導通を制御するゲート端子と、を具備する電界効果トランジスタと、
を備え、
前記不揮発性記憶素子の駆動方法は、
前記第1の端子と前記第2の入出力端子間に第1の極性の書き込み電圧パルスを印加することにより、前記抵抗変化層を高抵抗状態から低抵抗状態へ変化させる書き込みステップと、
前記第1の端子と前記第2の入出力端子間に前記第1の極性とは異なる第2の極性の消去電圧パルスを印加することにより、前記抵抗変化層を低抵抗状態から高抵抗状態へ変化させる消去ステップと、
を含み、
前記書き込みステップにおいて、前記第1の入出力端子はソース端子であり、
前記書き込み電圧パルスのパルス幅をPWLRとし、前記消去電圧パルスのパルス幅をPWHRとした場合に、PWLR及びPWHRはPWLR<PWHRの関係を満たす、
不揮発性記憶素子の駆動方法。 - 前記書き込み電圧パルスの電圧値をVLRとし、前記消去電圧パルスの電圧値をVHRとした場合に、VLR及びVHRの絶対値は|VLR|=|VHR|の関係を満たす、
請求項1に記載の不揮発性記憶素子の駆動方法。 - 前記書き込み電圧パルスの電圧値をVLRとし、前記消去電圧パルスの電圧値をVHRとした場合に、VLR及びVHRの絶対値は|VLR|>|VHR|の関係を満たす、
請求項1に記載の不揮発性記憶素子の駆動方法。 - 前記抵抗変化層がタンタル酸化物を含んで構成され、
VLR及びVHRの絶対値は、さらに|VLR|>|VHR|+0.3Vの関係を満たす、
請求項3に記載の不揮発性記憶素子の駆動方法。 - 前記電界効果トランジスタはN型MISFETであり、
前記第1の極性は、前記第2の入出力端子の電位が前記第1の端子の電位よりも高くなる極性である、
請求項1~4のいずれか1項に記載の不揮発性記憶素子の駆動方法。 - 前記電界効果トランジスタはP型MISFETであり、
前記第1の極性は、前記第2の入出力端子の電位が前記第1の端子の電位よりも低くなる極性である、
請求項1~4のいずれか1項に記載の不揮発性記憶素子の駆動方法。 - 前記抵抗変化層がタンタル酸化物を含んで構成される、
請求項1~6のいずれか1項に記載の不揮発性記憶素子の駆動方法。 - 前記抵抗変化層は、TaOxで表される組成を有する酸素不足型のタンタル酸化物を含む第1の領域と、
TaOy(但し、x<y)で表される組成を有する第2のタンタル酸化物を含む第2の領域とを備える、
請求項7に記載の不揮発性記憶素子の駆動方法。 - 第1の端子と、第2の端子と、前記第1の端子と前記第2の端子との間に設けられ前記第1の端子と前記第2の端子との間に印加される電圧パルスに応じて可逆的に抵抗値が変化する抵抗変化層とを具備する抵抗変化素子と、
前記第2の端子に接続された第1の入出力端子と、第2の入出力端子と、前記第1の入出力端子と前記第2の入出力端子間の導通を制御するゲート端子とを具備する電界効果トランジスタと、
を備える不揮発性記憶素子と、
前記第1の端子と前記第2の入出力端子間に第1の極性の書き込み電圧パルスを印加することにより、前記抵抗変化層を高抵抗状態から低抵抗状態へ変化させる書き込みステップと、前記第1の端子と前記第2の入出力端子間に前記第1の極性とは異なる第2の極性の消去電圧パルスを印加することにより、前記抵抗変化層を低抵抗状態から高抵抗状態へ変化させる消去ステップとを実行する電圧印加ユニットと、
を備え、
前記第1の入出力端子は、前記書き込みステップにおいてソース端子であり、
前記電圧印加ユニットは、前記書き込み電圧パルスのパルス幅をPWLRとし、前記消去電圧パルスのパルス幅をPWHRとした場合に、PWLR及びPWHRがPWLR<PWHRの関係を満たすように、前記不揮発性記憶素子に前記書き込み電圧及び前記消去電圧を印加する、
不揮発性記憶装置。 - 前記書き込み電圧パルスの電圧値をVLRとし、前記消去電圧パルスの電圧値をVHRとした場合に、
前記電圧印加ユニットは、VLR及びVHRの絶対値が|VLR|=|VHR|の関係を満たすように、前記不揮発性記憶素子に前記書き込み電圧及び前記消去電圧を印加する、
請求項9に記載の不揮発性記憶装置。 - 前記電圧印加ユニットは、前記書き込み電圧パルスの電圧値をVLRとし、前記消去電圧パルスの電圧値をVHRとした場合に、VLR及びVHRの絶対値が|VLR|>|VHR|の関係を満たすように、前記不揮発性記憶素子に前記書き込み電圧及び前記消去電圧を印加する、
請求項9に記載の不揮発性記憶装置。 - 前記抵抗変化層は、タンタル酸化物を含んで構成され、
前記電圧印加ユニットは、VLR及びVHRの絶対値が|VLR|>|VHR|+0.3Vの関係を満たすように、前記不揮発性記憶素子に前記書き込み電圧及び前記消去電圧を印加する、
請求項11に記載の不揮発性記憶装置。 - 前記電界効果トランジスタはN型MISFETであり、
前記電圧印加ユニットは、書き込みステップにおいて、前記第2の入出力端子の電位が前記第1の端子の電位よりも高くなる極性の電圧を印加する、
請求項9~12のいずれか1項に記載の不揮発性記憶装置。 - 前記電界効果トランジスタはP型MISFETであり、
前記電圧印加ユニットは、消去ステップにおいて、前記第2の入出力端子の電位が前記第1の端子の電位よりも低くなる極性の電圧を印加する、
請求項9~12のいずれか1項に記載の不揮発性記憶装置。 - 前記抵抗変化層は、遷移金属酸化物を含んで構成されている、
請求項9~14のいずれか1項に記載の不揮発性記憶装置。 - 前記遷移金属酸化物は、タンタル酸化物、ジルコニウム酸化物およびハフニウム酸化物からなる群より選択される、
請求項15に記載の不揮発性記憶装置。 - 前記遷移金属酸化物は、
MOxで表される組成を有する酸素不足型の遷移金属酸化物を含む第1の領域と、
MOy(但し、x<y)で表される組成を有する遷移金属酸化物を含む第2の領域とを有している、
請求項15に記載の不揮発性記憶装置。 - 前記第1の領域及び前記第2の領域において、前記遷移金属酸化物の遷移金属元素Mが、タンタル、ジルコニウムおよびハフニウムからなる群より選択される、
請求項17に記載の不揮発性記憶装置。 - 前記遷移金属酸化物は、
第1の遷移金属をMと表した場合に、MOxで表される組成を有する酸素不足型の遷移金属酸化物を含む第1の領域と、
前記第1の遷移金属と異なる第2の遷移金属をNと表した場合に、NOyで表される組成を有する遷移金属酸化物を含む第2の領域とを有し、
前記NOyの酸素不足度は、前記MOxの酸素不足度より小さい、
請求項15に記載の不揮発性記憶装置。 - 前記第2の遷移金属Nの標準電極電位は、前記第1の遷移金属Mの標準電極電位より低い、
請求項19に記載の不揮発性記憶装置。
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