WO2012124191A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2012124191A1 WO2012124191A1 PCT/JP2011/070909 JP2011070909W WO2012124191A1 WO 2012124191 A1 WO2012124191 A1 WO 2012124191A1 JP 2011070909 W JP2011070909 W JP 2011070909W WO 2012124191 A1 WO2012124191 A1 WO 2012124191A1
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- semiconductor substrate
- semiconductor device
- leakage current
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 360
- 239000000758 substrate Substances 0.000 claims abstract description 191
- 230000002093 peripheral effect Effects 0.000 claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 84
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000002344 surface layer Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 24
- 230000000903 blocking effect Effects 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
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- 229910052751 metal Inorganic materials 0.000 description 7
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- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
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- 239000000470 constituent Substances 0.000 description 1
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Definitions
- the present invention relates to a semiconductor device.
- bidirectional switching elements to direct link type conversion circuits such as matrix converters.
- the matrix converter performs, for example, AC (AC) / AC conversion, AC / DC (DC) conversion, DC / AC conversion, and the like.
- Application of the bidirectional switching element to the direct link type conversion circuit has attracted attention because the circuit can be miniaturized, reduced in weight, increased in efficiency, increased in response speed, and reduced in cost.
- the matrix converter is characterized by higher power conversion efficiency than the inverter / converter.
- the inverter / converter generates an intermediate DC voltage from an AC power supply to further convert this intermediate voltage to an AC voltage, whereas the matrix converter directly generates AC intermediate power without generating an intermediate voltage. This is because an alternating voltage is generated.
- the inverter / converter uses an electrolytic capacitor for the capacitor that generates the intermediate voltage, there is a problem that the lifetime of the device is determined by the lifetime of the electrolytic capacitor.
- the matrix converter does not have to include a capacitor for generating an intermediate voltage between the AC power supply and the output part of the AC voltage, it is possible to avoid the above-mentioned problem occurring in the inverter / converter.
- FIG. 11 is an equivalent circuit diagram showing a matrix converter.
- FIG. 12 is an equivalent circuit diagram showing a conventional reverse blocking semiconductor device.
- FIG. 13 is a characteristic diagram showing the electrical characteristics of the conventional reverse blocking semiconductor device.
- a power semiconductor element 101 applied to a matrix converter as shown in FIG. 11 is a reverse blocking semiconductor device having a configuration in which two transistors 102 having reverse withstand voltages are connected in antiparallel as shown in FIG.
- the reverse blocking semiconductor device has a normal forward breakdown voltage (a positive voltage is applied to the drain with reference to the source potential), and has a reverse breakdown voltage (source potential) equal to the forward breakdown voltage. Apply a negative voltage to the drain as a reference).
- FIG. 14 is a cross-sectional view showing a conventional reverse blocking semiconductor device.
- the p well region 202, the n + source region 203, the gate oxide film 204, the gate electrode 205 and the source electrode 206 are provided on the front surface of the semiconductor substrate to be the n ⁇ drift region 201. And the like are provided.
- a p-type region hereinafter, referred to as FP: field plate
- a p-type region 208 in contact with the FP 207 and penetrating from the front surface to the back surface of the semiconductor substrate is provided on the side surface of the semiconductor substrate.
- a drain electrode 209 in contact with the n ⁇ drift region 201 is provided on the back surface of the semiconductor substrate.
- a MOS gate structure including a gate electrode and an emitter electrode is provided on one surface layer of an n -- type drift layer made of a semiconductor substrate having a GaN semiconductor or SiC semiconductor as a main semiconductor crystal. cut end surface for chips is, the n - having a p-type protective region connecting the front and back surfaces of the type drift layer, wherein the n - collector electrode shot in contact with the rear surface of the type drift layer key metal
- An apparatus having a membrane has been proposed (see, for example, Patent Document 1 below).
- a silicon substrate, a buffer layer formed on the silicon substrate, a gallium nitride semiconductor layer formed on the buffer layer, a silicon substrate and a buffer from the back surface of the silicon substrate A trench groove formed to a depth reaching the gallium nitride semiconductor layer through the layer and a metal film formed in the trench groove, and the metal film and the gallium nitride semiconductor layer form a Schottky junction
- Patent Document 2 An apparatus to be formed has been proposed (see, for example, Patent Document 2 below).
- the cut surface (hereinafter referred to as a side surface) of the semiconductor substrate cut into chips is of a conductivity type different from that of the semiconductor substrate by, for example, ion implantation and annealing. It is difficult to form a semiconductor region with a desired width and depth. For this reason, development of a semiconductor device having a configuration capable of easily obtaining reverse breakdown voltage is desired. Further, in the technique described in Patent Document 1 described above, when a reverse voltage is applied to the drain electrode, there is a possibility that the reverse leakage current may increase on the front surface side and the back surface side of the outer peripheral portion of the semiconductor substrate. When reverse leakage current occurs, there is a problem that reverse breakdown voltage decreases.
- An object of the present invention is to provide a semiconductor device having a high reverse breakdown voltage in order to solve the above-mentioned problems of the prior art.
- Another object of the present invention is to provide a semiconductor device capable of reducing the leakage current in order to solve the above-mentioned problems of the prior art.
- a semiconductor device comprises: a semiconductor substrate of a first conductivity type made of a semiconductor material having a wider band gap than silicon; A control electrode provided on the main surface of the semiconductor substrate, an output electrode provided on the second main surface and the side surface of the semiconductor substrate to form a Schottky junction with the semiconductor substrate, and at least an outer peripheral end of the semiconductor substrate And a layer for reducing leakage current generated from at least the outer peripheral end.
- the layer for reducing the leakage current is provided on a surface layer of the first main surface of the semiconductor substrate and has a second conductivity type in contact with the output electrode. It is characterized by being a first semiconductor region of
- the first semiconductor region forms an ohmic junction with the output electrode.
- the layer for reducing the leakage current is provided on a surface layer of the second main surface of the semiconductor substrate and is a second conductivity type in contact with the output electrode. And a second semiconductor region.
- the layer for reducing the leakage current is an insulating film covering a first main surface of the semiconductor substrate.
- the layer reducing the leakage current is an auxiliary electrode electrically connected to the output electrode.
- the layer for reducing the leakage current is in contact with the insulating film covering the first main surface of the semiconductor substrate and the output electrode;
- An auxiliary electrode provided across the surface of the insulating film, wherein the auxiliary electrode is in contact with the first semiconductor region exposed to the first main surface of the semiconductor substrate.
- the layer for reducing the leakage current is further provided on a surface layer of a second main surface of the semiconductor substrate and in contact with the output electrode.
- a second semiconductor region of a conductive type is included.
- the output electrode is provided across the outer peripheral end of the first main surface from the second main surface to the first main surface of the semiconductor substrate. It is characterized by
- a semiconductor device is characterized in that, in the above-mentioned invention, the semiconductor substrate is made of silicon carbide or gallium nitride.
- n consisting of the semiconductor substrate - and the drift region, as well as from the interface between the output electrodes provided on the back surface of the semiconductor substrate, n - drift region, provided on the side surface of the semiconductor substrate output A depletion layer also extends from the interface with the electrode. Therefore, it is possible to configure a reverse blocking semiconductor device configured to maintain reverse breakdown voltage without forming a p-type region (p-type region 208 in FIG. 14) on the side surface of the semiconductor substrate as in the prior art. Therefore, a semiconductor device having a reverse breakdown voltage can be configured more easily than a conventional semiconductor device.
- the semiconductor device further includes a layer for reducing the leakage current covering the n ⁇ drift region exposed on the front surface of the semiconductor substrate in the outer peripheral portion of the semiconductor substrate.
- the n ⁇ drift region and the output electrode are compared to the case where a semiconductor substrate made of silicon is used.
- the reverse breakdown voltage maintained by the Schottky junction can be improved.
- the reverse withstand voltage can be improved.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to the embodiment.
- FIG. 2 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 3 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 4 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 5 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 7 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 8 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to the embodiment.
- FIG. 2 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 3 is a cross-
- FIG. 9 is a cross-sectional view showing another example of the semiconductor device according to the embodiment.
- FIG. 10 is a characteristic diagram showing the electrical characteristics of the semiconductor device according to the embodiment.
- FIG. 11 is an equivalent circuit diagram showing a matrix converter.
- FIG. 12 is an equivalent circuit diagram showing a conventional reverse blocking semiconductor device.
- FIG. 13 is a characteristic diagram showing the electrical characteristics of the conventional reverse blocking semiconductor device.
- FIG. 14 is a cross-sectional view showing a conventional reverse blocking semiconductor device.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to the embodiment.
- the semiconductor device shown in FIG. 1 is provided with an active region 10 through which current flows when the semiconductor device is in an on state, and a breakdown voltage structure 11 surrounding the active region 10.
- the breakdown voltage structure portion 11 is provided on an outer peripheral portion of an n-type (first conductivity type) semiconductor substrate to be the n ⁇ drift region 1.
- This withstand voltage structure 11 is located to the left and right of the active region 10 as viewed in the cross-sectional view shown in FIG.
- the semiconductor substrate is made of a semiconductor material having a wider band gap than silicon (so-called "wide band gap semiconductor material").
- the semiconductor substrate is preferably made of, for example, silicon carbide (SiC) or gallium nitride (GaN).
- SiC silicon carbide
- GaN gallium nitride
- the semiconductor substrate made of a wide band gap semiconductor material it is possible to improve the reverse breakdown voltage maintained by a Schottky junction, which will be described later, as compared to the case where a semiconductor substrate made of silicon is used.
- a semiconductor substrate made of a wide band gap semiconductor material a semiconductor device with low loss and high efficiency can be manufactured as compared to the case where a semiconductor substrate made of silicon is used.
- the p-well region 2 is selectively provided in the surface layer of the front surface (first main surface) of the semiconductor substrate.
- An n + source region 3 is selectively provided in the surface layer of the p well region 2.
- a gate electrode 5 is provided via a gate oxide film 4 on the surface of the p well region 2 exposed on the front surface of the semiconductor substrate between the n ⁇ drift region 1 and the n + source region 3.
- Source electrode 6 is in contact with p well region 2 and n + source region 3.
- the source electrode 6 is insulated from the gate electrode (control electrode) 5 by an interlayer insulating film (not shown).
- an interlayer insulating film not shown.
- a drain electrode (output electrode) 7 in contact with the n ⁇ drift region 1 is provided from the back surface (second main surface) of the semiconductor substrate to a cut surface (hereinafter referred to as a side surface) of the semiconductor substrate cut into chips. There is.
- the drain electrode 7 is provided from the active region 10 to the breakdown voltage structure portion 11, and is provided on the entire back surface and side surface of the semiconductor substrate.
- Drain electrode 7 is provided to form a Schottky junction with n - drift region 1 formed of a semiconductor substrate, and a shot by drain electrode 7 and n - drift region 1 is formed on the entire back and side surfaces of the semiconductor substrate. A key junction is formed. Thereby, when a reverse voltage is applied to the drain electrode 7, a depletion layer extends from the interface between the n ⁇ drift region 1 and the drain electrode 7 on the back surface and the side surface of the semiconductor substrate. Therefore, the reverse breakdown voltage of the semiconductor device can be maintained.
- the side surface of the drain electrode 7 has, for example, a configuration (tapered shape) inclining with such an inclination that the width of the semiconductor substrate gradually increases from the back surface side (drain side) to the front surface side (source side). can do.
- the side surface of the drain electrode 7 is, for example, a configuration (tapered shape) in which the width of the semiconductor substrate gradually widens from the front surface side (source side) to the back surface side (drain side) And may be perpendicular to the front surface of the semiconductor substrate.
- a layer (hereinafter referred to as a leakage current reduction layer) 20 for reducing the leakage current from the outer peripheral end is provided as a withstand voltage structure 11 at least at the outer peripheral end of the semiconductor substrate.
- the leakage current reduction layer 20 is provided between at least the left and right outer peripheral ends of the withstand voltage structure 11 and the active region 10.
- a plurality of p-type guard rings or field limiting rings may be provided on the surface of the pressure-resistant structure portion 11. By providing these p-type guard rings and field limiting rings, the width of the pressure-resistant structure 11 can be narrowed.
- the n ⁇ drift region 1 is not exposed on the front surface of the semiconductor substrate in the withstand voltage structure 11. . Therefore, when a negative voltage (reverse voltage) is applied to the drain electrode 7 with reference to the source potential, carriers are not generated on the front surface side of the semiconductor substrate of the n ⁇ drift region 1 of the withstand voltage structure 11. Thereby, it is possible to reduce the leakage current (hereinafter referred to as a reverse leakage current) when applying the reverse voltage.
- a reverse leakage current the leakage current
- the outer peripheral end 20 a of the leakage current reduction layer 20 is provided in contact with the upper end 7 a of the drain electrode 7.
- n ⁇ between the outer peripheral end 20 a of the leak current reduction layer 20 and the upper end 7 a of the drain electrode 7 There is no gap where the drift region 1 is exposed.
- the leakage current reduction layer 20 may be, for example, a layer covering the surface of the front surface of the semiconductor substrate, or may be a layer provided inside the semiconductor substrate. Although not shown in FIG. 1, the leakage current reduction layer 20 surrounds the active region 10.
- FIGS. 2 and 4 show an example in which the leakage current reduction layer 20 is provided on the surface of the front surface of the semiconductor substrate.
- FIG. 3 shows an example in which the leakage current reduction layer 20 is provided on the surface layer of the front surface of the semiconductor substrate.
- the leakage current reduction layer 20 shown in the description of the semiconductor device shown in FIGS. 2 to 4 is an example of the leakage current reduction layer 20 shown in FIG. 1 (the same applies to the semiconductor device shown in FIGS.
- the leakage current reduction layer 20 shown in the description of the semiconductor device is the leakage current reduction layer 20 shown in FIG.
- the leakage current reduction layer 20 is an insulating film 21 covering at least the n ⁇ drift region 1 exposed on the front surface of the semiconductor substrate in the outer peripheral portion of the semiconductor substrate.
- the outer peripheral portion is a portion outside the active region 10 and indicates the pressure resistant structure portion 11.
- the gap is provided between the outer peripheral end 21 a of the insulating film 21 and the upper end 7 a of the drain electrode 7 without any gap for exposing the n ⁇ drift region 1.
- FIG. 2 the semiconductor device of the structure which provided the insulating film 21 as the leakage current reduction layer 20 is shown.
- n ⁇ drift region 1 p well region 2, n + source region 3, gate oxide film 4, gate electrode 5, source electrode 6 and drain electrode 7 which are other configurations are shown. It has the same arrangement as that of the semiconductor device shown in FIG.
- the insulating film 21 as the leakage current reduction layer 20 in the breakdown voltage structure portion 11 the n ⁇ drift region 1 exposed on the front surface of the semiconductor substrate can be reduced.
- generation of carriers at the outer peripheral portion of the semiconductor substrate can be suppressed, and an increase in reverse leakage current can be prevented.
- the leakage current reduction layer 20 is provided on the surface layer on the front surface of the outer peripheral portion of the semiconductor substrate and is in contact with the drain electrode 7 provided on the side surface of the semiconductor substrate. It is a mold region (first semiconductor region of the second conductivity type) 22.
- the first p-type region 22 is provided to be exposed at the outer peripheral end of the front surface of the semiconductor substrate.
- the gap is not provided between the outer peripheral end 22a of the first p-type region 22 and the upper end 7a of the drain electrode 7 so that the n ⁇ drift region 1 is not exposed.
- the protrusion of the first p-type region 22 is in the reverse direction to the depletion layer extending from the active region toward the breakdown voltage structure when forward bias is applied. , Suppresses the spread of the depletion layer and acts as a channel stopper. During reverse bias, the protrusion of the first p-type region 22 is forward with respect to the depletion layer extending from the drain electrode toward the active region, and the depletion layer can be expanded to reduce the electric field strength.
- the junction between the first p-type region 22 and the drain electrode 7 provided on the side surface of the semiconductor substrate is preferably an ohmic junction in order to stabilize the potential of the drain electrode 7.
- the semiconductor device shown in FIG. 3 has a configuration in which the first p-type region 22 is provided as the leakage current reduction layer 20, and other configurations such as n - drift region 1, p well region 2 and n + source region 3 are provided.
- the gate oxide film 4, the gate electrode 5, the source electrode 6, and the drain electrode 7 are arranged in the same manner as the semiconductor device shown in FIG. Further, an insulating film (not shown) may be provided on the semiconductor substrate between the first p-type region 22 and the p-well region 2.
- the depletion layer also extends from the pn junction portion formed of the first p-type region 22 and the n ⁇ drift region 1. Therefore, when a reverse voltage is applied to the drain electrode 7, it is possible to suppress the reverse leakage current generated from the corner portion 41 on the front surface side of the semiconductor substrate which is likely to generate the reverse leakage current.
- the corner portion 41 on the front surface side of the semiconductor substrate is the first edge at the outer peripheral end on the front surface side of the semiconductor substrate. The interface between the p-type region 22 and the drain electrode 7 in FIG.
- the drain electrode 23 is provided to extend from the side surface of the semiconductor substrate to the front surface of the semiconductor substrate so as to straddle the outer peripheral end of the front surface.
- the drain electrode 23 is provided on the whole of the back surface and the side surface of the semiconductor substrate, and on part of the front surface.
- the width of the folded portion 23a in which the drain electrode 23 straddles the front surface of the semiconductor substrate can be variously changed in accordance with the design conditions of the semiconductor device, and at least the corner 41 on the front surface side of the semiconductor substrate is covered. The width should be sufficient. In this case, a portion (folded portion 23 a) covering the outer peripheral portion of the front surface of the semiconductor substrate of the drain electrode 23 becomes the leakage current reduction layer 20.
- the semiconductor device shown in FIG. 4 has a configuration in which the folded portion 23a of the drain electrode 23 is provided as the leakage current reduction layer 20, and other configurations such as n - drift region 1, p well region 2 and n + source region 3 are provided.
- the gate oxide film 4, the gate electrode 5, the source electrode 6, and the drain electrode 23 are arranged in the same manner as the semiconductor device shown in FIG.
- the semiconductor substrate In the outer peripheral portion of the semiconductor substrate, it is exposed on the front surface of the semiconductor substrate from the end on the active region 10 side of the folded portion 23 a of the drain electrode 23 to the end on the breakdown voltage structure 11 side of the p well region 2.
- the width of the n ⁇ drift region 1 becomes shorter, the electric field strength in the vicinity of the end of the active region 10 on the side of the withstand voltage structure 11 becomes higher. Therefore, the width of the folded portion 23a of the drain electrode 23 may be variously changed in accordance with the design conditions of the semiconductor device.
- the n ⁇ drift region 1 and the turnback portion 23a of the drain electrode 23 on the front surface of the semiconductor substrate A depletion layer also extends from the interface. Therefore, when a reverse voltage is applied to the drain electrode 23, it is possible to suppress the reverse leakage current generated from the corner 42 on the front surface side of the semiconductor substrate which is likely to generate the reverse leakage current.
- the corner 42 on the front surface side of the semiconductor substrate corresponds to the outer peripheral edge on the front surface side of the semiconductor substrate.
- the leakage current reduction layer 20 includes the insulating film 21 and the first p-type region 22 described above, and the folded portion 23a of the drain electrode 23 provided across the outer peripheral portion of the front surface from the side surface of the semiconductor substrate.
- the leakage current reduction layer 20 includes the insulating film 21 and the first p-type region 22 described above, and the folded portion 23a of the drain electrode 23 provided across the outer peripheral portion of the front surface from the side surface of the semiconductor substrate.
- Various combinations may be provided.
- 5 to 9 are cross-sectional views showing another example of the semiconductor device according to the embodiment.
- the leakage current reduction layer 20 includes the insulating film 21 covering the n ⁇ drift region 1 exposed at least on the front surface of the semiconductor substrate and the front surface of the semiconductor substrate. It is a first p-type region 22 exposed at the outer peripheral end of the surface. In the semiconductor device shown in FIG. 5, the n ⁇ drift region 1 and the first p type region 22 are exposed on the front surface of the semiconductor substrate in the outer peripheral portion of the semiconductor substrate.
- the insulating film 21 may cover the n ⁇ drift region 1 and the first p type region 22 exposed on the front surface of the semiconductor substrate.
- the outer peripheral end 22a of the first p-type region 22 is provided in a state where there is no gap for exposing the n - drift region 1 between the upper end 7a of the drain electrode 7.
- the outer peripheral end 21 a of the insulating film 21 may be provided between the upper end 7 a of the drain electrode 7 and the space where the first p-type region 22 is exposed.
- the semiconductor device shown in FIG. 5 has a configuration in which insulating film 21 and first p-type region 22 are provided as leakage current reduction layer 20, and n ⁇ drift region 1, p well region 2 and n are other configurations.
- the + source region 3, the gate oxide film 4, the gate electrode 5, the source electrode 6, and the drain electrode 7 are configured in the same arrangement as the semiconductor device shown in FIG. 1.
- the leakage current reduction layer 20 includes the first p-type region 22 exposed at the outer peripheral end of the front surface of the semiconductor substrate and the outer peripheral portion of the front surface from the side of the semiconductor substrate.
- the folded portion 23 a of the drain electrode 23 straddles the In the semiconductor device shown in FIG. 6, the n ⁇ drift region 1 and the first p type region 22 are exposed on the front surface of the semiconductor substrate in the outer peripheral portion of the semiconductor substrate.
- a portion (folded portion 23a) provided on the front surface of the semiconductor substrate of the drain electrode 23 covers the first p-type region 22 exposed on the front surface of the semiconductor substrate.
- the outer peripheral end 22a of the first p-type region 22 is provided in a state where the n - drift region 1 is in contact with the folded portion 23a of the drain electrode 23 and there is no gap.
- the semiconductor device shown in FIG. 6 has a configuration in which the first p-type region 22 and the folded portion 23a of the drain electrode 23 are provided as the leakage current reduction layer 20, and other configurations are n - drift region 1 and p well.
- Region 2, n + source region 3, gate oxide film 4, gate electrode 5, source electrode 6, and drain electrode 23 are configured in the same arrangement as the semiconductor device shown in FIG.
- the first p-type region 22 causes the corner on the front surface side of the semiconductor substrate to easily generate reverse leakage current.
- the reverse leakage current generated from the part 41 can be suppressed.
- a reverse voltage is applied to the drain electrode 23 by the folded back portion 23 a of the drain electrode 23, the reverse leakage current generated from the corner 42 on the front surface side of the semiconductor substrate is easily generated. It can be suppressed.
- the leakage current reduction layer 20 is in contact with the insulating film 21 covering the n ⁇ drift region 1 exposed on the front surface of at least the semiconductor substrate in the outer peripheral portion of the semiconductor substrate It is the electrode 24.
- the insulating film 21 covers at least the corner 42 on the front surface side of the semiconductor substrate.
- the auxiliary electrode 24 is in contact with the drain electrode 7 and covers a part of the insulating film 21 across the surface of the insulating film 21 from the drain electrode 7. Since the auxiliary electrode 24 is not in contact with the n ⁇ drift region 1, it is not necessary to form a Schottky junction.
- the auxiliary electrode 24 functions as a field plate and weakens the electric field strength on the front surface side of the semiconductor substrate when a reverse voltage is applied to the drain electrode 7.
- the reverse breakdown voltage of the semiconductor device can be easily maintained.
- the outer peripheral end 21a of the insulating film 21 is provided between the upper end 7a of the drain electrode 7 and the space where the n - drift region 1 is exposed.
- the auxiliary electrode 24 is provided without any gap between the auxiliary electrode 24 and the upper end 7 a of the drain electrode 7 so as to be joined to the upper end 7 a of the drain electrode 7.
- the semiconductor device shown in FIG. 7 has a configuration in which insulating film 21 and auxiliary electrode 24 are provided as leakage current reduction layer 20, and n ⁇ drift region 1, p well region 2 and n + source region 3 are other configurations.
- the gate oxide film 4, the gate electrode 5, the source electrode 6, and the drain electrode 7 are arranged in the same manner as the semiconductor device shown in FIG.
- the insulating film 21 and the auxiliary electrode 24 As described above, by providing the insulating film 21 and the auxiliary electrode 24, generation of carriers at the outer peripheral portion of the semiconductor substrate can be suppressed by the insulating film 21, and an increase in reverse leakage current can be prevented. Further, when a reverse voltage is applied to the drain electrode 7 by the auxiliary electrode 24, the electric field strength of the front surface of the semiconductor substrate is reduced. Therefore, the reverse breakdown voltage of the semiconductor device can be easily maintained.
- the leakage current reduction layer 20 is an insulating film 21 covering the n ⁇ drift region 1 exposed on the front surface of at least the semiconductor substrate in the outer peripheral portion of the semiconductor substrate, and the front surface of the semiconductor substrate.
- the auxiliary electrode 25 electrically connected to the drain electrode 7.
- the n ⁇ drift region 1 and the first p type region 22 are exposed on the front surface of the semiconductor substrate in the outer peripheral portion of the semiconductor substrate.
- the insulating film 21 may cover a part of the first p-type region 22.
- the auxiliary electrode 25 is provided across the outer peripheral end of the front surface and the surface of the insulating film 21.
- the first p-type region 22 not covered by the insulating film 21 is covered by the auxiliary electrode 25.
- the semiconductor device shown in FIG. 8 differs from the semiconductor device shown in FIG. 7 in that it has a first p-type region 22 and a first p-type region 22 exposed on the front surface of the semiconductor substrate. It is a point where the auxiliary electrode 25 contacts.
- the auxiliary electrode 25 is in contact with the first p-type region 22 and provided across the surface of the insulating film 21 from the first p-type region 22 to have, for example, a step-like cross-sectional shape.
- the auxiliary electrode 25 is electrically connected to the drain electrode 7 provided on the side surface of the semiconductor substrate via the first p-type region 22.
- the auxiliary electrode 25 may or may not be in direct contact with the drain electrode 7 provided on the side surface of the semiconductor substrate.
- the outer peripheral end of the first p-type region 22 is provided between the upper end 7 a of the drain electrode 7 and the space where the n ⁇ drift region 1 is exposed.
- the insulating film 21 as a leakage current reducing layer 20 a structure in which a first p-type region 22 and the auxiliary electrode 25, as other constituent n - drift region 1, p-well Region 2, n + source region 3, gate oxide film 4, gate electrode 5, source electrode 6, and drain electrode 7 are configured in the same arrangement as the semiconductor device shown in FIG.
- the insulating film 21 suppresses generation of carriers in the outer peripheral portion of the semiconductor substrate by providing the insulating film 21, the first p-type region 22 and the auxiliary electrode 25.
- the reverse leakage current can be prevented from increasing.
- the first p-type region 22 is provided to suppress the reverse leakage current generated from the corner portion 41 on the front surface side of the semiconductor substrate which is likely to cause the reverse leakage current. be able to.
- the provision of the auxiliary electrode 25 can reduce the electric field strength on the front surface of the semiconductor substrate when a reverse voltage is applied to the drain electrode 7.
- the reverse breakdown voltage of the semiconductor device can be easily maintained.
- the semiconductor device shown in FIG. 9 is provided as a leakage current reduction layer 20 on the side surface of the semiconductor substrate and the surface layer on the back surface of the semiconductor substrate.
- a second p-type region (second semiconductor region of a second conductivity type) 26 in contact with the drain electrode 7 is provided.
- the second p-type region 26 is provided at the corner portion 43 on the back surface side of the semiconductor substrate, and is in contact with the drain electrode 7 provided on the side surface and the back surface of the semiconductor substrate.
- the corner 43 on the back surface side of the semiconductor substrate refers to the interface between the n ⁇ drift region 1 and the drain electrode 7 at the outer peripheral end on the back surface side of the semiconductor substrate when the second p-type region 26 is not provided. is there.
- the semiconductor device shown in FIG. 9 has a configuration in which a second p-type region 26 is further provided in addition to the insulating film 21, the first p-type region 22 and the auxiliary electrode 25 as the leakage current reduction layer 20.
- the n - drift region 1, the p well region 2, the n + source region 3, the gate oxide film 4, the gate electrode 5, the source electrode 6 and the drain electrode 7 are arranged in the same arrangement as the semiconductor device shown in FIG. It is done.
- the depletion layer also extends from the pn junction formed of the second p-type region 26 and the n ⁇ drift region 1. Therefore, when the reverse voltage is applied to the drain electrode 7, it is possible to suppress the reverse leakage current generated from the corner 43 on the back surface side of the semiconductor substrate which is likely to generate the reverse leakage current.
- the semiconductor device shown in FIGS. 5 to 8 described above the insulating film 21 provided as the leakage current reduction layer 20 in the semiconductor device shown in FIGS. 2 to 4, the first p-type region 22 and the folded portion of the drain electrode 23 It contains two or more of any of 23a. Therefore, the semiconductor device shown in FIGS. 5 to 8 can obtain an effect obtained by combining a plurality of effects obtained by the semiconductor devices shown in FIGS. 1 to 4. Specifically, in each case, the following effects can be obtained.
- the reverse direction to the drain electrode 7 is provided.
- a voltage is applied, generation of carriers at the outer peripheral portion of the semiconductor substrate can be suppressed, and an increase in reverse leakage current can be prevented.
- the first p-type region 22 exposed at the outer peripheral end of the front surface of the semiconductor substrate is provided (FIGS. 5, 6, and 8), and from the side surface of the semiconductor substrate to the outer peripheral portion of the front surface.
- the folded portion 23a of the drain electrode 23 is provided straddling (FIG. 6)
- the pn junction composed of the first p-type region 22 and the n - drift region 1, the n - drift region 1 and the drain A depletion layer also extends from the interface of the electrode 23 with the folded portion 23a. Therefore, when a reverse voltage is applied to the drain electrode 7, it is possible to suppress the reverse leakage current generated from the corner 41 on the front surface side of the semiconductor substrate.
- auxiliary electrodes 24 and 25 electrically connected to the drain electrode 7 are provided (FIGS. 7 and 8), when a reverse voltage is applied to the drain electrode 7 by the auxiliary electrodes 24 and 25, The electric field strength of the front surface of the semiconductor substrate can be reduced. Therefore, the reverse breakdown voltage of the semiconductor device can be easily maintained.
- the second p-type region 26 is provided at the corner 43 on the back side of the semiconductor substrate provided as the leakage current reduction layer 20 in the semiconductor device shown in FIG. You may provide.
- the depletion is also caused from the pn junction consisting of the second p-type region 26 and the n ⁇ drift region 1 Layers extend. Therefore, when a reverse voltage is applied to the drain electrode 7, it is possible to suppress the reverse leakage current generated from the corner 43 on the back surface side of the semiconductor substrate.
- the front and back surfaces of the semiconductor substrate forming the Schottky junction are preferably flat and clean in order to reduce reverse leakage current generated from the surface of the semiconductor substrate.
- the side surface of the semiconductor substrate in each configuration example described above may be perpendicular to the front surface of the semiconductor substrate or may be tapered.
- the side surface of the semiconductor substrate is inclined such that the width of the semiconductor substrate gradually increases from the back surface side (drain side) to the front surface side (source side)
- the structure was inclined.
- the interface of the semiconductor substrate in contact with the Schottky electrode needs to be processed into a flat and clean surface.
- the drain electrodes 7 and 23 are formed on the back surface and the side surface of the semiconductor substrate by sputtering or evaporation as compared with the case where the side surface of the semiconductor substrate is perpendicular to the front surface. It becomes easy to form.
- a metal film to be the drain electrodes 7 and 23 on the entire side surface of the semiconductor substrate as compared to the case where the side surface of the semiconductor substrate is perpendicular to the front surface. It becomes easy to form a film uniformly.
- annealing can be uniformly performed on the metal films to be the drain electrodes 7 and 23.
- the drain electrodes 7 and 23 can be formed on the side surfaces of the semiconductor substrate with good controllability.
- the side surface of the semiconductor substrate may be perpendicular to the front surface, as long as a metal film to be the drain electrodes 7 and 23 can be uniformly formed and annealed on the side surface of the semiconductor substrate. Further, the side surface of the semiconductor substrate may be perpendicular to the front surface as long as a Schottky junction can be formed by the drain electrodes 7 and 23 on the side surface of the semiconductor substrate.
- FIG. 10 is a characteristic diagram showing the electrical characteristics of the semiconductor device according to the embodiment.
- FIG. 10 shows reverse leakage current waveforms of the semiconductor device shown in FIGS. 1 to 9 described above.
- the horizontal axis of FIG. 10 is a voltage Vsd applied to the drain with reference to the source potential.
- the vertical axis in FIG. 10 is the leakage current Isd that flows when the voltage Vsd is applied to the drain.
- the voltage Vsd is positive when a negative voltage is applied to the drain.
- the leakage current Isd makes the current flowing from the source to the drain positive.
- a first curve 31 is a reverse leakage current waveform of the semiconductor device in which the leakage current reduction layer 20 is not provided.
- the semiconductor device in which the leakage current reduction layer 20 is not provided is a semiconductor device for verifying the effect of the leakage current reduction layer 20 provided in the semiconductor device according to the embodiment.
- the second curve 32 is a reverse leakage current waveform of the semiconductor device shown in FIGS.
- the third curve 33 is a reverse leakage current waveform of the semiconductor device shown in FIG.
- the semiconductor devices (the second curve 32 and the third curve 33) shown in FIGS. 1 to 9 are the same as the semiconductor device (the first curve 31) in which the leakage current reduction layer 20 is not provided.
- the reverse leakage current is smaller than that.
- the semiconductor device (third curve 33) shown in FIG. 9 has a smaller reverse leakage current than the semiconductor device (second curve 32) shown in FIGS. Thereby, the reverse leakage current is reduced more than the semiconductor device shown in FIGS. 1 to 8 by the extent that the semiconductor device shown in FIG. I was able to confirm that.
- the drain electrode 7 is provided from the back surface to the side surface of the semiconductor substrate.
- the drain electrode 7 forms a Schottky junction with the n ⁇ drift region 1 made of a semiconductor substrate.
- the depletion layer also extends from it. Therefore, it is possible to configure a reverse blocking semiconductor device configured to maintain reverse breakdown voltage without forming a p-type region (p-type region 208 in FIG. 14) on the side surface of the semiconductor substrate as in the prior art.
- the semiconductor device of the embodiment does not need to form a p-type region on the side surface of the semiconductor substrate as in the conventional semiconductor device. Therefore, as compared with the conventional semiconductor device in which the p-type region is formed on the side surface of the semiconductor substrate by ion implantation and annealing, for example, the reverse blocking semiconductor device can be easily formed only by forming the drain electrode 7 by sputtering or evaporation. You can get it.
- the reverse blocking semiconductor device can be easily manufactured as compared to the case of manufacturing the conventional semiconductor device (see FIG. 14). Further, according to the embodiment, by forming the side surface of the semiconductor substrate in a tapered shape, it is possible to manufacture a reverse blocking semiconductor device having a configuration in which the drain electrode 7 can be easily formed.
- the semiconductor device of the embodiment includes the leakage current reduction layer 20 covering the n ⁇ drift region 1 exposed to the front surface of the semiconductor substrate at the outer peripheral portion of the semiconductor substrate.
- reverse breakdown voltage maintained by a Schottky junction by n - drift region 1 and drain electrode 7 is improved as compared to the case of using a semiconductor substrate made of silicon. It can be improved. Specifically, when a semiconductor substrate made of silicon is used, the breakdown voltage maintained by the Schottky junction is about 200V. On the other hand, in the case of using a semiconductor substrate made of a wide band gap semiconductor material, the withstand voltage maintained by the Schottky junction can be about 1200 V.
- the present invention is not limited to the above-described embodiment, and various combinations of the insulating film to be the leakage current reduction layer, the first p-type region, the folded portion of the drain electrode, and the second p-type region can be used.
- a folded portion of the insulating film and the drain electrode may be provided as a leakage current reduction layer, and the folded portion of the drain electrode may be provided so as to cover a part of the surface of the insulating film.
- the first conductivity type is n-type and the second conductivity type is p-type, but the present invention similarly applies even if the first conductivity type is p-type and the second conductivity type is n-type You can get the effect of
- the semiconductor device according to the present invention is useful for a power semiconductor device used for a direct link type converter circuit such as a matrix converter.
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Abstract
Description
図1は、実施の形態にかかる半導体装置を示す断面図である。図1に示す半導体装置には、半導体装置がオン状態のときに電流が流れる活性領域10と、活性領域10を囲む耐圧構造部11とが設けられている。耐圧構造部11は、n-ドリフト領域1となるn型(第1の導電型)の半導体基板の外周部に設けられている。この耐圧構造部11は、図1に示す断面図でみて、活性領域10の左右に位置する。半導体基板は、シリコンよりもバンドギャップが広い半導体材料(いわゆる「ワイドバンドギャップ半導体材料」)からなる。
2 pウェル領域
3 n+ソース領域
4 ゲート酸化膜
5 ゲート電極
6 ソース電極
7 ドレイン電極
10 活性領域
11 耐圧構造部
20 漏れ電流低減層
Claims (10)
- シリコンよりもバンドギャップが広い半導体材料からなる第1導電型の半導体基板と、
前記半導体基板の第1の主面に設けられた制御電極と、
前記半導体基板の第2の主面および側面に設けられ、当該半導体基板とのショットキー接合を形成する出力電極と、
前記半導体基板の少なくとも外周端部に設けられ、少なくとも当該外周端部から生じる漏れ電流を低減する層と、
を備えることを特徴とする半導体装置。 - 前記漏れ電流を低減する層は、前記半導体基板の第1の主面の表面層に設けられた、前記出力電極に接する第2導電型の第1の半導体領域であることを特徴とする請求項1に記載の半導体装置。
- 前記第1の半導体領域は、前記出力電極とのオーミック接合を形成することを特徴とする請求項2に記載の半導体装置。
- 前記漏れ電流を低減する層は、前記半導体基板の第2の主面の表面層に設けられた、前記出力電極に接する第2導電型の第2の半導体領域であることを特徴とする請求項1に記載の半導体装置。
- 前記漏れ電流を低減する層は、前記半導体基板の第1の主面を覆う絶縁膜であることを特徴とする請求項1に記載の半導体装置。
- 前記漏れ電流を低減する層は、前記出力電極に電気的に接続された補助電極であることを特徴とする請求項1に記載の半導体装置。
- 前記漏れ電流を低減する層は、
前記半導体基板の第1の主面を覆う絶縁膜と、
前記出力電極に接し、当該出力電極から前記絶縁膜の表面に跨って設けられた補助電極と、からなり、
前記補助電極は、前記半導体基板の第1の主面に露出する前記第1の半導体領域に接することを特徴とする請求項2に記載の半導体装置。 - 前記漏れ電流を低減する層は、さらに、前記半導体基板の第2の主面の表面層に設けられた、前記出力電極に接する第2導電型の第2の半導体領域を含むことを特徴とする請求項7に記載の半導体装置。
- 前記出力電極は、前記半導体基板の第2の主面から第1の主面にかけて、第1の主面の外周端部に跨って設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体基板は、炭化珪素または窒化ガリウムからなることを特徴とする請求項1~9のいずれか一つに記載の半導体装置。
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DE112011105029.1T DE112011105029T5 (de) | 2011-03-14 | 2011-09-13 | Halbleitervorrichtung |
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US11081410B2 (en) | 2018-10-30 | 2021-08-03 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
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DE112015000206T5 (de) | 2014-10-03 | 2016-08-25 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
CN105023949A (zh) * | 2015-08-12 | 2015-11-04 | 无锡同方微电子有限公司 | 能实现反向阻断的mosfet |
EP3182463A1 (en) * | 2015-12-17 | 2017-06-21 | ABB Technology AG | Reverse blocking power semiconductor device |
CN105810723B (zh) * | 2016-03-21 | 2018-07-13 | 无锡紫光微电子有限公司 | 能实现反向阻断的mosfet的结构和方法 |
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JPWO2018034250A1 (ja) * | 2016-08-19 | 2019-07-11 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
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US9018633B2 (en) | 2015-04-28 |
DE112011105029T5 (de) | 2014-01-02 |
US20140061672A1 (en) | 2014-03-06 |
JPWO2012124191A1 (ja) | 2014-07-17 |
CN103370791B (zh) | 2016-09-14 |
JP5655932B2 (ja) | 2015-01-21 |
CN103370791A (zh) | 2013-10-23 |
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