WO2012100721A1 - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
WO2012100721A1
WO2012100721A1 PCT/CN2012/070629 CN2012070629W WO2012100721A1 WO 2012100721 A1 WO2012100721 A1 WO 2012100721A1 CN 2012070629 W CN2012070629 W CN 2012070629W WO 2012100721 A1 WO2012100721 A1 WO 2012100721A1
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WO
WIPO (PCT)
Prior art keywords
layer
package structure
chip
package
glue
Prior art date
Application number
PCT/CN2012/070629
Other languages
English (en)
French (fr)
Inventor
陶玉娟
石磊
高国华
杨国继
李红雷
沈海军
Original Assignee
南通富士通微电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN2011100322641A external-priority patent/CN102169879B/zh
Priority claimed from CN2011100323907A external-priority patent/CN102176452B/zh
Priority claimed from CN2011200321080U external-priority patent/CN201994277U/zh
Priority claimed from CN2011100324026A external-priority patent/CN102163603B/zh
Priority claimed from CN2011200320872U external-priority patent/CN202094109U/zh
Application filed by 南通富士通微电子股份有限公司 filed Critical 南通富士通微电子股份有限公司
Priority to US13/981,123 priority Critical patent/US9497862B2/en
Publication of WO2012100721A1 publication Critical patent/WO2012100721A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly, to a package structure.
  • Wafer Level Packaging (WLP) technology is a technology that performs a package test on a whole wafer and then cuts a single finished chip.
  • the packaged chip size is exactly the same as the chip.
  • Wafer-level chip-scale packaging technology revolutionizes traditional packaging such as Ceramic Leadless Chip Carriers and Organic Leadless Chip Carriers, and is increasingly light in the market for microelectronics. , small, short, thin and low-cost requirements.
  • the chip size after being packaged by wafer level chip size packaging technology is highly miniaturized, and the chip cost is significantly reduced as the chip size is reduced and the wafer size is increased.
  • Wafer-level chip-scale packaging technology is a technology that integrates IC design, wafer fabrication, package testing, and substrate manufacturing. It is a hot spot in the current packaging field and a trend in the future. Fan-out wafer packages are a type of wafer-level package.
  • Chinese invention patent application is a type of wafer-level package.
  • No. 200910031885.0 discloses a wafer level fan-out chip packaging method, comprising the following steps: sequentially covering a surface of a carrier wafer with a release film and a thin film dielectric layer I, forming a photolithographic pattern opening I on the thin film dielectric layer I; I and its surface realize a metal electrode and a rewiring metal trace connected to the substrate end; the surface of the metal electrode connected to the substrate end, the surface of the rewiring metal trace, and the surface of the thin film dielectric layer I cover the thin film dielectric layer, and Forming a lithographic pattern opening on the thin film dielectric layer II; forming a metal electrode connected to the chip end in the lithographic pattern opening II; flipping the chip to the metal electrode connected to the chip end, then molding the sealing layer and curing, forming a strip a package having a plastic sealing layer; separating the carrier wafer and the release film from the package with the molding compound layer to form a plastic sealing disc; the ball is reflowed to form a solder ball
  • the present invention provides a package structure comprising: a bonding layer of a carrier board and a surface thereof; a chip and a passive device attached to the bonding layer; and a chip formed on the carrier board and One side of the passive device is used to encapsulate the cured sealant layer.
  • the sealing layer is further filled in a space between the chip and the chip, between the chip and the passive device, and/or between the passive device and the passive device.
  • the thickness of the sealing layer is greater than the thickness of the thickest of the individual chips and passive components.
  • the passive device includes a capacitor, a resistor, and an inductor.
  • the material of the sealing layer is an epoxy resin.
  • the glue layer is a UV glue.
  • the chip comprises a plurality of different chips.
  • the carrier is a glass carrier.
  • the chip and the passive device are packaged devices, and the shape and position of the glue layer are adapted to the shape of the functional surface of the packaged device and the bonding position on the carrier.
  • the carrier board is further provided with an alignment portion.
  • the shape and size of the alignment portion are defined by a plurality of limiting portions.
  • the shape of the limiting portion includes a cross shape, a double line cross shape, a * shape, an L shape, a double line L shape, or a dot type.
  • the glue layer is composed of a plurality of glue blocks separated from each other.
  • At least two of the glue blocks have different shapes.
  • the shape of the glue block comprises a square, a rectangle or a circle.
  • the glue blocks are arranged in a matrix on the carrier.
  • the glue blocks are arranged at the same pitch on the carrier.
  • the pitch of the glue block is reserved according to an arrangement plan of the packaged device.
  • the chip and the passive device are encapsulated devices, and the surface of the sealing layer corresponds to a groove provided between the packaged devices.
  • each groove is closed around the package device.
  • the shape enclosed by each groove includes a square, a rectangle or a circle.
  • the same distance is maintained between each groove.
  • the cross section of the groove comprises a U-shape, a V-shape or a concave shape.
  • the depth of the groove is smaller than the thickness of the sealing layer.
  • the depth of the groove is greater than a difference in thickness between the sealing layer and the packaged device.
  • the surface of the sealing layer exposes a chip and a functional surface of the passive device
  • the package structure further includes: a metal rewiring layer electrically formed on the surface of the sealing layer and electrically connected to the chip and the functional surface of the passive device a protective film layer formed on a surface of the sealing layer, the protective film layer having an opening exposing the metal rewiring layer; and an under-ball metal layer formed in the opening and connected to the metal re-wiring layer; a metal solder ball formed on the under-metal layer of the ball.
  • the chip and the passive device are integrated and integrated, and thus are packaged products including the overall system function instead of a single chip function, compared to the existing system-level package.
  • the structure due to its high integration, reduces the interference factors such as resistance and inductance in the system, and is also more responsive to the trend of thinness and shortness of the semiconductor package.
  • the shape and position of the glue layer formed on the carrier board is adapted to the shape of the functional surface of the packaged device and the bonding position on the carrier board, thereby facilitating the mounting of the chip.
  • the positioning can avoid the difficulty of stripping or large-area cleaning in the subsequent process.
  • FIG. 1 is a schematic view showing a first embodiment of a package structure according to the present invention
  • FIG. 2 is a schematic flow chart of an embodiment of a package method
  • FIG. 3 to FIG. 10 are schematic diagrams showing a package structure in the flow shown in FIG.
  • Figure 11 is a schematic view of a second embodiment of the package structure of the present invention
  • Figure 12 is a schematic view of the first embodiment of the limit portion shown in Figure 11
  • Figure 13 is a schematic view of the second embodiment of the limit portion shown in Figure 11
  • Figure 11 is a schematic view of a third embodiment of the limiting portion shown in Figure 11
  • Figure 15 is a schematic view of a fourth embodiment of the limiting portion shown in Figure 11
  • Figure 16 is a schematic view of a third embodiment of the packaging structure of the present invention
  • 16 is a schematic view of an embodiment of a groove.
  • the package structure includes: a sealing layer 105, a chip 103 encapsulated in the sealing layer 105, and a passive device 104; a surface of the 105 exposes the functional surface of the chip 103 and the passive device 104; a metal re-wiring layer 106 formed on the surface of the sealing layer 105 and electrically connected to the chip 103 and the functional surface of the passive device 104; formed on the sealing layer a protective film layer 107 on the surface of the 105, the protective film layer 107 has an opening exposing the metal rewiring layer 106; a sub-spherical metal layer 108 formed in the opening and connected to the metal rewiring layer 106; The metal tin ball 109 on the under-metal layer 108.
  • the chip 103 and the passive device 104 are integrated and integrated and then packaged together, and thus are package products including overall system functions rather than a single chip function.
  • the package structure of the present invention will be further described below in conjunction with a specific package method embodiment.
  • FIG. 2 a schematic flowchart of an embodiment of a packaging method is shown, including the steps:
  • 5202 attaching a functional surface of the chip and the passive component to the glue layer; 5203, forming a sealing layer on a side of the carrier board with the chip and the passive component, and performing package curing;
  • step S201 is first performed to form a glue layer 102 on the carrier 101 to form a structure as shown in FIG.
  • carrier 101 is the basis for carrying subsequent chips 103 and passive components 104.
  • the carrier 101 is made of glass, which can provide better hardness and flatness, and reduce the failure ratio of the packaged device.
  • the carrier plate 101 made of glass is easily peeled off and has high corrosion resistance, and physical and chemical properties are not changed due to contact with the bonding layer 102, so that it can be performed. Reuse.
  • the carrier 101 can also achieve the objects of the present invention using, for example, a silicon compound.
  • the glue layer 102 formed on the carrier 101 is used to fix the chip 103 and the passive device 104 on the carrier 101.
  • the glue layer 102 can be selected from a variety of materials.
  • the glue layer 102 is made of UV glue.
  • UV glue is a kind of reaction that can respond to ultraviolet light of a specific wavelength.
  • UV glue can be divided into two kinds according to the change of viscosity after ultraviolet light irradiation.
  • One kind is UV curing glue, that is, the photoinitiator or photosensitizer in the material absorbs ultraviolet light under ultraviolet light to generate active radicals or cations.
  • Monomer polymerization, cross-linking and chemical reaction, the UV-curable adhesive is converted from a liquid to a solid in a few seconds to bond the surface of the object it is in contact with; the other is UV glue is not exposed to UV light.
  • step S202 can be performed to attach the functional surfaces of the chip 103 and the passive device 104 to the glue layer 102 to form a structure as shown in FIG.
  • the functional faces of the chip 103 and the passive device 104 refer to the surface of the metal electrode of the chip 103 and the pad of the passive device 104.
  • the plurality of chips 103 attached to the glue layer 102 may be a plurality of different chips, each of which becomes a part of a system-level package product, each performing system level functions.
  • the passive device 104 is an external circuit device that implements system-level functions of the packaged product together with the chip 103, including capacitors, resistors, and inductors. By combining the passive device 104 with the differently functioning chips 103, the required system level functionality can be achieved.
  • the combination of chip 103 and passive device 104 is based on System features are designed. Therefore, around a chip 103, there may be the same or different additional chips 103, or passive components 104 of the same or different capacitance, resistance or inductance; similarly, around a passive device 104, there may be The same or different other passive devices 104, or one or more identical or different chips 103.
  • step S203 the carrier surface on which the chip and the passive device are attached is packaged and cured by a molding material layer to form a package body with the sealing layer 105, that is, a structure as shown in FIG. 5 is formed.
  • the package protects the surface of the chip 103 and other functional surfaces of the passive device 104, and serves as a carrier for subsequent processes.
  • the material forming the sealant layer 105 is an epoxy resin. This material has good sealing properties and is easy to mold, and is a preferred material for forming the sealing layer 105.
  • the method of forming the sealing layer 105 can be, for example, a method of infusion or printing. The specific steps of these methods are well known to those skilled in the art and will not be described herein.
  • the sealing layer 105 is also filled between the chip 103 and the chip 103, between the chip 103 and the passive device 104, and/or the passive device 104 and passive components. The space between 104.
  • the thickness of the sealing layer 105 should be greater than the thickness of the thickest of the individual chips 103 and the passive devices 104 to provide the most for the chip 103 and the passive device 104. Good protection.
  • the glue layer 102 is removed. Since the glue layer 102 is an organic material, it can be dissolved in a specific organic solvent. Therefore, the organic solvent cleaning method can be employed to dissolve the glue layer 102 in an organic solvent.
  • step S205 is performed to separate the carrier 101 from the functional faces of the chip 103 and the passive device 104. That is, after the step S204 is performed, the glue layer 102 has been dissolved, or in a strippable molten state, the carrier 101 can be easily peeled off from the functional surface of the chip 103 and the passive device 104, thereby The functional faces of the chip 103 and the passive device 104 are exposed.
  • step S206 the functional surface of the chip 103 and the passive device 104 are cleaned, and the glue layer 102 remaining on the functional surface is formed into a structure as shown in FIG. 6.
  • the chip 103 and the passive device 104 are no longer transmitted through the carrier. They are fixed together and are fixed together by the package, and the metal electrodes of the chip and the pads of the passive device are also exposed.
  • the step S207 to the step S210 are further performed, including: performing metal rewiring 106 on the exposed functional surface of the chip 103 and the passive device 104, so that the metal electrode and the passive device 104 of the chip 103 are provided.
  • the pads are interconnected and routed through the re-wired metal lines; a protective film 107 is formed on the surface of the metal rewiring 106, and an opening required for the design is formed on the protective film 107 to expose the metal rewiring 106;
  • a sub-spherical metal layer 108 is formed on the metal rewiring 106 in the opening of the protective film; a metal tin ball 109 is formed on the surface of the under-ball metal layer 108.
  • Steps S207 to S210 are the same as the method of the existing fan-out wafer package, and are not described herein again.
  • the metal tin ball 109 is taken as an example here, and may also be a metal solder ball of other materials, which is not limited in the present invention.
  • the package has been substantially completed. It can be seen from the above packaging method that the present invention integrates the chip and the passive device by integrating the functional surface of the chip and the passive device on the intermediate medium carrier and then using the sealing layer for package curing.
  • Fig. 11 a schematic view of a second embodiment of the package structure of the present invention is shown.
  • the package structure 200 includes a carrier 201 and a glue layer 202 on the carrier 201.
  • the carrier 201 is the basis for carrying the subsequently packaged device.
  • the carrier 201 can be made of glass to provide better hardness and flatness and reduce the failure ratio of the packaged device.
  • the glass carrier plate 201 is easily peeled off and has high corrosion resistance, and physicality does not occur due to contact with other coatings. And chemical properties change, so it can be reused.
  • the glue layer 202 can be selected from a variety of materials.
  • the glue layer 202 is made of UV glue.
  • UV glue is a glue that reacts to ultraviolet light of a particular wavelength.
  • UV glue can be divided into two kinds according to the change of viscosity after ultraviolet light irradiation.
  • One kind is UV curing glue, that is, the photoinitiator or photosensitizer in the material absorbs ultraviolet light under ultraviolet light to generate active radicals or cations.
  • Monomer polymerization, cross-linking and grafting chemical reaction the UV-curable adhesive is converted from a liquid state to a solid state in a few seconds to bond the surface of the object in contact with it; the other is UV glue is not exposed to ultraviolet light.
  • the viscosity is very high, and the cross-linking chemical bond in the material after being irradiated by ultraviolet light is broken to cause the viscosity to drop or disappear greatly.
  • the UV glue used in the glue layer 202 here is the latter. Since the packaged devices such as different chips and passive components need to be glued to the carrier 201 through the bonding layer 202 during wafer fan-out packaging. Therefore, without other supplementary measures, The packaged devices cannot be accurately aligned on the carrier 201. If the packaged device cannot be accurately arranged on the carrier board 201, the packaged product finally produced may have defects or even failures, thereby reducing the package yield.
  • the shape and location of the glue layer 202 is adapted to the shape of the functional surface of the packaged device and the location of attachment on the carrier. During the subsequent bonding of the wafer package and the packaged device, the packaged device can be bonded directly to the location on the glue layer 202. That is, the glue layer 202 can provide alignment for the packaged device.
  • the glue layer 202 on a carrier 201 is also comprised of a plurality of separate glue blocks.
  • the mutually separate glue blocks may be formed on the carrier plate 201 by mask printing, stencil printing or pen-writing. The specific steps of these methods are well known to those skilled in the art and will not be described herein.
  • the shape of the glue block can include square, rectangular or circular shapes, etc., to accommodate the needs of different functional surfaces of the packaged device.
  • the glue block can also be an irregular pattern, such as an irregular pattern designed according to requirements.
  • the packaged devices such as different chips and passive components need to be glued to the carrier 201 through the bonding layer 202 during the wafer fan-out package.
  • the functional planes of different chips and different passive components are different in shape and size. Therefore, it is possible to form glue blocks of different shapes as needed.
  • the shape of at least two of the glue blocks is different. This design is determined based on the characteristics of the fan-out wafer package, but the present invention is not limited thereto, and it is possible that the functions of the chips are different, but the dimensions are the same, so that the shape of the glue blocks can be the same.
  • the glue blocks can be arranged in a matrix on the carrier 201.
  • the glue block is set according to the distribution of the packaged device such as the chip and the passive device, and the chip and the passive device form a system unit according to the design ratio, and the system unit is formed. Matrix arrangement.
  • the spacing of such matrix arrangements is the same according to the spacing between the glue blocks of the packaged device to accommodate the needs of the subsequent molding step.
  • an alignment portion 203 is further provided on the carrier 201. The alignment portion 203 is used to position the direction of the packaged device. The packaged device can be oriented in a specific direction as needed without the reverse of the bonding direction.
  • the packaged device can directly determine the bonding direction according to the alignment portion 203.
  • the shape of the alignment portion 203 may be customized according to the actual needs, in accordance with the shape of the functional surface of the packaged device, and may include, for example, a square, a rectangle, or a circle.
  • the alignment portion 203 may be on the carrier 201 by etching or laser writing. Specific methods of etching or laser writing are well known to those skilled in the art and will not be described herein.
  • the glue layer 202 is a plurality of glue blocks separated from each other.
  • the present invention is not limited thereto, and the shape of the alignment portion 203 itself may be an integral formed as needed and not separated, so that the shape of the glue layer 202 defined therein may also be an overall shape rather than being separated. Glue blocks.
  • the shape and size of the alignment portion 203 may be framed by the plurality of limiting portions 204.
  • the limiting portion 204 may be a cross shape. As shown in FIG. 12, the limiting portion 204 may also be a two-line cross shape; as shown in FIG. 13, the limiting portion 204 may also be a * shape; as shown in FIG.
  • the bit portion 204 may also be L-shaped; as shown in FIG. 15, the limiting portion 204 may also be a double-line L-shape.
  • the limiting portion 204 can still be on the carrier 201 by etching or laser writing.
  • the package structure 300 including a carrier 301 and a glue layer 302 on the carrier 301.
  • Carrier 301 is the basis for carrying subsequent packaged devices.
  • the carrier 301 can be made of glass to provide better hardness and flatness and reduce the failure ratio of the packaged device.
  • the glass carrier plate 301 is easily peeled off and has high corrosion resistance, and physicality does not occur due to contact with other coatings. And chemical properties change, so it can be reused.
  • the glue layer 302 can be selected from a variety of materials.
  • the glue layer 302 is made of UV glue.
  • UV glue is a glue that reacts to ultraviolet light of a particular wavelength.
  • UV glue can be divided into two kinds according to the change of viscosity after ultraviolet light irradiation.
  • One kind is UV curing glue, that is, the photoinitiator or photosensitizer in the material absorbs ultraviolet light under ultraviolet light to generate active radicals or cations.
  • Monomer polymerization, cross-linking and grafting chemical reaction the UV-curable adhesive is converted from a liquid state to a solid state in a few seconds to bond the surface of the object in contact with it; the other is UV glue is not exposed to ultraviolet light.
  • the packaged device attached to the glue layer 302 may include a plurality of chips 303, and may further include a plurality of passive devices 304.
  • the plurality of chips 303 can be a plurality of different chips, each of which becomes part of a system-in-package product.
  • the passive device 304 is an external circuit device that implements system-level functions of the packaged product together with the chip 303, including capacitors, resistors, and inductors.
  • the passive device 304 is combined with the chip 303 of different functions, and can be packaged.
  • the system level features required now. Additionally, packaged devices over glue layer 302 may include chips and passive components.
  • a side of the carrier 301 to which the chip 303 and the passive device 304 are bonded is further provided with a sealing layer 305.
  • the package protects the surface of the chip 303 and other components other than the functional surface of the passive device 304, and serves as a carrier for subsequent processes.
  • the material forming the sealant layer 305 is an epoxy resin. This material has good sealing properties and is easy to mold, and is a preferred material for forming the sealing layer 305.
  • a recess 306 is provided between each packaged component of the sealant layer 305. These grooves 306 are formed by printing through the stencil stencil opening and depth design. After the recess 306 is formed, the stress within the sealant layer 305 can be balanced to avoid warping deformation during subsequent processing of the wafer package.
  • the cross-section of the recess 306 can be designed differently depending on the stress within the sealant layer 305 and the contour of the packaged device.
  • the cross section of the recess 306 includes a U-shape, a V-shape, or a concave shape.
  • the depth of the groove 306 is related to the design of the stencil stencil.
  • the thickness of the groove 106 provided according to the stencil stencil design can effectively balance the stress inside the sealing layer 305.
  • the stress around 303 and passive component 304 further balances the stress distribution inside sealant layer 305.
  • the ring surrounded by each of the grooves 306 includes a square, a rectangle or a circle.
  • a plurality of chips 303 may be included in the packaged device enclosed by each annular groove 306, and the passive device 304 may be combined.
  • the packaged devices are matrix-arranged, and the recesses 306 are disposed between the packaged devices, similar to interlaced.
  • the annular grooves 306 are arranged in a variety of ways to accommodate different arrangements of the chip 303 and the passive device 304. In another preferred embodiment of the invention, a plurality of annular grooves 306 are arranged in a matrix.

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Abstract

本发明涉及一种封装结构，包括：载板及其表面的胶合层；功能面贴于所述胶合层上的芯片和无源器件；还包括形成于载板贴有芯片和无源器件的一面用于封装固化的封料层。本发明中芯片和无源器件是集成整合后再一并封装的，因此是包含整体系统功能而非单一的芯片功能的封装产品，具有高集成度，更是降低了系统内电阻、电感等干扰因素，也更能顺应半导体封装轻薄短小的趋势要求。

Description

封装结构
本申请要求 2011年 1月 30日提交中国专利局、申请号为 201110032402.6 、 发明名称为 "系统级扇出晶圆封装结构"的中国专利申请的优先权， 2011年 1月 30 日提交中国专利局、 申请号为 201120032087.2、 发明名称为 "晶圆封 装的承载装置"的中国专利申请的优先权， 2011年 1月 30提交中国专利局、 申请号为 201110032390.7、 发明名称为 "高密度系统级芯片封装结构" 的中国 专利申请的优先权， 2011年 1月 30提交中国专利局、申请号为 201120032108.0、 发明名称为 "晶圆封装结构" 的中国专利申请的优先权， 2011年 1月 30提交 中国专利局、 申请号为 201110032264.1、 发明名称为 "高集成度晶圆扇出封装 结构" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域， 更具体地， 本发明涉及一种封装结构。
背景技术
晶圆级封装（ Wafer Level Packaging, WLP )技术是对整片晶圆进行封装 测试后再切割得到单个成品芯片的技术， 封装后的芯片尺寸与棵片完全一致。 晶圆级芯片尺寸封装技术彻底颠覆了传统封装如陶瓷无引线芯片载具 ( Ceramic Leadless Chip Carrier ) 以及有机无引线芯片载具 ( Organic Leadless Chip Carrier )等模式， 顺应了市场对微电子产品日益轻、 小、 短、 薄化和低价 化要求。 经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微型化， 芯 片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。晶圆级芯片尺寸封 装技术是可以将 IC设计、 晶圆制造、 封装测试、 基板制造整合为一体的技术， 是当前封装领域的热点和未来发展的趋势。 扇出晶圆封装是晶圆级封装的一种。 例如， 中国发明专利申请第
200910031885.0号公开一种晶圆级扇出芯片封装方法， 包括以下工艺步骤： 在 载体圆片表面依次覆盖剥离膜和薄膜介质层 I, 在薄膜介质层 I上形成光刻图形 开口 I； 在图形开口 I及其表面实现与基板端连接之金属电极和再布线金属走 线； 在与基板端连接之金属电极表面、 再布线金属走线表面以及薄膜介质层 I 的表面覆盖薄膜介质层 Π, 并在薄膜介质层 II上形成光刻图形开口 Π; 在光刻图 形开口 II实现与芯片端连接之金属电极； 将芯片倒装至与芯片端连接之金属电 极后进行注塑封料层并固化， 形成带有塑封料层的封装体； 将载体圆片和剥离 膜与带有塑封料层的封装体分离， 形成塑封圆片； 植球回流， 形成焊球凸点； 单片切割， 形成最终的扇出芯片结构。 按照上述方法所封装制造的最终产品仅具有单一的芯片功能。如需实现完 整的系统功能， 需要在最终产品之外加上包含有各种电容、 电感或电阻等的外 围电路。
发明内容 本发明解决的问题是提供一种高密度的封装结构。 为了解决现有技术的问题， 本发明提供一种封装结构包括： 载板及其表面 的胶合层； 贴于所述胶合层上的芯片和无源器件； 还包括形成于载板贴有芯片 和无源器件的一面用于封装固化的封料层。 可选地， 所述封料层还填充于所述芯片与芯片之间、 芯片与无源器件之间 和 /或无源器件和无源器件之间的空间。 可选地， 所述封料层的厚度大于各个芯片与无源器件中最厚的一个的厚 度。
可选地， 所述无源器件包括电容、 电阻和电感。
可选地， 所述封料层的材料为环氧树脂。
可选地， 所述胶合层为 UV胶。
可选地， 所述芯片包括多个不同的芯片。
可选地， 所述载板为玻璃载板。
可选地， 所述芯片和无源器件为被封装器件， 所述胶合层的形状和位置与 被封装器件的功能面的形状和在载板上的贴合位置相适应。
可选地， 所述载板上还设有对准部。
可选地， 所述对准部的形状和大小由多个限位部所圈定。
可选地， 所述限位部的形状包括十字形、 双线十字形、 *型、 L型、 双线 L 型或点型。
可选地， 所述胶合层由多个相互分离的胶合块所组成。
可选地， 至少两块所述胶合块的形状不相同。
可选地， 所述胶合块的形状包括正方形、 长方形或圆形。
可选地， 所述胶合块在所述载板上成矩阵排列。
可选地， 所述胶合块在所述载板排列的间距相同。
可选地， 所述胶合块的间距根据所述被封装器件的布置规划而预留。 可选地， 所述芯片和无源器件为被封装器件， 所述封料层表面对应于被封 装器件之间设有凹槽。
可选地， 所述凹槽有多条， 每一条凹槽围绕所述封装器件而封闭。 可选地， 每一条凹槽所围成的形状包括正方形、 长方形或圆形。
可选地， 每一条凹槽之间保持相同距离。
可选地， 所述凹槽成矩阵排列。
可选地， 所述凹槽的横截面包括 U型、 V型或凹型。
可选地， 所述凹槽的深度小于所述封料层的厚度。
可选地， 所述凹槽的深度大于所述封料层与所述被封装器件的厚度差。 可选地， 所述封料层表面露出芯片以及无源器件的功能面， 所述封装结构 还包括：形成于封料层表面与所述芯片以及无源器件功能面电连接的金属再布 线层； 形成于所述封料层表面的保护膜层， 所述保护膜层具有露出所述金属再 布线层的开口； 形成于所述开口内与所述金属再布线层连接的球下金属层； 形 成于所述球下金属层上的金属焊球。 与现有技术相比， 本发明具有以下优点：
1. 本发明请求保护的封装结构中， 芯片和无源器件是集成整合后再一并 封装的， 因此是包含整体系统功能而非单一的芯片功能的封装产品， 相比现有的系统级封装结构， 由于具有高集成度， 更是降低了系统内 电阻、 电感等干扰因素，也更能顺应半导体封装轻薄短小的趋势要求。
2. 可选方案中， 在载板上所形成的胶合层的形状和位置与被封装器件的 功能面的形状和在载板上的贴合位置相适应， 因此既方便贴装芯片时 的定位， 又可以避免后续工艺中难以剥除或大面积的清洗。
3. 可选方案中， 封料层的整片封装分解成多个小被封装器件， 同时设置 于被封装器件之间的凹槽可以降低封料层的内应力， 可以避免封料层 在晶圆封装的后续过程中出现翘曲变形，提高了晶圆封装成品的质量。 附图说明 图 1为本发明封装结构第一实施例的示意图； 图 2为封装方法一实施方式的流程示意图； 图 3至图 10为图 2所示流程中封装结构示意图。 图 11为本发明封装结构第二实施例的示意图； 图 12为图 11所示限位部第一实施例的示意图； 图 13为图 11所示限位部第二实施例的示意图； 图 14为图 11所示限位部第三实施例的示意图； 图 15为图 11所示限位部第四实施例的示意图； 图 16为本发明封装结构第三实施例的示意图； 图 17为图 16所示凹槽一实施例的示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明 能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背 本发明内涵的情况下做类似推广， 因此本发明不受下面公开的具体实施的限 制。 其次， 本发明利用示意图进行详细描述， 在详述本发明实施例时， 为便于 说明， 所述示意图只是实例， 其在此不应限制本发明保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明 能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背 本发明内涵的情况下做类似推广， 因此本发明不受下面公开的具体实施的限 制。
其次， 本发明利用示意图进行详细描述， 在详述本发明实施例时， 为便于 说明， 所述示意图只是实例， 其在此不应限制本发明保护的范围。
图 1为本发明封装结构第一实施例的剖面示意图； 所述封装结构包括： 封 料层 105、 封装固化于所述封料层 105中的芯片 103、 无源器件 104; 所述封 料层 105的表面露出芯片 103以及无源器件 104的功能面； 形成于封料层 105 表面与所述芯片 103以及无源器件 104功能面电连接的金属再布线层 106; 形 成于所述封料层 105表面的保护膜层 107, 所述保护膜层 107具有露出所述金 属再布线层 106的开口；形成于所述开口内与所述金属再布线层 106连接的球 下金属层 108; 形成于所述球下金属层 108上的金属锡球 109。
上述封装结构中， 芯片 103和无源器件 104是集成整合后再一并封装的， 因此是包含整体系统功能而非单一的芯片功能的封装产品。为进一步说明本发 明封装结构之优点，以下结合一个具体的封装方法实施例对本发明封装结构作 进一步介绍。
下面结合附图对本发明的具体实施方式做详细的说明。 参考图 2, 示出了封装方法一实施方式的流程示意图， 包括步骤：
5201 , 在载板上形成胶合层；
5202, 将芯片和无源器件的功能面贴于胶合层上； 5203 , 将载板贴有芯片和无源器件的一面形成封料层， 进行封装固化；
5204, 去除胶合层；
5205 , 将载板与芯片和无源器件的功能面进行分离；
5206, 清洗芯片和无源器件的功能面； S207, 在芯片和无源器件棵露的功能面进行金属再布线；
5208,在金属再布线所在表面形成保护膜，并在保护膜上形成露出金属面 的开口；
5209, 在保护膜开口内的金属面上形成球下金属层；
5210, 在球下金属层表面形成金属锡球。 在本实施例中， 首先执行步骤 S201 , 在载板 101上形成胶合层 102, 形成 如图 3所示的结构。
在这一步骤中，载板 101是用来承载后续芯片 103和无源器件 104的基础。 在本实施例中， 载板 101采用玻璃材质， 可以提供较好的硬度和平整度， 降低封装器件的失效比例。 另外， 由于载板 101在后续步骤中会被剥离， 且玻 璃材质的载板 101易剥离、抗腐蚀能力强， 不会因为与胶合层 102的接触而发 生物理和化学性能的改变， 因此可以进行重复利用。 当然， 本领域技术人员了 解， 载板 101采用例如硅化合物也能实现本发明的目的。 在载板 101上形成的胶合层 102是用于将芯片 103和无源器件 104固定在 载板 101上。胶合层 102可选用的材质有多种，在本发明一个优选的实施例中， 胶合层 102采用 UV胶。 UV胶是一种能对特殊波长的紫外光照射产生反应的 胶合材料。 UV胶根据紫外光照射后粘性的变化可分为两种， 一种是 UV固化 胶，即材料中的光引发剂或光敏剂在紫外线的照射下吸收紫外光后产生活性自 由基或阳离子， 引发单体聚合、 交联和接支化学反应， 使紫外光固化胶在数秒 钟内由液态转化为固态，从而将与其接触的物体表面粘合； 另一种是 UV胶是 在未经过紫外线照射时粘性很高，而经过紫外光照射后材料内的交联化学键被 打断导致粘性大幅下降或消失。 这里的胶合层 102所采用的 UV胶即是后者。 在载板 101上形成胶合层 102的方法可以例如是通过旋涂或印刷等方法将 胶合层 102涂覆在载板 101上。这样的方法在半导体制造领域中已为本领域技 术人员所熟知， 在此不再赘述。 在载板 101上形成胶合层 102后， 即可执行步骤 S202, 将芯片 103和无 源器件 104的功能面贴于胶合层 102上， 形成如图 4所示的结构。 在本发明的具体实施方式中， 芯片 103和无源器件 104的功能面，是指芯 片 103的金属电极和无源器件 104的焊盘所在表面。 在本发明的一个优选的实施例中， 贴合于胶合层 102之上的多个芯片 103 可以是多个不同的芯片， 这些芯片各自成为一个系统级封装产品的一部分，各 自完成实现系统级功能中的一个或多个单独的功能。 无源器件 104是与芯片 103共同实现封装产品的系统级功能的外部电路器 件， 包括电容、 电阻和电感等。 将无源器件 104与不同功能的芯片 103组合在 一起封装， 可以实现所需的系统级功能。 在本发明的一个优选的实施例中，芯片 103与无源器件 104的组合是根据 系统功能来设计的。 因此， 在一个芯片 103的周围， 可能有相同或不同的另外 的芯片 103 , 或者相同或不同的电容、 电阻或电感等无源器件 104; 类似的， 在一个无源器件 104的周围， 可能有相同或不同的其他的无源器件 104, 或者 一个或多个相同或不同芯片 103。
然后执行步骤 S203 , 将贴有芯片和无源器件的载板面进行塑封料层封装 并固化， 形成带有封料层 105的封装体， 即形成如图 5所示的结构。 在后续工 艺过程中，封装体即可保护芯片 103和无源器件 104的功能面以外的其他表面， 又可作为后续工艺的承载体。 在本发明的一个实施例中， 形成封料层 105的材料是环氧树脂。这种材料 的密封性能好， 塑型容易， 是形成封料层 105 的较佳材料。 形成封料层 105 的方法可以例如是灌注或印刷的方法。这些方法的具体步骤已为本领域技术人 员所熟知， 在此不再赘述。
如前所述， 在一个芯片 103的周围， 可能有另外的芯片 103 , 或者无源器 件 104; 在一个无源器件 104的周围， 也可能有相同或不同的其他的无源器件 104, 或者一个或多个相同或不同芯片 103。 因此， 在芯片 103或者无源器件 104的周围会有空隙。 为了对芯片 103和无源器件 104形成更好的保护， 封料 层 105还填充于芯片 103与芯片 103之间、 芯片 103与无源器件 104之间和 / 或无源器件 104和无源器件 104之间的空间。
由于芯片 103与无源器件 104的厚度并不尽相同， 有可能芯片 103更厚， 也有可能无源器件 104更厚。 因此， 封料层 105的厚度应该大于各个芯片 103 与无源器件 104中最厚的一个的厚度，用以对芯片 103和无源器件 104提供最 佳的保护。
去除胶合层 102。 由于胶合层 102是有机材料， 可以溶解于特定的有机溶 剂。因此，可以采用有机溶剂清洗的方法，使得胶合层 102溶解于有机溶剂中。
然后执行步骤 S205 , 将载板 101与芯片 103和无源器件 104的功能面进 行分离。 也就是说， 在执行步骤 S204之后， 胶合层 102已经溶解掉了， 或者 处于可剥离的熔融状态下， 可以轻松将载板 101从芯片 103和无源器件 104 的功能面上剥离下来， 从而棵露出芯片 103和无源器件 104的功能面。
再执行步骤 S206, 清洗芯片 103和无源器件 104的功能面， 将功能面上 残留的胶合层 102, 形成如图 6所示的结构， 此时芯片 103和无源器件 104不 再透过载板固定在一起而是通过封装体固定在一起了，同时芯片的金属电极和 无源器件的焊盘也棵露出来。
如图 7至图 10所示， 接着再执行步骤 S207至步骤 S210, 包括： 在芯片 103和无源器件 104棵露的功能面进行金属再布线 106, 使芯片 103的金属电 极和无源器件 104的焊盘透过再布的金属线实现功能性系统互联和走线；在金 属再布线 106所在表面形成保护膜 107 , 并在保护膜 107上形成设计所需的开 口以露出金属再布线 106; 在保护膜开口内的金属再布线 106上形成球下金属 层 108; 在球下金属层 108表面形成金属锡球 109。 步骤 S207至步骤 S210与 现有扇出晶圆封装的方法相同， 在此不再赘述。
需要说明的是此处以金属锡球 109为例， 还可以是其他材料的金属焊球， 本发明对此不做限制。 经过上述步骤， 已基本完成封装。 由上述封装方法可知， 本发明通过将芯 片与无源器件的功能面一并贴于中间介质载板， 再使用封料层进行封装固化， 从而实现了将芯片与无源器件的集成整合封装。 如图 11所示， 示出了本发明封装结构第二实施例的示意图。 所述封装结 构 200包括载板 201和载板 201上的胶合层 202。 载板 201是用于承载后续被封装器件的基础。载板 201可以采用玻璃材质， 用以提供较好的硬度和平整度， 降低封装器件的失效比例。 另外， 在实际使用 过程中， 由于晶圆载板 201在封装的过程中会被剥离， 且玻璃材质的载板 201 易剥离、抗腐蚀能力强， 不会因为与其他涂层的接触而发生物理和化学性能的 改变， 因此可以进行重复利用。
上。 胶合层 202可选用的材质有多种， 在本发明一个优选的实施例中， 胶合层 202采用 UV胶。 UV胶是一种能对特殊波长的紫外光照射产生反应的胶合材 料。 UV胶根据紫外光照射后粘性的变化可分为两种， 一种是 UV固化胶， 即 材料中的光引发剂或光敏剂在紫外线的照射下吸收紫外光后产生活性自由基 或阳离子， 引发单体聚合、 交联和接支化学反应， 使紫外光固化胶在数秒钟内 由液态转化为固态， 从而将与其接触的物体表面粘合； 另一种是 UV胶是在未 经过紫外线照射时粘性很高，而经过紫外光照射后材料内的交联化学键被打断 导致粘性大幅下降或消失。 这里的胶合层 202所采用的 UV胶即是后者。 由于在进行晶圆扇出封装时，需要将不同的芯片和无源器件等被封装器件 通过胶合层 202胶合在载板 201上。 因此， 在没有其他辅助措施的情况下， 被 封装器件无法在载板 201上准确地排列。如果被封装器件不能准确地排布在载 板 201上， 最终所制造出封装产品有可能会出现缺陷甚至失效等后果，从而降 低封装良率。
因此，在本发明的具体实施方式中，胶合层 202的形状和位置与被封装器 件的功能面的形状和在载板上的贴合位置相适应。在晶圆封装的后续胶和被封 装器件的过程中，被封装器件可以直接按照胶合层 202上的位置进行贴合。也 就是说， 胶合层 202可以为被封装器件提供对准定位。
在本发明的一个优选的实施例中，在一块载板 201上的胶合层 202也是由 多个相互分离的胶合块所组成。 相互分离的胶合块可以是由掩膜印刷 （mask printing )、 模板印刷 ( stencil printing )或者直写 ( pen-writing ) 的方法形成在 载板 201上。这些方法的具体步骤已为本领域技术人员所熟知，在此不再赘述。
胶合块的形状可以包括正方形、 长方形或圆形等， 以适应不同的被封装器 件的不同功能面的形状的需要。 当然， 胶合块也可以是不规则图形， 例如是根 据需求所设计出来的不规则图案等。
如前所述， 由于在进行晶圆扇出封装时， 需要将不同的芯片和无源器件等 被封装器件通过胶合层 202胶合在载板 201上。而不同的芯片和不同的无源器 件的功能面， 其形状和大小是不同的。 因此， 可以根据需要形成不同形状的胶 合块。在一块载板 201上所形成的胶合块中， 至少两块胶合块的形状是不相同 的。 这一设计是根据扇出晶圆封装的特性来确定的， 但是本发明并不限于此， 有可能芯片功能不同， 但尺寸一样， 因此胶合块的形状也可相同。
胶合块在载板 201上可以成矩阵排列。但是，在本发明的一个优选的实施 例中，在系统级扇出晶圆封装时，胶合块是根据芯片和无源器件等被封装器件 的分布来设置的， 芯片和无源器件根据设计配比形成一个系统单元， 系统单元 间成矩阵排列。在另一个优选的实施例中， 这种矩阵排列的间距根据被封装器 件的胶合块之间的间距是相同的， 用以适应后续的塑封步骤的需要。 另外， 本发明在载板 201上还设有对准部 203。 对准部 203用于对被封装 器件的方向进行定位。使得被封装器件可以按照需要朝向特定的方向而不会发 生贴合方向的颠倒等情况。 因此在晶圆封装的后续胶合被封装器件的过程中， 被封装器件可以直接按照对准部 203确定贴合方向。 对准部 203的形状可以根据实际需要，按照符合被封装器件功能面的形状 来定制， 例如可以包括正方形、 长方形或圆形。 对准部 203可以是通过蚀刻或 激光刻写的方式在载板 201上。蚀刻或激光刻写的具体方法已为本领域技术人 员所熟知， 在此不再赘述。
在上述实施例中，胶合层 202是相互分离的多个胶合块。但是本发明并不 限于此， 对准部 203 自身的形状也可以是根据需要所形成并不分离的一个整 体，因而其所限定的胶合层 202的形状也可以是一个整体形状而非分离的多个 胶合块。
对准部 203的形状和大小可以由多个限位部 204所框定。限位部 204可以 是十字形， 如图 12所示， 限位部 204还可以是双线十字形； 如图 13所示， 限 位部 204还可以是 *形； 如图 14所示， 限位部 204还可以是 L形； 如图 15所 示， 限位部 204还可以是双线 L形。 类似的， 在这些实施例中， 限位部 204 仍然可以是通过蚀刻或激光刻写的方式在载板 201上。 参考图 16, 示出了本发明封装结构第三实施例的示意图， 封装结构 300 包括载板 301和载板 301上的胶合层 302。 载板 301是用于承载后续被封装器件的基础。载板 301可以采用玻璃材质， 用以提供较好的硬度和平整度， 降低封装器件的失效比例。 另外， 在实际使用 过程中， 由于晶圆载板 301在封装的过程中会被剥离， 且玻璃材质的载板 301 易剥离、抗腐蚀能力强， 不会因为与其他涂层的接触而发生物理和化学性能的 改变， 因此可以进行重复利用。
上。 胶合层 302可选用的材质有多种， 在本发明一个优选的实施例中， 胶合层 302采用 UV胶。 UV胶是一种能对特殊波长的紫外光照射产生反应的胶合材 料。 UV胶根据紫外光照射后粘性的变化可分为两种， 一种是 UV固化胶， 即 材料中的光引发剂或光敏剂在紫外线的照射下吸收紫外光后产生活性自由基 或阳离子， 引发单体聚合、 交联和接支化学反应， 使紫外光固化胶在数秒钟内 由液态转化为固态， 从而将与其接触的物体表面粘合； 另一种是 UV胶是在未 经过紫外线照射时粘性很高，而经过紫外光照射后材料内的交联化学键被打断 导致粘性大幅下降或消失。 这里的胶合层 302所采用的 UV胶即是后者。 在进行系统级晶圆封装时，贴合于胶合层 302之上的被封装器件可以包括 多个芯片 303 , 也可以还包括多个无源器件 304。 多个芯片 303可以是多个不 同的芯片， 这些芯片各自成为一个系统级封装产品的一部分。 而无源器件 304 是与芯片 303共同实现封装产品的系统级功能的外部电路器件， 包括电容、 电 阻和电感等。将无源器件 304与不同功能的芯片 303组合在一起封装， 可以实 现所需的系统级功能。此外，胶合层 302之上的被封装器件可能包括有芯片和 无源器件。
载板 301上粘合有芯片 303和无源器件 304的一面还设有封料层 305。 在 后续工艺过程中，封装体即可保护芯片 303和无源器件 304的功能面以外的其 他表面， 又可作为后续工艺的承载体。 在本发明的一个实施例中， 形成封料层 305的材料是环氧树脂。这种材料的密封性能好，塑型容易，是形成封料层 305 的较佳材料。
由于封料层 305与载板 301两种材料的热收缩比例不同， 导致封料层 305 内部应力不均勾， 这会导致封料层 305 在晶圆封装的后续过程中出现翘曲变 形， 进而影响到封装成品的质量。 因此， 如图 17所示， 在本发明的具体实施方式中， 在封料层 305的每一 个被封装器件间设有凹槽 306。这些凹槽 306是通过 stencil网板开孔和深度的 设计， 在印刷后形成的。 在形成凹槽 306后， 可以平衡封料层 305内的应力， 从而避免在晶圆封装的后续过程中出现翘曲变形。 凹槽 306的横截面可以根据封料层 305内的应力和被封装器件的轮廓进行 不同的设计。 在优选的实施例中， 凹槽 306的横截面包括 U型、 V型或凹型。
凹槽 306的深度跟 stencil网板的设计有关。 根据 stencil网板设计所设置 的凹槽 106厚度可以有效平衡封料层 305内部的应力。 在本发明的一个优选的实施例中， 凹槽 306有多条，每一条凹槽 306围绕 被一个封装器件而封闭成环。 这种环状结构可以有效降低封料层 305 在芯片 303和无源器件 304周围的应力，从而进一步平衡封料层 305内部的应力分布。 每一条凹槽 306所围成的环形包括正方形、长方形或圆形。每一个环形的凹槽 306所圈定的封装器件内可以包含多颗芯片 303 , 也可组合无源器件 304。 封 装器件之间是矩阵排列的， 而凹槽 306设置于封装器件间， 类似阡陌交错。 环形的凹槽 306有多种排列方式，可以适应芯片 303和无源器件 304的不 同排列。在本发明的另一个优选的实施例中，多个环形的凹槽 306成矩阵排列。 虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领 域技术人员， 在不脱离本发明的精神和范围内， 均可作各种更动与修改， 因此 本发明的保护范围应当以权利要求所限定的范围为准。

Claims

权 利 要 求
1. 一种封装结构， 其特征在于， 包括： 载板及其表面的胶合层； 贴于所 述胶合层上的芯片和无源器件；还包括形成于载板贴有芯片和无源器件的一面 用于封装固化的封料层。
2. 如权利要求 1所述的封装结构， 其特征在于： 所述封料层还填充于所 述芯片与芯片之间、 芯片与无源器件之间和 /或无源器件和无源器件之间的空 间。
3. 如权利要求 2所述的封装结构， 其特征在于， 所述封料层的厚度大于 各个芯片与无源器件中最厚的一个的厚度。
4. 如权利要求 1所述的封装结构，其特征在于：所述无源器件包括电容、 电阻和电感。
5. 如权利要求 1所述的封装结构， 其特征在于： 所述封料层的材料为环 氧树脂。
6. 如权利要求 1所述的封装结构， 其特征在于： 所述胶合层为 UV胶。
7. 如权利要求 1所述的封装结构， 其特征在于： 所述芯片包括多个不同 的芯片。
8. 如权利要求 1所述的封装结构， 其特征在于： 所述载板为玻璃载板。
9.如权利要求 1所述的封装结构， 其特征在于： 所述芯片和无源器件为被 封装器件，所述胶合层的形状和位置与被封装器件的功能面的形状和在载板上 的贴合位置相适应。
10. 如权利要求 9所述的封装结构， 其特征在于： 所述载板上还设有对 准部。
11. 如权利要求 10所述的封装结构， 其特征在于： 所述对准部的形状和 大小由多个限位部所圈定。
12. 如权利要求 11所述的封装结构， 其特征在于： 所述限位部的形状包 括十字形、 双线十字形、 *型、 L型、 双线 L型或点型。
13. 如权利要求 9所述的封装结构， 其特征在于： 所述胶合层由多个相 互分离的胶合块所组成。
14. 如权利要求 13所述的封装结构， 其特征在于： 至少两块所述胶合块 的形状不相同。
15. 如权利要求 13所述的封装结构， 其特征在于： 所述胶合块的形状包 括正方形、 长方形或圆形。
16. 如权利要求 13所述的封装结构， 其特征在于： 所述胶合块在所述载 板上成矩阵排列。
17. 如权利要求 16所述的封装结构， 其特征在于： 所述胶合块在所述载 板排列的间距相同。
18. 如权利要求 13所述的封装结构， 其特征在于： 所述胶合块的间距根 据所述被封装器件的布置规划而预留。
19. 如权利要求 1所述的封装结构， 其特征在于， 所述芯片和无源器件 为被封装器件， 所述封料层表面对应于被封装器件之间设有凹槽。
20. 如权利要求 19所述的封装结构， 其特征在于： 所述凹槽有多条， 每 一条凹槽围绕所述封装器件而封闭。
21. 如权利要求 20所述的封装结构， 其特征在于： 每一条凹槽所围成的 形状包括正方形、 长方形或圆形。
22. 如权利要求 20所述的封装结构， 其特征在于： 每一条凹槽之间保持 相同距离。
23. 如权利要求 20所述的封装结构，其特征在于：所述凹槽成矩阵排列。
24. 如权利要求 19所述的封装结构， 其特征在于： 所述凹槽的横截面包 括 U型、 V型或凹型。
25. 如权利要求 19所述的封装结构， 其特征在于： 所述凹槽的深度小于 所述封料层的厚度。
26. 如权利要求 19所述的封装结构， 其特征在于： 所述凹槽的深度大于 所述封料层与所述被封装器件的厚度差。
27. 如权利要求 1所述的封装结构， 其特征在于， 所述封料层表面露出芯 片以及无源器件的功能面， 所述封装结构还包括： 形成于封料层表面与所述芯 片以及无源器件功能面电连接的金属再布线层；形成于所述封料层表面的保护 膜层， 所述保护膜层具有露出所述金属再布线层的开口； 形成于所述开口内与 所述金属再布线层连接的球下金属层； 形成于所述球下金属层上的金属焊球。
PCT/CN2012/070629 2011-01-30 2012-01-20 封装结构 WO2012100721A1 (zh)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6406235B2 (ja) * 2015-12-16 2018-10-17 オムロン株式会社 電子装置及びその製造方法
US10872832B2 (en) * 2015-12-16 2020-12-22 Intel Corporation Pre-molded active IC of passive components to miniaturize system in package
US9929078B2 (en) * 2016-01-14 2018-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10617010B2 (en) * 2016-08-29 2020-04-07 Brewer Science, Inc. Polymer film stencil process for fan-out wafer-level packaging of semiconductor devices
US11804416B2 (en) * 2020-09-08 2023-10-31 UTAC Headquarters Pte. Ltd. Semiconductor device and method of forming protective layer around cavity of semiconductor die

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387240A (zh) * 2001-05-18 2002-12-25 株式会社东芝 叠层式半导体器件的制造方法
CN1707792A (zh) * 2004-06-08 2005-12-14 三洋电机株式会社 加工精度良好的半导体模块及其制造方法和半导体装置
JP2005347514A (ja) * 2004-06-03 2005-12-15 Towa Corp マルチチップモールド方法
CN101009269A (zh) * 2006-01-24 2007-08-01 富士通株式会社 半导体器件及其制造方法
CN101174601A (zh) * 2006-11-03 2008-05-07 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101425469A (zh) * 2007-10-30 2009-05-06 育霈科技股份有限公司 使用大尺寸面板的半导体构装方法
CN102163603A (zh) * 2011-01-30 2011-08-24 南通富士通微电子股份有限公司 系统级扇出晶圆封装结构
CN102169879A (zh) * 2011-01-30 2011-08-31 南通富士通微电子股份有限公司 高集成度晶圆扇出封装结构
CN102176452A (zh) * 2011-01-30 2011-09-07 南通富士通微电子股份有限公司 高密度系统级芯片封装结构
CN201994277U (zh) * 2011-01-30 2011-09-28 南通富士通微电子股份有限公司 晶圆封装结构
CN202094109U (zh) * 2011-01-30 2011-12-28 南通富士通微电子股份有限公司 晶圆封装的承载装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220463A (ja) 1988-02-29 1989-09-04 Seiko Epson Corp 半導体装置
JPH053143A (ja) * 1991-04-19 1993-01-08 Hitachi Ltd 位置合せ方法および装置
JP2770662B2 (ja) 1992-07-21 1998-07-02 三菱電機株式会社 エンジンの排気ガス浄化装置
JP2001257291A (ja) 2000-03-13 2001-09-21 Sanyo Electric Co Ltd 回路装置
JP2003243604A (ja) * 2002-02-13 2003-08-29 Sony Corp 電子部品及び電子部品の製造方法
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
CN101604638B (zh) 2009-06-26 2010-10-06 江阴长电先进封装有限公司 圆片级扇出芯片封装方法
WO2011077962A1 (ja) * 2009-12-24 2011-06-30 株式会社 村田製作所 電子部品の製造方法
US8361842B2 (en) * 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
KR101711479B1 (ko) * 2010-10-06 2017-03-03 삼성전자 주식회사 반도체 패키지 장치 및 그의 검사 시스템
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
CN102157401B (zh) 2011-01-30 2013-05-15 南通富士通微电子股份有限公司 高密度系统级芯片封装方法
CN102169840A (zh) 2011-01-30 2011-08-31 南通富士通微电子股份有限公司 系统级扇出晶圆封装方法
CN102157400B (zh) 2011-01-30 2013-06-19 南通富士通微电子股份有限公司 高集成度晶圆扇出封装方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387240A (zh) * 2001-05-18 2002-12-25 株式会社东芝 叠层式半导体器件的制造方法
JP2005347514A (ja) * 2004-06-03 2005-12-15 Towa Corp マルチチップモールド方法
CN1707792A (zh) * 2004-06-08 2005-12-14 三洋电机株式会社 加工精度良好的半导体模块及其制造方法和半导体装置
CN101009269A (zh) * 2006-01-24 2007-08-01 富士通株式会社 半导体器件及其制造方法
CN101174601A (zh) * 2006-11-03 2008-05-07 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101425469A (zh) * 2007-10-30 2009-05-06 育霈科技股份有限公司 使用大尺寸面板的半导体构装方法
CN102163603A (zh) * 2011-01-30 2011-08-24 南通富士通微电子股份有限公司 系统级扇出晶圆封装结构
CN102169879A (zh) * 2011-01-30 2011-08-31 南通富士通微电子股份有限公司 高集成度晶圆扇出封装结构
CN102176452A (zh) * 2011-01-30 2011-09-07 南通富士通微电子股份有限公司 高密度系统级芯片封装结构
CN201994277U (zh) * 2011-01-30 2011-09-28 南通富士通微电子股份有限公司 晶圆封装结构
CN202094109U (zh) * 2011-01-30 2011-12-28 南通富士通微电子股份有限公司 晶圆封装的承载装置

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