WO2012088774A1 - 一种soi型p-ldmos - Google Patents

一种soi型p-ldmos Download PDF

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Publication number
WO2012088774A1
WO2012088774A1 PCT/CN2011/070171 CN2011070171W WO2012088774A1 WO 2012088774 A1 WO2012088774 A1 WO 2012088774A1 CN 2011070171 W CN2011070171 W CN 2011070171W WO 2012088774 A1 WO2012088774 A1 WO 2012088774A1
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Prior art keywords
ldmos
soi type
layer
dielectric
semiconductor active
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PCT/CN2011/070171
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English (en)
French (fr)
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张波
吴丽娟
乔明
胡盛东
胡曦
李肇基
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电子科技大学
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Publication of WO2012088774A1 publication Critical patent/WO2012088774A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a SOI type P-LDMOS.
  • SOI semiconductor On Insulator
  • SOI power devices have higher operating speed and integration, better insulation performance, stronger radiation resistance, and no thyristor self-locking effect.
  • the application of SOI power devices in the field of VLSI has received extensive attention, but its low breakdown voltage and self-heating effects have limited its application range.
  • the breakdown voltage of an SOI power device depends on the lower of the lateral breakdown voltage and the longitudinal breakdown voltage.
  • the lateral breakdown voltage design principle and technology of the existing mature Si-based devices can be used in the lateral breakdown voltage control. Therefore, how to increase the vertical breakdown voltage becomes a difficult point in the research of SOI power devices.
  • FIG. 1 Schematic diagram of a P-channel lateral double-diffused metal oxide semiconductor, wherein 101 is a semiconductor substrate layer, 102 is an I layer (Insulator layer, dielectric buried layer;), and 103 is an S layer (Semiconductor layer, semiconductor active layer) 104 is a dielectric isolation region, two dielectric isolation regions define an active region of the device, 105 is a gate oxide layer, 106 is a gate electrode on the gate oxide layer, 107 is an n-well in the active region, and 108 is located at n a p + source region in the well, 109 is a p + drain region, 110 is a drain electrode formed on the drain region, 111 is a source electrode formed on the p + source region 108, and 112 is a lightly doped layer formed in the active region A hetero-drain region in which a p + drain region 109 is formed in the lightly doped drain region 112.
  • the P-LDMOS which does not include the lightly doped drain region 112 has a low withstand voltage, the on-resistance is large, and only a peak of the surface electric field appears at the source end, and the channel is deep enough and sufficient to avoid the source punch-through. Large, the concentration should be high enough, otherwise the withstand voltage is only about 5V, so in order to completely deplete the drift region and increase its withstand voltage capability, the P-LDMOS must be provided with a lightly doped drain region 112. The arrangement of the lightly doped drain region 112 complicates the fabrication process of the P-LDMOS.
  • the longitudinal breakdown voltage of the P-LDMOS is mainly shared by the S layer 103 and the I layer 102. According to the Gauss's theorem, the electric field of the I layer 102 during longitudinal breakdown is:
  • c is the critical breakdown electric field of the S layer 103
  • & and & are the dielectric constants of the S layer 103 and the I layer 102, respectively
  • ⁇ and & are the dielectric constants of the S layer 103 and the I layer 102, respectively
  • ⁇ and & are the dielectric constants of the S layer 103 and the I layer 102, respectively
  • ⁇ and & are the dielectric constants of the S layer 103 and the I layer 102, respectively
  • ⁇ is the interface charge introduced between the S layer 103 and the I layer 102.
  • the longitudinal pressure of the device is:
  • V BV ⁇ 0.5t s + ? >t I )E sc ( 3 )
  • the longitudinal breakdown voltage increases with the thickness of the S layer 103 and the thickness of the I layer 102, and the longitudinal breakdown voltage of the I layer of the same thickness is the S layer. 3 times.
  • the longitudinal breakdown voltage can be increased to some extent by increasing the thickness of the S layer or the I layer.
  • the S layer is too thick, there is a great difficulty in forming the dielectric isolation region in the S layer; if the I layer is too thick, the process is difficult to implement and is not conducive to heat dissipation of the device. Therefore, due to the structure and process limitations of the device, the S layer and the I layer should not be too thick, which limits the increase of the vertical breakdown voltage of the SOI type P-LDMOS, thereby limiting the increase of the breakdown voltage and affecting its application range.
  • the embodiment of the present invention provides the following technical solutions:
  • An SOI type P-LDMOS includes: a semiconductor substrate layer, a dielectric buried layer, and a semiconductor active layer, wherein the semiconductor active layer has a plurality of spaced n + doped regions located in the dielectric buried layer and the semiconductor active layer a side of the semiconductor active layer of the interface of the layers;
  • the concentration of the n + doped region ranges from 1 10 16 cm - 3 to 1 10 20 cm" 3 o
  • the injection pattern of the n + doped region is circular, rectangular, trapezoidal, triangular, square or hexagonal.
  • n + doped region is circular, rectangular, trapezoidal, triangular, square or hexagonal.
  • the ions doped in the n + doping region are the fifth main group element of phosphorus, arsenic, antimony or bismuth.
  • the distances between adjacent n + doped regions are equal or unequal.
  • the depth into which each of the n + doped regions protrudes into the semiconductor active layer is equal or unequal.
  • the material of the semiconductor active layer is Si, SiC, GaAs, SiGe or GaN.
  • a silicon window for dissipating heat is disposed in the buried layer of the medium.
  • the material of the dielectric buried layer is SiO 2 , CDO or SiOF.
  • a medium groove is disposed in the interval between the n + doped regions;
  • the material of the dielectric groove is Si0 2 , a low dielectric constant material or a variable dielectric constant material.
  • a medium groove is disposed in the interval between the n + doped regions
  • One side of the dielectric trench is an n + doped region, and the other side is a p + doped region;
  • the material of the dielectric groove is Si0 2 , a low dielectric constant material or a variable dielectric constant material.
  • a plurality of n + doped regions are disposed at a side of the semiconductor active layer side located at the interface between the dielectric buried layer and the semiconductor active layer.
  • the interface forms an interface charge island between two adjacent un-depleted n + doped regions.
  • the breakdown voltage of LDMOS enables it to increase the range of high voltage applications.
  • the withstand voltage capability of the SOI type P-LDMOS is improved, the setting of the lightly doped drain region can be eliminated, that is, the SOI type P-LDMOS provided by the present invention does not include the lightly doped drain region, and further The manufacturing process of the SOI type P-LDMOS can be completed, and the production efficiency can be improved.
  • FIG. 1 is a schematic structural view of a typical SOI type P-LDMOS in the prior art
  • FIG. 2 is a schematic diagram of a longitudinal electric field distribution under a source region of a conventional SOI type P-LDMOS
  • FIG. 3 is a schematic diagram showing a partial structure of an SOI type P-LDMOS according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic structural diagram of an SOI type P-LDMOS according to Embodiment 1 of the present invention
  • FIG. 6 is an isometric line division of a SOI type P-LDMOS in reverse breakdown according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic diagram of interface hole density distribution when a SOI type P-LDMOS is broken down according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic diagram showing a longitudinal electric field distribution when a SOI type P-LDMOS is broken down according to Embodiment 1 of the present invention.
  • FIG. 9 is a schematic diagram showing a partial structure of an SOI type P-LDMOS according to Embodiment 2 of the present invention
  • FIG. 10 is a partial structural diagram of an SOI type P-LDMOS according to Embodiment 3 of the present invention
  • Another partial structure diagram of the provided SOI type P-LDMOS is a schematic diagram showing a partial structure of an SOI type P-LDMOS according to Embodiment 2 of the present invention.
  • FIG. 10 is a partial structural diagram of an SOI type P-LDMOS according to Embodiment 3 of the present invention. Another partial structure diagram of the provided SOI type P-LDMOS;
  • FIG. 12 is a schematic diagram showing still another partial structure of a SOI type P-LDMOS according to Embodiment 3 of the present invention.
  • 13a is a schematic diagram of a withstand voltage mechanism of an n + doped region according to a third embodiment of the present invention.
  • FIG. 13b is a schematic diagram showing the equipotential line distribution of the n + doped region according to the third embodiment of the present invention
  • FIG. 14a is a schematic diagram of the withstand voltage mechanism of the p + doped region according to the third embodiment of the present invention
  • FIG. 14b is a schematic diagram showing an equipotential line distribution of a p + doped region according to a third embodiment of the present invention
  • FIG. 15a is a schematic diagram of a pressure withstand mechanism of a dielectric trench according to Embodiment 3 of the present invention
  • 15b is a schematic diagram showing the equipotential line distribution of a dielectric slot according to Embodiment 3 of the present invention.
  • 101 semiconductor substrate layer
  • 102 dielectric buried layer
  • 103 semiconductor active layer
  • 104 dielectric isolation region
  • 105 gate oxide layer
  • 106 gate electrode
  • 107 n well
  • 108 p + Source region
  • 109 p + drain region
  • 110 drain electrode
  • 111 source electrode
  • 112 lightly doped drain region
  • 113 n + doped region
  • 114 silicon window
  • 115 dielectric trench
  • 116 p + Doped area.
  • the SOI type P-LDMOS in the prior art is limited by structure and process, and the S layer and the I layer are not too thick, which limits the increase of the vertical breakdown voltage of the SOI type P-LDMOS, thereby limiting the breakdown voltage thereof. Improvement has affected its scope of application.
  • FIG. 3 a schematic diagram of the equipotential line distribution of the SOI type P-LDMOS excluding the lightly doped drain region, it can be seen that the surface electric field of the P-LDMOS has only one peak appearing at the source end, and its on-resistance is very high. Large, low pressure.
  • the P-LDMOS in order to completely deplete the drift region, avoid source penetration, and improve its withstand voltage capability, the P-LDMOS must be provided with a lightly doped drain region.
  • the setting of the lightly doped drain region complicates the manufacturing process of the P-LDMOS.
  • an embodiment of the present invention provides an SOI type P-LDMOS, including: a semiconductor substrate layer, a dielectric buried layer, and a semiconductor active layer; and the semiconductor active layer has a plurality of spaced n + dopings
  • a plurality of n + doped regions are disposed at a side of the semiconductor active layer side located at the interface between the dielectric buried layer and the semiconductor active layer.
  • the interface forms an interface charge island between two adjacent un-depleted n + doped regions.
  • the breakdown voltage of LDMOS enables it to increase the range of high voltage applications.
  • the withstand voltage capability of the SOI type P-LDMOS is improved, the setting of the lightly doped drain region can be eliminated, that is, the SOI type P-LDMOS provided by the present invention does not include the lightly doped drain region, and further The manufacturing process of the SOI type P-LDMOS can be completed, and the production efficiency can be improved.
  • Embodiment 1 is a core idea of the present invention.
  • the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Rather than all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • Embodiment 1 is a core idea of the present invention.
  • FIG. 4 is a partial structural diagram of the device, including: a semiconductor substrate layer 101, a dielectric buried layer 102, and a semiconductor active layer 103.
  • a dielectric isolation region 104 two dielectric isolation regions defining an active region of the device, a gate oxide layer 105, a gate electrode 106 on the gate oxide layer 105, an n-well 107 in the active region, located in the n-well 107
  • the semiconductor active layer 103 has a plurality of spaced-apart n + doped regions 113 disposed on the side of the semiconductor active layer 103 at the interface between the dielectric buried layer 102 and the semiconductor active layer 103.
  • the P-LDMOS is different from the existing P-LDMOS in that the present embodiment provides a light-doped drain region in the semiconductor active layer 103 of the P-LDMOS, and the p + drain region 109 is directly formed in the semiconductor. Inside the active layer 103.
  • the plurality of n+ doping regions 113 may be dispersedly disposed on the dielectric buried layer
  • the portion of the interface between 102 and the semiconductor active layer 103 is within a range or a whole range.
  • the n+ doping region 113 may be a semiconductor material, and the n+ doping region 113 of the semiconductor material may be directly formed by applying ion implantation techniques and devices in the prior art. Since the insulating material is not present in the n+ doping region 113 of the semiconductor material, the generation of the self-heating effect of the attached port can be avoided.
  • the n+ doping region 113 may be doped at a high concentration to contain a relatively high concentration of electrons therein to fix the inversion hole, thereby improving the buried layer of the dielectric. Electric field strength.
  • the concentration of the doped ions is greater than 1 10 16 cm" 3 , preferably between 1 10 16 cm -3 and 1 10 2 cm -3 .
  • the n+ doping region 113 may be formed in the semiconductor active layer by an ion implantation process.
  • the material of the n+ doping region 113 may be SiO 2 (silicon oxide), a low dielectric constant material, or a variable dielectric constant material.
  • the ions implanted in the n+ doping region 113 may be: a fifth main group element of phosphorus, arsenic, antimony or bismuth.
  • the injection pattern of the n+ doping region 113 may be: a circle, an ellipse, a triangle, a square, a rectangle, a trapezoid, a hexagon, or other patterns.
  • the implantation patterns of each n + doped region may be the same or different, and the range of distribution of each n + doped region at the interface of the dielectric buried layer 102 and the semiconductor active layer 103 may be equal or unequal.
  • the depth of each of the n + doped regions implanted into the semiconductor active layer 103 may be equal or unequal.
  • the distance between adjacent two n + doped regions may also be equal or unequal.
  • the material of the semiconductor active layer 103 may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), SiGe (silicon germanium), GaN (gallium nitride) or the like. semiconductors.
  • the material of the dielectric buried layer 102 may be SiO 2 or a low dielectric constant material, and the low dielectric constant material may be CDO (carbon doped oxide) or SiOF (fluorine containing silicon oxide).
  • the structure of the SOI type P-LDMOS provided in this embodiment can be specifically applied to a PN junction of a P-LDMOS, an IGBT (Insulated Gate Bipolar Transistor), an SOI and a PSOI (partial SOI) structure.
  • FIG. 5 it is a schematic diagram of a cell structure of a local region of the interface between the dielectric buried layer 102 and the semiconductor active layer 103 of the SOI type P-LDMOS shown in FIG. 4;
  • FIG. 6 is the reverse of the P-LDMOS. Schematic diagram of the equipotential line distribution at the time of breakdown;
  • FIG. 7 is a schematic diagram showing the interface hole density distribution when the P-LDMOS is broken down, and
  • FIG. 8 is a schematic diagram showing the longitudinal electric field distribution when the P-LDMOS is broken down. .
  • an interface charge island is formed between two adjacent un-depleted n + doped regions, and holes are accumulated in the intersection of the semiconductor active layer 103 and the dielectric buried layer 102 under the action of electron Coulomb force.
  • the interface can effectively increase the value of the second term on the right side of the background technology formula (1), thereby increasing the electric field strength of the dielectric buried layer and increasing the longitudinal breakdown voltage of the device.
  • the principle of the device having the SOI structure provided by the embodiment is the same as that of the P-LDMOS, and the similarities can be referred to each other, and details are not described herein again.
  • Embodiment 2 is the same as that of the P-LDMOS, and the similarities can be referred to each other, and details are not described herein again.
  • this embodiment provides another structure of the SOI type P-LDMOS, as shown in FIG. 9, which is a partial structure diagram of the device.
  • the SOI type P-LDMOS includes: a semiconductor substrate layer 101, a dielectric buried layer 102, a semiconductor active layer 103, and an n + doping region 113, and the n + doping region 113 is located on the dielectric buried layer 102 and the semiconductor active layer 103.
  • the interface of the semiconductor active layer 103-side, the dielectric buried layer 102 can also be provided with heat dissipation Silicon window 114.
  • one or more silicon windows 114 may be disposed in the dielectric buried layer 102, and the distribution of each silicon window may be equal or unequal.
  • Embodiment 3 focuses on the differences between the SOI-type P-LDMOS and the first embodiment, and the similarities are not mentioned here.
  • the heat dissipation of the SOI type P-LDMOS can be accelerated, and the self-heating effect of the device can be effectively alleviated.
  • FIG. 10 a partial structural diagram of the SOI type P-LDMOS provided in this embodiment is shown.
  • the SOI type P-LDMOS includes: a semiconductor substrate layer 101, a dielectric buried layer 102, a semiconductor active layer 103, and an n+ doping region 113, and the n+ doping region 113 is located at an interface between the dielectric buried layer 102 and the semiconductor active layer 103.
  • a dielectric groove 115 is disposed in the space between the n + doped regions 113, and the material of the dielectric groove 115 is Si0 2 , a low dielectric constant material or a variable dielectric constant material.
  • FIG. 11 another partial structure of the SOI type P-LDMOS provided in this embodiment is shown.
  • the SOI type P-LDMOS includes: a semiconductor substrate layer 101, a dielectric buried layer 102, a semiconductor active layer 103, and an n+ doping region 113, and the n+ doping region 113 is located at an interface between the dielectric buried layer 102 and the semiconductor active layer 103.
  • the n + doped region may be a combination of a SiO 2 , a low dielectric constant material or a variable dielectric constant material and a p + doped region 116 .
  • FIG. 12 another partial structure of the SOI type P-LDMOS provided in this embodiment is shown.
  • the SOI type P-LDMOS includes: a semiconductor substrate layer 101, a dielectric buried layer 102, a semiconductor active layer 103, and an n+ doping region 113, and the n+ doping region 113 is located at an interface between the dielectric buried layer 102 and the semiconductor active layer 103.
  • One side of the dielectric trench 115 is an n + doped region 113 and the other side is a p + doped region 116;
  • the material of the dielectric groove 115 is Si0 2 , a low dielectric constant material or a variable dielectric constant material.
  • the withstand voltage mechanism of the n + doped region is as shown in FIG. 13a, and the equipotential line distribution diagram is shown in FIG. 13b;
  • the withstand voltage mechanism of the p + doped region is as shown in FIG. 14a, its equipotential line distribution diagram is shown in Figure 14b;
  • the pressure resistance mechanism of the dielectric tank is shown in Figure 15a, and its equipotential line distribution is shown in Figure 15b.
  • the ionization impurity Coulomb force effect and the electric field force combination effect of the undepleted n + doped region will bind the accumulated holes at the interface of the dielectric layer, and enhance the dielectric field by the interface charge.
  • the ionization impurity Coulomb force and the electric field force combination of the undepleted p + doped region will bind the inversion electron at the interface of the dielectric layer, using the interface charge pair
  • the enhancement of the dielectric field and the weakening effect on the top silicon electric field to improve the voltage withstand capability of the device; the dielectric trench can block the extraction of the inversion layer charge (hole) by the transverse electric field, thereby binding a high concentration charge in the dielectric tank to enhance the buried Layer electric field, improve the pressure resistance of the device.
  • This embodiment provides various specific structures of the SOI type P-LDMOS having a higher breakdown voltage, and focuses on the difference from the SOI type P-LDMOS provided in the first embodiment, and the similarities thereof are referred to each other. Yes, I won't go into details here.
  • a plurality of n + doped regions are disposed at a side of the semiconductor active layer side located at the interface between the dielectric buried layer and the semiconductor active layer. Compared with the prior art, the interface forms an interface charge island between two adjacent un-depleted n + doped regions. When a voltage is applied, holes accumulate in the semiconductor active under the action of Coulomb force.
  • the interface between the layer and the dielectric buried layer can enhance the electric field strength of the dielectric buried layer, thereby increasing the longitudinal breakdown voltage of the device, so as to improve the SOI type P without increasing the thickness of the semiconductor active layer and the dielectric buried layer.
  • the breakdown voltage of LDMOS enables it to increase the range of high voltage applications.
  • the setting of the lightly doped drain region can be eliminated, that is, the SOI type P-LDMOS provided by the present invention does not include the lightly doped drain region, and further Can be a manufacturer of SOI type P-LDMOS Art, improve its production efficiency.
  • the n + doped region is a semiconductor material, wherein no insulating material exists, so that generation of an additional self-heating effect can be avoided.
  • the ions doped in the n + doped region are formed by an ion implantation process, the process cartridge is single, and can be sufficiently compatible with existing processes.
  • the SOI type P-LDMOS provided by the present invention can be applied to a common SOI lateral power device, and is particularly suitable for a SIMOX (separation by implantation of oxygen) process.
  • the solution provided by the present invention is applied to a high voltage power device or a power integrated circuit, and its withstand voltage capability is greatly improved compared with the conventional SOI type P-LDMOS due to the significant enhancement of the electric field of the dielectric layer.
  • the various embodiments of the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments may be referred to each other. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention.

Description

一种 SOI型 P-LDMOS
本申请要求于 2010 年 12 月 30 日提交中国专利局、 申请号为 201010612349.2、 发明名称为"一种 S0I型 P-LDM0S"的中国专利申请的优先 权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件技术领域， 特别涉及一种 SOI型 P-LDMOS。
背景技术
SOI ( Semiconductor On Insulator, 绝缘衬底上的硅 )功率器件具有较高的 工作速度和集成度、 较好的绝缘性能、 较强的抗辐射能力、 以及无可控硅自锁 效应等优势， 因此， SOI功率器件在超大规模集成电路领域的应用得到广泛关 注， 但其存在较低的击穿电压和自热效应等缺陷， 限制了其应用范围。 SOI功 率器件的击穿电压取决于横向击穿电压和纵向击穿电压的较低者。在横向击穿 电压控制上可沿用现有成熟的 Si基器件横向耐压设计原理和技术， 因此， 如 何提高纵向击穿电压成为 SOI功率器件研究中的一个难点。
如图 1所示，为典型的 SOI型的 P-LDMOS( P-lateral double-diffusion MOS ,
P沟道横向双扩散金属氧化物半导体） 的结构示意图， 其中， 101为半导体衬 底层， 102为 I层 （ Insulator层， 介质埋层；)， 103为 S层（ Semiconductor层， 半导体有源层）， 104 为介质隔离区， 两个介质隔离区定义了器件的有源区， 105为栅氧化层， 106为栅氧化层上的栅电极， 107为有源区中的 n阱， 108 为位于 n阱中的 p+源区， 109为 p+漏区， 110为形成于漏区上的漏电极， 111 为形成于 p+源区 108上的源电极， 112为有源区中形成的轻掺杂漏区域，其中， p+漏区 109形成于轻掺杂漏区域 112中。
由于不包括轻掺杂漏区域 112的 P-LDMOS的耐压低， 导通电阻很大， 表 面电场只有一个尖峰出现在源端， 为了避免其出现源下穿通， 其沟道要足够深 和足够大， 浓度也要足够高， 否则其耐压只有 5V左右， 所以为了完全的耗尽 漂移区， 提高其耐压能力， P-LDMOS就必须设置轻掺杂漏区域 112。 轻掺杂 漏区域 112的设置使 P-LDMOS的制造工艺较为复杂。 P-LDMOS的纵向击穿电压主要由 S层 103和 I层 102共同承担， 根据高 斯定理， 纵向击穿时的 I层 102电场 为：
Figure imgf000004_0001
其中， ， c是 S层 103的临界击穿电场， &和 &分别是 S层 103和 I层 102 的介电常数， „为 S层 103与 I层 102间引入的界面电荷。 由此可知该器件 纵向 压为：
Figure imgf000004_0002
其中， 和 分别是 I层 102和 S层 103的厚度。
对于如图 1所示的 SOI型 P-LDMOS , 由于横向电场对电荷的抽取， 上述
( 1 )和（2 ) 式右边第二项可以忽略不计， 所以当 S层 103为硅， I层 102为 二氧化硅时， E^Es'c , 从而可知该器件纵向击穿电压为：
VB V = {0.5ts + ? >tI )Es c ( 3 ) 源区下纵向电场分布如图 2所示（ =5μιη, 尸 Ι μιη, 仿真结果）。 可见， I 层 102击穿电场受 S层 103击穿电场的限制，纵向击穿电压随 S层 103厚度和 I层 102厚度的增加而提高， 且同样厚度的 I层纵向击穿电压为 S层的 3倍。
由上述结构的 SOI型 P-LDMOS可知，通过增加 S层或 I层的厚度能够在 一定程度上提高其纵向击穿电压。但是， 若 S层太厚， 则在 S层中形成介质隔 离区会存在较大的困难；若 I层太厚，则工艺实施难度大，且不利于器件散热。 因此， 受器件结构和工艺的限制， S 层和 I 层都不能太厚， 限制了 SOI 型 P-LDMOS的纵向击穿电压的提高， 进而限制了其击穿电压的提高， 影响了其 应用范围。 发明内容
本发明的目的在于提供一种 SOI型的 P-LDMOS , 以实现通过提高其纵向 击穿电压， 进而提高该器件的击穿电压， 扩展 SOI型 P-LDMOS的应用范围。 为解决上述问题， 本发明实施例提供了如下技术方案：
一种 SOI型 P-LDMOS, 包括： 半导体衬底层、介质埋层和半导体有源层， 所述半导体有源层内具有多个间隔设置的 n+掺杂区，位于介质埋层与半导体有 源层的交界面的半导体有源层一侧；
所述 P-LDMOS的半导体有源层内无轻掺杂漏区域。
优选的，
所述 n+掺杂区的浓度范围为 1 1016cm-3至 1 1020cm"3 o
优选的，
所述 n+掺杂区的注入图形为圆形、矩形、梯形、三角形、正方形或六边形。 优选的，
所述 n+掺杂区内掺杂的离子为磷、 砷、 锑或铋的第五主族元素。
优选的，
相邻的 n+掺杂区之间相隔的距离为相等或不等。
优选的，
每个 n+掺杂区伸入至所述半导体有源层内的深度为相等或不等。
优选的， 相等或不等。
优选的，
所述半导体有源层的材质为 Si, SiC, GaAs, SiGe或 GaN。
优选的，
所述介质埋层中设置有散热的硅窗口。
优选的，
所述介质埋层的材料为 Si02、 CDO或 SiOF。
优选的，
所述 n+掺杂区之间的间隔中设置有介质槽； 所述介质槽的材料为 Si02、 低介电常数材料或变介电常数材料。 优选的，
所述 n+掺杂区之间的间隔中设置有介质槽；
所述介质槽的一侧为 n+掺杂区， 另一侧为 p+掺杂区；
所述介质槽的材料为 Si02、 低介电常数材料或变介电常数材料。
与现有技术相比， 上述技术方案具有以下优点：
本发明实施例提供的 SOI型 P-LDMOS中，在位于介质埋层与半导体有源 层的交界面的半导体有源层一侧间隔的设置了多个 n+掺杂区。该方案与现有技 术相比，相邻的两个未耗尽的 n+掺杂区之间形成了界面电荷岛，当外加电压时， 在库仑力的作用下， 空穴积累在半导体有源层与介质埋层的交界面， 能够增强 介质埋层的电场强度，从而提高该器件的纵向击穿电压， 以实现在不增加半导 体有源层和介质埋层厚度的前提下，提高 SOI型 P-LDMOS的击穿电压， 实现 其提升高压应用范围的能力。 同时， 由于该 SOI型 P-LDMOS中的耐压能力得 到了提高， 因此可以取消其轻掺杂漏区域的设置， 即本发明提供的 SOI 型 P-LDMOS中不包括轻掺杂漏区域， 进而可以筒化 SOI型 P-LDMOS的制造工 艺， 提高其生产效率。
附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1为现有技术中典型的 SOI型 P-LDMOS结构示意图；
图 2为现有的 SOI型 P-LDMOS源区下纵向电场分布示意图；
图 3为本发明实施例一提供的 SOI型 P-LDMOS的局部结构示意图； 图 4为本发明实施例一提供的 SOI型 P-LDMOS的一种结构示意图； 图 5为本发明实施例一提供的 SOI型 P-LDMOS的介质埋层和半导体有源 层交界面的元胞结构示意图；
图 6为本发明实施例一提供的 SOI型 P-LDMOS在反向击穿时的等势线分 布示意图；
图 7为本发明实施例一提供的 SOI型 P-LDMOS击穿时的界面空穴密度分 布示意图；
图 8为本发明实施例一提供的 SOI型 P-LDMOS击穿时的纵向电场分布示 意图；
图 9为本发明实施例二提供的 SOI型 P-LDMOS的局部结构示意图； 图 10为本发明实施例三提供的 SOI型 P-LDMOS的一种局部结构示意图； 图 11为本发明实施例三提供的 SOI型 P-LDMOS的另一种局部结构示意 图；
图 12为本发明实施例三提供的 SOI型 P-LDMOS的又一种局部结构示意 图；
图 13a为本发明实施例三提供的 n+掺杂区的耐压机理示意图；
图 13b为本发明实施例三提供的 n+掺杂区的等势线分布示意图； 图 14a为本发明实施例三提供的 p+掺杂区的耐压机理示意图；
图 14b为本发明实施例三提供的 p+掺杂区的等势线分布示意图； 图 15a为本发明实施例三提供的介质槽的耐压机理示意图；
图 15b为本发明实施例三提供的介质槽的等势线分布示意图。
上述图中标记： 101 : 半导体衬底层， 102: 介质埋层， 103: 半导体有源层， 104: 介质隔 离区， 105: 栅氧化层， 106: 栅电极， 107: n阱， 108: p+源区， 109: p+漏区， 110: 漏电极， 111 : 源电极， 112: 轻掺杂漏区域， 113 : n+掺杂区， 114: 硅 窗口， 115: 介质槽， 116: p+掺杂区。 具体实施方式
现有技术中的 SOI型 P-LDMOS受结构和工艺的限制， S层和 I层都不能 太厚， 限制了 SOI型 P-LDMOS的纵向击穿电压的提高， 进而限制了其击穿电 压的提高， 影响了其应用范围。 此外，如图 3所示， 为不包括轻掺杂漏区域的 SOI型 P-LDMOS的等势线 分布示意图， 可知该 P-LDMOS的表面电场只有一个尖峰出现在源端， 其导通 电阻很大， 耐压低。 因此， 为了完全的耗尽漂移区， 避免出现源下贯通， 提高 其耐压能力， P-LDMOS 就必须设置轻掺杂漏区域。 轻掺杂漏区域的设置使 P-LDMOS的制造工艺较为复杂。
为此，本发明实施例提供了一种 SOI型 P-LDMOS, 包括： 半导体衬底层、 介质埋层和半导体有源层； 所述半导体有源层内具有多个间隔设置的 n+掺杂
P-LDMOS的半导体有源层内无轻掺杂漏区域。
本发明实施例提供的 SOI型 P-LDMOS中，在位于介质埋层与半导体有源 层的交界面的半导体有源层一侧间隔的设置了多个 n+掺杂区。该方案与现有技 术相比，相邻的两个未耗尽的 n+掺杂区之间形成了界面电荷岛，当外加电压时， 在库仑力的作用下， 空穴积累在半导体有源层与介质埋层的交界面， 能够增强 介质埋层的电场强度，从而提高该器件的纵向击穿电压， 以实现在不增加半导 体有源层和介质埋层厚度的前提下，提高 SOI型 P-LDMOS的击穿电压， 实现 其提升高压应用范围的能力。 同时， 由于该 SOI型 P-LDMOS中的耐压能力得 到了提高， 因此可以取消其轻掺杂漏区域的设置， 即本发明提供的 SOI 型 P-LDMOS中不包括轻掺杂漏区域， 进而可以筒化 SOI型 P-LDMOS的制造工 艺， 提高其生产效率。
以上是本发明的核心思想， 下面将结合本发明实施例中的附图，对本发明 实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本 发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普 通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本 发明保护的范围。 实施例一：
本实施例提供了一种 SOI型 P-LDMOS , 如图 4所示， 为该器件的一种局 部结构示意图， 包括： 半导体衬底层 101 , 介质埋层 102, 半导体有源层 103 , 介质隔离区 104, 两个介质隔离区定义了该器件的有源区， 栅氧化层 105 , 位 于为栅氧化层 105上的栅电极 106, 位于有源区中的 n阱 107, 位于 n阱 107 中的 p+源区 108, p+漏区 109,形成于漏区上的漏电极 110,形成于 p+源区 108 上的源电极 111。
所述半导体有源层 103内具有多个间隔设置的 n+掺杂区 113 ,位于介质埋 层 102与半导体有源层 103的交界面的半导体有源层 103—侧。
同时， 该 P-LDMOS与现有的 P-LDMOS的一个不同之处在于， 本实施例 提供 P-LDMOS的半导体有源层 103内无轻掺杂漏区域， p+漏区 109直接形成 于半导体有源层 103内。
本发明实施例中， 所述多个 n+掺杂区 113可以分散式的设置于介质埋层
102和半导体有源层 103交界面的部分范围内或全部范围内。
为了与现有的工艺充分的兼容， 所述 n+掺杂区 113可以为半导体材质， 半导体材质的 n+掺杂区 113可以直接通过应用现有技术中离子注入技术和设 备形成。 由于半导体材质的 n+掺杂区 113 中不存在绝缘材料， 因此能够避免 附力口自热效应的生成。
为了保证 n+掺杂区 113不被完全耗尽， 所述 n+掺杂区 113可以为高浓度 掺杂， 以使其内部含有较高浓度的电子来固定反型空穴，从而提高介质埋层的 电场强度。 具体的， 所述 n+掺杂区 113 中， 掺杂的离子的浓度的范围大于 1 1016cm"3, 较佳的可以为 1 1016cm-3至 1 102。cm-3之间。
本实施例中， 所述 n+掺杂区 113可以通过离子注入工艺在半导体有源层 中形成。 n+掺杂区 113的材料可以为 Si02 (氧化硅）、 低介电常数材料或变介 电常数材料。 n+掺杂区 113中注入的离子可以为： 磷、 砷、 锑或铋的第五主族 元素。
所述 n+掺杂区 113的注入图形可以为： 圆形、 椭圆形、 三角形、 正方形、 矩形、 梯形、 六边形或其它图形。 每个 n+掺杂区的注入图形可以相同或不同， 且每个 n+掺杂区在介质埋层 102和半导体有源层 103交界面上分布的范围可以 为相等或不等。 本实施例中，每个 n+掺杂区注入至所述半导体有源层 103内的深度可以为 相等或不等。 相邻的两个 n+掺杂区之间相隔的距离也可以为相等或不等。
此外， 本实施例中， 所述半导体有源层 103 的材质可以为 Si (硅）、 SiC (碳化硅）、 GaAs (砷化镓）、 SiGe (硅锗）、 GaN (氮化镓）或其它半导体材 料。 所述介质埋层 102的材料可以为 Si02或低介电常数材料、 所述低介电常 数材料可以为 CDO (碳掺杂氧化物）或 SiOF (含氟氧化硅）。
本实施例所提供的 SOI 型 P-LDMOS 的结构， 可以具体的应用于 P-LDMOS, IGBT ( Insulated Gate Bipolar Transistor, 绝缘栅双极型晶体管；)、 SOI及 PSOI (部分 SOI )结构的 PN结二极管、 SOI及 PSOI结构的 PN结二 极管、 SOI及 PSOI结构的横向晶闸管。
如图 5所示，为附图 4中所示的 SOI型 P-LDMOS的介质埋层 102和半导 体有源层 103交界面的局部区域的元胞结构示意图； 图 6为该 P-LDMOS在反 向击穿时的而为等势线分布示意图； 图 7所示为该 P-LDMOS击穿时的界面空 穴密度分布示意图， 图 8所示为该 P-LDMOS击穿时的纵向电场分布示意图。 由上述可知，相邻的两个未耗尽的 n+掺杂区之间形成了界面电荷岛，在电子库 仑力的作用下， 空穴积累在半导体有源层 103与介质埋层 102的交界面， 能够 有效的增加背景技术部分公式（ 1 ) 中等号右边的第二项的值， 从而能够提高 介质埋层的电场强度，提高该器件的纵向击穿电压。其它具有本实施例提供的 SOI结构的器件的原理与 P-LDMOS类同， 其相似之处可相互参见， 在此不再 赘述。 实施例二：
为了解决 SOI型 P-LDMOS的自热效应，本实施例提供了 SOI型 P-LDMOS 的另一种结构， 如图 9所示， 为该器件的局部结构示意图。
所述 SOI型 P-LDMOS包括： 半导体衬底层 101、 介质埋层 102、 半导体 有源层 103和 n+掺杂区 113 , n+掺杂区 113位于介质埋层 102与半导体有源层 103的交界面的半导体有源层 103—侧， 所述介质埋层 102中还可以设置散热 的硅窗口 114。
具体的， 所述介质埋层 102中可以设置一个或多个硅窗口 114, 每个硅窗 口的分布的范围可以为相等或不等。
本实施例着重描述和实施例一提供的 SOI型 P-LDMOS的不同之处，其类 同之处相互参见即可， 在此不再赘述。 通过在介质埋层设置的硅窗口， 可以加 快 SOI型 P-LDMOS的散热， 有效的緩解器件的自热效应。 实施例三：
如图 10所示， 为本实施例提供的 SOI型 P-LDMOS的一种局部结构示意 图。
所述 SOI型 P-LDMOS包括： 半导体衬底层 101、 介质埋层 102、 半导体 有源层 103和 n+掺杂区 113 , n+掺杂区 113位于介质埋层 102与半导体有源层 103的交界面的半导体有源层 103—侧；
所述 n+掺杂区 113之间的间隔中设置有介质槽 115 , 所述介质槽 115的材 料为 Si02、 低介电常数材料或变介电常数材料。
如图 11所示， 为本实施例提供的 SOI型 P-LDMOS的另一种局部结构示 意图。
所述 SOI型 P-LDMOS包括： 半导体衬底层 101、 介质埋层 102、 半导体 有源层 103和 n+掺杂区 113 , n+掺杂区 113位于介质埋层 102与半导体有源层 103的交界面的半导体有源层 103—侧；
所述 n+掺杂区可以为 Si02、 低介电常数材料或变介电常数材料和 p+掺杂 区 116的结合。
如图 12所示， 为本实施例提供的 SOI型 P-LDMOS的另一种局部结构示 意图。
所述 SOI型 P-LDMOS包括： 半导体衬底层 101、 介质埋层 102、 半导体 有源层 103和 n+掺杂区 113 , n+掺杂区 113位于介质埋层 102与半导体有源层 103的交界面的半导体有源层 103—侧； 替换页 （细则第 26条) 所述 n+掺杂区之间的间隔中设置有介质槽 115;
所述介质槽 115的一侧为 n+掺杂区 113 , 另一侧为 p+掺杂区 116;
所述介质槽 115的材料为 Si02、 低介电常数材料或变介电常数材料。 本实施例提供的 SOI型 P-LDMOS中， n+掺杂区的耐压机理如图 13a所示， 其等势线分布示意图如图 13b所示； p+掺杂区的耐压机理如图 14a所示， 其等 势线分布示意图如图 14b所示； 介质槽的耐压机理如图 15a所示， 其等势线分 布示意图如图 15b所示。
本实施例 SOI型 P-LDMOS中，未耗尽的 n+掺杂区的电离杂质库仑力作用 以及电场力综合作用将在介质层界面束縛积累的空穴，利用界面电荷对介质场 的增强作用和对顶层硅电场的削弱作用来提高器件耐压能力；未耗尽的 p+掺杂 区的电离杂质库仑力作用以及电场力综合作用将在介质层界面束縛反型的电 子，利用界面电荷对介质场的增强作用和对顶层硅电场的削弱作用来提高器件 耐压能力;介质槽可以阻挡横向电场对反型层电荷 （空穴） 的抽取， 从而在介 质槽内束縛高浓度电荷以增强埋层电场， 提高器件耐压能力。
本实施例提供了具有较高击穿电压的 SOI型 P-LDMOS的多种具体结构， 着重描述了和实施例一提供的 SOI型 P-LDMOS的不同之处，其类同之处相互 参见即可， 在此不再赘述。 本发明实施例提供的 SOI型 P-LDMOS中，在位于介质埋层与半导体有源 层的交界面的半导体有源层一侧间隔的设置了多个 n+掺杂区。该方案与现有技 术相比，相邻的两个未耗尽的 n+掺杂区之间形成了界面电荷岛，当外加电压时， 在库仑力的作用下， 空穴积累在半导体有源层与介质埋层的交界面， 能够增强 介质埋层的电场强度，从而提高该器件的纵向击穿电压， 以实现在不增加半导 体有源层和介质埋层厚度的前提下，提高 SOI型 P-LDMOS的击穿电压， 实现 其提升高压应用范围的能力。 同时， 由于该 SOI型 P-LDMOS中的耐压能力得 到了提高， 因此可以取消其轻掺杂漏区域的设置， 即本发明提供的 SOI 型 P-LDMOS中不包括轻掺杂漏区域， 进而可以筒化 SOI型 P-LDMOS的制造工 艺， 提高其生产效率。
此外， 本发明实施例中， 所述 n+掺杂区为半导体材质， 其中不存在绝缘材 料， 因此能够避免附加自热效应的生成。所述 n+掺杂区中掺杂的离子通过离子 注入工艺形成， 工艺筒单， 且能够和现有工艺充分的兼容。
本发明提供的 SOI型 P-LDMOS能够适用于常见的 SOI横向功率器件，特 别适用于 SIMOX ( separation by implantation of oxygen, 注氧隔离）工艺。 将 本发明提供的方案应用于高压功率器件或功率集成电路中，其耐压能力由于介 质层电场的显著增强而较常规的 SOI型 P-LDMOS大大提高。 本发明说明书中各个实施例采用递进的方式描述，每个实施例重点说明的 都是与其他实施例的不同之处， 各个实施例之间相同相似部分互相参见即可。 对所公开的实施例的上述说明， 使本领域专业技术人员能够实现或使用本发 明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它 实施例中实现。 因此， 本发明将不会被限制于本文所示的这些实施例， 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1、 一种 SOI型 P-LDMOS , 包括： 半导体衬底层、 介质埋层和半导体有 源层， 其特征在于：
所述半导体有源层内具有多个间隔设置的 n+掺杂区，位于介质埋层与半导 体有源层的交界面的半导体有源层一侧；
所述 P-LDMOS的半导体有源层内无轻掺杂漏区域。
2、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述 n+掺杂区的浓度范围为 1 1016cm-3至 1 1020cm"3 o
3、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述 n+掺杂区的注入图形为圆形、矩形、梯形、三角形、正方形或六边形。
4、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述 n+掺杂区内掺杂的离子为磷、 砷、 锑或铋的第五主族元素。
5、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
相邻的 n+掺杂区之间相隔的距离为相等或不等。
6、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
每个 n+掺杂区伸入至所述半导体有源层内的深度为相等或不等。
7、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于： 相等或不等。
8、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述半导体有源层的材质为 Si, SiC, GaAs, SiGe或 GaN。
9、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述介质埋层中设置有散热的硅窗口。
10、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述介质埋层的材料为 Si02、 CDO或 SiOF。
11、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于：
所述 n+掺杂区之间的间隔中设置有介质槽； 所述介质槽的材料为 Si02、 低介电常数材料或变介电常数材料。
12、 根据权利要求 1所述的 SOI型 P-LDMOS, 其特征在于： 所述 n+掺杂区之间的间隔中设置有介质槽；
所述介质槽的一侧为 n+掺杂区， 另一侧为 p+掺杂区；
所述介质槽的材料为 Si02、 低介电常数材料或变介电常数材料。
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