WO2012069262A1 - Verfahren zum herstellen eines optoelektronischen halbleiterchips und derartiger halbleiterchip - Google Patents
Verfahren zum herstellen eines optoelektronischen halbleiterchips und derartiger halbleiterchip Download PDFInfo
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- WO2012069262A1 WO2012069262A1 PCT/EP2011/068476 EP2011068476W WO2012069262A1 WO 2012069262 A1 WO2012069262 A1 WO 2012069262A1 EP 2011068476 W EP2011068476 W EP 2011068476W WO 2012069262 A1 WO2012069262 A1 WO 2012069262A1
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- layer stack
- semiconductor
- semiconductor chip
- growth substrate
- semiconductor layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 183
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 134
- 238000000034 method Methods 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- 230000005855 radiation Effects 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 29
- 230000006911 nucleation Effects 0.000 claims description 23
- 238000010899 nucleation Methods 0.000 claims description 23
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 238
- 238000011161 development Methods 0.000 description 15
- 230000018109 developmental process Effects 0.000 description 15
- 239000013078 crystal Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02461—Phosphides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2301/00—Functional characteristics
- H01S2301/17—Semiconductor lasers comprising special layers
- H01S2301/173—The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/3201—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures incorporating bulkstrain effects, e.g. strain compensation, strain related to polarisation
Definitions
- the invention relates to a method for producing an optoelectronic semiconductor chip comprising a
- LEDs light-emitting diodes
- a growth substrate for example, a GaAs substrate is used.
- a GaAs substrate is used.
- an AlInGaP semiconductor layer sequence is pseudomorphically grown on such a GaAs growth substrate, such LEDs produced due to the band at short wavelengths in the range of about 530 to 590 nm only a small depth of the potential well, which disadvantageously high internal
- Semiconductor layer sequences are used, for example, GaAs or GaP growth substrates. However, due to tensile stresses between, for example, a GaAs growth substrate and a semiconductor layer sequence, the active layer of the semiconductor layer sequence can not be included
- GaP substrates find use, however, which are disadvantageously available only in small wafer sizes and at high prices.
- Wafer composite can be produced.
- Claim 1 and by a semiconductor chip, which is produced by such a method, having the features of claim 11 solved.
- Semiconductor layer stack based on the material system AlInGaP comprises the following process steps:
- An optoelectronic semiconductor chip is, in particular, a semiconductor chip which enables the conversion of electronically generated data or energies into light emission or
- Semiconductor chip a radiation-emitting semiconductor chip, such as an LED or a laser diode.
- the growth substrate comprises silicon.
- the growth substrate has a silicon surface facing the semiconductor layer stack.
- the semiconductor layer stack has a silicon surface facing the semiconductor layer stack.
- the growth substrate may also be formed as a silicon volume substrate or as an SOI substrate ("silicon on _insulator substrate”) .
- the growth substrate may contain, in addition to silicon, further materials or material components.
- silicon is a cost-effective growth substrate material that
- the semiconductor layers advantageously on a low-cost and with a large disk diameter of up to 300 mm available Si growth substrate
- Semiconductor layer stack arranged buffer layer stack advantageously allows the production of metamorphic AlInGaP semiconductor layers. metamorphic
- Lattice constants of the materials Such grown semiconductor layers thus have a high crystal quality, which allows an improved radiation efficiency in the operation of the semiconductor chips. Due to the buffer layer stack, a difference in lattice constants of the growth substrate material and the semiconductor layer stack material can be compensated. These are almost all dislocations due to
- Lattice mismatching is included in the relaxed buffer layer stack so that no dislocations or distortions occur in the semiconductor layer stack.
- Pseudomorphic semiconductor layers are in particular
- the growth substrate material and the layer stack material and acts in a strain of the layer.
- the lattice mismatch does not affect dislocations.
- the semiconductor layer stack is based on the AlInGaP material system. This means that the semiconductor layer sequence is an epitaxially deposited on the substrate layer sequence which has at least one layer of AlInGaP connecting material, so Al n Ga m In] __ _ m n P, with
- This material does not have to necessarily have a mathematically exact composition according to the above formula. Rather, it can be one or more
- AlInGaP material does not change.
- the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, P), although these may be partially replaced by small amounts of other substances.
- the active layer of the semiconductor layer stack preferably contains a pn junction, a double heterostructure, a single quantum well structure (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation.
- SQL single quantum well structure
- MQW multiple quantum well structure
- quantum wells In terms of the dimensionality of the quantization. It includes, among other things, quantum wells, quantum wires and
- Quantum dots and any combination of these structures.
- a pseudomorphic intermediate layer is applied to the growth substrate and subsequently to the
- Buffer layer stack applied to the intermediate layer.
- the interlayer because of its pseudomorphic
- the intermediate layer is, for example, a buffer layer which has GaAllnPAs and is pseudomorphic to silicon.
- the intermediate layer is between growth substrate and
- Buffer layer stack arranged.
- the use of such an intermediate layer allows the growth of the layers of the semiconductor layer stack with compressive prestressing on the silicon growth substrate, which prevents occurring mechanical damage of the epitaxial layers.
- a nucleation layer is applied to the substrate before the intermediate layer is applied
- the nucleation layer has, for example, AlGaP.
- the nucleation layer is
- the intermediate layer in particular arranged between the intermediate layer and the growth substrate.
- the buffer layer stack is gradual to the larger lattice constant in dislocations
- the AlInGaP semiconductor layer stack then becomes on the buffer layer stack
- Buffer layer stack grown.
- the buffer layer stack advantageously has a lattice constant adapted to the lattice constant of the growth substrate on the side of the growth substrate, and a lattice constant adapted to the lattice constant of the growth substrate and to the side of the semiconductor layer stack
- Lattice constant of the semiconductor layer stack adapted lattice constant.
- Lattice constant of the buffer layer stack increased by the addition of indium and / or arsenic. In one direction from
- Semiconductor chip can be avoided, which is characterized by increased radiation efficiency in the operation of the semiconductor chip
- the buffer layer stack is thus composed of a layer sequence, each having a lattice constant such that the
- Buffer layer stack one adapted to silicon
- the method has the following further method steps:
- the silicon growth substrate is thus at least partially or completely detached after the epitaxial deposition of the layers of the semiconductor layer stack. So can one
- Semiconductor chip are produced, which is known in the art as a thin-film chip.
- a semiconductor chip is regarded as a thin-film chip, during its production the growth substrate on which the
- the carrier substrate has silicon, for example, is formed, for example, as a silicon volume substrate.
- Such a silicon carrier substrate is distinguished by a low-cost substrate material which is optimally thermally matched to the semiconductor layers and the growth substrate.
- Carrier substrate is when the material of the carrier substrate has a good thermal connection and thermal conductivity.
- the mirror layer arranged.
- the mirror layer faces
- a metal or a metal alloy for example, a metal or a metal alloy.
- Radiation decoupling structures can be three-dimensional
- Structures ie structures that are spatially formed, can be used.
- a radiation decoupling for example, a roughening of the remote from the carrier substrate surface of the semiconductor chip can be used.
- the radiation coupling-out structures can arise, for example, in the detachment process of the growth substrate, wherein in the detachment process, moreover, the nucleation layer, the Intermediate layer and / or the Buffer Anlagenpel can be at least partially detached.
- Buffer layer stack formed.
- the radiation generated in the active layer can be improved and coupled out of the semiconductor chip with greater efficiency, since the angle of the radiation which is formed in the active layer and impinges on the surface of the semiconductor chip is changed due to the coupling-out structures, the total reflection effect of the radiation at the surface is reduced.
- Semiconductor chips grown on a common growth substrate made of silicon Since silicon is available as a substrate material in large diameters of up to 12 inches, so a large number of semiconductor chips can be grown together on the substrate, which allows advantageously mass production of semiconductor chips in a process.
- a semiconductor chip fabricated by a method as described above has a carrier substrate and a semiconductor layer stack on the carrier substrate.
- the semiconductor layer stack is based on the AlInGaP material system.
- the carrier substrate preferably has a good thermal conductivity. For example, this indicates Support substrate on silicon, is formed for example as a silicon volume substrate.
- This mirror layer arranged. This mirror layer leads
- Radiation efficiency during operation of the semiconductor chip can be increased.
- the semiconductor chip is on the side remote from the carrier substrate side of the
- Such semiconductor chip a high crystal quality
- the side of the semiconductor chip facing away from the semiconductor layer stack is
- Buffer layer stack arranged an intermediate layer comprising AlInGaAsP.
- the intermediate layer is for example an optional buffer layer that is pseudomorphic to silicon.
- the intermediate layer and / or the buffer layer stack have a structuring.
- This structuring serves in particular to increase the
- Radiation decoupling and can be generated for example by the detachment process of the growth substrate.
- the semiconductor chip is preferably an LED, a thin-film LED or a laser.
- Figure 1 is a schematic cross section of a
- FIG. 2 is a flowchart with the individual
- Figure 3 is a schematic cross section of a
- Size ratios among each other are basically not to be considered as true to scale. Rather, individual can
- Components such as layers, structures,
- FIG. 1 shows an exemplary embodiment of a semiconductor chip 10 in cross section in the production process.
- the semiconductor chip 10 has a growth substrate 2 which comprises silicon. On the silicon growth substrate 2, individual layers of the semiconductor chip 10 are grown.
- Silicon growth substrate 2 a special growth or nucleation process is used. Such a process offers the possibility of growth of
- Growth on silicon surfaces includes, in particular, the growth of a nucleation layer 5 on the surface
- the nucleation layer 5 contains, for example, AIP, GaP or AlGaP.
- an intermediate layer 4 can be applied to the nucleation layer.
- the intermediate layer 4 is
- a buffer layer comprising AlInGaAsP.
- the intermediate layer 4 may have pseudomorphic properties to silicon. Pseudomorph means that the
- Interlayer lattice mismatched to silicon that is, the lattice constant of the intermediate layer deviates from the lattice constant of the growth substrate, although the stress generated thereby is not relaxed in dislocations.
- the intermediate layer 4 further serves to reduce the defect.
- the intermediate layer 4 serves to improve the morphology of the nucleation layer 5.
- the semiconductor layers to be applied can be deposited with improved crystalline quality and homogeneity.
- the buffer layer stack can be composed of a layer sequence.
- the buffer layer stack can be composed of a layer sequence.
- Buffer layer stack AlInGaAsP.
- the buffer layer stack 3 has compressively relaxed properties, with which a high-quality buffer layer stack can be achieved. Due to the compressively relaxing buffer layer stack, the semiconductor layers to be applied with high crystal quality can be deposited on this buffer layer stack
- Damage to the layers of the semiconductor chip can be avoided or reduced so.
- the lattice constant of the buffer layer stack increases
- the lattice constant of the buffer layer stack on the growth substrate side can be matched to the lattice constant of the growth substrate and at the same time to the semiconductor layer stack to be applied to the lattice constant of this semiconductor layer stack
- Advantage tensions in the layers of the semiconductor chip during the growth process can be reduced or avoided, creating a higher
- An increase in the lattice constant of the buffer layer stack in the direction of the semiconductor layer stack to be applied can be achieved, for example, by adding indium and / or by adding arsenic.
- the areas of the buffer layer stack have a higher indium and / or arsenic content on the side of the semiconductor layer stack to be applied than the areas of the buffer layer stack on the side of the growth substrate 2.
- Buffer layers formed so the lattice constant of the buffer layers can be arranged in the direction
- the lattice constant in the buffer layer stack has a step-shaped elevation to be applied from the growth substrate in the direction
- Semiconductor layer stack hardly occur or not relax in dislocations.
- the semiconductor layer stack 1 is based on the
- Semiconductor chip an LED chip, a thin-film chip or a
- the present production method allows
- Substrate material for the production of metamorphic AlInGaP semiconductor chips using a compressively relaxed and therefore high-quality buffer layer stack is provided.
- silicon is the substrate material
- Method step may be on the side facing away from the growth substrate 2 side of the semiconductor layer stack 1 a
- Carrier substrate are applied, in which case the growth substrate is partially or completely detached. This makes it possible to produce a thin-film chip.
- the carrier substrate preferably also comprises silicon, which is characterized by its cost-effectiveness.
- the silicon carrier substrate used for the thin-film chip makes it possible to realize a cost-effective semiconductor chip whose carrier substrate is optimally thermally matched to the semiconductor layers of the semiconductor chip and the growth substrate. A ready-made semiconductor chip will be explained in more detail below in conjunction with FIG.
- FIG. 2 shows a flow chart for producing an optoelectronic semiconductor chip using the method according to the invention.
- a silicon growth substrate is provided. On a growth page of the
- a nucleation layer is applied, which is optional for the growth of
- Semiconductor layers on the silicon surface can be used. In particular, due to the
- Nucleation layer defective reduced semiconductor layers are grown on the silicon surface of the growth substrate. Silicon as a growth substrate is particularly preferred because of the inexpensive substrate material.
- a pseudomorphic intermediate layer is subsequently applied to the nucleation layer
- the intermediate layer is, for example, a buffer layer made of AlInGaAsP, which can furthermore optionally be used for a defectively reduced epitaxy of semiconductor layers on the silicon growth substrate.
- Intermediate layer serves, for example, to improve the morphology of the nucleation layer, whereby the
- applied semiconductor layers can be deposited with an improved crystalline quality and homogeneity.
- a compressively relaxed buffer layer stack is deposited on the intermediate layer.
- the buffer layer stack preferably has a gradually increasing lattice constant in the direction away from the growth substrate.
- Semiconductor layer stack grown metamorphic epitaxially on the buffer layer stack.
- the semiconductor layer stack is lattice-matched on the
- Buffer layer stack grown, whereby strains in the layers of the semiconductor layer stack are avoided or not relax in dislocations, which has a positive effect on the radiation efficiency of the semiconductor chip in operation.
- step 205 the side of the side facing away from the growth substrate is subsequently coated on
- the carrier substrate preferably also has inexpensive silicon.
- the carrier substrate may be on the Semiconductor layer stack side facing a mirror layer, so that the mirror layer between the semiconductor layer stack and carrier substrate is arranged.
- Interlayer may be at least partially in this
- the structuring may extend into the buffer layer stack, so that this too is at least partially detached.
- FIG. 3 shows a semiconductor chip
- the semiconductor chip has a carrier substrate 6 made of silicon. On the carrier substrate 6, a mirror layer 7 is arranged. On the mirror layer 7 is the
- Semiconductor layer stack 1 is arranged, the one to the
- the mirror layer 7 is thus arranged between the carrier substrate 6 and the semiconductor layer stack 1. On the side facing away from the carrier substrate 6 side of
- the buffer layer stack 3 is arranged.
- the buffer layer stack 3 has unevenness or so-called radiation decoupling structures 8, which have been produced by the detachment process of the growth substrate.
- the intermediate layer 4 is at least partially arranged.
- the intermediate layer 4 is at least partially removed due to the detachment process of the growth substrate, so that only residues of the intermediate layer 4 are arranged on the buffer layer stack 3.
- the intermediate layer 4 is structured
- the semiconductor chip 10 is in
- Embodiment of Figure 3 formed as a thin-film LED.
- the semiconductor chip 10 as a laser diode
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Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP11773460.8A EP2643859A1 (de) | 2010-11-26 | 2011-10-21 | Verfahren zum herstellen eines optoelektronischen halbleiterchips und derartiger halbleiterchip |
CN201180056609.5A CN103222072B (zh) | 2010-11-26 | 2011-10-21 | 用于制造光电子半导体芯片的方法以及半导体芯片 |
JP2013540282A JP2013545312A (ja) | 2010-11-26 | 2011-10-21 | オプトエレクトロニクス半導体チップの製造方法およびそのような半導体チップ |
US13/883,782 US9093604B2 (en) | 2010-11-26 | 2011-10-21 | Method of producing an optoelectronic semiconductor chip, and such a semiconductor chip |
KR1020137015964A KR101470780B1 (ko) | 2010-11-26 | 2011-10-21 | 광전 반도체 칩의 제조 방법 및 그러한 반도체 칩 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010052727.0 | 2010-11-26 | ||
DE102010052727.0A DE102010052727B4 (de) | 2010-11-26 | 2010-11-26 | Verfahren zum Herstellen eines optoelektronischen Halbleiterchips und derartiger Halbleiterchip |
Publications (1)
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WO2012069262A1 true WO2012069262A1 (de) | 2012-05-31 |
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PCT/EP2011/068476 WO2012069262A1 (de) | 2010-11-26 | 2011-10-21 | Verfahren zum herstellen eines optoelektronischen halbleiterchips und derartiger halbleiterchip |
Country Status (8)
Country | Link |
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US (1) | US9093604B2 (de) |
EP (1) | EP2643859A1 (de) |
JP (1) | JP2013545312A (de) |
KR (1) | KR101470780B1 (de) |
CN (1) | CN103222072B (de) |
DE (1) | DE102010052727B4 (de) |
TW (1) | TWI523264B (de) |
WO (1) | WO2012069262A1 (de) |
Families Citing this family (5)
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US10715380B2 (en) | 2011-05-23 | 2020-07-14 | Apple Inc. | Setting a reminder that is triggered by a target user device |
US8971924B2 (en) | 2011-05-23 | 2015-03-03 | Apple Inc. | Identifying and locating users on a mobile network |
US9104896B2 (en) | 2012-06-04 | 2015-08-11 | Apple Inc. | System and method for remotely initiating lost mode on a computing device |
TWI790928B (zh) * | 2019-05-24 | 2023-01-21 | 晶元光電股份有限公司 | 半導體元件 |
US11721954B2 (en) | 2019-07-19 | 2023-08-08 | Visual Photonics Epitaxy Co., Ltd. | Vertical cavity surface emitting laser diode (VCSEL) having AlGaAsP layer with compressive strain |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19755009C1 (de) * | 1997-12-11 | 1999-08-19 | Vishay Semiconductor Gmbh | Verfahren zum Herstellen einer Halbleiteranordnung für Leuchtdioden |
WO2000034989A1 (en) * | 1998-12-11 | 2000-06-15 | Nova Crystals, Inc. | Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates |
US20050062049A1 (en) * | 2003-09-23 | 2005-03-24 | United Epitaxy Co., Ltd. | Series connection of two light emitting diodes through semiconductor manufacture process |
US20070181905A1 (en) * | 2006-02-07 | 2007-08-09 | Hui-Heng Wang | Light emitting diode having enhanced side emitting capability |
US20080149915A1 (en) * | 2006-06-28 | 2008-06-26 | Massachusetts Institute Of Technology | Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission |
US20080283819A1 (en) * | 2007-05-15 | 2008-11-20 | Hitachi Cable, Ltd. | Semiconductor light emitting device |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5866353A (ja) | 1981-10-15 | 1983-04-20 | Agency Of Ind Science & Technol | 半導体装置 |
JPS621293A (ja) | 1985-06-26 | 1987-01-07 | Sharp Corp | 半導体発光素子 |
JPS6258690A (ja) | 1985-09-04 | 1987-03-14 | Daido Steel Co Ltd | 砒素化ガリウム系半導体発光素子 |
JPH0371679A (ja) | 1989-08-11 | 1991-03-27 | Kokusai Denshin Denwa Co Ltd <Kdd> | 半導体発光素子 |
JPH04257276A (ja) * | 1991-02-08 | 1992-09-11 | Mitsubishi Cable Ind Ltd | 半導体素子 |
JP2962639B2 (ja) | 1993-09-06 | 1999-10-12 | シャープ株式会社 | 半導体発光素子 |
JPH10223929A (ja) * | 1996-12-05 | 1998-08-21 | Showa Denko Kk | AlGaInP発光素子用基板 |
DE10051465A1 (de) * | 2000-10-17 | 2002-05-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements auf GaN-Basis |
US6583034B2 (en) * | 2000-11-22 | 2003-06-24 | Motorola, Inc. | Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure |
JP4333426B2 (ja) | 2004-03-19 | 2009-09-16 | ソニー株式会社 | 化合物半導体の製造方法、及び半導体装置の製造方法 |
US7244630B2 (en) * | 2005-04-05 | 2007-07-17 | Philips Lumileds Lighting Company, Llc | A1InGaP LED having reduced temperature dependence |
JP2007096157A (ja) | 2005-09-30 | 2007-04-12 | Hitachi Cable Ltd | 半導体発光素子 |
US20080259980A1 (en) * | 2007-04-19 | 2008-10-23 | Philips Lumileds Lighting Company, Llc | Semiconductor Light Emitting Device Including Oxide Layer |
JP5146817B2 (ja) | 2008-03-24 | 2013-02-20 | スタンレー電気株式会社 | 半導体発光素子の製造方法 |
JP4721017B2 (ja) * | 2008-04-07 | 2011-07-13 | ソニー株式会社 | 半導体デバイスの製造方法 |
JP2010186829A (ja) * | 2009-02-10 | 2010-08-26 | Toshiba Corp | 発光素子の製造方法 |
US20100263707A1 (en) * | 2009-04-17 | 2010-10-21 | Dan Daeweon Cheong | Base structure for iii-v semiconductor devices on group iv substrates and method of fabrication thereof |
KR101047617B1 (ko) * | 2009-05-21 | 2011-07-07 | 엘지이노텍 주식회사 | 반도체 발광소자 및 그 제조방법 |
-
2010
- 2010-11-26 DE DE102010052727.0A patent/DE102010052727B4/de active Active
-
2011
- 2011-10-21 WO PCT/EP2011/068476 patent/WO2012069262A1/de active Application Filing
- 2011-10-21 CN CN201180056609.5A patent/CN103222072B/zh active Active
- 2011-10-21 KR KR1020137015964A patent/KR101470780B1/ko active IP Right Grant
- 2011-10-21 US US13/883,782 patent/US9093604B2/en active Active
- 2011-10-21 EP EP11773460.8A patent/EP2643859A1/de not_active Withdrawn
- 2011-10-21 JP JP2013540282A patent/JP2013545312A/ja active Pending
- 2011-10-27 TW TW100139073A patent/TWI523264B/zh not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19755009C1 (de) * | 1997-12-11 | 1999-08-19 | Vishay Semiconductor Gmbh | Verfahren zum Herstellen einer Halbleiteranordnung für Leuchtdioden |
WO2000034989A1 (en) * | 1998-12-11 | 2000-06-15 | Nova Crystals, Inc. | Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates |
US20050062049A1 (en) * | 2003-09-23 | 2005-03-24 | United Epitaxy Co., Ltd. | Series connection of two light emitting diodes through semiconductor manufacture process |
US20070181905A1 (en) * | 2006-02-07 | 2007-08-09 | Hui-Heng Wang | Light emitting diode having enhanced side emitting capability |
US20080149915A1 (en) * | 2006-06-28 | 2008-06-26 | Massachusetts Institute Of Technology | Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission |
US20080283819A1 (en) * | 2007-05-15 | 2008-11-20 | Hitachi Cable, Ltd. | Semiconductor light emitting device |
Also Published As
Publication number | Publication date |
---|---|
DE102010052727B4 (de) | 2019-01-31 |
CN103222072B (zh) | 2016-06-08 |
TWI523264B (zh) | 2016-02-21 |
CN103222072A (zh) | 2013-07-24 |
US9093604B2 (en) | 2015-07-28 |
US20130328101A1 (en) | 2013-12-12 |
KR101470780B1 (ko) | 2014-12-08 |
JP2013545312A (ja) | 2013-12-19 |
DE102010052727A1 (de) | 2012-05-31 |
KR20130098407A (ko) | 2013-09-04 |
EP2643859A1 (de) | 2013-10-02 |
TW201232817A (en) | 2012-08-01 |
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