WO2012054686A2 - Trench dmos device with improved termination structure for high voltage applications - Google Patents

Trench dmos device with improved termination structure for high voltage applications Download PDF

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Publication number
WO2012054686A2
WO2012054686A2 PCT/US2011/057020 US2011057020W WO2012054686A2 WO 2012054686 A2 WO2012054686 A2 WO 2012054686A2 US 2011057020 W US2011057020 W US 2011057020W WO 2012054686 A2 WO2012054686 A2 WO 2012054686A2
Authority
WO
WIPO (PCT)
Prior art keywords
termination
trench
substrate
region
termination structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/057020
Other languages
English (en)
French (fr)
Other versions
WO2012054686A3 (en
Inventor
Chih-Wei Hsu
Florin Udrea
Yih-Yin Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay General Semiconductor LLC
Original Assignee
Vishay General Semiconductor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay General Semiconductor LLC filed Critical Vishay General Semiconductor LLC
Priority to CN2011800509355A priority Critical patent/CN103180958A/zh
Priority to JP2013535075A priority patent/JP5990525B2/ja
Priority to KR1020137012912A priority patent/KR101836888B1/ko
Priority to EP11835123.8A priority patent/EP2630661B1/en
Publication of WO2012054686A2 publication Critical patent/WO2012054686A2/en
Publication of WO2012054686A3 publication Critical patent/WO2012054686A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H10D8/605—Schottky-barrier diodes  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]

Definitions

  • a key issue for achieving a high voltage Schottky rectifier is the design of its termination region.
  • the termination region is prone to higher electric fields due to the absence of self multi-cell protection and the curvature effect.
  • the breakdown voltage is typically dramatically reduced from its ideal value.
  • the termination region should be designed to reduce the crowding of the electric field at the edge of the device (near the active region).
  • Conventional approaches to reduce electric field crowding include termination structures with local oxidation of silicon (LOCOS) regions, field plates, guard rings, trenches and various combinations thereof.
  • LOC local oxidation of silicon
  • a high temperature oxidation process is performed to form gate oxide layer 125.
  • the gate oxide layer 125 which in some examples has a thickness between about 150 angstroms and 3000 angstroms, is formed on the sidewalls 110A, 120A and bottoms 110B, 120B of the first and second trenches 1 10, 120 and the surface of mesa 115.
  • the gate oxide layer 125 may be formed by high temperature deposition to form a HTO (high temperature oxide deposition) layer.
  • a first conductive layer 140 is formed by CVD on the gate oxide 125 and fills the first trenches 110 and the second trench 120.
  • the first conductive layer 140 has a thickness such that it extends over mesas 115.
  • the first conductive layer 140 may be any suitable material such as a metal, doped-polysilicon or doped-amorphous silicon.
  • the first conductive layer 140 may have a thickness of about 0.5 to 3.0 microns.
  • the first conductive layer 140 may be polysilicon formed by an LPCVD (low pressure CVD) process, which has good step coverage.
  • LPCVD low pressure CVD
  • amorphous silicon may be better able to eliminate voids than polysilicon.
  • a recrystallization process may be employed.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/US2011/057020 2010-10-21 2011-10-20 Trench dmos device with improved termination structure for high voltage applications Ceased WO2012054686A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2011800509355A CN103180958A (zh) 2010-10-21 2011-10-20 用于高压应用的具有改善终端结构的沟槽dmos器件
JP2013535075A JP5990525B2 (ja) 2010-10-21 2011-10-20 改善された終端構造を備えた高電圧用途のためのトレンチｄｍｏｓデバイス
KR1020137012912A KR101836888B1 (ko) 2010-10-21 2011-10-20 개선된 종단 구조 기술로 설계된 고전압 트렌치 dmos 소자
EP11835123.8A EP2630661B1 (en) 2010-10-21 2011-10-20 Trench dmos device with improved termination structure for high voltage applications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/909,033 US8928065B2 (en) 2010-03-16 2010-10-21 Trench DMOS device with improved termination structure for high voltage applications
US12/909,033 2010-10-21

Publications (2)

Publication Number Publication Date
WO2012054686A2 true WO2012054686A2 (en) 2012-04-26
WO2012054686A3 WO2012054686A3 (en) 2012-07-05

Family

ID=45975878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/057020 Ceased WO2012054686A2 (en) 2010-10-21 2011-10-20 Trench dmos device with improved termination structure for high voltage applications

Country Status (7)

Country Link
US (1) US8928065B2 (enExample)
EP (1) EP2630661B1 (enExample)
JP (1) JP5990525B2 (enExample)
KR (1) KR101836888B1 (enExample)
CN (1) CN103180958A (enExample)
TW (1) TWI565064B (enExample)
WO (1) WO2012054686A2 (enExample)

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CN103426906B (zh) * 2012-05-21 2016-05-04 科轩微电子股份有限公司 沟槽式功率金氧半场效晶体管与其制造方法
US9105494B2 (en) * 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
US9496382B2 (en) * 2013-11-21 2016-11-15 Chengdu Monolithic Power Systems Co., Ltd. Field effect transistor, termination structure and associated method for manufacturing
US9178015B2 (en) * 2014-01-10 2015-11-03 Vishay General Semiconductor Llc Trench MOS device having a termination structure with multiple field-relaxation trenches for high voltage applications
TWI546970B (zh) * 2014-05-13 2016-08-21 帥群微電子股份有限公司 半導體元件的終端結構及其製造方法
US9899477B2 (en) * 2014-07-18 2018-02-20 Infineon Technologies Americas Corp. Edge termination structure having a termination charge region below a recessed field oxide region
WO2016080322A1 (ja) * 2014-11-18 2016-05-26 ローム株式会社 半導体装置および半導体装置の製造方法
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TWI566410B (zh) * 2014-12-12 2017-01-11 漢磊科技股份有限公司 半導體元件、終端結構及其製造方法
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JP2017139289A (ja) * 2016-02-02 2017-08-10 トヨタ自動車株式会社 ダイオード
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US10388801B1 (en) * 2018-01-30 2019-08-20 Semiconductor Components Industries, Llc Trench semiconductor device having shaped gate dielectric and gate electrode structures and method
US10566466B2 (en) 2018-06-27 2020-02-18 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method
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CN109244136B (zh) * 2018-09-19 2021-07-27 电子科技大学 槽底肖特基接触SiC MOSFET器件
CN111092113B (zh) * 2018-10-24 2023-06-02 力士科技股份有限公司 金氧半场效应晶体管的终端区结构及其制造方法
TWI681458B (zh) * 2018-10-24 2020-01-01 禾鼎科技股份有限公司 金氧半場效應電晶體之終端區結構及其製造方法
CN109742135B (zh) * 2018-12-03 2022-05-20 北京大学深圳研究生院 一种碳化硅mosfet器件及其制备方法
CN110444583B (zh) * 2019-08-08 2023-04-11 江苏芯长征微电子集团股份有限公司 低成本高可靠性的功率半导体器件及其制备方法
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CN117936573B (zh) * 2024-01-25 2025-01-14 赛晶亚太半导体科技(浙江)有限公司 一种igbt半导体结构及其制造方法
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WESLEY CHIH-WEI HSU ET AL.: "A Novel Trench Termination Design for 100-V TMBS Diode Application", IEEE ELECTRON DEVICE LETTERS, vol. 22, no. 11, November 2001 (2001-11-01), pages 551 - 552, XP001110356, DOI: doi:10.1109/55.962660

Also Published As

Publication number Publication date
US20110227152A1 (en) 2011-09-22
JP2013545296A (ja) 2013-12-19
EP2630661A4 (en) 2014-01-22
TW201238050A (en) 2012-09-16
EP2630661A2 (en) 2013-08-28
KR20130093645A (ko) 2013-08-22
EP2630661B1 (en) 2018-01-03
KR101836888B1 (ko) 2018-03-09
CN103180958A (zh) 2013-06-26
TWI565064B (zh) 2017-01-01
WO2012054686A3 (en) 2012-07-05
US8928065B2 (en) 2015-01-06
JP5990525B2 (ja) 2016-09-14

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