TWI681458B - 金氧半場效應電晶體之終端區結構及其製造方法 - Google Patents

金氧半場效應電晶體之終端區結構及其製造方法 Download PDF

Info

Publication number
TWI681458B
TWI681458B TW107137622A TW107137622A TWI681458B TW I681458 B TWI681458 B TW I681458B TW 107137622 A TW107137622 A TW 107137622A TW 107137622 A TW107137622 A TW 107137622A TW I681458 B TWI681458 B TW I681458B
Authority
TW
Taiwan
Prior art keywords
layer
forming
trench
metal
doped region
Prior art date
Application number
TW107137622A
Other languages
English (en)
Other versions
TW202017044A (zh
Inventor
張淵舜
Original Assignee
禾鼎科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 禾鼎科技股份有限公司 filed Critical 禾鼎科技股份有限公司
Priority to TW107137622A priority Critical patent/TWI681458B/zh
Priority to US16/421,592 priority patent/US20200135846A1/en
Application granted granted Critical
Publication of TWI681458B publication Critical patent/TWI681458B/zh
Publication of TW202017044A publication Critical patent/TW202017044A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明提供一種金氧半場效應電晶體之終端區結構之製造方法。首先，於半導體基板上形成摻雜區，於摻雜區形成多個溝渠環。接著，形成閘極氧化層於各溝渠環內。下一步驟，以多晶矽沉積於閘極氧化層上方，進行多晶矽回蝕刻而於各溝渠環的二側壁形成自對準的二島狀多晶矽區，二島狀多晶矽區互不接觸。最後，形成絕緣氧化層於各溝渠環內並覆蓋金屬層於摻雜區，並對金屬層進行圖形佈建以形成不連續金屬層。

Description

金氧半場效應電晶體之終端區結構及其製造方法
本發明有關於一種金氧半場效應電晶體之終端區結構及其製造方法，更詳而言之，其為一種具有中高壓保護環之金氧半場效應電晶體之終端區結構及其製造方法。
金氧半場效應電晶體被廣泛地應用於電力裝置之切換元件，例如是電源供應器、整流器或低壓馬達控制器等等。現今之金氧半場效應電晶體多採取垂直結構的設計，例如溝渠式(trench)金氧半場效應電晶體，以提升元件密度。一般金氧半場效應電晶體會有主體區與終端區之設計，主體區設有電晶體元件，終端區位於主體區邊緣而用以提高元件邊緣的耐壓能力。最常見的終端區設計方式，是利用井區形成多個保護環(guard ring)，可降低終端區的電場迫使元件崩潰點發生在主體區。而為了不降低主體區的整體崩潰電壓能力，較合適的方式是確保在終端區中的崩潰電壓(其為側向崩潰電壓)大於主體區的崩潰電壓(其為垂直崩潰電壓)。
習知由井區形成之保護環之終端區結構，其保護環深度(即井區深度)與崩潰電壓成正比，增加保護環深度即可增加崩潰電壓，然而在半導體製程中，井區深度越深，意味著就需要更高的熱預算(thermal budge)來將雜質做趨入擴散，因此耐壓與磊晶層厚度亦成正比。這樣的製程，會使得實務上必須要選用更厚的磊晶層來製作產品，而這樣的選擇，會使產品的導通電阻增加，不利生產。
有鑑於上述習知的問題，本發明之目的在於提供一種具有中高壓崩潰電壓且不受保護環深度影響的金氧半場效應電晶體之終端區結構及其製造方法。
為達上述目的，本發明提供一種金氧半場效應電晶體之終端區結構之製造方法，依序包含下列步驟：於半導體基板上形成摻雜區；於摻雜區形成多個溝渠環；形成閘極氧化層於各溝渠環內；以多晶矽沉積於閘極氧化層上方；進行多晶矽回蝕刻而於各溝渠環的二側壁形成自對準的二島狀多晶矽區，二島狀多晶矽區互不接觸；形成絕緣氧化層於各溝渠環內；以及覆蓋金屬層於摻雜區，並對金屬層進行圖形佈建以形成不連續金屬層。
在一實施例中，於摻雜區形成該些溝渠環依序包含下列步驟：於摻雜區上方沉積硬質罩幕(hard mask)；於硬質罩幕上形成圖形化光阻(patterned photoresist)；以圖形化光阻於硬質罩幕進行溝渠環圖形佈建；以及進行乾蝕刻，於摻雜區形成該些溝渠環。
在一實施例中，於摻雜區形成該些溝渠環之後，以及形成閘極氧化層於各溝渠環內之前更包含下列步驟：形成犧牲氧化層於各溝渠環內，再移除犧牲氧化層。
在一實施例中，在形成絕緣氧化層於各溝渠環內之後，以及在覆蓋金屬層於摻雜區之前更包含下列步驟：於絕緣氧化層上形成圖形化光阻；以圖形化光阻於金氧半場效應電晶體之主體區對暴露的絕緣氧化層進行蝕刻以形成接觸窗，再移除圖形化光阻；以及通過接觸窗於主體區的摻雜區形成源極多晶矽區及重摻雜區。
在一實施例中，形成絕緣氧化層於各溝渠環內依序包含下列步驟：形成內層介電(Inter-Layer Dielectric,ILD)層於各溝渠環內；以及形成硼磷矽玻璃(Boro-Phospho-Silicate Glass,BPSG)層於內層介電層上。
在一實施例中，對金屬層進行圖形佈建以形成不連續金屬層依序包含下列步驟：於摻雜區上方沉積金屬層；於金屬層上方形成圖形化光阻；以圖形化光阻對金屬層進行蝕刻並移除圖形化光阻；以及形成不連續金屬層。
本發明另提供一種金氧半場效應電晶體之終端區結構，包含半導體基板、摻雜區、閘極氧化層、二島狀多晶矽區、絕緣氧化層以及不連續金屬層。摻雜區形成於半導體基板上，摻雜區具有多個溝渠環。閘極氧化層形成於各溝渠環內。二島狀多晶矽區形成於各溝渠環的二側壁的閘極氧化層上，二島狀多晶矽區互不接觸。絕緣氧化層覆蓋於二島狀多晶矽區上方。不連續金屬層形成於摻雜區及溝渠環內之閘極氧化層及絕緣氧化層上方。
在一實施例中，二島狀多晶矽區所使用之材料包含：多晶矽、摻雜多晶矽、金屬、非晶矽或上述之組合，且其中閘極氧化層所使用之材料為氧化矽。
在一實施例中，半導體基板包含基底(substrate)以及磊晶層(epitaxial layer)。磊晶層形成於基底上方。
在一實施例中，絕緣氧化層包含內層介電層以及硼磷矽玻璃層。硼磷矽玻璃層形成於內層介電層上方。
100‧‧‧基底
102‧‧‧磊晶層
104‧‧‧摻雜區
106‧‧‧硬質罩幕
108‧‧‧圖形化光阻
110‧‧‧溝渠環
112‧‧‧犧牲氧化層
114‧‧‧閘極氧化層
116‧‧‧多晶矽
118‧‧‧島狀多晶矽區
120‧‧‧內層介電層
122‧‧‧硼磷矽玻璃層
123‧‧‧圖形化光阻
124‧‧‧源極多晶矽區
126‧‧‧重摻雜區
128‧‧‧金屬層
130‧‧‧圖形化光阻
132‧‧‧不連續金屬層
圖1A至圖1D依序為根據本發明之一實施例說明形成溝渠環之製程中各階段的簡化截面圖。
圖2A至圖2B依序為根據本發明之一實施例說明形成與移除犧牲氧化層之製程中各階段的簡化截面圖。
圖3A至圖3C依序為根據本發明之一實施例說明形成島狀多晶矽區之製程中各階段的簡化截面圖。
圖4A至圖4C依序為根據本發明之一實施例說明形成絕緣氧化層、源極多晶矽區及重摻雜區之製程中各階段的簡化截面圖。
圖5A至圖5C依序為根據本發明之一實施例說明形成不連續金屬層之製程中各階段的簡化截面圖。
在圖式中，為了清楚起見，膜層、區域及/或結構元件的相對厚度及位置可能縮小或放大，且省略部分習知的元件。
圖1A至圖1D依序為根據本發明之一實施例說明形成溝渠環110之製程中各階段的簡化截面圖，其中最左邊為金氧半場效應電晶體之主體區邊緣。如圖1A所示，在此實施例中提供半導體基板。半導體基板可包含基底100以及磊晶層102。基底100由離子佈植第一導電型重摻雜物於矽基底所形成。磊晶層102磊晶地成長於基底100上方，並由離子佈植第一導電型輕摻雜物所形成。舉例而言，在一實施例中，第一導電型為N型，第二導電型為P型。在另一實施例中，第一導電型為P型，第二導電型為N型。接著，如圖1B所示，進行毯覆式本體植入及驅入製程(drive-in)以沿著磊晶層102上先形成第二導電型摻雜區104，例如形成P型井區於磊晶層102上方，之後再於摻雜區104上方沉積硬質罩幕106。接著，如圖1C所示，將光阻塗佈於硬質罩幕106上方並使用光罩進行曝光與顯影以形成圖形化光阻108。接著，如圖1D所示，先以圖形化光阻108為遮罩對暴露的硬質罩幕106進行蝕刻後移除圖形化光阻108，實現於硬質罩幕106進行溝渠環圖形佈建而定義出溝渠環的位置與範圍，再以蝕刻後剩下的硬質罩幕 106為遮罩對暴露的摻雜區104及其下方的磊晶層102進行蝕刻(例如乾蝕刻)，進而於摻雜區104形成多個溝渠環110。該些溝渠環110位於終端區，彼此互相獨立且均圍繞主體區邊緣。
圖2A至圖2B依序為根據本發明之一實施例說明形成與移除犧牲氧化層112之製程中各階段的簡化截面圖。如圖2A所示，以氧化方式形成犧牲氧化層112於各溝渠環110內。此時由於熱效應影響使得摻雜區104擴散，增加摻雜區104之厚度。接著，如圖2B所示，移除犧牲氧化層112及硬質罩幕106。
圖3A至圖3C依序為根據本發明之一實施例說明形成島狀多晶矽區118之製程中各階段的簡化截面圖。如圖3A所示，以氧化方式形成閘極氧化層114於摻雜區104上方並覆蓋各溝渠環110。接著，如圖3B所示，使用習知多晶矽沉積技術，例如化學氣相沉積(Chemical Vapor Deposition,CVD)、物理氣相沉積(Physical Vapor Deposition,PVD)或其他適當的成膜製程於溝渠環110內閘極氧化層114上沉積多晶矽116並填補各溝渠環110。應注意的是，終端區之溝渠環110寬度較寬，約為主體區之溝渠的10倍寬，各溝渠環110並無法為多晶矽116所填滿。接著，如圖3C所示，使用習知蝕刻製程，例如非等向性蝕刻、回蝕刻、乾蝕刻等，蝕刻多晶矽116，亦因終端區之溝渠環110寬度較寬，進行多晶矽回蝕刻時將於各溝渠環110的二側壁形成自對準的二島狀多晶矽區118，此二島狀多晶矽區118互不接觸。
圖4A至圖4C依序為根據本發明之一實施例說明形成絕緣氧化層、源極多晶矽區124及重摻雜區126之製程中各階段的簡化截面圖。如圖4A所示，以氧化方式形成絕緣氧化層於各溝渠環110內。在終端區結構中，絕緣氧化層用以覆蓋二島狀多晶矽區118，防止後續沉積的金屬層(參見後面圖5C所示的不連續金屬層132)導致二島狀多晶矽區118電連接形成等電位。在本實施例中，形成絕緣氧化層於各溝渠環110內依序包含下列步驟：形成內層介電層120於各溝渠 環110內，以及形成硼磷矽玻璃層122於內層介電層120上。接著，如圖4A所示，將光阻塗佈於絕緣氧化層(內層介電層120及硼磷矽玻璃層122)上並使用光罩進行曝光與顯影以形成圖形化光阻123。接著，如圖4B所示，以圖形化光阻123為遮罩於金氧半場效應電晶體之主體區(圖中最左邊為金氧半場效應電晶體之主體區邊緣)對暴露的絕緣氧化層(內層介電層120及硼磷矽玻璃層122)進行蝕刻形成接觸窗，再移除圖形化光阻123，然後以離子佈植方式通過接觸窗於主體區的摻雜區104形成第一導電型源極多晶矽區124，例如N型源極區。接著，如圖4C所示，最後進行毯覆式本體植入及驅入製程以形成第二導電型重摻雜區126，例如P型重摻雜區。
圖5A至圖5C依序為根據本發明之一實施例說明形成不連續金屬層132之製程中各階段的簡化截面圖。如圖5A所示，於摻雜區104上方沉積金屬層128。接著，如圖5B所示，將光阻塗佈於金屬層128上方並使用光罩進行曝光與顯影以形成圖形化光阻130。接著，如圖5C所示，以圖形化光阻130為遮罩對金屬層128進行蝕刻並移除圖形化光阻130，最後形成不連續金屬層132。不連續金屬層132用以感應金氧半場效應電晶體之終端區結構之側向電位，提升金氧半場效應電晶體之終端區結構側向之崩潰電壓。
如圖5C所示，本實施例之金氧半場效應電晶體之終端區結構，包含半導體基板、摻雜區104、閘極氧化層114、二島狀多晶矽區118、絕緣氧化層以及不連續金屬層132。半導體基板包含基底100以及磊晶層102，磊晶層102形成於基底100上方。摻雜區104形成於半導體基板上，更具體來說，摻雜區104是形成於磊晶層102上。摻雜區104具有多個溝渠環110。閘極氧化層114形成於各溝渠環110內。二島狀多晶矽區118形成於各溝渠環110的二側壁的閘極氧化層114上，二島狀多晶矽區118互不接觸。絕緣氧化層覆蓋於二島狀多晶矽區118上方，更具體來說，絕緣氧化層包含內層介電層120以及硼磷矽 玻璃層122，硼磷矽玻璃層122形成於內層介電層120上方。不連續金屬層132形成於摻雜區及溝渠環110內之閘極氧化層114及絕緣氧化層上方。
在一實施例中，二島狀多晶矽區所使用之材料包含多晶矽、摻雜多晶矽、金屬、非晶矽或上述之組合，且其中閘極氧化層所使用之材料為氧化矽。
下面表1與表2分別為本發明與習知之終端區結構在相同磊晶層條件下之保護環深度與崩潰電壓之模擬結果。如表1所示，本發明之終端區結構之崩潰電壓已與保護環深度無關，使得元件設計更有彈性，且在各溝渠環內不互相接觸之二島狀多晶矽區及不連續金屬層的作用下，側向崩潰電壓得以感應，再以分壓形式使得總和側向崩潰電壓得以提高，使元件崩潰點發生在主體區。如表2所示，習知之終端區結構之崩潰電壓與保護環深度成正比，保護環深度越深就需要越高的熱預算來將雜質做趨入擴散，且需要越厚的磊晶層容納保護環而導致導通電阻增加。
Figure 107137622-A0305-02-0009-1
Figure 107137622-A0305-02-0010-2
Figure 107137622-A0305-02-0010-4
本發明之終端區結構特別適用於溝渠式金氧半場效應電晶體之終端區結構，其可在主體區形成溝渠時同時形成終端區之溝渠環，因此可輕易整合而於主體區與終端區採用同一個三層光罩製程(包含形成有圖形化光阻108、123與130)，縮短製程時間，降低產品的成本。而且，相較於傳統井區式保護環，本發明之終端區結構使用溝渠式保護環(故稱為溝渠環)，可以縮短保護環的長度，進而縮小晶片面積，在特性上對於元件可降低崩潰電壓與保護環深度的敏感度，進一步提升良率及穩定性。
上述之目的在於解釋，各種特定細節是為了提供對於本發明之徹底理解。熟知本發明領域之通常知識者應可實施本發明，而無需其中某些特定細節。在其他實施例中，習知的結構及裝置並未顯示於方塊圖中。在圖式元件之間可能包含中間結構。所述的元件可能包含額外的輸入和輸出，其並未詳細描繪於附圖中。
若文中有元件A連接(或耦接)至元件B，元件A可能直接連接(或耦接)至元件B，亦或是經元件C間接地連接(或耦接)至元件B。若說明書載明元件、特徵、結構、程序或特性A會導致元件、特徵、結構、程序或特性B,其表示A至少為B之一部分原因，亦或是表示有其他元件、特徵、結構、程序或特性協助造成B。在說明書中所提到的“可能”一詞，其元件、特徵、程序或特性不受限於說明書中；說明書中所提到的數量不受限於“一”或“一個”等詞。
本發明無論就目的、手段及功效，在在均顯示其迥異於習知技術之特徵，為一大突破。惟須注意，上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明之範圍。雖然在這裡已闡明與解釋特定實施例與所揭露之應用，實施例並不意圖侷限於精確解釋，任何熟於此項技藝之人士均可在不違背本發明之技術原理及精神下，對實施例作修改與變化。也應當了解，在不背離本發明所揭露之精神與範疇下，本發明所揭露於此之元件與其之各種修正、變更、對於此領域之技術者為顯而易見之加以排列之延伸、操作、方法之細節，以及在此所揭露之裝置與方法將不被侷限，且應包含於下述專利申請範圍內。
100‧‧‧基底
102‧‧‧磊晶層
104‧‧‧摻雜區
110‧‧‧溝渠環
114‧‧‧閘極氧化層
118‧‧‧島狀多晶矽區
120‧‧‧內層介電層
122‧‧‧硼磷矽玻璃層
132‧‧‧不連續金屬層

Claims (9)

  1. 一種金氧半場效應電晶體之終端區結構之製造方法，依序包含下列步驟：提供一半導體基板，該半導體基板包含一基底以及一磊晶層，該磊晶層形成於該基底上方；於該磊晶層上形成一摻雜區；於該摻雜區形成多個溝渠環，該些溝渠環穿過該摻雜區進入到該磊晶層；形成一閘極氧化層於各該溝渠環內；以多晶矽沉積於該閘極氧化層上方；進行多晶矽回蝕刻而於各該溝渠環的二側壁形成自對準的二島狀多晶矽區，該二島狀多晶矽區互不接觸；形成一絕緣氧化層於各該溝渠環內；以及覆蓋一金屬層於該摻雜區，並對該金屬層進行圖形佈建以形成一不連續金屬層。
  2. 如申請專利範圍第1項所述之金氧半場效應電晶體之終端區結構之製造方法，其中於該摻雜區形成該些溝渠環依序包含下列步驟：於該摻雜區上方沉積一硬質罩幕；於該硬質罩幕上形成一圖形化光阻；以該圖形化光阻於該硬質罩幕進行溝渠環圖形佈建；以及進行乾蝕刻，於該摻雜區形成該些溝渠環。
  3. 如申請專利範圍第1項所述之金氧半場效應電晶體之終端區結構之製造方法，其中於該摻雜區形成該些溝渠環之後，以及形成該閘極氧化層於各該溝渠環內之前更包含下列步驟：形成一犧牲氧化層於各該溝渠環內，再移除該犧牲氧化層。
  4. 如申請專利範圍第1項所述之金氧半場效應電晶體之終端區結構之製造方法，其中在形成該絕緣氧化層於各該溝渠環內之後，以及在覆蓋該金屬層於該摻雜區之前更包含下列步驟：於該絕緣氧化層上形成一圖形化光阻；以該圖形化光阻於該金氧半場效應電晶體之一主體區對暴露的該絕緣氧化層進行蝕刻形成一接觸窗，再移除該圖形化光阻；以及通過該接觸窗於該主體區的該摻雜區形成一源極多晶矽區及一重摻雜區。
  5. 如申請專利範圍第1項所述之金氧半場效應電晶體之終端區結構之製造方法，其中形成該絕緣氧化層於各該溝渠環內依序包含下列步驟：形成一內層介電層於各該溝渠環內；以及形成一硼磷矽玻璃層於該內層介電層上。
  6. 如申請專利範圍第1項所述之金氧半場效應電晶體之終端區結構之製造方法，其中對該金屬層進行圖形佈建以形成該不連續金屬層依序包含下列步驟：於該摻雜區上方沉積該金屬層；於該金屬層上方形成圖形化光阻；以該圖形化光阻對該金屬層進行蝕刻並移除圖形化光阻；以及形成該不連續金屬層。
  7. 一種金氧半場效應電晶體之終端區結構，包含：一半導體基板，包含一基底以及一磊晶層，該磊晶層形成於該基底上方；一摻雜區，形成於該磊晶層上，該摻雜區具有多個溝渠環，該些溝渠環穿過該摻雜區進入到該磊晶層；一閘極氧化層，形成於各該溝渠環內； 二島狀多晶矽區，形成於各該溝渠環的二側壁的該閘極氧化層上，該二島狀多晶矽區互不接觸；一絕緣氧化層，覆蓋於該二島狀多晶矽區上方；以及一不連續金屬層，形成於該摻雜區及該溝渠環內之該閘極氧化層及該絕緣氧化層上方。
  8. 如申請專利範圍第7項所述之金氧半場效應電晶體之終端區結構，其中該二島狀多晶矽區所使用之材料包含：多晶矽、摻雜多晶矽、金屬、非晶矽或上述之組合，且其中該閘極氧化層所使用之材料為氧化矽。
  9. 如申請專利範圍第7項所述之金氧半場效應電晶體之終端區結構，其中該絕緣氧化層包含：一內層介電層；以及一硼磷矽玻璃層，形成於該內層介電層上方。
TW107137622A 2018-10-24 2018-10-24 金氧半場效應電晶體之終端區結構及其製造方法 TWI681458B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107137622A TWI681458B (zh) 2018-10-24 2018-10-24 金氧半場效應電晶體之終端區結構及其製造方法
US16/421,592 US20200135846A1 (en) 2018-10-24 2019-05-24 Termination structure of MOSFET and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107137622A TWI681458B (zh) 2018-10-24 2018-10-24 金氧半場效應電晶體之終端區結構及其製造方法

Publications (2)

Publication Number Publication Date
TWI681458B true TWI681458B (zh) 2020-01-01
TW202017044A TW202017044A (zh) 2020-05-01

Family

ID=69942406

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107137622A TWI681458B (zh) 2018-10-24 2018-10-24 金氧半場效應電晶體之終端區結構及其製造方法

Country Status (2)

Country Link
US (1) US20200135846A1 (zh)
TW (1) TWI681458B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113193036A (zh) * 2021-03-24 2021-07-30 深圳深爱半导体股份有限公司 晶体管终端结构及其制备方法
CN113675078B (zh) * 2021-08-24 2022-08-05 江苏东海半导体股份有限公司 Mos器件的形成方法
CN114784099B (zh) * 2022-06-21 2022-09-02 南京融芯微电子有限公司 一种mosfet电流路径优化结构及其制备方法
CN117238770B (zh) * 2023-11-01 2024-05-10 深圳市美浦森半导体有限公司 一种沟槽栅mosfet器件及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227152A1 (en) * 2010-03-16 2011-09-22 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
TWI521604B (zh) * 2007-05-09 2016-02-11 半導體組件工業公司 半導體元件及製備方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI521604B (zh) * 2007-05-09 2016-02-11 半導體組件工業公司 半導體元件及製備方法
US20110227152A1 (en) * 2010-03-16 2011-09-22 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications

Also Published As

Publication number Publication date
US20200135846A1 (en) 2020-04-30
TW202017044A (zh) 2020-05-01

Similar Documents

Publication Publication Date Title
TWI681458B (zh) 金氧半場效應電晶體之終端區結構及其製造方法
US9728632B2 (en) Deep silicon via as a drain sinker in integrated vertical DMOS transistor
TWI548086B (zh) 溝渠式橫向擴散金屬氧化半導體元件及其製造方法
TWI484567B (zh) 半導體結構與其製造方法
US10032766B2 (en) VDMOS transistors, BCD devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices
TWI463571B (zh) 半導體裝置的製造方法
TWI407564B (zh) 具有溝槽底部多晶矽結構之功率半導體及其製造方法
TWI515893B (zh) 垂直式功率金氧半場效電晶體與其形成方法
KR20120012705A (ko) 반도체 소자 및 그 제조 방법
CN107564953B (zh) 变容晶体管及其制造方法
TWI527096B (zh) Ｍｏｓ電晶體及其形成方法
TWI599041B (zh) 具有底部閘極之金氧半場效電晶體功率元件及其製作方法
TW201611269A (zh) 串聯式電晶體結構及其製造方法
TW201822295A (zh) 屏蔽閘極溝槽式半導體裝置及其製造方法
TWI517411B (zh) 半導體裝置、功率金屬氧化物半導體場效電晶體裝置及其製作方法
TWI566410B (zh) 半導體元件、終端結構及其製造方法
CN108400166A (zh) 在端子降低表面电场区域中具有端子沟槽的功率晶体管
TW201622139A (zh) 高壓半導體裝置與其製造方法
US20190067424A1 (en) Silicon carbide semiconductor device and method for manufacturing the same
KR20140015508A (ko) 반도체 장치
US10818495B2 (en) Semiconductor devices and methods of making the same
TW201405819A (zh) 半導體裝置及其製造方法
CN111092113B (zh) 金氧半场效应晶体管的终端区结构及其制造方法
CN108630533A (zh) 一种半导体器件的制造方法
TWI509813B (zh) 延伸源極－汲極金屬氧化物半導體電晶體及其形成方法