CN114784099B - 一种mosfet电流路径优化结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种MOSFET电流路径优化结构及其制备方法，包括：基底和位于基底表面的外延层，外延层的本体内靠近上表面处两侧均设有掺杂区，每个掺杂区包括N+掺杂区、P+掺杂区和P‑掺杂区，外延层的上表面开有两列凹槽组，外延层的上表面和凹槽表面均生长有闸极氧化层；闸极氧化层上表面沉积有顶部闸极多晶硅层，且位于凹槽内的闸极氧化层内沉积有闸极多晶硅部，闸极多晶硅部向上连接顶部闸极多晶硅层；闸极氧化层和顶部闸极多晶硅层的上表面沉积有介电层；介电层、P+掺杂区和N+掺杂区的上表面沉积有金属层。本发明将闸极多晶硅采间隔方式埋在通道间，不仅可提高载子迁移率，降低通道阻值，而且加快了切换速度，降低了功率损耗。
Description
技术领域
本发明属于半导体领域，特别涉及一种MOSFET电流路径优化结构及其制备方法。
背景技术
随着全球用电量的增加，对节能减碳的要求也与日俱增，因此高效率的功率组件也开始成为各个半导体业者追求的目标。所谓的高效率的功率组件必须满足能够承受高电压与高电流、可操作于高频率且具备低切换速度及低功率损耗等要求。因此以传统的硅作为基板的功率组件已不符合上述所要求。相较于传统硅材料，以目前的宽能隙材料碳化硅(SiC)和纯硅的特性较为接近，同样能满足上述需求，更适合做为体积较小的功率组件。
碳化硅是一种极性晶体，即不同极性面向就有不同的特性。对于以碳化硅为基底外延材料所做成的功率金属氧化物半导体场效晶体管(MOSFET)而言，除了制程如生长方式与闸极氧化层等问题要克服，最大的影响便是通道阻值，以平面式SiC MOSFET为例，如图1所示，其通道随着闸极电压增加而开启，电流I1延着闸极下方的XZ面(极性面0001)而流通，但以此极性面所流过的电流所产生的通道阻值却占了组件全部阻值的8成以上，导致组件不易发挥出碳化硅本身材料的优势。
发明内容
针对现有技术中存在的问题，本发明公开了一种MOSFET电流路径优化结构及其制备方法，将闸极多晶硅采间隔方式埋在通道间，不仅可提高载子迁移率，降低通道阻值，而且加快了切换速度，降低了功率损耗。
本发明的上述技术目的是通过以下技术方案得以实现的：
一种MOSFET电流路径优化结构，包括：
基底和位于基底表面的外延层；
所述外延层的本体内靠近上表面处两侧均设有掺杂区，每个所述掺杂区包括N+掺杂区、P+掺杂区和P-掺杂区，所述N+掺杂区和P+掺杂区均位于所述P-掺杂区内，所述P+掺杂区包覆所述N+掺杂区一侧边以及所述N+掺杂区平行于外延层上表面的部分区域，所述N+掺杂区和P+掺杂区的上表面与外延层上表面齐平；
所述外延层的上表面有两列对称设置的凹槽组, 且每列凹槽组包括若干等间距排列的凹槽，所述外延层的上表面和凹槽表面均生长有闸极氧化层，且所述闸极氧化层覆盖所述N+掺杂区部分上表面；
所述闸极氧化层上表面沉积有顶部闸极多晶硅层，且位于凹槽内的闸极氧化层内沉积有闸极多晶硅部，所述闸极多晶硅部向上连接顶部闸极多晶硅层；
所述闸极氧化层和顶部闸极多晶硅层的上表面沉积有介电层，且所述介电层包覆顶部闸极多晶硅层侧边；
所述介电层、P+掺杂区和N+掺杂区的上表面沉积有金属层。
优选地，所述基底和外延层均为碳化硅材料，且所述外延层为N型外延层。
优选地，所述凹槽的深度小于0.4μm，位于所述凹槽内的闸极氧化层同时与N+掺杂区、P-掺杂区和外延层接触。
优选地，位于所述凹槽内的闸极氧化层的厚度A取值为0.03 -0.08μm，位于所述外延层上表面的闸极氧化层的厚度B取值为0.08 -0.14μm，且厚度B大于厚度A。
优选地，所述P-掺杂区的布植材料为铝，且铝的整体浓度为1015cm-2等级。
优选地，所述N+掺杂区的布植材料为磷，且磷的整体浓度为1015cm-2等级。
优选地，所述P+掺杂区的布植材料为铝，且铝的整体浓度为1016cm-2等级。
优选地，所述顶部闸极多晶硅层的厚度为0.4-1.0μm。
优选地，所述金属层为铝金属层，且金属层厚度为3-5μm 。
一种MOSFET电流路径优化结构的制备方法，具体制备步骤如下：
S1：在所述外延层上表面沉积氧化物，之后利用光刻板完成曝光制程，接着在离子布植后将氧化物去除，同样的步骤重复三次依次形成P-掺杂区, N+掺杂区和P+掺杂区；
S2：使用一层光刻板在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层上蚀刻出通道内的凹槽，随后在1200-1300℃高温氧气环境下在外延层、N+掺杂区、P+掺杂区和凹槽表面生长出闸极氧化层；
S3：在闸极氧化层表面沉积形成闸极多晶硅I,且闸极多晶硅I填充在凹槽内的闸极氧化层表面；
S4：采用化学机械研磨方式清除表面的闸极多晶硅I，形成闸极多晶硅部，且闸极多晶硅部表面与闸极氧化层表面齐平；
S5：在1200-1300℃高温氧气环境下，将闸极多晶硅部表面氧化，使得闸极氧化层包覆闸极多晶硅部，再采用沉积氧化物方式将闸极氧化层表面垫高，使其厚度大于凹槽内的闸极氧化层；
S6：采用一层光刻板在闸极氧化层上蚀刻出两个埋入式的闸极多晶硅接触孔，随后在闸极氧化层表面沉积形成顶部闸极多晶硅层，并填充在闸极多晶硅接触孔中，与凹槽内的闸极多晶硅部接触，再利用一层光刻板将顶部闸极多晶硅层两侧的闸极多晶硅蚀刻去除，露出部分闸极氧化层；
S7：在闸极氧化层和顶部闸极多晶硅层表面沉积介电层，并采用光刻技术在介电层两侧进行干蚀刻，进一步去除闸极氧化层两侧多余的闸极氧化层，露出P+掺杂区和部分N+掺杂区上表面，形成金属接触孔，最后将金属沉积在介电层表面，并填充在金属接触孔中形成金属层，使得金属层位于P+掺杂区和部分N+掺杂区的上表面，即得到MOSFET器件。
有益效果：本发明公开了一种MOSFET电流路径优化结构及其制备方法，具有如下优点：
1）本发明提出一种新的MOSFET器件结构，将闸极多晶硅埋在通道间，此结构的通道电流将分成同样是闸极多晶硅下方延着XZ面的电流I1，以及与闸极多晶硅侧面延着XY面(极性面1120)的电流I2，此极性面在通道浓度为1017~1018 cm-3之间时，可将载子迁移率提高到90 cm2/Vs，从而大大降低了通道阻值。
2）本发明中由于图2的闸极氧化层厚度B远大于图1的闸极氧化层厚度A，且闸极多晶硅部几乎被P-掺杂区所包覆，因此降低了闸汲极间的电容CGD与闸汲极间的电荷QGD, 加快了切换速度，降低了功率损耗。
附图说明
图1为现有的MOSFET器件结构示意图。
图2为实施例1的MOSFET器件结构示意图（省略基底）。
图3为实施例1的MOSFET器件结构的部分俯视图（省略介电层和金属层）。
图4为本发明中步骤S1完成后的示意图。
图5为本发明中步骤S2完成后的示意图。
图6为本发明中步骤S3完成后的示意图。
图7为本发明中步骤S4完成后的示意图。
图8为本发明中步骤S5完成后的示意图。
图9为本发明中步骤S6完成后的示意图。
图中：外延层1、P-掺杂区2、N+掺杂区3、P+掺杂区4、闸极氧化层5、顶部闸极多晶硅层6、闸极多晶硅部6-1、闸极多晶硅I6-2、介电层7、金属层8、凹槽9。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
实施例1
一种MOSFET电流路径优化结构，包括：
基底和位于基底表面的外延层1，且外延层1为N型外延层；
所述外延层1的本体内靠近上表面处两侧均设有掺杂区，每个所述掺杂区包括N+掺杂区3、P+掺杂区4和P-掺杂区2，所述N+掺杂区3和P+掺杂区4均位于所述P-掺杂区2内，所述P+掺杂区4包覆所述N+掺杂区3一侧边以及所述N+掺杂区3平行于外延层1上表面的部分区域，所述N+掺杂区3和P+掺杂区4的上表面与外延层上表面齐平, 所述P-掺杂区2的布植材料为铝，且铝的整体浓度为1015cm-2等级；所述N+掺杂区3的布植材料为磷，且磷的整体浓度为1015cm-2等级，所述P+掺杂区4的布植材料为铝，且铝的整体浓度为1016cm-2。等级。
如图3所示，所述外延层1的上表面有两列对称设置的凹槽组，且每列凹槽组包括若干等间距排列的凹槽9，所述外延层1的上表面和凹槽9表面均生长有闸极氧化层5，所述闸极氧化层5覆盖N+掺杂区3部分上表面, 位于所述凹槽9内的闸极氧化层5同时与N+掺杂区3、P-掺杂区2和外延层1接触；
所述闸极氧化层5上表面沉积有顶部闸极多晶硅层6，且位于凹槽内的闸极氧化层5内沉积有闸极多晶硅部6-1，所述闸极多晶硅部6-1向上连接顶部闸极多晶硅层6；
所述闸极氧化层5和顶部闸极氧化层6的上表面生长有介电层7，且所述介电层7包覆顶部闸极多晶硅层6侧边；
所述介电层7、P+掺杂区4和N+掺杂区3的上表面生长有金属层8，金属层8为铝金属层。
本发明中，如图2所示的位于所述凹槽9内的闸极氧化层5的厚度A取值为0.03-0.08μm ，位于所述外延层1上表面的闸极氧化层5的厚度B取值为0.08-0.14μm，且厚度B大于厚度A，所述顶部闸极多晶硅层6的厚度为0.4-1.0μm ；金属层厚度为3-5μm。
本发明中MOSFET电流路径优化结构的具体制备步骤如下：
S1：在所述外延层1上表面沉积氧化物，之后利用光刻板完成曝光制程，接着在离子布植后将氧化物去除，同样的步骤重复三次依次形成P-掺杂区2, N+掺杂区3和P+掺杂区4，如图4所示。
S2：使用一层光刻板在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层1上蚀刻出通道内的凹槽9，随后在1200-1300℃高温氧气环境下在外延层1和凹槽9表面生长出闸极氧化层5，且所述闸极氧化层5覆盖N+掺杂区3和P+掺杂区4，如图5所示；
S3：在闸极氧化层5表面沉积形成闸极多晶硅I6-2,且闸极多晶硅I6-2填充在凹槽9内的闸极氧化层5表面，如图6所示；
S4：采用化学机械研磨方式依次清除表面的闸极多晶硅I6-2,形成闸极多晶硅部6-1，且闸极多晶硅部6-1表面与闸极氧化层5表面齐平,如图7所示；
S5：在1200-1300℃高温氧气环境下，将闸极多晶硅部6-1表面氧化，使得闸极氧化层5包覆闸极多晶硅部6-1，再采用沉积氧化物方式将闸极氧化层5表面垫高，使其厚度大于凹槽内的闸极氧化层5，如图8所示；
S6：采用一层光刻板在闸极氧化层5上蚀刻出两个埋入式的闸极多晶硅接触孔，随后在闸极氧化层5表面沉积形成顶部闸极多晶硅层6，并填充在闸极多晶硅接触孔中，与凹槽9内的闸极多晶硅部6-1接触，再利用一层光刻板将顶部闸极多晶硅层6两侧的闸极多晶硅蚀刻去除，露出部分闸极氧化层5，如图9所示；
S7：在闸极氧化层5和顶部闸极多晶硅层6表面沉积介电层7，并采用光刻技术在介电层7两侧进行干蚀刻，进一步去除闸极氧化层5两侧多余的闸极氧化层，露出P+掺杂区4和部分N+掺杂区2上表面，形成金属接触孔，最后将金属（铝）沉积在介电层7表面，并填充在金属接触孔中，形成金属层8，使得金属层位于P+掺杂区和部分N+掺杂区的上表面，即得到MOSFET器件，如图2所示。
如图2所示，本发明的MOSFET器件的通道电流将分成闸极多晶硅部6-1下方延着XZ面的电流I1以及闸极多晶硅部6-1侧面延着XY面的电流I2，此极性面在通道浓度为1017~1018cm-3之间时，可将载子迁移率提高到90 cm2/Vs，将通道阻值大大的降低。图3为图2中MOSFET器件的俯视图(不含介电层和金属层)，从图3可清楚的得知，闸极多晶硅是采间隔方式埋入通道内，如此可让电流I2有空间延XY面流过。
本具体实施例仅仅是对本发明的解释，其并不是对本发明的限制，本领域技术人员在阅读完本说明书后可以根据需要对本实施例做出没有创造性贡献的修改，但只要在本发明的权利要求范围内都受到专利法的保护。
Claims (10)
1.一种MOSFET电流路径优化结构，其特征在于，包括：
基底和位于基底表面的外延层；
所述外延层的本体内靠近上表面处两侧均设有掺杂区，每个所述掺杂区包括N+掺杂区、P+掺杂区和P-掺杂区，所述N+掺杂区和P+掺杂区均位于所述P-掺杂区内，所述P+掺杂区包覆所述N+掺杂区一侧边以及所述N+掺杂区平行于外延层上表面的部分区域，所述N+掺杂区和P+掺杂区的上表面与外延层上表面齐平；
所述外延层的上表面有两列对称设置的凹槽组, 且每列凹槽组包括若干等间距排列的凹槽，所述外延层的上表面和凹槽表面均生长有闸极氧化层，所述闸极氧化层覆盖所述N+掺杂区部分上表面，且位于所述凹槽内的闸极氧化层同时与N+掺杂区、P-掺杂区和外延层接触；
所述闸极氧化层上表面沉积有顶部闸极多晶硅层，且位于凹槽内的闸极氧化层内沉积有闸极多晶硅部，所述闸极多晶硅部向上连接顶部闸极多晶硅层；
所述闸极氧化层和顶部闸极多晶硅层的上表面沉积有介电层，且所述介电层包覆顶部闸极多晶硅层侧边；
所述介电层、P+掺杂区和N+掺杂区的上表面沉积有金属层。
2.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述基底和外延层均为碳化硅材料，且所述外延层为N型外延层。
3.根据权利要求1或2所述的MOSFET电流路径优化结构，其特征在于，所述凹槽的深度小于0.4μm。
4.根据权利要求1或2所述的MOSFET电流路径优化结构，其特征在于，位于所述凹槽内的闸极氧化层的厚度A取值为0.03 -0.08μm，位于所述外延层上表面的闸极氧化层的厚度B取值为0.08 -0.14μm，且厚度B大于厚度A。
5.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述P-掺杂区的布植材料为铝，且铝的整体浓度为1015cm-2等级。
6.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述N+掺杂区的布植材料为磷，且磷的整体浓度为1015cm-2等级。
7.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述P+掺杂区的布植材料为铝，且铝的整体浓度为1016cm-2等级。
8.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述顶部闸极多晶硅层的厚度为0.4-1.0μm。
9.根据权利要求1所述的MOSFET电流路径优化结构，其特征在于，所述金属层为铝金属层，且金属层厚度为3-5μm 。
10.一种权利要求1-9任一所述的MOSFET电流路径优化结构的制备方法，其特征在于，具体制备步骤如下：
S1：在所述外延层上表面沉积氧化物，之后利用光刻板完成曝光制程，接着在离子布植后将氧化物去除，同样的步骤重复三次依次形成P-掺杂区, N+掺杂区和P+掺杂区；
S2：使用一层光刻板在900-1000℃高温氯气环境下以湿蚀刻制程的方式在外延层上蚀刻出通道内的凹槽，随后在1200-1300℃高温氧气环境下在外延层、N+掺杂区、P+掺杂区和凹槽表面生长出闸极氧化层；
S3：在闸极氧化层表面沉积形成闸极多晶硅I,且闸极多晶硅I填充在凹槽内的闸极氧化层表面；
S4：采用化学机械研磨方式清除表面的闸极多晶硅I，形成闸极多晶硅部，且闸极多晶硅部表面与闸极氧化层表面齐平；
S5：在1200-1300℃高温氧气环境下，将闸极多晶硅部表面氧化，使得闸极氧化层包覆闸极多晶硅部，再采用沉积氧化物方式将闸极氧化层表面垫高，使其厚度大于凹槽内的闸极氧化层；
S6：采用一层光刻板在闸极氧化层上蚀刻出两个埋入式的闸极多晶硅接触孔，随后在闸极氧化层表面沉积形成顶部闸极多晶硅层，并填充在闸极多晶硅接触孔中，与凹槽内的闸极多晶硅部接触，再利用一层光刻板将顶部闸极多晶硅层两侧的闸极多晶硅蚀刻去除，露出部分闸极氧化层；
S7：在闸极氧化层和顶部闸极多晶硅层表面沉积介电层，并采用光刻技术在介电层两侧进行干蚀刻，进一步去除闸极氧化层两侧多余的闸极氧化层，露出P+掺杂区和部分N+掺杂区上表面，形成金属接触孔，最后将金属沉积在介电层表面，并填充在金属接触孔中形成金属层，使得金属层位于P+掺杂区和部分N+掺杂区的上表面，即得到MOSFET器件。
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