WO2012049792A1 - Procédé de production d'un dispositif semiconducteur en carbure de silicium - Google Patents

Procédé de production d'un dispositif semiconducteur en carbure de silicium Download PDF

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Publication number
WO2012049792A1
WO2012049792A1 PCT/JP2011/003582 JP2011003582W WO2012049792A1 WO 2012049792 A1 WO2012049792 A1 WO 2012049792A1 JP 2011003582 W JP2011003582 W JP 2011003582W WO 2012049792 A1 WO2012049792 A1 WO 2012049792A1
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silicon carbide
main surface
carbide substrate
warpage
forming
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PCT/JP2011/003582
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English (en)
Japanese (ja)
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洋介 中西
隆夫 沢田
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Definitions

  • the present invention relates to a method for manufacturing a semiconductor element made of silicon carbide.
  • a silicon carbide semiconductor element can have a resistance value during semiconductor operation lower than that of a silicon (Si) semiconductor element due to the excellent material properties of silicon carbide (SiC).
  • SiC silicon carbide
  • each region is first formed on the surface of a SiC substrate.
  • a contact electrode film is formed so as to cover the entire surface on the back side.
  • a high-temperature heat treatment is performed to form a silicide film at the interface between the contact electrode film and the SiC substrate.
  • the high-temperature heat treatment temperature for obtaining ohmic contact is much higher than that of Si.
  • internal stress is applied due to the difference in thermal expansion coefficient between the contact electrode film and the SiC substrate, and between the silicide film and the SiC substrate, and a large warp occurs in the wafer after the heat treatment.
  • Patent Documents 1 and 2 are known as documents disclosing a method for reducing the warpage.
  • the substrate has a region for forming a desired semiconductor element on the substrate surface.
  • a contact electrode film is provided on the back side of the substrate so as to cover the entire surface.
  • the contact electrode film is patterned in such a manner that it is subdivided over substantially the entire back surface of the substrate. By this patterning, the film stress generated by the high-temperature heat treatment is relieved, so that the warpage of the wafer is reduced.
  • the film stress generated by high-temperature heat treatment is relaxed by patterning the back contact electrode film.
  • substrate can be reduced, when adjusting the curvature after high temperature heat processing, it is necessary to change patterning. Even if the warpage generated after the high-temperature heat treatment can be alleviated, the film stress generated in the subsequent process, particularly the film stress generated during the formation of the Schottky electrode film on the surface, again causes a large warp in the wafer.
  • the warpage amount of the wafer is controlled by removing at least a part of the work-affected layer formed on the ground surface, and the subsequent back surface and front surface
  • An object of the present invention is to reduce the amount of wafer warpage generated in the electrode forming step to a value that does not affect the manufacturing process.
  • a method for manufacturing a silicon carbide semiconductor element includes a step of forming an activation region on a first main surface of a silicon carbide substrate, and a second method of facing the silicon carbide substrate on which the activation region is formed to the first main surface.
  • FIG. 6 is a cross-sectional view of a SiC-SBD manufactured in Embodiments 1 to 5 of the present invention.
  • FIG. 6 is a first flowchart of a SiC-SBD manufacturing process used in the first to fifth embodiments of the present invention. It is a cross-sectional TEM image of the grinding surface of a SiC substrate. This is a calculated value of the amount of warpage of the wafer with respect to the thickness of the work-affected layer on which a compressive stress of 1.0 GPa works (wafer thickness: 190 ⁇ m).
  • FIG. 5 is a diagram for explaining first processes (a) to (e) for adjusting a warp amount.
  • FIG. 6 is a diagram for explaining cases 1 to 3 for first processes (a) to (f). 6 is a second flowchart of the SiC-SBD manufacturing process used in the first to fifth embodiments of the present invention. FIG. 6 is a diagram for explaining cases 4 to 6 for second processes (a) to (f).
  • FIG. 1 shows a cross-sectional view of SiC-SBD.
  • the SiC substrate 10 is an n-type low-resistance substrate having a 4H polytype in which the plane orientation of the first main surface is 4 ° or 8 ° off from the ⁇ 0001> silicon surface.
  • An n-type SiC epitaxial layer (drift layer) 20 is formed on the first main surface.
  • the concentration and film thickness of the epitaxial layer 20 vary depending on the assumed breakdown voltage, but are 5 ⁇ 10 15 cm ⁇ 3 and 10 ⁇ m, for example.
  • the SiC substrate 10 and the epitaxial layer 20 are collectively referred to as a SiC substrate 11.
  • a p-type ion implantation region (activation region) 30 containing aluminum (Al) as a p-type impurity is formed in a portion separated by a certain width.
  • the ion implantation region 30 has a ring shape with a certain width.
  • the implantation amount of Al ions is, for example, 5 ⁇ 10 17 cm ⁇ 3 .
  • another ring-shaped JTE (Junction Termination Extension) region 31 may be provided outside the ion implantation region 30 in some cases. Edge termination such as JTE is applied to the periphery of the device in order to reduce the electric field strength on the surface.
  • the Schottky region 40 is formed on the surface side of the epitaxial layer 20 surrounded by the ion implantation region 30.
  • a Schottky electrode 50 is formed on the surface of the Schottky region 40 so as to protrude from the periphery of the ion implantation region 30. Examples of materials used for the Schottky electrode 50 include Ti, W, Mo, and Cr.
  • a wiring electrode 60 is formed on the upper surface of the Schottky electrode 50. Examples of the material used for the wiring electrode 60 include Al.
  • Silicide layer 71 is formed on the second main surface opposite to the first main surface of SiC substrate 10, that is, on the back surface side.
  • the silicide layer (back electrode) 71 is a reaction between the contact electrode film and SiC, and is in ohmic contact with the SiC substrate 10.
  • the material used for the contact electrode include Ni, Ti, Co, Mo, and W.
  • SBD was mentioned as an example of a SiC semiconductor device structure, this may be a field effect transistor (MOSFET: Metal-Oxide-Semiconductor-Field-Effect-Transistor).
  • the reduction of the absolute value of the substrate resistance becomes an issue.
  • One method for reducing the absolute value of the substrate resistance value is to thin the substrate by grinding the substrate during device fabrication.
  • substrate thinning is introduced into the SiC semiconductor device manufacturing process, the greater the thickness of the work-affected layer formed by grinding, the greater the amount of warpage after forming a contact electrode film and performing high-temperature heat treatment. There was found. Details are described below.
  • FIG. 2 shows a flow chart of a manufacturing method of SiC-SBD that can realize a low-resistance semiconductor element by thinning the substrate.
  • Ion implantation region 30 is formed in silicon carbide substrate 11 through ion implantation and activation annealing.
  • the silicon carbide substrate is thinned to form a back electrode. Warpage occurs when the substrate is thinned in the back electrode forming process.
  • the warpage amount of the substrate is adjusted by removing (surface treatment) at least a part of the work-affected layer formed on the ground surface after thinning.
  • a silicide layer 71 is formed on the substrate with reduced warpage. For example, assume that a SiC semiconductor element is manufactured using a 3 inch SiC wafer having a thickness of 400 ⁇ m.
  • the thickness of the entire wafer surface is reduced to 200 ⁇ m or less before forming the contact electrode film on the back side.
  • the wafer is subjected to high-temperature heat treatment at 1000 ° C. or higher.
  • the contact electrode film is silicided at the interface with the SiC substrate, and an ohmic contact is formed between them.
  • surface electrodes such as the Schottky electrode 50 and the wiring electrode 60 are formed on the first main surface of the silicon carbide substrate. In this way, a SiC semiconductor element in which the SiC substrate is thinned is manufactured.
  • the properties of the work-affected layer will be described, and the effects of removal processing will be described in the first to fifth embodiments.
  • FIG. 3 is a cross-sectional TEM (Transmission / Electron / Microscope) image of the ground surface.
  • An enlarged photograph of the lower right square is an enlarged display of the upper left square region.
  • a film that is visible in the range of 350 nm in depth from the surface is the work-affected layer 80.
  • the formed work-affected layer generates compressive stress, and the SiC wafer warps (swells) the ground surface (second main surface) in a convex manner.
  • the upper layer of the work-affected layer 80 is an organic protective film that is attached to protect the surface during TEM observation.
  • the black streaks seen in the film is Au, which is a mark for observation. There is no such film after grinding.
  • FIG. 4 shows the result of calculating the amount of warpage of a 3-inch SiC wafer (thickness: 190 ⁇ m) with respect to the thickness of the work-affected layer that generates a compressive stress of 1.0 GPa on the entire surface of the wafer. From this graph, it can be seen that the greater the thickness of the work-affected layer, the greater the amount of warpage of the wafer.
  • the results of evaluating the amount of warpage of the wafer when a 3-inch SiC wafer is thinned and a contact electrode film is formed and high-temperature heat treatment is performed will be described.
  • FIG. 5 shows the amount of warpage before and after grinding when the 3-inch SiC wafer is ground to 190 ⁇ m in the backside electrode formation process of the SiC-SBD manufacturing process. This is a plot of the amount of warping after forming a Ni film (thickness of 200 nm or less) and performing high-temperature heat treatment at 1000 ° C. (after ohmic contact formation). The amount of warpage after grinding is indicated by ⁇ , and the amount of warpage after forming ohmic contact is indicated by ⁇ .
  • the amount of change in warpage before and after grinding shown on the horizontal axis corresponds to the thickness of the work-affected layer.
  • the thickness of the work-affected layer formed after grinding on each wafer is not measured.
  • the amount of change in warpage before and after grinding has a correlation with the film thickness of the work-affected layer, and the greater the amount of change, the thicker the film thickness of the work-affected layer.
  • the variation in the warping amount ( ⁇ ) observed after grinding is due to the difference in the film thickness of the work-affected layer. The thicker the film thickness, the larger the warping amount.
  • the amount of warpage varies greatly depending on the thickness of the work-affected layer. It can be seen that the greater the thickness of the work-affected layer, the greater the amount of warpage.
  • the thermal expansion coefficient of the silicide film depends on the film thickness of the work-affected layer. The thicker the film thickness, the larger the thermal stress, that is, the amount of change in warpage in the high temperature heat treatment process.
  • the warpage amount ( ⁇ ) after forming a silicide layer by performing high-temperature heat treatment and forming an ohmic contact between SiC and Ni film depends on the film thickness of the work-affected layer, and the work-affected layer The thicker the is, the greater the amount of change in warpage.
  • a solid line represents a function optimally fitted to the experimental value of the warpage after grinding and after the formation of the ohmic contact. It can be seen that the fitted curves (thick lines and thin lines) reproduce the experimental results well.
  • the y-intercept in which the film thickness of the work-affected layer was zero was found to be ⁇ 47 ⁇ m. This result was confirmed to be substantially the same as the amount of warpage observed when CMP (Chemical-Mechanical-Polishing) was performed and a contact electrode was formed on a surface having almost no work-affected layer.
  • FIG. 6 shows the result of calculating the amount of warpage for a 3-inch SiC wafer having a thickness of 150 ⁇ m. Similar to FIG. 4, the calculation result shows the relationship between the thickness of the work-affected layer that generates a compressive stress of 1.0 GPa on the entire surface of the wafer and the amount of warpage. This graph also shows that the amount of warpage of the wafer increases as the thickness of the work-affected layer increases.
  • this 3-inch SiC wafer having a thickness of 150 ⁇ m was thinned, a contact electrode film was formed, high-temperature heat treatment was performed, and the amount of warpage of the wafer was evaluated.
  • FIG. 7 shows the result of evaluating the amount of warpage of a 3-inch SiC wafer when it is ground to a thickness of 150 ⁇ m in the back electrode forming step of the SiC-SBD manufacturing process.
  • a Ni film thinness of 200 nm or less
  • a high temperature heat treatment at 1000 ° C. was performed.
  • the horizontal axis represents the amount of change in warpage before and after grinding. This corresponds to the fact that the greater the amount of change in warpage before and after grinding, the greater the thickness of the work-affected layer.
  • the amount of warpage after grinding is indicated by ⁇
  • the amount of warpage after forming ohmic contact is indicated by ⁇ .
  • the amount of warpage observed when CMP was performed and a silicide layer was formed on the surface with almost no work-affected layer was the amount of warpage before and after grinding (horizontal axis) after ohmic contact formation with 0 ⁇ m. The amount of warpage.
  • the amount of warpage generated after high-temperature heat treatment increases due to the work-affected layer formed by grinding before film formation of the contact electrode film.
  • the generated large warpage causes a wafer chucking error and a crack of the wafer in the subsequent process, which hinders smooth substrate transfer and thus automation of the semiconductor manufacturing system.
  • a part of the work-affected layer is removed so as to leave a part of the work-affected layer formed on the ground surface when the substrate is thinned.
  • a surface treatment surface removal process
  • the amount of adjustment depends on the film stress generated in the subsequent process. The thickness of the work-affected layer formed from the amount of warpage after grinding is calculated, and the etching film thickness of the work-affected layer is estimated from that value.
  • the warpage is minimized by reducing the work-affected layer by leaving only a film stress that offsets the amount of warpage that occurs during subsequent metal film (contact electrode film, Schottky electrode film, wiring electrode film) deposition.
  • FIGS. 8A to 8E are diagrams for explaining the main points of the manufacturing process of the silicon carbide semiconductor element according to the present application.
  • FIG. 8A shows a process for forming an activation region. Ion implantation and activation annealing are performed on the silicon carbide substrate 10 on which the epitaxial layer 20 is formed to form an ion implantation region (activation region) 30.
  • FIG. 8B shows a process for grinding the silicon carbide substrate. When the substrate is ground from the second main surface side in order to reduce the thickness of the substrate, a work-affected layer is formed on the second main surface.
  • FIG. 8C shows a process for thinning the work-affected layer.
  • Surface treatment is performed to remove the work-affected layer, and the warpage of the substrate is adjusted. Since the warpage generated in the subsequent processes is taken into consideration, the base is kept in a state of warping with the second main surface convex.
  • FIG. 8D shows a process for forming a Ni film. With the work-affected layer remaining, a contact electrode film 75 such as a Ni film is formed on the second main surface.
  • FIG. 8E shows a process for performing high-temperature heat treatment.
  • a silicide film 71 is formed by performing high-temperature heat treatment at 1000 ° C. so that the contact electrode film 75 and SiC react. In this figure, the curvature of the substrate is expressed as zero. However, after the silicide film 71 is formed, surface electrodes such as Schottky electrodes and wiring electrodes are formed on the first main surface. It is also conceivable that the first main surface is convex and warped.
  • the amount of warpage of the wafer after adjusting the amount of warpage depends on the size of the wafer.
  • the amount of warpage is desirably 10 ⁇ m or more and 100 ⁇ m or less with a convex surface on a 3 inch SiC wafer (thickness 200 ⁇ m), and 10 ⁇ m or more and 250 ⁇ m or less with a convex surface on a 4 inch SiC wafer (thickness 200 ⁇ m).
  • the amount of warpage of the wafer after adjusting the amount of warpage is the same as that of SiC-SBD.
  • the warpage amount shown here is the case where the thickness of the substrate is 200 ⁇ m, and if the thickness is different, the range of the warpage amount also changes according to the thickness.
  • the range of warpage if the thickness of the wafer after thin plate is t ⁇ m, 3 inches is 10 ⁇ m to 100 ⁇ (200 / t) 2 ⁇ m or less, and 4 inches is 10 ⁇ m to 250 ⁇ (200 / t) 2 ⁇ m or less. It is.
  • the method of warping the substrate differs depending on the initial state of the substrate, the type of film formed on the surface, and the like.
  • the typical warping methods are classified and shown in FIGS. Based on this figure, assuming that the film stress of the Schottky electrode 50 is a compressive stress (force acting in the direction in which the first main surface is convex), it is considered to minimize the warp after the Schottky electrode is formed.
  • FIG. 9 deals with a case where the substrate is warped convexly on the second main surface (back surface) before grinding.
  • Point A represents the substrate after grinding.
  • Point B represents the substrate after the surface treatment.
  • Point C represents the substrate after the ohmic contact is formed.
  • the substrate subjected to the surface treatment moves from point A to point B. Even if the surface treatment is performed, the substrate warps the second main surface in a convex manner.
  • the substrate moves from point B to point C.
  • the work-affected layer is thinned to a thickness that minimizes the warpage after the Schottky electrode is formed, and the second main surface remains convex.
  • the second main surface is made convex so that the warpage is minimized after the formation of the Schottky electrode (see case 3 in FIG. 11).
  • FIG. 10 deals with a case where the substrate warps the first main surface (surface) convexly before grinding.
  • the substrate moves from point A to point B and further from point B to point C with processing.
  • the substrate subjected to the surface treatment after grinding has the first main surface warped convexly. Even when the substrate warps the first main surface convexly before grinding, the amount of warpage during the formation of ohmic contact is minimized by thinning the work-affected layer after grinding. Thereby, the curvature at the time of forming the Schottky electrode can be significantly reduced as compared with the case where a part of the work-affected layer is not removed.
  • the present invention can also be applied to the case where the warping after thinning and thinning the work-affected layer warps the first main surface convexly (see case 1 in FIG. 11).
  • the substrate can be obtained by slicing a cylindrical rod. Since the rods are not necessarily homogeneous, the substrate after slicing is different from one to the other.
  • FIG. 11 shows a process for adjusting the warpage of the substrate using the substrates in different initial states.
  • Case 1 represents the case where the substrate obtained from the rod 90 is warped in a convex manner on the first main surface in the initial state.
  • Case 2 represents the case where the substrate obtained from the rod 90 is flat in the initial state.
  • Case 3 represents a case where the substrate obtained from the rod 90 is warped in a convex manner on the second main surface in the initial state.
  • the contents shown in the processes (a) to (e) are the same as the processes (a) to (e) shown in FIG.
  • Process (f) represents forming a surface electrode on the surface of the substrate after the ohmic contact is formed.
  • FIG. 12 shows a second flowchart of the SiC-SBD manufacturing method according to the present invention.
  • surface electrodes such as the Schottky electrode 50 and the wiring electrode 60 are formed on the silicon carbide substrate.
  • thinning is performed and surface treatment is performed.
  • a Ni film is formed on the back surface, and laser annealing is performed on the Ni film, thereby forming a silicide layer.
  • large warping occurs when the substrate is thinned.
  • the warpage amount of the substrate is adjusted by removing (surface treatment) at least a part of the work-affected layer formed on the ground surface after thinning.
  • the thinning step is the latter half of the flow, it is desirable to minimize the amount of warpage after the back electrode is formed.
  • the work-affected layer is thinned (removed) so that the amount of warpage is minimized, and after forming the contact electrode film, a silicide layer is formed using laser annealing without temperature rise of the surface electrode, An ohmic contact is formed.
  • FIG. 13 shows a process of adjusting the warpage of the substrate using a substrate having a different initial state in the second SiC-SBD manufacturing method.
  • Case 4 represents a case where the substrate obtained from the rod 90 warps the first main surface convexly in the initial state.
  • Case 5 represents the case where the substrate obtained from the rod 90 is flat in the initial state.
  • Case 6 represents a case where the substrate obtained from the rod 90 warps the second main surface convexly in the initial state.
  • Process (a) shows a process for forming an activated region. Ion implantation and activation annealing are performed on silicon carbide substrate 10 on which epitaxial layer 20 is formed to form an ion implantation region (activation region).
  • Process (b) represents a process of forming the surface electrode 50 on the first main surface of the substrate on which the epitaxial layer is formed.
  • Process (c) shows a process for grinding a silicon carbide substrate. When the substrate is ground from the second main surface side in order to reduce the thickness of the substrate, a work-affected layer is formed on the second main surface.
  • Process (d) shows a process for thinning the work-affected layer. Surface treatment is performed to remove the work-affected layer, and the warpage of the substrate is adjusted in consideration of the warpage generated in the subsequent processes.
  • Process (e) shows a process for forming a Ni film. With the work-affected layer remaining, a contact electrode film 75 such as a Ni film is formed on the second main surface.
  • Process (f) shows a process for performing laser annealing. The silicide film 71 is formed by irradiating a laser so that the contact electrode film 75 and SiC react.
  • Embodiment 1 FIG. In Embodiments 1 to 5, a method for removing a work-affected layer performed in the back electrode forming step will be described.
  • the warpage amount before film formation of the contact electrode film is adjusted, that is, the warpage amount is changed on the thin solid line in FIG.
  • SiC-SBD In the production of SiC-SBD, consider a case where the SiC substrate 11 is warped 100 ⁇ m in convex on the second main surface after grinding.
  • the film stress in Schottky electrode formation which is a process after thinning, is compressive stress (the direction in which the first main surface is convex)
  • the amount of warpage to be performed before film formation is adjusted to almost all of the work-affected layer. It removes and the amount of curvature is adjusted so that the 2nd principal surface of SiC substrate 11 may become convex, for example to 15 micrometers.
  • RIE Reactive Ion Etching
  • the etching rate is preferably in the range of 1 nm / min to 1 ⁇ m / min.
  • a contact electrode film is formed on the entire back surface of the SiC substrate.
  • the amount of warpage is in the region indicated by the vertical arrow in FIG.
  • an ohmic contact is formed by high-temperature heat treatment at 1000 ° C. or higher.
  • the subsequent warpage amount is a value on the thick solid line in FIG. 5, and the first main surface is 46 ⁇ m convex.
  • the amount of warpage after the ohmic contact is formed is about 120 ⁇ m. By removing the work-affected layer, the amount of warpage was greatly reduced. This result is a value sufficient to smoothly carry the wafer automatically, and the problem can be sufficiently solved.
  • the contact resistance of the back electrode can be reduced.
  • RIE since the work-affected layer is removed while maintaining the surface state before etching, the surface roughness of the substrate surface before and after etching is roughly maintained. Further, the surface roughness is maintained before and after the ohmic contact formation. Therefore, by setting the maximum surface roughness in the amount of warp that can be transferred to the RIE equipment, the surface roughness after the ohmic contact can be increased, so the contact resistance can be reduced by increasing the surface area of the back electrode. It becomes.
  • the SiC substrate When the SiC substrate is thinned to 150 ⁇ m and the SiC substrate is warped by 200 ⁇ m convexly after grinding, most of the work-affected layer is removed, and the amount of warpage protrudes from the second principal surface of the SiC substrate. To 50 ⁇ m. Thereafter, ohmic contacts were formed by high-temperature heat treatment at 1000 ° C. or higher. The amount of warpage thereafter was 88 ⁇ m with the first main surface convex. When the work-affected layer was not removed, the amount of warpage after forming the ohmic contact was about 200 ⁇ m.
  • FIG. Embodiment 2 provides a method for removing a work-affected layer formed on a ground surface using an ionized inert gas.
  • the gas species Ar is preferable, but He, Ne, or the like may be used.
  • a sputter deposition apparatus is used, and removal of the work-affected layer by Ar ions and Ni film formation are performed in the same apparatus. Prior to film formation, a part of the work-affected layer is removed by sputtering the wafer with an inert gas, and then Ni film formation is performed.
  • This sputtering apparatus is improved for a wafer with a warped conveyance system, and is equipped with a non-contact wafer chuck mechanism and the like.
  • the etching rate is desirably about 1 nm / min to 1 ⁇ m / min.
  • the etching rate is preferably in the range of 1 nm / min to 100 nm / min.
  • the removal of the work-affected layer by ion irradiation at a low energy of 500 eV or less is particularly effective as the work-affected layer thickness that is desired to remain is reduced.
  • at least a part of the work-affected layer is removed by inert gas ion sputtering to adjust the warping amount of the wafer after grinding.
  • Embodiment 3 the ground surface is first subjected to an oxidation treatment, and then silicon oxide formed on the surface is completely removed.
  • the oxidation method wet oxidation is desirable.
  • the wet oxidation is performed at about 1400 ° C., and the film thickness to be oxidized is adjusted by the oxidation time.
  • the oxidation rate is preferably about 1 nm / min to 1 ⁇ m / min.
  • a method for removing silicon oxide wet etching with hydrofluoric acid or dry etching using a gas containing C 3 H 8 or the like is desirable. By this method, at least a part of the work-affected layer formed on the ground surface is removed, and the warpage amount of the wafer after grinding is adjusted.
  • Embodiment 4 a part of the work-affected layer formed on the ground surface is removed by dry polishing. Dry polishing is performed by rotating both in a slurry-free state while the polishing wheel is pressed against the wafer at a constant pressure. Since dry polishing can be performed without forming a work-affected layer even with SiC, which is a difficult-to-process material, the amount of warpage can be reduced by removing the work-affected layer.
  • the wafer is fixed to the support substrate using a protective tape or wax.
  • the support substrate is disposed on the processing stage.
  • the processing rate is desirably about 1 nm / min to 1 ⁇ m / min.
  • Embodiment 5 a part of the work-affected layer formed on the ground surface is removed by CMP to reduce the amount of warpage.
  • CMP the wafer is pressed against the surface plate so that both are rotated, and the slurry is dropped on the surface plate. Since the wafer is polished by the effect of polishing by the abrasive grains contained in the slurry and the chemical reaction acting on the wafer during polishing, the processing can be performed without forming a work-affected layer.
  • the wafer is fixed to the support substrate using a protective tape or wax.
  • the support substrate is arranged on a surface plate (processing stage).
  • the processing rate is desirably about 1 nm / min to 1 ⁇ m / min. After the processing, cleaning is performed by an appropriate method, and the next film formation process is performed.
  • SiC-SBD has been described as an example of the present embodiment, the same applies to a MOSFET, and a method of adjusting the amount of warpage after grinding so that the warpage during the formation of a wiring electrode is minimized after the back electrode formation step.
  • a 3-inch SiC wafer has been described as an example of the present embodiment, the present invention can also be applied to an increase in aperture.
  • the method for adjusting the amount of warpage from the back grinding process to the ohmic contact forming process has been described by taking the case of forming a Ni film as an example, but it can be applied to a metal film that silicides with SiC, for example, Ti, Co, Mo, W, etc.
  • the present invention is also applicable to this case.

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Abstract

La présente invention vise à contrôler la déformation d'une tranche par élimination d'au moins une partie d'une couche affectée qui est formée sur une surface de base et à réduire la déformation de la tranche qui se produit dans une étape ultérieure de formation d'électrode sur la surface postérieure et la surface antérieure, lorsqu'une étape d'amincissement du substrat est ajoutée à l'étape de production d'un dispositif semiconducteur en carbure de silicium. La déformation est réduite dans ce cas au point que celle-ci n'affecte plus le processus de production. L'invention concerne un procédé de production d'un dispositif semiconducteur en carbure de silicium, comprenant les étapes suivantes : former une région activée sur une première surface principale d'un substrat de carbure de silicium ; rectifier, à partir d'une seconde surface principale, opposée à la première surface principale, le substrat de carbure de silicium sur lequel a été formée la région activée ; éliminer, à partir de la seconde surface principale, le substrat de carbure de silicium rectifié qui a été déformé avec formation d'une saillie par la seconde surface principale, ce qui réduit la déformation ; former une électrode de surface postérieure sur la seconde surface principale du substrat de carbure de silicium où la déformation a été réduite et où la seconde surface principale fait saillie ; et former une électrode de surface antérieure sur la première surface principale du substrat de carbure de silicium où a été formée l'électrode de surface postérieure.
PCT/JP2011/003582 2010-10-15 2011-06-23 Procédé de production d'un dispositif semiconducteur en carbure de silicium WO2012049792A1 (fr)

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JP2014139972A (ja) * 2013-01-21 2014-07-31 Sumitomo Electric Ind Ltd 炭化珪素半導体装置の製造方法
JP2014216474A (ja) * 2013-04-25 2014-11-17 コバレントマテリアル株式会社 窒化物半導体基板
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WO2015020219A1 (fr) * 2013-08-08 2015-02-12 富士電機株式会社 Procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
JP2016009712A (ja) * 2014-06-23 2016-01-18 住友電気工業株式会社 炭化珪素半導体装置
JP2016046310A (ja) * 2014-08-20 2016-04-04 住友電気工業株式会社 炭化珪素半導体装置の製造方法
WO2017098659A1 (fr) 2015-12-11 2017-06-15 新電元工業株式会社 Procédé de fabrication d'un dispositif à semi-conducteur de carbure de silicum, procédé de fabrication d'un corps de base de semi-conducteur, dispositif à semi-conducteur de carbure de silicium et appareil de fabrication d'un dispositif à semi-conducteur de carbure de silicum
JP2017168675A (ja) * 2016-03-16 2017-09-21 富士電機株式会社 半導体装置およびその製造方法
JP2017183730A (ja) * 2017-04-25 2017-10-05 住友電気工業株式会社 炭化珪素半導体基板およびその製造方法、ならびに炭化珪素半導体装置の製造方法
JP2019151543A (ja) * 2018-03-02 2019-09-12 国立研究開発法人産業技術総合研究所 炭化珪素エピタキシャルウェハ及びその製造方法
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