WO2012020613A1 - 非可逆回路素子 - Google Patents
非可逆回路素子 Download PDFInfo
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- WO2012020613A1 WO2012020613A1 PCT/JP2011/065249 JP2011065249W WO2012020613A1 WO 2012020613 A1 WO2012020613 A1 WO 2012020613A1 JP 2011065249 W JP2011065249 W JP 2011065249W WO 2012020613 A1 WO2012020613 A1 WO 2012020613A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/32—Non-reciprocal transmission devices
- H01P1/36—Isolators
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/32—Non-reciprocal transmission devices
- H01P1/38—Circulators
- H01P1/383—Junction circulators, e.g. Y-circulators
- H01P1/387—Strip line circulators
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- the present invention relates to non-reciprocal circuit elements, and more particularly to non-reciprocal circuit elements such as isolators and circulators used in the microwave band.
- nonreciprocal circuit elements such as isolators and circulators have a characteristic of transmitting a signal only in a predetermined specific direction and not transmitting in a reverse direction. Utilizing this characteristic, for example, an isolator is used in a transmission circuit unit of a mobile communication device such as a car phone or a mobile phone.
- this non-reciprocal circuit device has a problem that insertion loss is inevitably increased because the high-frequency current passes through the first variable matching mechanism when a high-frequency current is input from the forward direction. .
- an object of the present invention is to provide a non-reciprocal circuit device capable of adjusting an isolation frequency without deteriorating insertion loss.
- the nonreciprocal circuit device is With permanent magnets, A ferrite to which a DC magnetic field is applied by the permanent magnet; A plurality of central electrodes arranged in an insulating state intersecting the ferrite; A termination resistor connected in parallel with one of the central electrodes between the input and output ports; Capacitance means having a variable capacity connected between the input and output ports and connected to the termination resistor, It is provided with.
- a parallel resonant circuit formed by a center electrode connected in parallel to the termination resistor and a capacitance means having a variable capacitance Is attenuated (isolated).
- the isolation frequency is adjusted by changing the capacitance value of the capacitance means.
- the attenuation is adjusted by selecting the impedance of the terminating resistor.
- the non-reciprocal circuit device is With permanent magnets, A ferrite to which a DC magnetic field is applied by the permanent magnet; A first center electrode and a second center electrode, which are arranged to intersect the ferrite in an insulated state; With The first center electrode has one end electrically connected to the input port and the other end electrically connected to the output port; The second center electrode has one end electrically connected to the output port and the other end electrically connected to the ground port.
- a termination resistor is electrically connected between the input port and the output port, Between the input port and the output port, a capacitance means having a variable capacitance is connected in parallel with the termination resistor, A matching capacitor is electrically connected between the output port and the ground port; It is characterized by.
- a high-frequency current when a high-frequency current is input from the output port, it is attenuated (isolated) by a parallel resonant circuit formed by the first center electrode and a capacitance means having a variable capacitance.
- the isolation frequency is adjusted by changing the capacitance value of the capacitance means.
- the attenuation is adjusted by selecting the impedance of the terminating resistor.
- a large high-frequency current flows through the second center electrode, and almost no high-frequency current flows through the termination resistor or the capacitor means. The resulting loss is negligible and the insertion loss does not increase.
- the non-reciprocal circuit device is With permanent magnets, A ferrite to which a DC magnetic field is applied by the permanent magnet; A first center electrode and a second center electrode, which are arranged to intersect the ferrite in an insulated state; With The first center electrode has one end electrically connected to the input port and the other end electrically connected to the output port; The second center electrode has one end electrically connected to the output port and the other end electrically connected to the ground port.
- a first matching capacitor is electrically connected between the input port and the output port;
- a second matching capacitor is electrically connected between the output port and the ground port;
- a termination resistor is electrically connected between the input port and the output port, Between the input port and the output port, a capacitance means having a variable capacitance is connected in parallel with the termination resistor, It is characterized by.
- the circuit when a high frequency current is input from the output port, the circuit is attenuated by a parallel resonance circuit formed by the first center electrode, the first matching capacitor, and the capacitance means having a variable capacitance. (Isolated).
- the isolation frequency is adjusted by changing the capacitance value of the capacitance means.
- the attenuation is adjusted by selecting the impedance of the terminating resistor.
- the isolation frequency can be adjusted without deteriorating the insertion loss characteristic.
- the nonreciprocal circuit device (two-port isolator) according to the first embodiment intersects a ferrite 32 to which a DC magnetic field is applied by a permanent magnet (not shown) and the ferrite 32 in an insulated state.
- the first center electrode 35 (L1) and the second center electrode 36 (L2) are provided.
- the first center electrode 35 has one end connected to the input port P1 and the other end connected to the output port P2.
- the second center electrode 36 has one end connected to the output port P2 and the other end connected to the ground port P3.
- a termination resistor R is connected in parallel with the first center electrode 35 between the input port P1 and the output port P2, and a variable capacitance capacitor C11 is connected between the input port P1 and the output port P2.
- a matching capacitor C2 is connected to the ground port P3.
- this nonreciprocal circuit device when a high frequency current is input from the output port P2, it is attenuated (isolated) by a parallel resonance circuit formed by the first center electrode 35 and the variable capacitance capacitor C11.
- the isolation frequency is adjusted by changing the capacitance value of the variable capacitance capacitor C11. Further, the attenuation amount is adjusted by selecting the impedance of the termination resistor R.
- a high frequency current flows from the input port P1 to the output port P2
- a large high frequency current flows through the second center electrode 36, and almost no high frequency current flows through the termination resistor R and the variable capacitance capacitor C11. Even if C11 is added, the loss due to it can be ignored, and the insertion loss does not increase.
- variable capacitance capacitor C11 may have either a capacitance value that can be changed stepwise or a capacitance value that can be changed steplessly.
- the non-reciprocal circuit device (two-port isolator) of the second embodiment has a termination resistor R and a first matching capacitor C1 connected in parallel with the first center electrode 35, and the input port P1 side.
- the impedance matching capacitors CS1 and CA are connected to the output port P2
- the impedance matching capacitor CS2 is connected to the output port P2
- the adjustment capacitor C12 and the capacitor are connected in parallel with the first center electrode 35 and the termination resistor R.
- a switching element S11 for switching on and off of C12 is connected.
- Other configurations are the same as those of the first embodiment. The characteristics of the second embodiment will be described with reference to FIGS. 9 to 12 below.
- the nonreciprocal circuit device (two-port isolator) of the third embodiment is configured by configuring the switching device S11 shown in the second embodiment as a semiconductor switch S12.
- the semiconductor switch S12 is known as an SPST switch including a diode D15, a resistor R15, and a capacitor C15.
- the other structure is the same as that of 2nd Example, The effect is also as having demonstrated in 2nd Example.
- an SPDT switch, a MEMS switch, or the like may be used as the switching element.
- the nonreciprocal circuit device (two-port type isolator) according to the fourth embodiment has another adjustment capacitor C13 added in parallel to the adjustment capacitor C12, and two adjustment capacitors C12, 13 is connected to a switching element S13 that selectively switches on and off.
- the switching element S13 can individually switch on and off the capacitors C12 and 13 and can also select a neutral position.
- An SPDT switch or a MEMS switch may be used as the switching element.
- the adjustment capacitance value can be switched in three stages.
- Other configurations are the same as those of the second embodiment, and the operation and effects thereof are basically the same as those of the second embodiment. The characteristics of the fourth embodiment will be described with reference to FIGS. 13 to 16 below.
- This non-reciprocal circuit element has a ferrite substrate 32 in which first and second center electrodes (not shown) are formed of a conductor film on a circuit board 20 and a pair of permanent magnets 41 via an adhesive layer 42. A fixed ferrite / magnet element 30 is mounted.
- Various elements C1, C2, CS1, CS2, CA, C12, S11, and R constituting the matching circuit and the resonance circuit are each configured as a chip type and mounted on the circuit board 20. These elements are electrically connected so as to form the equivalent circuit shown in FIG. 2 by means of electrodes and conductors formed on the surface and inside of the circuit board 20 laminated in multiple layers.
- the ferrite / magnet element 30 is mounted on a circuit board 20, and a termination resistor R and a switching element S 11 are mounted on the circuit board 20 as chip-type components.
- the other elements C1, C2, CS1, CS2, CA, C12 are formed of electrodes or the like formed in the circuit board 20 stacked in multiple layers.
- a flat yoke 10 is disposed on the ferrite / magnet element 30 via a bonding agent layer 15 for magnetic shielding.
- a first center electrode 35 and a second center electrode 36 are wound around the ferrite 32 while being electrically insulated from each other.
- the permanent magnet 41 is bonded to the ferrite 32 via an epoxy adhesive layer 42 so as to apply a DC magnetic field in the thickness direction.
- the first center electrode 35 is formed of a conductor film. That is, as shown in FIG. 8, the ferrite 32 is formed with a relatively small angle with respect to the long side in the state of rising from the lower right on the surface side of the ferrite 32 and bifurcating into two, rising up to the upper left, It is formed in a state of branching into two so as to wrap around on the rear surface side through the relay electrode 35a on the upper surface and overlap with the front surface side on the rear surface side, and one end thereof is connected to the connection electrode 35b formed on the lower surface Has been. The other end of the first center electrode 35 is connected to a connection electrode 35c formed on the lower surface. Thus, the first center electrode 35 is wound around the ferrite 32 for one turn. And the 1st center electrode 35 and the 2nd center electrode 36 demonstrated below cross
- the second center electrode 36 is formed of a conductor film.
- the 0.5th turn 36a is formed on the surface side in a state where it is inclined at a relatively large angle with respect to the long side from the lower right to the upper left and intersects the first center electrode 35, and the relay electrode 36b on the upper surface is formed.
- the first turn 36c is formed in a state of intersecting the first center electrode 35 substantially perpendicularly on the back surface side.
- the lower end portion of the first turn 36c wraps around to the surface side via the relay electrode 36d on the lower surface, and the 1.5th turn 36e is formed so as to intersect the first center electrode 35 on the surface side. It wraps around the back side through 36f.
- the eyes 36o are formed on the front and back surfaces and the top and bottom surfaces of the ferrite 32, respectively. Further, both ends of the second center electrode 36 are connected to connection electrodes 35 c and 36 p formed on the lower surface of the ferrite 32, respectively.
- the connection electrode 35 c is shared as a connection electrode at each end of the first center electrode 35 and the second center electrode 36.
- the second center electrode 36 is wound around the ferrite 32 in a spiral manner for four turns.
- the number of turns is calculated assuming that the state in which the center electrode 36 crosses the front and back surfaces once each is 0.5 turns.
- the crossing angle of the center electrodes 35 and 36 is set as necessary, and the input impedance and insertion loss are adjusted.
- the inductance of the second center electrode 36 is increased, the insertion loss is reduced, and the operating frequency band is expanded.
- FIGS. 9 to 12 The characteristics of the second embodiment (see FIG. 2) are shown in FIGS.
- FIG. 9 shows the input matching characteristics
- FIG. 10 shows the insertion loss in the forward direction.
- the adjustment capacitor C12 is turned on (when the capacitors C1 and C12 act as balanced capacitance) and off (when only the capacitor C1 acts).
- the curves indicating the characteristics are almost overlapped, and there is no influence due to the insertion of the capacitor C12.
- FIG. 11 shows the isolation characteristics in the reverse direction
- FIG. 12 shows the output matching characteristics.
- the isolation characteristic when the adjustment capacitor C12 is turned off is shown by a curve A
- the isolation characteristic when the adjustment capacitor C12 is turned on is shown by a curve B.
- the isolation frequency is shifted to the low frequency band. That is, the isolation characteristic is Band 8 (880-915 MHz) when the capacitor C12 is turned off, but shifts to Band 5 (824-849 MHz) when the capacitor C12 is turned on.
- FIG. 12 also shows the case where the adjustment capacitor C12 is turned on and the case where it is turned off, but the curves indicating the characteristics almost overlap each other.
- FIGS. 13 to 16 The characteristics of the fourth embodiment (see FIG. 4) are shown in FIGS. FIG. 13 shows the input matching characteristics, and FIG. 14 shows the forward insertion loss. 13 and 14, when adjustment capacitors C12 and C13 are off (when only capacitor C1 acts), when adjustment capacitor C12 is turned on (when capacitors C1 and C12 act as parallel capacitors) The case where the adjustment capacitor C13 is turned on (when the capacitors C1 and C13 act as parallel capacitors) is shown, but the curves indicating the characteristics almost overlap each other, and the capacitors C12 and C13 are inserted. There is no impact.
- FIG. 15 shows the isolation characteristic in the reverse direction
- FIG. 16 shows the output matching characteristic.
- the isolation characteristic when the adjustment capacitors C12 and C13 are turned off is indicated by a curve A
- the isolation characteristic when the adjustment capacitor C12 is turned on is indicated by a curve B
- the adjustment capacitor C13 is turned on.
- the isolation characteristic is shown by curve C.
- the isolation frequency is shifted to the low frequency band. That is, the isolation characteristic is Band 8 (880-915 MHz) when the capacitors C12 and C13 are turned off, but shifts to Band 5 (824-849 MHz) when the capacitor C12 is turned on, and Band 13 (777) when the capacitor C13 is turned on. -792 MHz).
- FIG. 16 also shows the case where the adjustment capacitors C12 and C13 are selectively turned on and off, but the curves indicating the characteristics almost overlap.
- the nonreciprocal circuit device according to the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist thereof.
- the input port P1 and the output port P2 are switched.
- the configuration of the ferrite / magnet element 30 and the shapes of the first and second center electrodes 35 and 36 can be variously changed.
- first and second center electrodes are arranged in a state of intersecting at a predetermined angle on one main surface of a ferrite having a flat plate shape (for example, described in detail in JP-A-9-232818). It is also possible to configure as a non-reciprocal circuit element.
- the present invention is useful for non-reciprocal circuit elements, and is particularly excellent in that the isolation frequency can be adjusted without deteriorating insertion loss.
- SYMBOLS 30 Ferrite magnet element 32 ... Ferrite 35 ... 1st center electrode 36 ... 2nd center electrode 41 ... Permanent magnet P1 ... Input port P2 ... Output port P3 ... Ground port C1, C2 ... Matching capacitor C11, C12, C13 ... Adjustment capacitor S11, S12, S13 ... Switching element R ... Termination resistor
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Abstract
Description
永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された複数の中心電極と、
入出力ポート間に前記中心電極の一つと並列に接続された終端抵抗と、
入出力ポート間であって前記終端抵抗と接続された容量が可変な容量手段と、
を備えたことを特徴とする。
永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された第1中心電極及び第2中心電極と、
を備え、
前記第1中心電極は、一端が入力ポートに電気的に接続され、他端が出力ポートに電気的に接続され、
前記第2中心電極は、一端が出力ポートに電気的に接続され、他端がグランドポートに電気的に接続され、
前記入力ポートと前記出力ポートとの間に終端抵抗が電気的に接続され、
前記入力ポートと前記出力ポートとの間に、容量が可変な容量手段が前記終端抵抗と並列に接続され、
前記出力ポートと前記グランドポートとの間に整合容量が電気的に接続されていること、
を特徴とする。
永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された第1中心電極及び第2中心電極と、
を備え、
前記第1中心電極は、一端が入力ポートに電気的に接続され、他端が出力ポートに電気的に接続され、
前記第2中心電極は、一端が出力ポートに電気的に接続され、他端がグランドポートに電気的に接続され、
前記入力ポートと前記出力ポートとの間に第1整合容量が電気的に接続され、
前記出力ポートと前記グランドポートとの間に第2整合容量が電気的に接続され、
前記入力ポートと前記出力ポートとの間に終端抵抗が電気的に接続され、
前記入力ポートと前記出力ポートとの間に、容量が可変な容量手段が前記終端抵抗と並列に接続されていること、
を特徴とする。
第1実施例である非可逆回路素子(2ポート型アイソレータ)は、図1に示すように、図示しない永久磁石により直流磁界が印加されるフェライト32と、該フェライト32に互いに絶縁状態で交差して配置された第1中心電極35(L1)及び第2中心電極36(L2)とを備えている。第1中心電極35は、一端が入力ポートP1に接続され、他端が出力ポートP2に接続されている。第2中心電極36は、一端が出力ポートP2に接続され、他端がグランドポートP3に接続されている。入力ポートP1と出力ポートP2との間に終端抵抗Rが第1中心電極35と並列に接続され、入力ポートP1と出力ポートP2との間に、容量可変コンデンサC11が接続され、出力ポートP2とグランドポートP3との間に整合コンデンサC2が接続されている。
第2実施例である非可逆回路素子(2ポート型アイソレータ)は、図2に示すように、第1中心電極35と並列に終端抵抗R及び第1整合コンデンサC1を接続し、入力ポートP1側にインピーダンス整合用のコンデンサCS1,CAを接続し、出力ポートP2側にインピーダンス整合用のコンデンサCS2を接続し、さらに、第1中心電極35や終端抵抗Rと並列に、調整用コンデンサC12と該コンデンサC12のオン、オフを切り替えるスイッチング素子S11が接続されている。他の構成は、前記第1実施例と同様である。なお、本第2実施例の特性は以下の図9~図12を参照して説明する。
第3実施例である非可逆回路素子(2ポート型アイソレータ)は、図3に示すように、前記第2実施例で示したスイッチング素子S11を半導体スイッチS12として構成したものである。半導体スイッチS12は、ダイオードD15、抵抗R15及びコンデンサC15からなるSPSTスイッチとして周知のものである。他の構成は第2実施例と同様であり、その作用効果も第2実施例で説明したとおりである。なお、スイッチング素子としては、SPDTスイッチやMEMSスイッチなどを用いてもよい。
第4実施例である非可逆回路素子(2ポート型アイソレータ)は、図4に示すように、調整用コンデンサC12にいま一つの調整用コンデンサC13を並列に追加し、二つの調整用コンデンサC12,13のオン、オフを選択的に切り替えるスイッチング素子S13を接続したものである。スイッチング素子S13は、コンデンサC12,13のオン、オフを個別に切り替えるとともに、中立位置をも選択できる。スイッチング素子としては、SPDTスイッチやMEMSスイッチを用いてもよい。本第4実施例では調整用の容量値を3段階に切り替え可能である。他の構成は、前記第2実施例と同様であり、その作用効果も基本的には第2実施例と同様である。なお、本第4実施例の特性は以下の図13~図16を参照して説明する。
ここで、前記第2実施例である非可逆回路素子の構成例1について図5を参照して説明する。この非可逆回路素子は、回路基板20上に、第1及び第2中心電極(図示せず)を導体膜にて形成したフェライト32の左右を一対の永久磁石41で接着剤層42を介して固定したフェライト・磁石素子30を実装したものである。整合回路や共振回路を構成する各種素子C1,C2,CS1,CS2,CA,C12,S11,Rは、それぞれ、チップタイプとして構成され、回路基板20上に実装されている。これらの素子は、多層に積層された回路基板20の表面や内部に形成された電極や導体によって図2に示した等価回路を形成するように電気的に接続されている。
次に、前記第2実施例である非可逆回路素子の構成例2について図6を参照して説明する。この非可逆回路素子は、回路基板20上に前記フェライト・磁石素子30を実装し、チップタイプの部品としては終端抵抗R及びスイッチング素子S11を回路基板20上に実装している。他の素子C1,C2,CS1,CS2,CA,C12は、多層に積層された回路基板20内に形成された電極などで形成されている。
フェライト32には、互いに電気的に絶縁された状態で第1中心電極35及び第2中心電極36が巻回されている。永久磁石41はフェライト32に対して直流磁界を厚み方向に印加するように、例えば、エポキシ系の接着剤層42を介して接着されている。
前記第2実施例(図2参照)の特性を図9~図12に示す。図9は入力整合特性を示し、図10は順方向の挿入損失を示している。図9及び図10において、調整用コンデンサC12をオンした場合(コンデンサC1,C12が平衡容量として作用する場合)とオフした場合(コンデンサC1のみが作用する場合)とを示しているが、いずれも特性を示す曲線はほとんど重なっており、コンデンサC12を挿入したことによる影響は生じていない。
前記第4実施例(図4参照)の特性を図13~図16に示す。図13は入力整合特性を示し、図14は順方向の挿入損失を示している。図13及び図14において、調整用コンデンサC12、C13がオフの場合(コンデンサC1のみが作用する場合)と、調整用コンデンサC12をオンした場合(コンデンサC1,C12が並列容量として作用する場合)と、調整用コンデンサC13をオンした場合(コンデンサC1,C13が並列容量として作用する場合)とを示しているが、いずれも特性を示す曲線はほとんど重なっており、コンデンサC12,C13を挿入したことによる影響は生じていない。
なお、本発明に係る非可逆回路素子は前記実施例に限定するものではなく、その要旨の範囲内で種々に変更することができる。
32…フェライト
35…第1中心電極
36…第2中心電極
41…永久磁石
P1…入力ポート
P2…出力ポート
P3…グランドポート
C1,C2…整合用コンデンサ
C11,C12,C13…調整用コンデンサ
S11,S12,S13…スイッチング素子
R…終端抵抗
Claims (7)
- 永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された複数の中心電極と、
入出力ポート間に前記中心電極の一つと並列に接続された終端抵抗と、
入出力ポート間であって前記終端抵抗と接続された容量が可変な容量手段と、
を備えたことを特徴とする非可逆回路素子。 - 永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された第1中心電極及び第2中心電極と、
を備え、
前記第1中心電極は、一端が入力ポートに電気的に接続され、他端が出力ポートに電気的に接続され、
前記第2中心電極は、一端が出力ポートに電気的に接続され、他端がグランドポートに電気的に接続され、
前記入力ポートと前記出力ポートとの間に終端抵抗が電気的に接続され、
前記入力ポートと前記出力ポートとの間に、容量が可変な容量手段が前記終端抵抗と並列に接続され、
前記出力ポートと前記グランドポートとの間に整合容量が電気的に接続されていること、
を特徴とする非可逆回路素子。 - 永久磁石と、
前記永久磁石により直流磁界が印加されるフェライトと、
前記フェライトに互いに絶縁状態で交差して配置された第1中心電極及び第2中心電極と、
を備え、
前記第1中心電極は、一端が入力ポートに電気的に接続され、他端が出力ポートに電気的に接続され、
前記第2中心電極は、一端が出力ポートに電気的に接続され、他端がグランドポートに電気的に接続され、
前記入力ポートと前記出力ポートとの間に第1整合容量が電気的に接続され、
前記出力ポートと前記グランドポートとの間に第2整合容量が電気的に接続され、
前記入力ポートと前記出力ポートとの間に終端抵抗が電気的に接続され、
前記入力ポートと前記出力ポートとに間に、容量が可変な容量手段が前記終端抵抗と並列に接続されていること、
を特徴とする非可逆回路素子。 - 前記第2中心電極は前記フェライトに複数回巻回されていること、を特徴とする請求項2又は請求項3に記載の非可逆回路素子。
- 前記容量手段は容量可変コンデンサからなること、を特徴とする請求項1ないし請求項4のいずれかに記載の非可逆回路素子。
- 前記容量手段は、少なくとも一つのコンデンサと該コンデンサのオン、オフを切り替えるスイッチング素子とを有していること、を特徴とする請求項1ないし請求項4のいずれかに記載の非可逆回路素子。
- 前記容量手段は、並列に接続された複数のコンデンサとそれぞれのコンデンサのオン、オフを切り替えるスイッチング素子とを有していること、を特徴とする請求項1ないし請求項4のいずれかに記載の非可逆回路素子。
Priority Applications (3)
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CN201180039131.5A CN103081219B (zh) | 2010-08-09 | 2011-07-04 | 非可逆电路元件 |
JP2012528618A JP5418682B2 (ja) | 2010-08-09 | 2011-07-04 | 非可逆回路素子 |
US13/761,951 US20130147574A1 (en) | 2010-08-09 | 2013-02-07 | Non-reciprocal circuit element |
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JP2010-178444 | 2010-08-09 | ||
JP2010178444 | 2010-08-09 |
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US13/761,951 Continuation US20130147574A1 (en) | 2010-08-09 | 2013-02-07 | Non-reciprocal circuit element |
Publications (1)
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WO2012020613A1 true WO2012020613A1 (ja) | 2012-02-16 |
Family
ID=45567583
Family Applications (1)
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PCT/JP2011/065249 WO2012020613A1 (ja) | 2010-08-09 | 2011-07-04 | 非可逆回路素子 |
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US (1) | US20130147574A1 (ja) |
JP (1) | JP5418682B2 (ja) |
CN (1) | CN103081219B (ja) |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013118355A1 (ja) * | 2012-02-06 | 2013-08-15 | 株式会社村田製作所 | 非可逆回路素子 |
WO2014112460A1 (ja) * | 2013-01-18 | 2014-07-24 | 株式会社村田製作所 | 非可逆回路素子 |
DE102014102207A1 (de) | 2014-02-20 | 2015-08-20 | Epcos Ag | Abstimmbarer Duplexer |
DE102014102518A1 (de) | 2014-02-26 | 2015-08-27 | Epcos Ag | Package für ein abstimmbares Filter |
DE102014102521A1 (de) | 2014-02-26 | 2015-08-27 | Epcos Ag | Abstimmbare HF-Filterschaltung |
DE102014102704A1 (de) | 2014-02-28 | 2015-09-03 | Epcos Ag | Kombinierte Impedanzanpass- und HF-Filterschaltung |
US9634368B2 (en) | 2013-11-29 | 2017-04-25 | Murata Manufacturing Co., Ltd. | Non-reciprocal circuit element |
US9866266B2 (en) | 2014-02-28 | 2018-01-09 | Snaptrack, Inc. | Front-end circuit having a tunable filter |
US10277259B2 (en) | 2014-02-28 | 2019-04-30 | Snaptrack, Inc. | Front-end circuit for simultaneous transmission and reception operation |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180287388A1 (en) * | 2017-03-30 | 2018-10-04 | Rheem Manufacturing Company | Controlled Distribution of Integrated Power Supplies for Electrical Loads |
JP7424176B2 (ja) * | 2020-04-08 | 2024-01-30 | 株式会社村田製作所 | 回路 |
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JPH0993003A (ja) * | 1995-09-26 | 1997-04-04 | Murata Mfg Co Ltd | 非可逆回路素子 |
WO2008087782A1 (ja) * | 2007-01-18 | 2008-07-24 | Murata Manufacturing Co., Ltd. | 非可逆回路素子 |
WO2009154024A1 (ja) * | 2008-06-18 | 2009-12-23 | 株式会社村田製作所 | 非可逆回路素子 |
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JPS57181202A (en) * | 1981-04-30 | 1982-11-08 | Clarion Co Ltd | Electronic tuning type circulator |
WO2006013865A1 (ja) * | 2004-08-03 | 2006-02-09 | Hitachi Metals, Ltd. | 非可逆回路素子 |
JP4596032B2 (ja) * | 2008-04-09 | 2010-12-08 | 株式会社村田製作所 | フェライト・磁石素子の製造方法、非可逆回路素子の製造方法及び複合電子部品の製造方法 |
JP4844625B2 (ja) * | 2008-12-19 | 2011-12-28 | 株式会社村田製作所 | 非可逆回路素子 |
JP2010157844A (ja) * | 2008-12-26 | 2010-07-15 | Murata Mfg Co Ltd | 非可逆回路素子 |
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2011
- 2011-07-04 WO PCT/JP2011/065249 patent/WO2012020613A1/ja active Application Filing
- 2011-07-04 CN CN201180039131.5A patent/CN103081219B/zh not_active Expired - Fee Related
- 2011-07-04 JP JP2012528618A patent/JP5418682B2/ja not_active Expired - Fee Related
-
2013
- 2013-02-07 US US13/761,951 patent/US20130147574A1/en not_active Abandoned
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JPH0993003A (ja) * | 1995-09-26 | 1997-04-04 | Murata Mfg Co Ltd | 非可逆回路素子 |
WO2008087782A1 (ja) * | 2007-01-18 | 2008-07-24 | Murata Manufacturing Co., Ltd. | 非可逆回路素子 |
WO2009154024A1 (ja) * | 2008-06-18 | 2009-12-23 | 株式会社村田製作所 | 非可逆回路素子 |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013118355A1 (ja) * | 2012-02-06 | 2013-08-15 | 株式会社村田製作所 | 非可逆回路素子 |
US9748624B2 (en) | 2012-02-06 | 2017-08-29 | Murata Manufacturing Co., Ltd. | Non-reciprocal circuit element |
WO2014112460A1 (ja) * | 2013-01-18 | 2014-07-24 | 株式会社村田製作所 | 非可逆回路素子 |
US9634368B2 (en) | 2013-11-29 | 2017-04-25 | Murata Manufacturing Co., Ltd. | Non-reciprocal circuit element |
DE102014102207A1 (de) | 2014-02-20 | 2015-08-20 | Epcos Ag | Abstimmbarer Duplexer |
DE102014102518A1 (de) | 2014-02-26 | 2015-08-27 | Epcos Ag | Package für ein abstimmbares Filter |
WO2015128004A1 (de) | 2014-02-26 | 2015-09-03 | Epcos Ag | Abstimmbare hf-filterschaltung |
WO2015128008A1 (de) | 2014-02-26 | 2015-09-03 | Epcos Ag | Package für ein abstimmbares filter |
DE102014102521A1 (de) | 2014-02-26 | 2015-08-27 | Epcos Ag | Abstimmbare HF-Filterschaltung |
US10079586B2 (en) | 2014-02-26 | 2018-09-18 | Snaptrack, Inc. | Package for a tunable filter |
DE102014102518B4 (de) | 2014-02-26 | 2022-04-28 | Snaptrack, Inc. | Package für ein abstimmbares Filter |
DE102014102521B4 (de) | 2014-02-26 | 2023-10-19 | Snaptrack, Inc. | Abstimmbare HF-Filterschaltung |
DE102014102704A1 (de) | 2014-02-28 | 2015-09-03 | Epcos Ag | Kombinierte Impedanzanpass- und HF-Filterschaltung |
US9866266B2 (en) | 2014-02-28 | 2018-01-09 | Snaptrack, Inc. | Front-end circuit having a tunable filter |
US10277259B2 (en) | 2014-02-28 | 2019-04-30 | Snaptrack, Inc. | Front-end circuit for simultaneous transmission and reception operation |
Also Published As
Publication number | Publication date |
---|---|
JPWO2012020613A1 (ja) | 2013-10-28 |
CN103081219B (zh) | 2016-01-13 |
CN103081219A (zh) | 2013-05-01 |
US20130147574A1 (en) | 2013-06-13 |
JP5418682B2 (ja) | 2014-02-19 |
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