WO2011160423A1 - 半导体器件的接触的制造方法及具有该接触的半导体器件 - Google Patents

半导体器件的接触的制造方法及具有该接触的半导体器件 Download PDF

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WO2011160423A1
WO2011160423A1 PCT/CN2011/000693 CN2011000693W WO2011160423A1 WO 2011160423 A1 WO2011160423 A1 WO 2011160423A1 CN 2011000693 W CN2011000693 W CN 2011000693W WO 2011160423 A1 WO2011160423 A1 WO 2011160423A1
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Prior art keywords
contact
layer
forming
interlayer dielectric
dielectric layer
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PCT/CN2011/000693
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English (en)
French (fr)
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钟汇才
梁擎擎
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中国科学院微电子研究所
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Priority to US13/201,073 priority Critical patent/US20120056278A1/en
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to GB1202166.3A priority patent/GB2484637B/en
Publication of WO2011160423A1 publication Critical patent/WO2011160423A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention generally relates to a semiconductor device and a method of fabricating the same, and, in particular, to a method of fabricating a contact hole of a semiconductor device having better contact conductivity and a semiconductor device having better contact conductivity.
  • the contact for connecting the gate and the source/drain the currently used structure is the contact hole and the trench contact. Both contacts are fabricated by etching the interlayer dielectric layer to the bottom and filling the conductive metal. Materials to form, metal materials such as W, Cu, etc., the resistivity of these metals has been as low as possible, but as the feature size continues to decrease, the electrical conductivity of the contact is also required to be higher and higher, and it is required to propose more conductive properties. Good contact and its manufacturing methods to improve the overall performance of the device. Summary of the invention
  • the present invention provides a method of fabricating a contact of a semiconductor device, the method comprising: providing a semiconductor substrate and a semiconductor device, the device including a gate region and a source/drain region; forming on the source/drain region An interlayer dielectric layer; a plurality of ordered via holes are formed in the interlayer dielectric layer, and the via holes are filled to form contact holes; and trench contact on the contact holes is formed in the interlayer dielectric layer .
  • the present invention also provides a semiconductor device, the device comprising: a semiconductor substrate; a gate region formed on the semiconductor substrate; and a semiconductor substrate formed on both sides of the gate region a source/drain region, and an interlayer dielectric layer formed on the source/drain region; a plurality of ordered contact holes formed in the interlayer dielectric layer; formed in the interlayer dielectric layer and located on the contact hole Groove contact.
  • a contact hole having a small aperture and an orderly arrangement is formed at a bottom portion in contact with the source/drain, and a groove contact is formed thereon to be connected with the metal layer of the upper layer, the ordered arrangement
  • the contact hole maintains good contact with the source/drain regions, and the upper portion is a larger-area trench contact, which is more easily connected to the upper metal, thereby improving the electrical conductivity of the contact and thereby improving the overall performance of the device.
  • FIG. 1 is a flow chart showing a method of manufacturing a contact of a semiconductor device according to an embodiment of the present invention
  • a schematic view , ⁇ , ', '. . - , ', .
  • Figure 14 is a schematic view showing an alumina plate mold in an embodiment of the present invention. detailed description
  • the following disclosure provides many different embodiments or examples for implementing the different structures of the present invention.
  • the components and settings of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • step S01 a semiconductor substrate including a gate stack and source/drain regions, as shown in Fig. 2, is provided.
  • the substrate 200 includes a silicon substrate (eg, a wafer) in a crystal structure, and may also include other basic semiconductors or compound semiconductors, such as e, GeSi, GaAs, InP, SiC or diamond.
  • the substrate 200 can include various doping configurations in accordance with design requirements well known in the art, such as a p-type substrate or an n-type substrate.
  • the substrate 200 may include an epitaxial layer that may be altered by stress to enhance performance, and may include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the semiconductor device is any device structure including a gate region and a source/drain region 210, and the structure, material, formation process, steps, and the like of the semiconductor device are not limited.
  • 2 is a schematic diagram of an embodiment of a semiconductor device according to the present invention.
  • a gate dielectric layer 202 and a gate electrode 204 may be sequentially deposited on a semiconductor substrate and patterned, and the gate dielectric layer 202 and the gate electrode 204 form a gate. Area.
  • a spacer 206 is then formed on the sidewalls of the gate dielectric layer 202 and the gate electrode 204. After the formation of the spacers 206, ion implantation is performed in the semiconductor substrates on both sides of the gate region to form source/drain regions 210.
  • the source/drain shallow junction 208 may also be formed by ion implantation in the semiconductor substrate before the source/drain regions 210 are formed.
  • a metal silicide layer 212 is formed by self-alignment, a metal is deposited on the device, and then annealed, and the metal reacts with the silicon surface in contact with any of them to form a metal silicide.
  • the silicon surface may be the semiconductor substrate 200 of the source/drain region 210 and/or the polysilicon layer in the gate electrode 204, etc.
  • the gate dielectric layer 202, the gate electrode 204, and the metal silicide layer 212 are formed. Gate stack 300.
  • step S02 an interlayer dielectric layer 21 4 is formed on the source/drain regions 210, with reference to FIG. A dielectric material is first covered over the device, and then a planarization process is performed to expose an upper surface of the gate stack 300 to form an interlayer dielectric layer 214.
  • the dielectric material may be, for example but not limited to, undoped silicon oxide (SiO 2 ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), silicon nitride (Si 3 N 4 ) and
  • the interlayer dielectric layer 214 may have a multilayer structure that may be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable processes.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • step S03 a plurality of ordered vias 2 20 are formed in the interlayer dielectric layer 214, and the through vias 220 are filled to form contact vias 222_, as shown in FIG.
  • the first selective etch removes a portion of the interlayer dielectric layer 214 such that the upper surface of the interlayer dielectric layer 214 is lower than the upper surface of the gate stack 300, as shown in FIG.
  • the interlayer dielectric layer having a plurality of perforations is formed on the interlayer dielectric layer, and then the interlayer dielectric layer is etched by using the mask as a mask, and a plurality of layers are formed in the interlayer dielectric layer. Order holes.
  • FIG. 5 to 8 show a preferred embodiment of the mask forming sheet of the present invention, on which metal aluminum is deposited and planarized to expose the upper surface of the gate stack, thereby only in the interlayer dielectric layer
  • a metal aluminum layer 216 is formed as shown in FIG.
  • the device is subjected to an anodized aluminum (AAO) process, and the metal aluminum layer 216 is oxidized to an alumina plate 218 having a plurality of ordered holes 218-1, thereby forming alumina.
  • AAO anodized aluminum
  • the mask version of the stamper 218 is shown in FIG. Figure 14 shows the structure of the alumina plate mold 218 having a plurality of perforations 218-1 having uniform sizes, substantially the same shape, and periodic arrangement. In the manner, the hole 218-1 has a diameter of about 1 to 60 nm.
  • the holes may also be formed into a reticle having a smaller aperture and a smaller pitch of the holes by a complicated photolithography method.
  • a mask (not shown) may be formed by a process of LELE (Litho-Ething Litho-Etching), first forming first and second hard mask layers on the interlayer dielectric layer, And performing a first mask, such as applying a photoresist coating, performing a first exposure, then etching the patterned first hard mask layer, removing the mask, and then performing a second mask, such as coating After the encapsulation coating, a second exposure is performed, and then the mask and the patterned first hard mask layer are used as a mask, the patterned second hard mask layer is etched, and the mask and the first hard mask are removed.
  • the film layer forms a reticle with perforations having a small aperture and a small hole pitch.
  • a reticle having a smaller aperture and a smaller aperture pitch may be formed by the LFLE method (Litho-Freeze Litho-Etch), specifically, first in the layer Forming a hard mask layer on the dielectric layer, and masking thereon, such as a photoresist layer, and then exposing the photoresist layer for the first time, and performing freezing, and then performing a second exposure to form a small aperture The mask is then etched to form a reticle having a smaller aperture and a smaller pitch.
  • the LFLE method Litho-Freeze Litho-Etch
  • a reticle (not shown) having a small aperture and a small aperture pitch may be formed by a method of patterning with aid from spacer, specifically, First, a hard mask layer is formed on the interlayer dielectric layer, and then an auxiliary layer and its sidewalls are formed on the newly described hard mask layer, and then the auxiliary step layer is removed, and the sidewall is patterned as a mask. A hard mask layer is formed to form a mask having a plurality of perforations.
  • a mask having a plurality of perforations formed by the above method the perforations exhibit a periodic arrangement with a small aperture and a hole pitch, the diameter of the perforations is about 1 to 60 nm, and the distance between the perforations is 1 to 60 nm. .
  • etching the interlayer dielectric layer 214 to form a via hole 220 therein by an etching technique, such as RIE. 7 is shown.
  • a contact conductive material is deposited on the device, and the conductive material is preferably a low resistivity material such as carbon nanotube, Cu, Ag, TiN, W or other low resistivity material, and is planarized.
  • the gate stack 300 and the metal over the mask are removed, as shown in FIG. 8, and then the mask 218 is selectively etched to form a contact hole 222 filling the via 220, as shown in FIG.
  • the ordered array of small-aperture nanotubes and the contact holes of the wires can be formed by the above method, and the contact holes of the nanotubes and the wires have high conductivity to achieve good compatibility with the source/drain regions. contact.
  • a trench contact 228 over the contact hole 222 is formed in the interlayer dielectric layer 214 as shown in FIG.
  • a dielectric material is deposited on the device, and the same or different materials may be used as the interlayer dielectric layer 214.
  • the dielectric material may be, but not limited to, for example, undoped silicon oxide (SiO 2 ), Doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), silicon nitride (Si 3 N 4 ), and combinations thereof, and then planarized, such as CMP, until the upper surface of the gate stack 300 is exposed, causing the layer The upper surface of the dielectric layer 214 is substantially flush with the upper surface of the gate stack 300.
  • a mask 224 is then performed on the device.
  • the opening of the mask 224 corresponds to the trench to be formed, as shown in FIG.
  • the number of openings of the mask 224 is one or more as needed, thereby correspondingly forming a trench contact having one or more trench structures.
  • a selective etching such as RIE, is performed to form trenches 226 in the interlayer dielectric layer 214 to contact the vias 222 as a stop layer, as shown in FIG.
  • the mask 224 is removed, and a conductive material is deposited on the device.
  • the conductive material is preferably a low resistivity material such as Cu, Ag, TiN, W or other conductive material, and is planarized to remove the gate.
  • Conductive material over stack 300 and interlayer dielectric layer 214 is formed to form trench contact 228, as shown in FIG. Thereby, a contact structure is formed in which the bottom is the contact hole 222 and the upper portion is the groove contact 228.
  • a contact structure having a plurality of ordered contact holes at the lower portion and a groove contact at the upper portion is formed on the source/drain regions, and the contact of the structure is in contact with the source/drain regions.
  • the bottom part is a contact hole with a small aperture
  • the upper part is a groove contact with a large contact area, which has better conductivity and is easily connected with the metal layer of the upper layer, thereby improving the conductive property of the contact, thereby improving the device.
  • FIG. 13 is a schematic diagram showing the structure of a semiconductor device according to an embodiment of the present invention.
  • the device includes: a semiconductor substrate 200; formed at a semiconductor substrate The gate regions 202, 204 on 200, and the source/drain regions 210 formed in the semiconductor substrate 200 on both sides of the gate regions 202, 204, And an interlayer dielectric layer 214 formed on the source/drain region 210; a plurality of ordered contact holes 222 formed in the interlayer dielectric layer 214; a trench formed in the interlayer dielectric layer 214 and located on the contact hole 222 Slot contact 228.
  • the contact hole 222 has a pore diameter of 1 to 60 nm, and the material forming the contact hole 222 may be carbon nanotube, Cu, Ag, TiN, W or other materials.
  • the semiconductor device has a contact structure in which a lower portion is a contact hole and an upper portion is a groove contact.
  • the contact of the structure has a plurality of ordered contact holes having a small aperture at a bottom portion in contact with the source/drain regions, and the upper portion is Larger groove contact, better conductivity, easy to connect with the upper metal layer, effectively improve the electrical conductivity of the device, thereby improving the overall performance of the device.

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Description

半导体器件的接触的制造方法及具有该接触的半导体器件 优先权要求
本申请要求了 2010年 6月 22日提交的、申请号为 201010215145.5、 发明名称为 "半导体器件的接触的制造方法及具有该接触的半导体器 件" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明通常涉及一种半导体器件及其制造方法， 具体来说， 涉及 一种其接触导电性能更好的半导体器件及接触导电性能更好的半导体 器件的接触孔的制造方法。 背景技术
随着半导体技术的发展， 具有更高性能和更强功能的集成电路要 求更大的元件密度， 而且各个部件、 元件之间或各个元件自身的尺寸、 大小和空间也需要进一步缩小， 对器件的工艺和性能都是很大的挑战。 对用于连接栅极、 源 /漏极的接触来说， 目前常用的结构为接触孔和沟 槽接触， 这两种接触的制作都是通过刻蚀层间介质层到底部后， 填充 导电金属材料来形成， 金属材料如 W、 Cu等， 这些金属的电阻率已经 尽可能低了， 但随着特征尺寸的不断减小， 对接触的导电性能也要求 越来越高， 需要提出导电性能更好的接触及其制造方法， 以提高器件 的整体性能。 发明内容
本发明提供了一种半导体器件的接触的制造方法， 所述方法 ^括： 提供半导体衬底以及半导体器件， 所述器件包括栅极区和源 /漏区； 在 所述源 /漏区上形成层间介质层； 在所述层间介质层内形成多个有序的 通孔， 并填充所述通孔形成接触孔； 在所述层间介质层内形成位于接 触孔之上的沟槽接触。
本发明还提供了一种半导体器件， 所述器件包括： 半导体衬底； 形成于半导体衬底上的栅极区， 以及形成于栅极区两侧的半导体衬底 内的源 /漏区， 以及形成于源 /漏区上的层间介质层; 形成于层间介质层 内的多个有序的接触孔； 形成于层间介质层内且位于接触孔上的沟槽 接触。
通过本发明的接触制造方法， 在与源 /漏接触的底部形成孔径较小 的、 有序排列的接触孔， 并在其上形成沟槽接触以和上层的金属层连 接， 这种有序排列的接触孔与源 /漏区保持良好的接触， 而其上部为面 积较大的沟槽接触， 更易于和上层金属相连， 因此， 提高了接触的导 电性能， 进而提高了器件的整体性能。 附图说明
图 1示出了本发明实施例的半导体器件的接触制造方法的流程图； 示意图； 、 ^、 ' 、' 。。- , '、 。 、 图 14示出了本发明实施例中氧化铝版模的示意图。 具体实施方式
下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进 行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了简 化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领 域普通技术人员可以意识到其他工艺的可应用性和 /或其他材料的使 用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一 和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成在 第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接 触。
参考图 1 , 图 1示出了本发明实施例的半导体器件的接触制造方法 的流程图。 在步骤 S01 , 提供半导体衬底以及半导体器件， 所述半导体 器件包括栅堆叠和源 /漏区， 如图 2所示。
在本实施例中， 村底 200 包括位于晶体结构中的硅衬底 （例如晶 片） ， 还可以包括其他基本半导体或化合物半导体， 例如 e、 GeSi、 GaAs、 InP、 SiC或金刚石等。 根据现有技术公知的设计要求 （例如 p 型衬底或者 n型衬底） , 衬底 200可以包括各种掺杂配置。 此外， 可 选地， 衬底 200 可以包括外延层， 可以被应力改变以增强性能， 以及 可以包括绝缘体上硅 （SOI ) 结构。
所述半导体器件为包括栅极区和源 /漏区 210的任一器件结构， 本 发明对所述半导体器件的结构、 材料以及形成工艺、 步骤等不做限定。 图 2 为本发明所述半导体器件的一个实施例的示意图， 可以先在半导 体衬底上依次沉积栅介质层 202、 栅电极 204并图形化， 所述栅介质层 202和栅电极 204构成栅极区。而后在栅介质层 202和栅电极 204的侧 壁形成侧墙 206。 在形成侧墙 206结构后， 在栅极区两侧的半导体衬底 内进行离子注入， 形成源 /漏区 210。 在形成源 /漏区 210前， 还可以在 半导体衬底内进行离子注入形成源 /漏浅结 208。 特别地， 在形成源 /漏 区 210后， 通过自对准方式形成金属硅化物层 212, 在所述器件上沉积 金属， 而后进行退火， 金属和与其任一接触的硅表面反应生成金属硅 化物， 硅表面可以为源 /漏区 210的半导体衬底 200和 /或栅电极 204中 的多晶硅层等， 本实施例中， 形成了包括栅介质层 202、 栅电极 204和 金属硅化物层 212的栅堆叠 300。
在步骤 S02,在所述源 /漏区 210上形成层间介质层 214，参考图 3。 首先将介质材料覆盖所述器件， 而后进行平坦化处理暴露所述栅堆叠 300的上表面， 以形成层间介质层 214。 所述介质材料可以是但不限于 例如未掺杂的氧化硅（Si02 ) 、 掺杂的氧化硅（如硼硅玻璃、 硼磷硅玻 璃等） 、 氮化硅 （Si3N4 ) 及其组合， 所述层间介质层 214可以具有多 层结构， 可以使用例如化学气相沉积（ CVD )、 物理气相沉积（ PVD ) 、 原子层沉积 （ALD ) 及 /或其他合适的工艺等方法形成。
在步骤 S03， 在所述层间介质层 214内形成多个有序的通孔 220, 填充所述—通孔 220形成接触孔 222_， 如图 8所示。 _具体来说-, 首 选择性蚀刻去除部分层间介质层 214, 以使层间介质层 214的上表面低 于栅堆叠 300的上表面， 如图 4所示。 而后， 可以通过在层间介质层 上形成具有多个穿孔的掩膜版， 而后以掩膜版为掩膜， 刻蚀所述层间 介质层， 在所述层间介质层内形成多个有序孔洞。 图 5-图 8示出了本 发明形成掩膜版的一个优选的实施例， 在所述器件上沉积金属铝， 并 进行平坦化处理， 暴露栅堆叠的上表面， 从而仅在层间介质层 214 上 形成金属铝层 216， 如图 5 所示。 而后， 对所述器件进行阳极氧化铝 ( AAO: Anodic Aluminum Oxide ) 工艺， 所述金属铝层 216被氧化为 具有多个有序的孔洞 218-1的氧化铝版模 218 , 从而形成了氧化铝版模 218的掩膜版， 如图 6所示。 图 14示出了所述氧化铝版模 218的结构， 所述氧化铝版模 218具有多个穿孔 218-1， 穿孔 218- 1的大小均匀、 具 有基本相同的形状， 并呈现周期性的排列方式， 孔洞 218-1的直径为大 约 1至 60纳米。
在另外的实施例中， 所述孔洞还可以通过复杂的光刻的方法来形 成具有较小孔径、 孔间距小的穿孔的掩模版。 在另一个实施例中， 可 以通过 LELE ( Litho-Ething Litho-Etching )的工艺形成掩膜版（图中未 示出） ， 首先在层间介质层上形成第一和第二硬掩膜层， 并进行第一 次掩膜， 例如涂光刻胶涂层后进行第一次曝光， 而后刻蚀图形化第一 硬掩膜层， 并去除掩膜， 而后进行第二次掩膜， 例如涂光刻胶涂层后 进行第二次曝光， 而后以掩膜和图形化后的第一硬掩膜层为掩膜， 刻 蚀图形化第二硬掩膜层， 并去除掩膜和第一硬掩膜层， 从而形成了具 有较小孔径、 孔间距小的穿孔的掩模版。
在又一个实施例中， 可以通过 LFLE 的方法 （ Litho-Freeze Litho-Etch ) 来形成具有较小孔径、 孔间距小的穿孔的掩模版 (图中未 示出） ， 具体来说， 首先在层间介质层上形成硬掩膜层， 并在其上掩 膜， 如光刻胶层， 而后第一次曝光所述光刻胶层， 并进行冷冻， 而后 进行第二次曝光， 以形成孔径小的掩膜， 而后刻蚀所述硬掩膜层以形 成具有较小孔径、 孔间距小的穿孔的掩模版。
在又一个实施例中， 还可以通过借助辅助侧墙的方法 （ Patterning with aid from spacer ) 来形成具有较小孔径、 孔间距小的穿孔的掩模版 (图中未示出） ， 具体来说， 首先在层间介质层上形成硬掩膜层， 而 ― 后在新述硬掩膜层上形成间隔排列的辅助层及其侧墙， 而后去除辅踏 层， 并以侧墙为掩膜图形化硬掩膜层， 以形成具有多个穿孔的掩膜版。
由上述方法形成的具有多个穿孔的掩膜版， 其穿孔呈现周期性的 排列方式， 具有较小孔径和孔间距， 穿孔的直径为大约 1至 60纳米， 穿孔间的距离为 1至 60纳米。
而后， 以所述掩膜版为掩膜， 通过掩膜版的穿孔， 利用刻蚀技术， 例如 RIE的方法， 刻蚀所述层间介质层 214在其内形成通孔 220, 如图 7所示。 而后， 在所述器件上沉积接触导电材料， 导电材料优选低电阻 率的材料， 例如碳纳米管 （Carbon nanotube ) 、 Cu、 Ag、 TiN、 W或 其他低电阻率的材料， 并进行平坦化处理， 去除栅堆叠 300 和掩膜版 之上的金属， 如图 8所示， 而后选择性刻蚀去除掩膜版 218 , 以形成填 满通孔 220的接触孔 222, 如图 9所示。 在优选的实施例中， 可以通过 上述方法形成有序的排列的、 小孔径的纳米管、 丝的接触孔， 纳米管、 丝的接触孔具有高导电性， 以实现与源 /漏区的良好接触。
在步骤 S04 ,在所述层间介质层 214内形成位于接触孔 222之上的 沟槽接触 228 , 如图 13所示。 具体来说， 首先， 在所述器件上沉积介 质材料， 可以与所述层间介质层 214 采用相同或不同的材料， 介质材 料可以是但不限于例如未掺杂的氧化硅（ Si02 ) 、 掺杂的氧化硅（如硼 硅玻璃、 硼磷硅玻璃等） 、 氮化硅 （Si3N4 ) 及其组合， 而后进行平坦 化， 例如 CMP， 直至暴露栅堆叠 300的上表面， 使层间介质层 214的 上表面与栅堆叠 300上表面大致相平， 如图 10所示， 接着在所述器件 上进行掩膜 224， 掩膜 224的开口对应将要形成的沟槽接触， 如图 1 1 所示， 根据需要， 掩膜 224 的开口数目为一个或多个， 从而对应形成 具有一个或多个沟槽结构的沟槽接触。 而后， 进行选择性刻蚀， 例如 RIE的方法， 在层间介质层 214内形成沟槽 226， 以接触孔 222为停止 层， 如图 12所示。 而后， 去除掩膜 224， 并在所述器件上沉积导电材 料， 导电材料优选低电阻率的材料， 例如 Cu、 Ag、 TiN、 W或其他导 电性能良好的材料， 并进行平坦化处理， 去除栅堆叠 300 和层间介质 层 214之上的导电材料， 以形成沟槽接触 228， 如图 13所示。 从而形 成了底部为接触孔 222、 上部为沟槽接触 228的接触结构。
根据本法明实施例的制造方法， 在源 /漏区上形成了下部为多个有 序的接触孔、 上部为沟槽接触的接触结构， 这种结构的接触， 其与源 / 漏区接触的底部部分为孔径较小的接触孔， 上部为接触面积较大的沟 槽接触， 具有更好的导电性， 易于和上层的金属层相连接， 从而提高 了接触的导电性能， 进而提高了器件的整体性能。
本发明还提供了具有上述方法形成的接触的半导体器件， 参考图 13 , 图 13示出了本发明实施例的半导体器件结构的示意图， 所述器件 包括： 半导体村底 200; 形成于半导体村底 200上的栅极区 202、 204, 以及形成于栅极区 202、 204两侧的半导体衬底 200内的源 /漏区 210, 以及形成于源 /漏区 210上的层间介质层 214; 形成于层间介质层 214 内的多个有序的接触孔 222; 形成于层间介质层 214 内且位于接触孔 222上的沟槽接触 228。 所述接触孔 222的孔径为 1- 60nm, 形成所述接 触孔 222的材料可以为碳纳米管、 Cu、 Ag、 TiN、 W或其他材料。 所 述半导体器件具有下部为接触孔、 上部为沟槽接触的接触结构， 这种 结构的接触， 在与源 /漏区接触的底部部分为孔径较小的多个有序的接 触孔， 上部为面积较大的沟槽接触， 具有更好的导电性， 易于和上层 的金属层相连接， 有效的提高了器件的导电性能， 从而提高了器件的 整体性能。
虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离 本发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些 实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技 术人员应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次 序可以变化。
· 此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开 内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或 者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步 骤， 其中它们执行与本发明描述的对应实施例大体相同的功能或者获 得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明 所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法 或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体器件的接触的制造方法， 所述方法包括：
A、 提供半导体衬底以及半导体器件， 所述器件包括栅极区和源 / 漏区；
B、 在所述源 /漏区上形成层间介质层；
C、 在所述层间介质层内形成多个有序的通孔， 并填充所述通孔形 成接触孔；
D、 在所述层间介质层内形成位于接触孔之上的沟槽接触。
2. 根据权利要求 1所述的方法， 其中步骤 C中形成所述通孔的步 骤包括： 在层间介质层上形成具有多个有序的穿孔的掩膜版； 以掩膜 版为掩膜刻蚀层间介质层， 以在所述层间介质层中形成多个有序的通 孔。
3. 根据权利要求 2所述的方法，其中形成所述掩模版的步骤包括： 在层间介质层上形成金属铝层， 将金属铝层氧化为具有多个穿孔的氧 化铝版模， 以所述氧化铝版模为掩模板。
4. 根据权利要求 2所述的方法，其中形成所述掩膜版的步骤包括： 在所述层间介质层上依次形成第二硬掩膜层和第一硬掩膜层； 通过第 一次掩膜形成图形化的第一硬掩膜层； 通过第二次掩膜及图形化的第 一硬掩膜层形成图形化的第二硬掩膜层， 从而形成具有多个穿孔的掩 膜版。
5. 根据权利要求 2所述的方法，其中形成所述掩膜版的步骤包括： 在所述层间介质层上形成硬掩膜层； 通过掩膜并两次曝光掩膜的方法， 图形化所述硬掩膜层形成具有多个穿孔的掩膜版。
6. 根据权利要求 2所述的方法，其中形成所述掩膜版的步骤包括： 在所述层间介质层上形成硬掩膜层； 在所述硬掩膜层上形^ 隔排列— 的辅助层及其侧墙； 去除辅助层并以侧墙为掩膜图形化硬掩膜层， 以 形成具有多个穿孔的掩膜版。
7. 根据权利要求 1-6 中任一项所述的方法， 其中所述通孔和穿孔 基本为周期排列， 且具有基本相同的形状。
8. 根据权利要求 1-6 中任一项所述的方法， 其中所述通孔和穿孔 的 径为 l-60nm。
9. 根据权利要求 1-6 中任一项所述的方法， 其中所述通孔之间和 穿孔之间的孔间距为 l-60nm。
10. 根据权利要求 1所述的方法， 在步骤 A和 B之间还包括步骤： 在所述源 /漏区上形成金属硅化物层或导电材料接触层。
1 1. 根据权利要求 1 所述的方法， 其中形成所述接触孔的材料包 括： 碳纳米管、 Cu、 Ag、 TiN或 W。
12. 根据权利要求 1所述的方法，其中所述沟槽接触具有一个或多 个沟槽结构。
13. 一种半导体器件， 所述器件包括：
半导体衬底；
形成于半导体衬底上的栅极区， 以及形成于栅极区两侧的半导体 衬底内的源 /漏区， 以及形成于源 /漏区上的层间介质层；
形成于层间介质层内的多个有序的接触孔；
形成于层间介质层内且位于接触孔上的沟槽接触。
14. 根据权利要求 13所述的器件， 其中所述器件还包括形成于所 述源极区和漏极区的半导体衬底上的金属硅化物层或导电材料接触 层。
15. 根据权利要求 13所述的器件， 其中所述接触孔的直径为 1至 60纳米。
16. 根据权利要求 13所述的器件， 其中所述多个接触孔基本为周 期性排列， 且具有大致相同的形状。
17. 根据权利要求 13所述的器件， 其中形成所述接触孔的材料包 括： 碳纳米管、 Cu、 Ag、 丁11^或 \ 。
18. 根据权利要求 13所述的器件， 其中所述沟槽接触具有一个或 多个沟槽结构。
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