WO2011150879A2 - 半导体器件封装方法及其结构 - Google Patents

半导体器件封装方法及其结构 Download PDF

Info

Publication number
WO2011150879A2
WO2011150879A2 PCT/CN2011/076087 CN2011076087W WO2011150879A2 WO 2011150879 A2 WO2011150879 A2 WO 2011150879A2 CN 2011076087 W CN2011076087 W CN 2011076087W WO 2011150879 A2 WO2011150879 A2 WO 2011150879A2
Authority
WO
WIPO (PCT)
Prior art keywords
molding
plastic
molded
mold
bare silicon
Prior art date
Application number
PCT/CN2011/076087
Other languages
English (en)
French (fr)
Other versions
WO2011150879A3 (zh
Inventor
杨雄
Original Assignee
华为终端有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为终端有限公司 filed Critical 华为终端有限公司
Priority to EP11789258.8A priority Critical patent/EP2565913B1/en
Priority to PCT/CN2011/076087 priority patent/WO2011150879A2/zh
Priority to CN2011800007541A priority patent/CN102203927B/zh
Publication of WO2011150879A2 publication Critical patent/WO2011150879A2/zh
Publication of WO2011150879A3 publication Critical patent/WO2011150879A3/zh
Priority to US13/710,764 priority patent/US9082777B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/23—Sheet including cover or casing
    • Y10T428/239—Complete cover or casing

Definitions

  • the present invention relates to the field of plastic packaging technology, and in particular, to a method for molding a device and a package structure thereof. Background technique
  • the current plastic packaging process is widely used in the IC (Integrated Circuit) industry to protect the device in epoxy materials and cure it for reliability and other protection requirements.
  • the prior art adopts a one-shot forming method, and the device is fixed on the first side and the second side of the carrier board to form a plastic part to be molded, and the plastic part to be molded is placed in the cavity of the lower mold, and the second side of the plastic part is to be molded. Supported by the support member, the upper and lower molds are closed, and the first surface is filled with resin through the injection hole on the upper mold. After the resin is filled, the first surface is solidified at one time to complete the first surface injection molding of the plastic molding to be molded. .
  • the inventors have found that at least the following problems exist in the prior art: due to the gravity of the carrier plate and the device or the partial deformation of the carrier plate caused by the deformation of the carrier itself, the first part of the injection molding, the molding to be molded
  • the two sides need to reserve more support positions to facilitate the support of the mold, to avoid local bending deformation of the carrier plate, and more support positions occupy the layout space of the device. Even so, the support surface still has insufficient defects, and the carrier plate is inevitably
  • the possibility of deformation, in order to further prevent deformation, the carrier plate needs to be appropriately increased in thickness. Summary of the invention
  • the object of the embodiments of the present invention is to provide a method for plastically molding a device capable of solving the problem of warpage of a molded article, in view of the above-mentioned drawbacks of the prior art.
  • Another object of embodiments of the present invention is to provide a package structure in which a device is molded.
  • a method for molding a device comprising the steps of: performing a first surface mount technology processing on a plastic part and/or a bare silicon wire;
  • the first surface molding technology and/or the bare silicon wafer to be molded are subjected to a first surface molding operation; the second surface surface mounting technology processing is performed on the first surface plastic molding to be molded and/or Or bare silicon wire bonding; second-side plastic sealing operation for the second surface-mounting technology processing and/or bare silicon wire bonding.
  • Another technical solution of the embodiment of the present invention is: a package structure of a two-sided plastic package, comprising a carrier board, wherein the surface of the carrier board and the lower surface are fixed with devices, and the upper and lower surface devices are plastically sealed In the sealant.
  • the second surface device when the first surface is sealed, the second surface device is not assembled, and the entire surface of the second surface is used as a support surface, and a separate support member is not needed, thereby solving the warpage deformation of the carrier.
  • the problem is that since the warpage factor does not need to be considered, the overall thickness of the carrier can be reduced, and the device can be packaged on both sides, thereby increasing the device layout density.
  • FIG. 2 is a schematic structural view of a single-sided carrier-on-board device according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view of a single-sided carrier plastic package provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a single-sided package provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of performing double-sided encapsulation according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a double-sided package provided by an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of the second surface plastic seal provided by the embodiment of the present invention after being plastically sealed by a dispensing method.
  • FIG. 8 is a schematic structural view showing a surface of a sealant according to an embodiment of the present invention.
  • a method of molding a device includes the following steps:
  • Step 101 First surface SMT (Surface Mounting Technology) processing and/or Die bonding (near silicon wafer bonding): processing the first surface surface technology of the plastic part and/or bare silicon wafer Line
  • Step 102 The first side molding: the first surface molding operation is performed on the first surface surface SMT processing and/or Die bonding;
  • Step 103 The second side of the SMT processing and / or Die bonding (naked silicon wire): To complete the first side of the plastic package The molding part performs SMT processing and/or Die bonding on the second surface;
  • Step 104 The second side molding: performing the second side molding operation on the second surface mount technology processing and/or the bare silicon wafer to be molded.
  • the device molding method provided by the embodiment of the invention, when the first surface molding is performed, the device of the second surface is not assembled, and no support is required when the first surface molding is performed, thereby solving the problem of warpage of the plastic molding to be molded.
  • the warpage factor is not required, the overall thickness of the carrier can be reduced, because there is no need to reserve the support position, and the device can be packaged on both sides, thereby increasing the device layout density.
  • Example 2 Example 2
  • a method of molding a device includes the following steps:
  • Step 101 Referring to FIG. 2, the first side SMT processing: completing single-sided solder paste printing, patching, reflow, etc., so that the device 1 is fixed on the front surface of the carrier 2; or Die bonding;
  • Step 102 Referring to FIG. 3, the first side plastic seal: the single-sided processing of the plastic to be molded is placed in the cavity of the mold 3, the upper and lower molds 3. 1, 3. 2 after the mold is closed, the bottom of the carrier 2 passes The vacuum adsorption hole 6 at the bottom of the lower mold 3. 2 is evacuated, injected through the injection hole 4, and finally solidified, so that the device 1 on the carrier 2 is plastically sealed by the seal 5;
  • Step 103 Referring to FIG. 4, the second surface SMT processing: completing the second surface solder paste printing, patching, reflow, etc., so that the reverse side of the carrier 2 is also fixed with the device 1; or Die bonding;
  • Step 104 Referring to FIG. 5, the second surface molding: placing the plastic molding to be finished in the second surface processing in the cavity of the mold 3, and placing the second surface to be molded under the injection hole 4, the upper and lower molds 3 After the mold is clamped, the bottom of the first side of the plastic mold is vacuumed by the vacuum suction hole 6 at the bottom of the lower mold 3. The flat surface is flattened by the injection hole 4, and the carrier plate 2 is finally solidified.
  • the device 1 on the front and back sides is plastically sealed by a sealant 5.
  • the entire surface of the second surface is used as a support surface, and a separate support member is not needed, thereby solving the problem of warpage deformation of the carrier, since no warpage is required.
  • Embodiment 3 Referring to FIG. 7 , on the basis of Embodiment 2, the second surface plastic seal is changed into a plastic sealing operation by using a dispensing method, and the mold is not used for injection molding, and the mold opening is not required in the operation, and the operation is simple.
  • a package structure of a device is packaged, including a carrier board 2, on which both the upper surface and the lower surface of the carrier board 2 are fixed, and the upper and lower surfaces of the device 1 are molded in the encapsulant 5.
  • the device of the embodiment of the invention has double-sided plastic sealing, so that both sides have the characteristics of dustproof and waterproof, and the internal structure has good confidentiality. Referring to Fig.
  • the upper surface and/or the lower surface of the sealant 5 is stepped, and preferably one of the surfaces of the sealant 5 is stepped.
  • the inner surface of the lower mold can also be formed into a stepped shape corresponding to the first surface, which is beneficial to the first surface.
  • the lower surface is evacuated to keep the plane flat.
  • the device in the embodiment of the present invention may be a main/passive component such as a resistor, a capacitor or/and a bare silicon wafer.
  • the sealant is an epoxy resin.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体器件封装方法包括以下步骤：（a）对塑件进行第一面表面贴装技术加工和/或裸硅片打线；（b）将处理后的塑件进行第一面塑封；（c）对塑件进行第二面表面贴装技术加工和/或裸硅片打线；（d）将处理后的塑件进行第二面塑封。该封装结构包括载板。载板上下表面固定有器件，上下表面的器件均塑封在封胶中。该方法减小了载板翘曲。该结构具有防尘、防水、内部结构保密性好的特点。

Description

半导体器件封装方法及其结构
技术领域
本发明涉及塑料封装技术领域， 特别涉及一种器件塑封的方法及其封装结构。 背景技术
当前塑料封装工艺广泛应用于 IC ( Integrated Circuit， 集成电路） 行业， 将器件保 护在环氧树脂材料中并固化成型， 以达到可靠性及其他防护要求。
现有技术是采用一次成型加工方式， 在载板的第一面和第二面都固定好器件， 形成待 塑封件， 将待塑封件放置在下模具的模腔中， 待塑封件的第二面通过支撑件支撑， 上、 下 模具合模， 通过上模具上的注胶孔给第一面填充树脂， 填充完树脂后， 将第一面一次性固 化成型， 完成待塑封件的第一面注塑。
在实现本发明的过程中， 发明人发现现有技术至少存在以下问题： 由于载板和器件的 重力或载板本身变形导致的载板局部弯曲， 因此在第一面注塑时， 待塑封件第二面需要预 留较多支撑位置， 以便于模具支撑， 避免载板局部弯曲变形， 较多支撑位置占用器件的布 局空间， 即使这样， 支撑面还是存在不够大的缺陷， 载板仍不可避免有变形的可能， 为进 一步防止变形， 载板需要适当增加厚度。 发明内容
本发明实施例的目的是针对上述现有技术的缺陷， 提供一种能够解决待塑封件翘曲问 题的器件塑封的方法。
本发明实施例的另一个目的是提供一种器件塑封的封装结构。
为了实现上述目的本发明采取的技术方案是： 一种器件塑封的方法， 包括以下步骤： 对待塑件进行第一面表面贴装技术加工和 /或裸硅片打线；
将完成第一面表面贴装技术加工和 /或裸硅片打线的待塑封件进行第一面塑封操作； 对完成第一面塑封的待塑封件进行第二面表面贴装技术加工和 /或裸硅片打线； 对完成第二面表面贴装技术加工和 /或裸硅片打线的待塑封件进行第二面塑封操作。 本发明实施例的另一个技术方案是： 一种器件双面塑封的封装结构， 包括载板， 所述 载板上表面和下表面都固定有器件， 所述上、 下表面的器件均塑封在封胶中。 本发明实施例提供的器件塑封方法， 在进行第一面塑封时， 未装配第二面的器件， 以 第二面的整个面为支撑面， 无需单独的支撑件， 从而解决载板翘曲变形问题， 因不需要考 虑翘曲因素， 因此可以降低载板总体厚度， 可以双面布局塑封器件， 从而提高器件布局密 度。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的描述中所需要使用的 附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本 领域普通技术人员来讲， 在不付出创造性劳动性的前提下， 还可以根据这些附图获得其他 的附图。
图 1是本发明实施例提供的工艺流程图；
图 2是本发明实施例提供的单面载板上固器件的结构示意图；
图 3是本发明实施例提供的进行单面载板塑封的结构示意图；
图 4是本发明实施例提供的单面封装后结构示意图；
图 5是本发明实施例提供的进行双面封装的结构示意图；
图 6是本发明实施例提供的双面封装后结构示意图；
图 7是本发明实施例提供的第二面塑封采用点胶方式进行塑封后的结构示意图。
图 8是本发明实施例提供的封胶一表面为阶梯型的结构示意图。
图中： 1器件， 2载板， 3模具， 3. 1上模具， 3. 2下模具， 4注胶孔， 5封胶， 6真空 吸附孔。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本发明实施方式作 进一步地详细描述。
实施例 1
参见图 1， 一种器件塑封的方法， 包括以下步骤：
步骤 101 : 第一面 SMT ( Surface Mounting Technology, 表面贴装技术）加工和 /或 Die bonding (裸硅片打线）： 对待塑件进行第一面表面贴装技术加工和 /或裸硅片打线；
步骤 102: 第一面塑封： 将完成第一面表面 SMT加工和 /或 Die bonding的待塑封件进 行第一面塑封操作；
步骤 103: 第二面 SMT加工和 /或 Die bonding (裸硅片打线）： 对完成第一面塑封的待 塑封件进行第二面表面 SMT加工和 /或 Die bonding;
步骤 104: 第二面塑封： 对完成第二面表面贴装技术加工和 /或裸硅片打线的待塑封件 进行第二面塑封操作。 本发明实施例提供的器件塑封方法， 在进行第一面塑封时， 未装配第二面的器件， 在进 行第一面塑封时无需支撑， 解决了待塑封件翘曲问题。 采用本发明实施例的方法， 因不需 要考虑翘曲因素， 因此可以降低载板总体厚度， 因无需预留支撑位置， 并可以双面布局塑 封器件， 从而提高器件布局密度。 实施例 2
参见图 1， 一种器件塑封的方法， 包括以下步骤：
步骤 101 : 参见图 2， 第一面 SMT加工： 完成单面的锡膏印刷、 贴片、 回流等作业， 使 器件 1固定在载板 2的正面上； 或进行 Die bonding;
步骤 102: 参见图 3， 第一面塑封： 将完成单面加工的待塑封件置于模具 3的模腔中， 上、 下模具 3. 1， 3. 2合模后， 载板 2底部通过下模具 3. 2底部的真空吸附孔 6抽真空， 通 过注胶孔 4注胶， 最后固化成型， 使载板 2上的器件 1被封胶 5塑封；
步骤 103: 参见图 4， 第二面 SMT加工： 完成第二面的锡膏印刷、 贴片、 回流等作业， 使载板 2的反面也固定有器件 1 ; 或进行 Die bonding;
步骤 104: 参见图 5， 第二面塑封： 将完成第二面加工的待塑封件置于模具 3的模腔中， 待塑封的第二面放置在注胶孔 4下方， 上、 下模具 3. 1， 3. 2合模后， 第一面塑封的底部通 过下模具 3. 2底部的真空吸附孔 6抽真空保持平面平整， 通过注胶孔 4注胶后固化成型， 最终使载板 2正反面上的器件 1被封胶 5塑封。
本发明实施例提供的器件塑封方法， 在进行第一面塑封时， 以第二面的整个面为支撑 面， 无需单独的支撑件， 从而解决载板翘曲变形问题， 因不需要考虑翘曲因素， 因此可以 降低载板总体厚度， 可以双面布局塑封器件， 从而提高器件布局密度； 使用塑封模具相对 一次成型方式， 无需支撑， 成本更低。 可以直接采用双面塑封工艺取代传统产品 （如手机 等其他电子产品） 的塑胶或金属外壳。
实施例 3 参见图 7， 本实施例是在实施例 2的基础上， 将第二面塑封改为采用点胶方式进行塑封 操作， 不采用模具注塑， 操作中不需要进行开模， 具有操作简单的优点。 参见图 6， 一种器件塑封的封装结构， 包括载板 2， 载板 2上表面和下表面都固定有器 件 1， 上、 下表面的器件 1均塑封在封胶 5中。 本发明实施例的器件双面塑封， 使双面均有防尘、 防水等特性， 内部构造保密性好。 参见图 8， 封胶 5的上表面或 /和下表面为阶梯型， 优选封胶 5其中一个表面为阶梯型。 当第一面的封胶表面为阶梯型时， 在对第二面进行封胶时， 可以将下模具的内腔表面 也做成与第一面相对应的阶梯型， 这样利于第一面的下表面抽真空保持平面平整。
本发明实施例中的器件可以为电阻、 电容或 /和裸硅片等主 /被动元器件。
本发明实施例中封胶为环氧树脂。
以上所述仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明的精神和原则 之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1、 一种器件塑封的方法， 其特征在于， 包括以下步骤：
对待塑件进行第一面表面贴装技术加工和 /或裸硅片打线；
将完成第一面表面贴装技术加工和 /或裸硅片打线的待塑封件进行第一面塑封操作； 对完成第一面塑封的待塑封件进行第二面表面贴装技术加工和 /或裸硅片打线； 对完成第二面表面贴装技术加工和 /或裸硅片打线的待塑封件进行第二面塑封操作。
2、根据权利要求 1所述的器件塑封的方法， 其特征在于， 所述第一面塑封操作的具体步 骤为：
将完成第一面表面贴装技术加工和 /或裸硅片打线的待塑封件置于下模具的模腔中， 上、 下模具合模；
第二面通过下模具底部的真空吸附孔抽真空， 保持第二面平面平整；
通过上模具的注胶孔给第一面注胶， 最后将第一面固化成型。
3、根据权利要求 1或 2所述的器件塑封的方法， 其特征在于， 所述第二面塑封操作的具 体步骤为：
将完成第二面表面贴装技术加工和 /或裸硅片打线的待塑封件置于下模具的模腔中，待塑 封的第二面放置在上模具的注胶孔下方， 上、 下模具合模；
第一面塑封的底部通过下模具底部的真空吸附孔抽真空， 保持第一面塑封的底部平面平 整；
通过上模具的注胶孔给第二面注胶， 最后将第二面固化成型。
4、 根据权利要求 2所述的器件塑封的方法，其特征在于，所述第二面塑封操作的具体步 骤为： 第二面塑封采用点胶方式进行塑封。
5、 一种使用权利要求 1所述器件塑封的方法制备的器件塑封封装结构， 其特征在于， 包 括载板， 所述载板上表面和下表面都固定有器件， 所述上、 下表面的器件均塑封在封胶中。
6、 根据权利要求 5所述的器件塑封封装结构， 其特征在于， 所述封胶的上表面或 /和下 表面为阶梯型。
7、 根据权利要求 5或 6所述的器件塑封封装结构， 其特征在于， 所述封胶为环氧树脂。
PCT/CN2011/076087 2011-06-22 2011-06-22 半导体器件封装方法及其结构 WO2011150879A2 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP11789258.8A EP2565913B1 (en) 2011-06-22 2011-06-22 Method for encapsulating of a semiconductor
PCT/CN2011/076087 WO2011150879A2 (zh) 2011-06-22 2011-06-22 半导体器件封装方法及其结构
CN2011800007541A CN102203927B (zh) 2011-06-22 2011-06-22 一种器件塑封的方法及其封装结构
US13/710,764 US9082777B2 (en) 2011-06-22 2012-12-11 Method for encapsulating semiconductor and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/076087 WO2011150879A2 (zh) 2011-06-22 2011-06-22 半导体器件封装方法及其结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/710,764 Continuation US9082777B2 (en) 2011-06-22 2012-12-11 Method for encapsulating semiconductor and structure thereof

Publications (2)

Publication Number Publication Date
WO2011150879A2 true WO2011150879A2 (zh) 2011-12-08
WO2011150879A3 WO2011150879A3 (zh) 2012-05-24

Family

ID=44662789

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/076087 WO2011150879A2 (zh) 2011-06-22 2011-06-22 半导体器件封装方法及其结构

Country Status (4)

Country Link
US (1) US9082777B2 (zh)
EP (1) EP2565913B1 (zh)
CN (1) CN102203927B (zh)
WO (1) WO2011150879A2 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102203927B (zh) 2011-06-22 2013-04-24 华为终端有限公司 一种器件塑封的方法及其封装结构
JP6098467B2 (ja) * 2013-10-08 2017-03-22 株式会社デンソー 電子装置の製造方法
US9397051B2 (en) 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US10762412B2 (en) 2018-01-30 2020-09-01 Composecure, Llc DI capacitive embedded metal card
US11618191B2 (en) 2016-07-27 2023-04-04 Composecure, Llc DI metal transaction devices and processes for the manufacture thereof
US10977540B2 (en) 2016-07-27 2021-04-13 Composecure, Llc RFID device
EP3491584B1 (en) * 2016-07-27 2022-07-13 Composecure LLC Overmolded electronic components for transaction cards and methods of making thereof
AU2018330181B2 (en) 2017-09-07 2022-03-31 Composecure, Llc Transaction card with embedded electronic components and process for manufacture
US11151437B2 (en) 2017-09-07 2021-10-19 Composecure, Llc Metal, ceramic, or ceramic-coated transaction card with window or window pattern and optional backlighting
PT3698280T (pt) 2017-10-18 2022-10-26 Composecure Llc Cartão de transação de metal, cerâmica ou revestido a cerâmica com janela ou padrão de janela e opcionalmente retroiluminação
CN108987289A (zh) * 2018-06-22 2018-12-11 江苏长电科技股份有限公司 一种双面塑封锡球制程方法
USD948613S1 (en) 2020-04-27 2022-04-12 Composecure, Llc Layer of a transaction card
CN113078070A (zh) * 2021-03-30 2021-07-06 无锡闻泰信息技术有限公司 器件塑封方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
EP1198005A4 (en) * 1999-03-26 2004-11-24 Hitachi Ltd SEMICONDUCTOR MODULE AND ITS MOUNTING METHOD
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
US6833628B2 (en) * 2002-12-17 2004-12-21 Delphi Technologies, Inc. Mutli-chip module
US20040178514A1 (en) * 2003-03-12 2004-09-16 Lee Sang-Hyeop Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method
DE112004002527T5 (de) * 2004-01-06 2008-03-06 Infineon Technologies Ag Verfahren zum Verkapseln von Schaltkreischips
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
CN1959947A (zh) * 2005-10-31 2007-05-09 南通富士通微电子股份有限公司 集成电路后道封装塑封成型方法
US20080251901A1 (en) * 2006-01-24 2008-10-16 Zigmund Ramirez Camacho Stacked integrated circuit package system
CN100589245C (zh) * 2006-07-20 2010-02-10 日月光封装测试(上海)有限公司 一种多芯片封装结构的封装方法
NL2000488C2 (nl) 2007-02-15 2008-08-18 Fico Bv Werkwijze en inrichting voor het met behulp van onderdruk omhullen van elektronische componenten.
JP2010010644A (ja) * 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
CN101719760B (zh) * 2009-12-04 2012-07-04 武汉盛华微系统技术股份有限公司 环氧树脂模塑封装smt晶体谐振器或振荡器的方法
CN102203927B (zh) * 2011-06-22 2013-04-24 华为终端有限公司 一种器件塑封的方法及其封装结构
US8597979B1 (en) * 2013-01-23 2013-12-03 Lajos Burgyan Panel-level package fabrication of 3D active semiconductor and passive circuit components

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None
See also references of EP2565913A4

Also Published As

Publication number Publication date
EP2565913A4 (en) 2013-07-31
EP2565913B1 (en) 2019-03-20
CN102203927A (zh) 2011-09-28
US9082777B2 (en) 2015-07-14
US20130102113A1 (en) 2013-04-25
EP2565913A2 (en) 2013-03-06
CN102203927B (zh) 2013-04-24
WO2011150879A3 (zh) 2012-05-24

Similar Documents

Publication Publication Date Title
WO2011150879A2 (zh) 半导体器件封装方法及其结构
TWI413195B (zh) 減少模封膠體內氣泡之壓縮模封方法與裝置
JP6598642B2 (ja) 樹脂封止装置及び樹脂封止方法
CN106128965A (zh) 一种无基板封装器件的制作方法
JP6640003B2 (ja) 樹脂封止装置及び樹脂封止方法
KR20110076604A (ko) Ｐｏｐ 패키지 및 그 제조 방법
TW201312711A (zh) 塑封預模內空封裝之結構改良
WO2021129092A1 (zh) 一种系统级封装结构及其封装方法
WO2018113574A1 (zh) 一种贴装预包封金属导通三维封装结构的工艺方法
KR20140067359A (ko) 적층형 반도체 패키지
WO2018113290A1 (zh) 半导体元件以及制造方法
Wang et al. The next generation advanced MEMS& sensor packaging
KR20080074468A (ko) 초음파를 이용한 반도체 칩의 표면실장방법
TW200935527A (en) Chip package apparatus and chip package process
Wang Film assisted technology for the advanced encapsulation of MEMS/sensors and LEDs
CN103354226B (zh) 堆叠封装器件
TW201419466A (zh) 半導體封裝件之製法
CN100463132C (zh) 晶片封装结构及其制造方法
CN110581109A (zh) 一种多芯片嵌入式异构封装结构及其制造方法
TW201630131A (zh) 電路模組封裝結構及其封裝方法
Hamelink Film assisted technology for the advanced encapsulation of MEMS/sensors and LEDs
TWM482842U (zh) 四方形扁平無引腳封裝（ｑｆｎ）之內封外露散熱裝置結構改良
CN202549825U (zh) Qfn封装结构
US20070108626A1 (en) Flip-chip integrated circuit packaging method
CN102738018A (zh) 一种基于框架载体开孔和锡球贴膜的aaqfn产品的二次塑封制作工艺

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180000754.1

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11789258

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011789258

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE