Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/83—FETs having PN junction gate electrodes
  • H10D30/831—Vertical FETs having PN junction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/051—Manufacture or treatment of FETs having PN junction gates
  • H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
  • H10D30/0515—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates of vertical FETs having PN homojunction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/343—Gate regions of field-effect devices having PN junction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide

Definitions

• This application relates generally to semiconductor devices and methods of making the devices and, in particular, to wide-bandgap semiconductor devices such as SiC vertical channel junction field effect transistors with reduced gate-source leakage under reverse bias.
• the use of an angled implantation can still result in heavier doping near the trench bottom and non-uniform doping along the sidewall which reduces device performance.
• the wafer has to be rotated during implantation.
• ion implantation requires multiple implants at different energies. Therefore, a process involving rotation of the wafer and angled implantation can add significantly to the complexity and cost of the manufacturing process.
• semiconductor devices such as vertical JFETs with more uniform and well-controlled channel width.
• a semiconductor device which comprises:
• a channel layer of a semiconductor material of the first conductivity type on an upper surface of the substrate layer comprising a lower surface and one or more raised regions comprising an upper surface and first and second sidewalls, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer, wherein the one or more raised regions comprises an inner portion of a semiconductor material of the first conductivity type and outer portions of a
• semiconductor material of a second conductivity type different than the first conductivity type wherein the outer portions are adjacent to the first and second sidewalls; gate regions of semiconductor material of the second conductivity type in the lower surface of the channel layer adjacent to and contiguous with the outer portions of adjacent raised regions; and
• outer portions of the raised regions are offset from the source layer such that the outer portions of the raised regions do not contact the source layer.
• a method is also provided which comprises:
• the channel layer is on an upper surface of a substrate layer and wherein the channel layer comprises a lower surface and one or more raised regions comprising an upper surface and first and second sidewalls, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate, wherein source regions of a semiconductor material of the first conductivity type are on the upper surfaces of the one or more raised regions, the source regions comprising side surfaces adjacent the first and second sidewalls and an upper surface and an implant mask is on the upper surface of the source regions, wherein the implanted gate regions are formed in the sidewalls and in the lower surface of the channel layer and wherein the implanted gate regions are offset from the upper surface of the raised regions; and
• implanted gate regions on the sidewalls are offset from the source layer such that the implanted gate regions on the sidewalls do not contact the source layer.
• FIG. 1A is a schematic of a vertical junction field effect transistor having sloped sidewalls wherein the n+ source region is offset 0.5 ⁇ or less from the p+ implanted gate region by a n, n-, p- or p region.
• FIG. IB illustrates the conduction band energy as a function of the distance from the source electrode for an SIT device and a power VJFET device.
• FIG. 1C is a schematic illustrating a method of making VJFET device having sloped sidewalls.
• FIG. ID is a schematic illustrating residual lattice implant damage at the p+/n+ gate-source junction of a device manufactured according to the method depicted in FIG. 1C.
• FIG. IE is a schematic illustrating the minimization of the p+/n+ gate-source junction in a device manufactured according to the method depicted in FIG. 1C using zero degree implantation.
• FIG. 2 is a schematic illustrating a method of making a device as set forth in FIG. 1 A using a conformal mask layer.
• FIG. 3 A illustrates the doping profile for a device having a p+/n+ junction.
• FIG. 3B illustrates the doping profile for a device having a p+/p/n+ junction made using a conformal mask showing reduced electric field and less implant damage.
• FIG. 4 is a schematic illustrating a method of making a device as set forth in FIG. 1 A using a non-conformal mask layer.
• FIG. 5 is a schematic illustrating a method of making a device as set forth in FIG. 1 A using thermal oxidation of the sidewall prior to sidewall implantation.
• FIG. 6 is a schematic illustrating a method of making a device as set forth in FIG. 1 A using an implant mask that overhangs the sidewalls.
• FIG. 7 is a schematic illustrating a method of making a device as set forth in FIG. 1 A using a multilayer implant mask comprising a layer with a high lateral oxidation rate.
• FIG. 8 is a schematic illustrating a method of making a device as set forth in FIG. 1 A by recessing the n+ source layer by oxidation such that the n+ source layer does not contact the p+ implanted regions.
• FIG. 9 is a schematic of a vertical junction field effect transistor having sloped sidewalls wherein the n+ source region is offset from the p+ implanted gate region by an n source region.
• a power junction field effect transistor should remain in the off-state even with very large biases applied to the drain terminal (e.g., 600 V - 10 kV). Accordingly, the power JFET device should have a minimal "drain-induced barrier lowering"
• DIBL DIBL
• the applied drain voltage lowers the energy barrier between the source and drain, thus allowing undesirable leakage current to flow through the device.
• the off-state energy barrier should occur near the source electrode and there should be a "long channel" separating the drain from the source.
• the energy barrier (which is modulated by the bias applied to the p+ gate) should be as far away from the drain as possible to minimize DIBL. This is accomplished by locating the narrowest part of the channel near the source, as is the case with a JFET that has sloped sidewalls as disclosed in U.S. Patent Application No. 12/613,065 or by a device having a non-uniform channel doping profile in which the doping concentration near the source is lower than the rest of the channel as disclosed in U.S. Patent Application Serial No. 12/117,121.
• the p+ gate should necessarily be located in very close proximity to the n+ source.
• the process by which the p+ gate is formed should also be self-aligned to the channel/finger. This is the case when a SiC vertical JFET is formed by etching a finger and implanting the p+ gate using the same mask.
• Other SiC vertical transistors such as the static induction transistor (SIT) are not designed to block large drain voltages, therefore the channel design requirements are less stringent and structures with a large, non-self-aligned separation between n+ source and p+ gate are permitted.
• SIT structures typically have the off-state barrier much closer to the drain terminal and typically have shorter channels (for high frequency operation) than a power JFET as shown in FIG. IB. See, for example, Nishizawa et al., IEEE Trans. Electron Devices, Vol. 4 (2000), pg. 482. Both of these features make the SIT unsuitable for high voltage (e.g., 600 V- 10 kV) applications. By design, a high voltage power JFET will be more effective at blocking high voltages if the off-state barrier is located close to the source terminal as shown in FIG. IB. [0037] As described in U.S. Patent Application No.
• a device having sloped sidewalls can be made by depositing an implant mask layer (e.g., Si0 2 ) on an epitaxially grown SiC layer structure, patterning and etching the implant mask layer and the SiC fingers and implanting the self- aligned p+ gate regions using the implant mask.
• an implant mask layer e.g., Si0 2
• FIG. 1C the implant mask in this process does not completely cover the n+ region.
• Lateral implant straggle may also result in implanted species extending under the implant mask. Both of these effects can result in a p+/n+ gate-source junction.
• a high voltage power JFET should have a long channel with gate-modulated electron barrier close to source. For the implanted gate vertical JFET, this may result in a p+/n+ gate-source junction as shown in FIG. 1C.
• High doping on both sides of the junction results in a narrow depletion region, and hence, a high electric field under reverse voltage bias which results in undesirable gate-source junction leakage.
• a PiN (or p+/n/n+, p+/p/n+) junction would result in a reduced electric field and hence lower leakage. Also because the junction receives a large implant dose during the p+ gate formation, residual lattice damage that is not removed during the implant activation process will may lead to enhanced generation- recombination leakage current during reverse bias. Implant damage at the p+/n+ gate- source junction is shown in FIG. ID.
• multi-slope devices with zero degree implant as described in U.S. Patent Application No. 12/613,065 minimize the p+/n+ junction problem because the implant mask prevents a heavy p+ dose from being implanted at the edge of the n+ region as shown in FIG. IE.
• the use of tilted or angled implantation in devices with vertical sidewalls results in high doping on both sides of the gate-source junction.
• Vertical junction field effect transistors are provided having self-aligned pin (or p+/n/n+, p+/p/n+) gate-source junctions.
• the p+ gate can be self-aligned to within 0.5 ⁇ of the n+ source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias.
• the p+ implant region can be offset from the n+ source either during the implant or afterwards through additional post- implant processing.
• the p+ and n+ regions have peak doping concentration greater than lxlO 19 cm "3 to minimize contact resistance.
• the region between the n+ and p+ regions has lower doping (n-, n, p-, or p) of less than lxlO 19 cm "3 .
• Both the device structure and methods for fabricating the structure are provided.
• the methods are applicable to the manufacture of vertical, single-slope, or multi-slope VJFET fingers with both tilted and zero degree gate implantation.
• the p+ implant region can be offset from n+ source by either a self-aligned mask layer during ion implantation or by the self-aligned recessing of n+ source layer after ion implantation.
• a VJFET device is shown in FIG. 1 A.
• the n+ source is offset from the p+ implanted gate regions by a distance of 0.5 ⁇ or less.
• conformal deposition of an implant blocking layer (e.g., Si0 2 ) over an existing implant mask can be used to offset the implanted gate regions from the source regions.
• an implant blocking layer e.g., Si0 2
• FIG. 2 the n+ source is offset from the p+ implanted gate regions by an n-, n, p- or p region.
• FIG. 3 A illustrates the doping profile for a device having a p+/n+ junction.
• FIG. 3B illustrates the doping profile for a device having a p+/p/n+ junction which was made using a conformal mask as set forth in FIG. 2. As can be seen from FIG. 3B, the device shows reduced electric field and less implant damage than the device of FIG. 3 A. The approximate dopant concentrations are shown in FIGS. 3A and 3B.
• the p+ implanted gate regions can be offset from the n+ source regions using a non-conformal deposition of an implant blocking layer (e.g., Si0 2 ) over existing an implant mask.
• an implant blocking layer e.g., Si0 2
• FIG. 4 the non-conformal mask layer is thicker on the sides of the implant mask than on the sidewalls of the raised channel regions.
• the p+ implanted gate regions can be offset from the n+ source regions by the formation of an implant blocking layer (e.g., Si0 2 ) on the sidewalls using thermal oxidation prior to implantation. This method is illustrated in FIG. 5.
• an implant blocking layer e.g., Si0 2
• the p+ implanted gate regions can be offset from the n+ source regions by using Si0 2 and SiC etch processes to form implant mask that overhangs finger sidewalk This method is illustrated in FIG. 6.
• the p+ implanted gate regions can be offset from the n+ source regions by using a multilayer implant mask consisting of one layer with high lateral oxidation rate at temperatures that will not significantly oxidize SiC (e.g. Si0 2 /Si/Si0 2 , Si0 2 /Ge/Si0 2 , Si0 2 /poly-Si/Si0 2 , SiN/Ge/SiN).
• the multilayer implant mask can be etched and oxidized using conditions which cause negligible oxide growth on SiC (e.g., ⁇ 1000 °C in 0 2 ). This method is illustrated in FIG. 7.
• the p+ implant region can be offset from n+ source by using a self-aligned mask layer during ion implantation.
• the p+ implant region can be offset from n+ source by self-aligned recessing of the n+ source layer after ion implantation.
• the n+ region can be recessed after p+ implantation to remove the overlap of the n+ source and the p+ gate regions.
• the differential oxidation rates of SiC crystal can be used to laterally oxidize the n+ region preferentially to the p+ region.
• the (0001) surface of SiC oxidizes slowly compared to the other surfaces of SiC. Von Munch et al, J. Electrochemical Soc, vol. 122, pg. 642 (1974).
• the oxide thickness on n+ SiC was about twice the thickness on p-type SiC.
• differential oxidation rates may be used to selectively oxidize the n+ source layer thus removing the p+/n+ overlap between gate and source.
• FIG. 8 A method of offsetting the p+ implanted gate regions from the n+ source regions by the self-aligned recessing of the n+ source layer is shown in FIG. 8. As shown in FIG. 8,
• the (0001) surfaces of SiC oxidize slowly whereas the (11 2 0) face oxidizes quickly, especially when the (11 2 0) face is n+.
• the source is recessed from the edges of the sidewalls such that the n+ source regions no longer contact the p+ gate regions.
• FIG. 9 is a schematic depicting an alternative embodiment wherein a non- uniformly doped source layer is used to offset the n+ source from the p+ implanted gate regions.
• the source layer comprises a lower source layer in contact with the p+ gate regions adjacent an upper source layer with a higher doping
• the lower source layer create a pin junction with the gate regions whereas the higher doping in the upper layer can reduce contact resistance.
• the upper source layer can have a doping concentration of lxlO 19 to lxlO 20 cm “3 and the lower source layer can have a doping concentration of less than lxlO 19 cm “3 .
• the thickness of each layer can be 0.25 ⁇ .
• the thickness and doping concentration of the upper and lower source layers can be varied to obtain desirable operating characteristics.

Landscapes

• Junction Field-Effect Transistors (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=45004680

Family Applications (1)

Country Status (6)

Families Citing this family (8)

Family Cites Families (38)

• 2011
  • 2011-05-20 WO PCT/US2011/037275 patent/WO2011149768A2/en not_active Ceased
  • 2011-05-20 CN CN2011800367015A patent/CN103038886A/zh active Pending
  • 2011-05-20 US US13/112,075 patent/US8659057B2/en active Active
  • 2011-05-20 EP EP11787156.6A patent/EP2577735A4/en not_active Withdrawn
  • 2011-05-20 JP JP2013512093A patent/JP2013530527A/ja active Pending
  • 2011-05-24 TW TW100118051A patent/TW201208076A/zh unknown
• 2012
  • 2012-09-13 US US13/613,453 patent/US20130011979A1/en not_active Abandoned

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events