JP5735429B2 - スロープの側壁を有する垂直接合型電界効果トランジスタ、及びその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 238000002513 implantation Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- -1 nitride compounds Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- Computer Hardware Design (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Description
本発明は、米国空軍研究所により与えられた、契約番号第FA8650−06−D−2680号に基づく米国政府の支援で行なわれた。米国政府は、本発明の特定の権利を有する。
(分野)
本出願は、概して半導体デバイス及びそのデバイスの製造方法に関する。
・オフ状態において、ソースからドレインまでの電子フローへのバリアは、ソースに位置され(ドレインから最も遠くに)、該ソースは、DIBLを減少させ、デバイスの阻止電圧を増加させる。
・ドレイン端部の幅広いチャネルは、オン状態中に、チャネルをピンチオフさせる必要があるドレイン電圧を増加させ、これにより、飽和電流を増加させる。そして、
・この構造は、垂直入射のイオン注入に適合し、従って、注入プロセスを単純化させ、コストを減少させる。
米国特許出願公報第2007/0187715号A1「Power Junction Field Effect Power Transistor with Highly Vertical Channel and Uniform Channel Opening」
米国特許第5,903,020号「Silicon Carbide Static Induction Transistor Structure」
Claims (15)
- 半導体デバイスであって、該デバイスは、
第1導電型の半導体材質の基板と、
前記基板の上部表面の上のチャネル層を備え、前記チャネル層は2又はそれより多い隆起領域を備え、前記各隆起領域は上部表面と該上部表面に向かってテーパー状になっている第1及び第2側壁を備え、前記チャネル層の表面に隣接する第1側壁及び第2側壁は前記基板の上部表面に対する垂直線から少なくとも5°の角度を形成し、前記各隆起領域の上部表面に隣接する第1側壁及び第2側壁は前記基板の上部表面に対する垂直線から5°より小さい角度を形成し、
前記各隆起領域は、第1導電型の半導体材質の内側部位と、前記第1導電型とは異なる第2導電型の半導体材質の外側部位を備え、前記外側部位は前記第1及び第2側壁の下にあり、
前記デバイスはさらに、
前記チャネル層表面の下であって前記隆起領域の前記外側部位に接触する、前記第2導電型の半導体材質のゲート領域を備え、
前記デバイスはさらに、
前記各隆起領域の前記上部表面上に前記第1導電型の半導体材質のソース層を備えることを特徴とする、前記半導体デバイス。 - 前記第1及び第2側壁は2重のスロープの側壁であることを特徴とする、請求項1記載の半導体デバイス。
- 前記各隆起領域の上部表面に隣接する前記第1及び第2側壁は、前記基板の前記上部表面に対する垂直線から、2°より小さい角度を形成することを特徴とする、請求項1記載の半導体デバイス。
- 前記チャネル層表面に隣接する前記第1及び第2側壁は、該上部表面に向かってテーパー状になっていて、 前記基板に近接する前記ゲート領域の各下方表面と、前記各隆起領域の前記上部表面との間の距離の少なくとも半分について、前記基板の前記上部表面に対する垂直線から少なくとも5°の角度を形成することを特徴とする、請求項1記載の半導体デバイス。
- 前記基板に近接する前記チャネル層の表面と、前記隆起表面の前記上部表面との間の垂直の距離は、0.5から5μmであり、前記チャネル層の内側部位は、1×1016から1×1018cm−3のドーピング濃度を有することを特徴とする、請求項1記載の半導体デバイス。
- 前記基板は100から500μmの厚さを有し、1×1019から5×1019cm−3までのドーピング濃度を有すること、
前記ソース層は、0.1から1.0μmの厚さを有し、1×1019から1×1020cm−3までのドーピング濃度を有すること、及び
前記隆起領域の前記外側部位と前記ゲート領域のそれぞれは、5×1018から1×1020cm−3のドーピング濃度を有すること、
のうちの少なくとも一つを備えることを特徴とする、請求項1記載の半導体デバイス。 - 前記基板と前記チャネル層との間に前記第1導電型の半導体材質のドリフト層をさらに備え、
前記ドリフト層は、5から15μmまでの厚さを有し、4×1015から2×1016cm−3のドーピング濃度を有することを特徴とする、請求項1記載の半導体デバイス。 - 前記基板と前記チャネル層との間のバッファ層をさらに備え、前記バッファ層は、0.1から1μmの厚さを有し、5×1017から5×1018cm−3のドーピング濃度を
有することを特徴とする、請求項1記載の半導体デバイス。 - 前記基板と前記ドリフト層との間に、バッファ層をさらに備えることを特徴とする、請求項6記載の半導体デバイス。
- 前記半導体材質は、SiCであることを特徴とする、請求項1記載の半導体デバイス。
- 前記デバイスは、接合型電界効果トランジスタ(JFET)であって、前記チャネル層の前記下部表面上の第1ゲートコンタクトと、前記ソース層のソースコンタクトと、前記チャネル層に対向する前記基板上のドレインコンタクトを更に備えることを特徴とする、請求項1記載の半導体デバイス。
- 半導体デバイスの製造方法であって、第1導電型とは異なる第2導電型の半導体材質の注入されたゲート領域を形成するために、第1導電型の半導体材質のチャネル層へイオンを注入する工程を備え、前記チャネル層は基板上にあり、前記チャネル層は2又はそれより多い隆起領域を備え、前記各隆起領域は上部表面と該上部表面に向かってテーパー状になっている第1及び第2側壁を備え、前記チャネル層の表面に隣接する第1側壁及び第2側壁は前記基板の上部表面に対する垂直線から少なくとも5°の角度を形成し、前記各隆起領域の上部表面に隣接する第1側壁及び第2側壁は前記基板の上部表面に対する垂直線から5°より小さい角度を形成し、前記注入されたゲート領域は、該側壁及び前記チャネル層表面の下で形成され、
方法はさらに、
前記隆起領域の前記上部表面上に前記第1導電型の半導体材質のソース層を形成する工程を備えることを特徴とする、前記方法。 - 前記イオンが、前記基板の前記上部表面に対する垂直線から、+/−2°の角度でチャ
ネル層へと注入されることを特徴とする、請求項12記載の方法。 - 前記第1及び第2側壁は2重のスロープの側壁であることを特徴とする、請求項12記載の方法。
- 前記各隆起領域の上部表面に隣接する前記第1及び第2側壁は、前記基板の前記上部表面に対する垂直線から、2°より小さい角度で形成されることを特徴とする、請求項12記載の方法。
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US11143708P | 2008-11-05 | 2008-11-05 | |
US61/111,437 | 2008-11-05 | ||
PCT/US2009/063391 WO2010054073A2 (en) | 2008-11-05 | 2009-11-05 | Vertical junction field effect transistors having sloped sidewalls and methods of making |
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JP2012508455A JP2012508455A (ja) | 2012-04-05 |
JP2012508455A5 JP2012508455A5 (ja) | 2012-11-22 |
JP5735429B2 true JP5735429B2 (ja) | 2015-06-17 |
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US (3) | US8058655B2 (ja) |
EP (1) | EP2345082A4 (ja) |
JP (1) | JP5735429B2 (ja) |
KR (1) | KR20110099006A (ja) |
CN (1) | CN102239563B (ja) |
AU (1) | AU2009313533A1 (ja) |
CA (1) | CA2740223A1 (ja) |
NZ (1) | NZ592399A (ja) |
WO (1) | WO2010054073A2 (ja) |
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CN102239563B (zh) | 2013-08-14 |
CA2740223A1 (en) | 2010-05-14 |
US20110020991A1 (en) | 2011-01-27 |
JP2012508455A (ja) | 2012-04-05 |
WO2010054073A3 (en) | 2010-07-15 |
NZ592399A (en) | 2013-12-20 |
KR20110099006A (ko) | 2011-09-05 |
EP2345082A2 (en) | 2011-07-20 |
US8513675B2 (en) | 2013-08-20 |
CN102239563A (zh) | 2011-11-09 |
WO2010054073A2 (en) | 2010-05-14 |
EP2345082A4 (en) | 2013-07-31 |
US8058655B2 (en) | 2011-11-15 |
AU2009313533A1 (en) | 2010-05-14 |
US20100148186A1 (en) | 2010-06-17 |
US20120223340A1 (en) | 2012-09-06 |
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