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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
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  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02455—Group 13/15 materials
  • H01L21/02458—Nitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
  • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/82—Heterojunctions
  • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

• the present invention relates to GaN MOSFETs and, more particularly, to an enhancement-mode GaN MOSFET with low leakage current and improved reliability.
• GaN MOSFETS are well known in the art, and are of utilized in high power, high frequency, and high temperature applications.
• GaN MOSFETS are typically based on the formation of a heterojunction between a GaN region, typically known as the channel layer, and an overlying AIGaN region, typically known as a barrier layer.
• the GaN channel layer and the AIGaN barrier layer have different band gaps that induce the formation of a two-dimensional electron gas (2DEG) that lies at the junction between the GaN channel layer and the AIGaN barrier layer and extends down into the GaN channel layer.
• 2DEG two-dimensional electron gas
• the 2DEG which functions as the "channel" of the transistor, produces a high concentration of electrons which causes a conventionally-formed GaN MOSFET to function as a depletion-mode device (nominally on when zero volts are applied to the gate of the device, and the source and drain regions of the device are differently biased).
• depletion-mode GaN MOSFETs Although there are applications for depletion-mode GaN MOSFETs, the nominally on state of a depletion-mode transistor requires the use of a control circuit during start up to ensure that source-to-drain conduction within the transistor does not begin prematurely.
• an enhancement-mode GaN MOSFET (nominally off when zero volts are applied to the gate of the device, and the source and drain regions of the device are differently biased) does not require a control circuit because the transistor is nominally off at start up when zero volts are placed on the gate.
• the AIGaN barrier layer must be made thin enough (e.g., a few nm thick) so that when zero volts are applied to the gate of the device, (and the source and drain regions of the device are differently biased) substantially no electrons are present in the 2DEG region, and when a voltage that exceeds a threshold voltage is applied to the gate of the device, (and the source and drain regions of the device are differently biased), electrons accumulate in the 2DEG region and flow from the source region to the drain region.
• AIGaN barrier layer One problem with reducing the thickness of the AIGaN barrier layer is that high levels of leakage current can pass through the AIGaN barrier layer to the gate, which is conventionally implemented as a Schottky contact.
• One solution to this problem is to add a gate insulation layer that lies between the AIGaN barrier layer and the gate.
• deposited oxides include AI 2 O 3 , HfO 2 , MgO, Gd 2 O 3 , Ga 2 O 3 , ScO 2 , and SiO 2 .
• SiO 2 has a bandgap Eg of 9 eV and a AEc to AIGaN that can be as high as 2.5 eV, thereby leading to the lowest leakage current and a threshold voltage as high as 2.5 volts.
• SiO 2 /Si3N 4 gate insulation layer on an AIGaN (or InAIGaN) barrier layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO 2 portion of the SiO 2 /Si3N 4 gate insulation layer significantly reduces the leakage current.
• the GaN MOSFET of the present invention includes a barrier layer, which includes AIGaN.
• the GaN MOSFET of the present invention also includes a layer of S13N4 that touches the barrier layer.
• the GaN MOSFET of the present invention further includes a layer of SiO 2 that touches and lies over the layer of Si3N 4 , and a metal gate that touches the layer of SiO 2 , and lies above the layer of Si0 2 , and the layer of S13N4.
• a method of forming the GaN MOSFET of the present invention includes forming a barrier layer, which includes AIGaN. The method also includes forming a layer of S13N4 that touches the barrier layer. The method further includes forming a layer of SiO 2 that touches the layer of Si 3 N 4 , and forming a metal gate that touches and lies over the layer of SiO 2 .
• FIGS. 1-4 are a series of cross-sectional views illustrating an example of a method of forming an enhancement-mode GaN MOSFET 100 in accordance with the present invention.
• FIGS. 5-9 are a series of cross-sectional views illustrating an example of a method of forming an enhancement-mode GaN MOSFET 500 in accordance with an alternate embodiment of the present invention.
• FIG. 10 is a band diagram illustrating the leakage current in accordance with the present invention.
• the present invention forms a SiO 2 /Si3N 4 gate insulation layer on an AIGaN barrier layer (or optional InAIGaN barrier layer) which significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer. Reducing the density of interface states significantly reduces the number of trapping sites which, in turn, improves the long-term reliability on the GaN devices.
• FIGS. 1-4 show a series of cross-sectional views that illustrate an example of a method of forming an enhancement-mode GaN MOSFET 100 in accordance with the present invention.
• the method of the present invention utilizes a conventionally-formed semiconductor substrate 110.
• Substrate 110 can be
• Epitaxial layer 112 which is formed in a metal organic chemical vapor deposition (MOCVD) reactor using a conventional process, includes an undoped AIGaN buffer layer 114, an undoped GaN channel layer 116, and an undoped or n-doped AIGaN barrier layer 118 (or optionally an undoped or n-doped InAIGaN barrier layer 118).
• the AIGaN buffer layer 114 includes a number of undoped AIGaN layers with different aluminum compositions that are used to mitigate stress.
• a S13N4 layer 120 is epitaxially grown on the AIGaN barrier layer 118 directly in the same MOCVD reactor as the AIGaN barrier layer 118 using SiH 4 and NH 3 .
• the S13N4 layer 120 is epitaxially grown after the AIGaN layer 118 is grown without removing the structure with the AIGaN layer 118 from the MOCVD reactor.
• the S13N4 layer 120 is preferably grown to have a thickness of approximately 10-lOOnm, with the specific thickness being application dependent. SiN and AIGaN share the same anion and, as a result, produce a transition layer between the S13N4 layer 120 and the AIGaN barrier layer 118 that has a very low density of interfacial states, e.g., expected to be less than lxlO n /cm 2 .
• part of the S13N4 layer 120 is oxidized in a steam/wet rapid thermal oxidation process to form a SiO 2 layer 122 that lies on the remaining S13N4 layer 120.
• the combination of the S13N4 and SiO 2 layers form a gate insulation layer 124 of the transistor which has, for example, a S13N4 layer that is 64 A thick and a SiO 2 layer that is 128A thick.
• the oxidation of the S13N4 layer 120 produces a transition layer between the S13N4 layer 120 and the SiO 2 layer 122 that also has a very low density of interfacial states.
• the method completes the formation of GaN MOSFET 100 by forming a metal gate region 130, a metal source region 132, and a metal drain region 134 in a conventional fashion, e.g., using titanium aluminum contacts, followed by the conventional formation of an overlying passivation layer.
• the metal gate region 130 is formed to touch the SiO 2 layer 122 of gate insulation layer 124.
• the metal source 132 and metal drain regions 134 are formed to make an ohmic contact with the GaN channel layer 116 and the AIGaN barrier layer 118.
• the AIGaN of the barrier layer and the GaN of the channel layer have different band gaps, and are conventionally formed to induce a two- dimensional electron gas (2DEG) that lies at the junction between the AIGaN barrier layer and the GaN channel layer and extends down into the GaN channel layer.
• 2DEG two- dimensional electron gas
• the 2DEG which functions as the "channel" of the transistor, produces a high concentration of electrons which causes a conventionally- formed GaN MOSFET to be a depletion mode device (nominally on when zero volts are applied to the gate of the device and the source and drain regions are differently biased).
• the AIGaN barrier layer 118 must be made thin enough (e.g., a few nm thick) so that when zero volts are applied to the metal gate region 130 (and the metal source region 132 and the metal drain region 134 are differently biased) substantially no electrons are present in the 2DEG region, and when a voltage that exceeds a threshold voltage is a applied to the metal gate region 130 (and the metal source region 132 and the metal drain region 134 are differently biased), electrons accumulate in the 2DEG region and flow from the metal source region 132 to the metal drain region 134.
• FIGS. 5-9 show a series of cross-sectional views that illustrate an example of a method of forming an enhancement-mode GaN MOSFET 500 in accordance with an alternate embodiment of the present invention.
• the alternate method of the present invention also utilizes a conventionally-formed semiconductor substrate 510.
• substrate 510 can also be implemented as an insulating substrate or with a highly resistive material such as silicon (e.g., ⁇ 111>), sapphire, or silicon carbide.
• the alternate method of the present invention begins by forming an epitaxial layer 512 on substrate 510 in the same manner that epitaxial layer 112 was formed (in a MOCVD reactor using a conventional process).
• epitaxial layer 512 includes an undoped AIGaN buffer layer 514, an undoped GaN channel layer 516, and an undoped or n-doped AIGaN barrier layer 518 (or optionally an undoped or n-doped InAIGaN barrier layer 518).
• the AIGaN buffer layer 514 includes a number of undoped AIGaN layers with different aluminum compositions that are used to mitigate stress.
• the AIGaN barrier layer 518 is formed to have a conventional (depletion-mode) thickness and, as a result, induces the formation of a two-dimensional electron gas (2DEG) that lies at the junction between the AIGaN barrier layer 518 and the GaN channel layer 516 and extends down into the GaN channel layer 516.
• 2DEG two-dimensional electron gas
• a mask 520 such as a layer of SiO 2 , is formed and patterned on the top surface of the AIGaN barrier layer 518.
• the regions exposed by the mask 520 are dry etched.
• the dry etch can stop above, at, or below a lowest level of the 2DEG that lies at the top surface of GaN channel layer 516. (FIG. 6 illustrates the dry etch stopping just below the lowest level of the 2DEG.)
• the dry etch produces an intermediate MOSFET structure 522 that has an exposed region 524.
• intermediate MOSFET structure 522 is next baked in H 2 and NH3 in the MOCVD reactor to repair damage to the lattice that was caused by the dry etch.
• the intermediate MOSFET structure 522 is baked after the dry etch without removing the intermediate MOSFET structure 522 from the MOCVD reactor.
• a thin undoped or n-doped AIGaN barrier film 526 (or optionally a thin undoped or n-doped InAIGaN barrier film 526) is epitaxially grown on the exposed region 524.
• a top surface of the thin AIGaN barrier film 526 can lie above, at, or below a lowest level of the 2DEG.
• FIG. 7 illustrates the top surface of the AIGaN barrier film 526 lying at the lowest level of the 2DEG.
• the thin AIGaN barrier film 526 has a thickness that is less than a largest thickness of the AIGaN barrier layer 518.
• a S13N4 layer 530 is epitaxially grown on the thin AIGaN barrier film 526 directly in the same MOCVD reactor as the thin AIGaN barrier film 526 using SiH 4 and NH3.
• the S13N4 layer 530 is epitaxially grown after the thin AIGaN barrier film 526 is grown without removing the structure with the thin AIGaN barrier film 526 from the MOCVD reactor. (As shown in FIG. 7, the S13N4 layer 530 also grows on the side walls of the AIGaN barrier layer 518 and on the S1O2 mask 520.)
• the S13N4 layer 530 is preferably grown to have a thickness of approximately
• the process produces a transition layer between the Si 3 N 4 layer 530 and the thin AIGaN barrier film 526 that has a very low density of interfacial states, e.g., expected to be less than lxlO n /cm 2 .
• S13N4 layer 530 is oxidized in a steam/wet rapid thermal oxidation process to form a S1O2 region 532 that lies on a S13N4 region 534 which, in turn, lies over the thin AIGaN barrier film 526.
• the AIGaN barrier layer 518 lies laterally adjacent to the S13N4 region 534. (The oxidation process also oxidizes the S13N4 layer 530 that lies over the S1O2 mask 520, thereby increasing the thickness of the S1O2 mask 520.)
• the combination of the S13N4 region 534 and the S1O2 region 532 forms a gate insulation layer 536 that lies over the thin AIGaN film 526 which has, for example, a S13N4 region that is 64 A thick and a S1O2 region that is 128A thick.
• the oxidation of the S13N4 layer 530 produces a transition layer between the S13N4 region 534 and the S1O2 region 532 that also has a very low density of interfacial states.
• the method completes the formation of GaN MOSFET 500 by forming a metal gate region 540, a metal source region 542, and a metal drain region 544 in a conventional fashion, e.g., using titanium aluminum contacts, followed by the conventional formation of an overlying passivation layer.
• the metal gate region 540 is formed to touch S1O2 region 532 of gate insulation layer 536.
• the metal source 542 and metal drain regions 544 are formed to make an ohmic contact with the GaN channel layer 516 and the AIGaN barrier layer 518.
• GaN MOSFET 500 shown in FIG. 9 is formed as an enhancement-mode device (nominally off when zero volts are applied to the metal gate region 540 and the metal source region 542 and the metal drain region 544 are differently biased) by forming the AIGaN barrier film 526 to be thin enough (e.g., a few nm thick) so that when zero volts are applied to the metal gate region 540 (and the metal source region 542 and the metal drain region 544 are differently biased) substantially no electrons accumulate directly under the gate insulation layer 536 and the metal gate region 540, and when a voltage that exceeds a threshold voltage is a applied to metal gate region 540 (and the metal source region 542 and the metal drain region 544 are differently biased), electrons accumulate directly under the gate insulation layer 536 and the metal gate region 540 and flow from the metal source region 542 to the metal drain region 544.
• the AIGaN barrier film 526 to be thin enough (e.g., a few nm thick) so that when zero volts
• the S13N4 portion of the SiO 2 /Si3N 4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the AIGaN barrier layer (or optional InAIGaN barrier layer). Significantly reducing the number of sites where electrons can be trapped significantly improves the long-term reliability of the GaN devices.
• a further advantage of the present invention is that by utilizing SiO 2 as the capping layer of the SiO 2 /Si3N 4 gate insulation layer, the present invention has the lowest leakage current and a threshold voltage as high as 2.5 volts (i.e., SiO 2 has a bandgap Eg of 9 eV and a AEc to AIGaN that can be as high as 2.5 eV).
• FIG. 10 shows a band diagram that illustrates the leakage current in
• the band lineup shows that there is limited tunneling in the gate oxide due to the low density of interface states and the wide band gap of SiO 2 .
• the effective AEc from SiO 2 to AIGaN is greater than 2 eV with a threshold voltage Vt that is greater than 2V.

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• 2010
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