WO2011030753A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- WO2011030753A1 WO2011030753A1 PCT/JP2010/065312 JP2010065312W WO2011030753A1 WO 2011030753 A1 WO2011030753 A1 WO 2011030753A1 JP 2010065312 W JP2010065312 W JP 2010065312W WO 2011030753 A1 WO2011030753 A1 WO 2011030753A1
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- electrode pad
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 239000007788 liquid Substances 0.000 claims abstract description 69
- 229910000679 solder Inorganic materials 0.000 claims description 71
- 238000005530 etching Methods 0.000 claims description 7
- 230000001965 increasing effect Effects 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 232
- 230000007246 mechanism Effects 0.000 description 45
- 230000008569 process Effects 0.000 description 42
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 11
- 229910052709 silver Inorganic materials 0.000 description 11
- 239000004332 silver Substances 0.000 description 11
- 238000003475 lamination Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 238000007641 inkjet printing Methods 0.000 description 6
- 239000010419 fine particle Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000007711 solidification Methods 0.000 description 5
- 230000008023 solidification Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000003028 elevating effect Effects 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005660 hydrophilic surface Effects 0.000 description 2
- 230000002209 hydrophobic effect Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 150000003961 organosilicon compounds Chemical class 0.000 description 2
- 239000011941 photocatalyst Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000002940 repellent Effects 0.000 description 2
- 239000005871 repellent Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
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- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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Definitions
- the present invention relates to a method for manufacturing a semiconductor device formed by stacking substrates.
- electrode pads provided on the substrate on which these semiconductor devices are formed and electrically connected to the outside of the substrate have also been miniaturized. Yes.
- a laminated structure must be formed after alignment with high accuracy.
- Patent Document 1 discloses a method of adjusting and then applying and curing an adhesive.
- Patent Document 1 in addition to the detection mechanism such as a CCD camera for optically detecting the pattern of the substrate, a mechanism for confirming the position by seeing through the substrate with X-rays or the like is required. There is a case.
- the force for pressing the substrate against the other substrate can be controlled independently. May require a mechanism to do this.
- the present invention has been made in view of the above points, and in the case of stacking and forming a substrate by electrically connecting electrode pads that have been miniaturized or narrowed in pitch, without using a complicated mechanism.
- a method for manufacturing a semiconductor device in which a substrate can be aligned with high accuracy and an electrode pad can be reliably electrically connected.
- a method of manufacturing a semiconductor device is provided in which a semiconductor device is formed by stacking and electrically connecting the first electrode pad and the corresponding second electrode pad.
- the manufacturing method includes a first hydrophilization process for hydrophilizing the first electrode pad, and a liquid supply for supplying a liquid to the surface of the first substrate on which the first electrode pad is formed.
- a placing step of placing the In the placing step, the first electrode pad and the second electrode pad are aligned by the liquid.
- a first substrate on which a first electrode pad is formed and a second substrate on which a second electrode pad corresponding to the first electrode pad is formed A method of manufacturing a semiconductor device is provided in which a semiconductor device is formed by stacking and electrically connecting the first electrode pad and the corresponding second electrode pad.
- a first wettability treatment step for increasing solder wettability in the first electrode pad and molten solder on the surface of the first substrate on which the first electrode pad is formed are supplied.
- a surface on which the first electrode pad is formed and a surface on which the second electrode pad is formed are opposed to each other on the first substrate supplied with the molten solder.
- a placing step of placing the second substrate In the placing step, the first electrode pad and the second electrode pad are aligned by the molten solder.
- FIG. 1A is a flowchart for explaining the procedure of each step of the stacking step of the semiconductor device manufacturing method according to the first embodiment, following FIG. 1A; It is sectional drawing which shows typically the structure of the board
- FIG. 2B is a cross-sectional view schematically showing the structure of the substrate in each step of the stacking step of the manufacturing method of the semiconductor device according to the first embodiment, following FIG. FIG.
- FIG. 2B is a cross-sectional view schematically showing the structure of the substrate in each step of the stacking step of the manufacturing method of the semiconductor device according to the first embodiment, following FIG. 2B.
- It is a longitudinal cross-sectional view which shows the example of the coating device by an inkjet printing technique.
- FIG. 8A is a flowchart for explaining the procedure of each step of the stacking step of the manufacturing method of the semiconductor device according to the second embodiment, following FIG. 8A. It is sectional drawing which shows typically the structure of the board
- FIG. 10A is a flowchart for explaining the procedure of each step of the stacking step of the manufacturing method of the semiconductor device according to the third embodiment, following FIG. 10A. It is sectional drawing which shows typically the structure of the board
- FIG. 11B is a cross-sectional view schematically showing the structure of the substrate in each step of the stacking step of the semiconductor device manufacturing method according to the third embodiment, following FIG. 11A.
- the substrate in a method of manufacturing a semiconductor device formed by stacking substrates by electrically connecting electrode pads, even when the electrode pads are miniaturized and narrow pitched, complicated Without using a mechanism, the substrate can be aligned with high accuracy, and the electrode pads can be reliably connected electrically.
- FIGS. 1A to 2B are flowcharts for explaining the procedure of each step of the stacking step of the semiconductor device manufacturing method according to the present embodiment.
- 2A to 2C are cross-sectional views schematically showing the structure of the substrate in each step of the stacking step of the semiconductor device manufacturing method according to the present embodiment.
- the semiconductor device manufacturing method includes a first hydrophilization treatment step (S11), a liquid supply step (S12), and a second hydrophilization treatment step (S13). ), A placing step (S14 to S17), a solder supplying step (S18 and S19), and a solder solidifying step (S20).
- the placement process includes a substrate inversion step (S14), a placement step (S15), an alignment step (S16), and an etching step (S17).
- the solder supply process includes a supply step (S18) and a pouring step (S19).
- a first hydrophilization treatment step is performed (S11 in FIG. 1A).
- the first wafer 11 on which the first electrode pads 12 are formed is prepared, and the first electrode pads 12 are hydrophilized.
- the surface of the first electrode pad 12 that has been hydrophilized is denoted by reference numeral 13. Further, the first electrode pad 12 is electrically connected to an electronic circuit (not shown) formed inside the first wafer 11.
- the hydrophilization treatment in the first hydrophilization treatment step can be performed by, for example, selectively irradiating UV light with a mask after applying a photocatalyst.
- the hydrophobization process is performed on the region other than the first electrode pad 12 in the first wafer 11.
- the hydrophobic treatment can be performed, for example, by selectively applying a water repellent material such as an organosilicon compound.
- a water repellent material such as an organosilicon compound.
- the first dummy pad 14 that is not electrically wired may be formed on the first wafer 11 separately from the first electrode pad 12.
- the first dummy pad 14 is not electrically connected to an electronic circuit (not shown) formed inside the first wafer 11, and aligns the first wafer 11 and the second wafer 21.
- the first dummy pad 14 may be formed on the peripheral edge of the first wafer 11.
- the hydrophilic treatment is also performed on the first dummy pad 14.
- a liquid supply step for supplying a liquid onto the first wafer 11 in which the surface 13 of the first electrode pad 12 is hydrophilized and the other regions are hydrophobized is performed (S12 in FIG. 1A). ).
- the liquid is supplied to the surface 13 of the first electrode pad 12 subjected to the hydrophilic treatment.
- the liquid may be supplied by various supply methods such as coating, spraying, and discharging.
- the supplied liquid remains in the form of droplets 15 on and around the surface 13 of the hydrophilized first electrode pad 12.
- the supplied liquid (droplet 15) may have conductivity.
- a hydrophilic liquid such as a liquid containing moisture can be used.
- the liquid is also supplied to the first dummy pad 14, and the droplet 15 is formed.
- a second hydrophilization treatment step is performed (S13 in FIG. 1A).
- a second wafer 21 on which the second electrode pads 22 are formed is prepared, and the second electrode pads 22 are hydrophilized.
- the surface of the second electrode pad 22 that has been hydrophilized is denoted by reference numeral 23.
- the second electrode pad 22 is electrically connected to an electronic circuit (not shown) formed inside the second wafer 21.
- the second electrode pads 22 are formed in advance so as to be connected to the corresponding first electrode pads 12 of the first wafer 11.
- the hydrophilic treatment in the second hydrophilization treatment step can also be performed by, for example, selectively irradiating UV light with a mask after applying a photocatalyst.
- the hydrophobization process is performed on the region other than the second electrode pad 22 in the second wafer 22.
- the hydrophobic treatment can be performed, for example, by selectively applying a water repellent material such as an organosilicon compound.
- a water repellent material such as an organosilicon compound.
- a second dummy pad 24 that is not electrically wired is formed on the second wafer 21 on the surface on which the second electrode pad 22 is formed. Also good.
- the second dummy pad 24 is not electrically connected to an electronic circuit or the like (not shown) formed inside the second wafer 21 and aligns the first wafer 11 and the second wafer 21.
- the second dummy pad 24 may be formed on the peripheral edge of the second wafer 21.
- a third electrode pad 25 is formed on the second wafer 21 on the surface opposite to the surface on which the second electrode pad 22 is formed. Further, a through hole 26 is formed to penetrate from the surface on which the second electrode pad 22 is formed to the surface on which the third electrode pad 25 is formed. The through hole 26 has an opening in contact with the second electrode pad 22 on the surface of the second wafer 21 where the second electrode pad 22 is formed.
- a placement process is performed (S14 to S17).
- the substrate inversion step (S14 in FIG. 1A) for inverting the second wafer 21 up and down, and the second wafer 21 on the supplied first wafer 11 coated with the droplet 15 are performed.
- a placing step (S15 in FIG. 1A) for placing the wafer 21, an alignment step (S16 in FIG. 2A) for aligning the first electrode pad 12 and the second electrode pad 22, and an etching step (FIG. 2A S17) is performed in this order.
- the second wafer 21 in which the second electrode pad 22 is hydrophilized is turned upside down. A method for inverting the second wafer 21 will be described later.
- the first wafer 11 is first coated with the droplet 15 applied on and around the surface 13 of the first electrode pad 12.
- the second wafer 21 is placed on the first wafer 11 with the surface of the second wafer 21 on which the second electrode pad 22 is formed facing the surface on which the electrode pad 12 is formed. .
- the placing step may be performed in a reduced pressure state.
- the steps from the placement step to the supply step described later are performed in a reduced pressure state.
- the second wafer 21 may be placed on the first wafer 11 after alignment by an alignment apparatus having an alignment mechanism or the like.
- a method of placing the second wafer 21 on the first wafer 11 using an apparatus having an alignment mechanism will be described later. However, as will be described later, it is not necessary to perform alignment by the alignment device with high accuracy. Further, when placing, it is not necessary to apply force to the second wafer 21 in any direction.
- the second wafer 21 placed on the first wafer 11 is self-aligned with the first wafer 11 in the alignment step (S16 in FIG. 2A). Aligned. This is in contact with the hydrophilic surface 13 of the first electrode pad 12 of the first wafer 11 and the corresponding hydrophilic surface 23 of the second electrode pad 22 of the second wafer 21. This is because the second wafer 21 can move so as to align with the first wafer 11 as the droplet 15 moves, and the droplet 15 itself does not spread, and the surface 13 and This is because it stays between 23. Therefore, in terms of utilizing surface tension, it is more preferable to use a hydrophilic liquid and make the first electrode pad 12 and the second electrode pad 22 hydrophilic.
- the first dummy pad 14 is formed on the first wafer 11 and the second dummy pad 24 is formed on the second wafer 21, the first dummy pad 14 and the second dummy pad are formed. Even the pad 24 is aligned through the droplet 15.
- the surface of the first electrode pad 12 is caused to drop by the droplet 15 as shown in FIG. 2B (g).
- FIG. 2B (g) shows an example in which the surface 13 of the first electrode pad 12 and the surface 23 of the second electrode pad 22 are etched.
- the droplet 15 preferably has a property of etching an oxide film or the like formed on the surface of the electrode pad. By etching the oxide film or the like formed on the surface of the electrode pad, the electrical connection between the first electrode pad 12 and the second electrode pad 22 using solder described later can be made more reliable. .
- solder supply process is performed in which molten solder is poured from the through holes 26 formed in the second wafer 21 (S18 and S19).
- the solder supply process includes a supply step (S18) and a pouring step (S19).
- the periphery of the second wafer 21 and the first wafer 11 on which the second wafer 21 is placed is maintained at a reduced pressure.
- the placement step (S15) and the alignment step (S16) are performed in a container that is connected to an exhaust device (not shown) and can be depressurized, and the container is depressurized after the alignment step. Good.
- a heating device such as a heater is provided on the wafer mounting portion in the container.
- the first wafer 11 and the second wafer 21 are thereby heated to a predetermined temperature.
- the droplet 15 between the first electrode pad 12 and the second electrode pad 22 evaporates.
- the melted solder 27 is supplied to the surface opposite to the surface facing the first wafer 11 in the second wafer 21. Specifically, molten solder 27 is supplied in the vicinity of the opening of the through hole 26 on the opposite surface.
- wettability treatment is performed to increase wettability of the surface of the third electrode pad 25 formed on the surface opposite to the surface on which the second electrode pad 22 of the second wafer 21 is formed with respect to the solder 27.
- the supplied solder 27 may be selectively gathered in the vicinity of the through hole 26.
- 2A and 2B show an example in which the second electrode pad 22 or the third electrode pad 25 is formed on one side of the through hole 26, but both sides of the through hole 26 are sandwiched.
- the second electrode pad 22 or the third electrode pad 25 may be formed so as to surround the through hole 26.
- the molten solder 27 is poured into the through hole 26. Specifically, the surrounding environment of the first wafer 11 and the second wafer 21 is returned to atmospheric pressure. At this time, since the through hole 26 is closed by the solder 27 and the inside of the through hole 26 is decompressed, the molten solder 27 is drawn into the through hole 26 as shown in FIG. 2C (j).
- the supply step (S18) may be performed under a normal pressure environment.
- the droplet 15 may be evaporated by heating the first wafer 11 and the second wafer 21, and the solder 27 may be pushed into the through hole 26 by applying pressure.
- solder solidification step is performed in which the solder 27 is solidified and the first electrode pad 12 and the second electrode pad 22 are solder-bonded (S20).
- the solder 27 is solidified by intentionally or naturally cooling the first wafer 11 and the second wafer 21, and as shown in FIG. 2C (k), the first electrode pads 12 are solidified. Between the first electrode pad 12 and the second electrode pad 22, and the second electrode pad 22 is electrically connected.
- FIG. 3 is a longitudinal cross-sectional view showing an example of a coating apparatus using an ink jet printing technique
- FIG. 4 is a plan view of the coating apparatus of FIG.
- the coating apparatus includes a main body 30, a liquid supply nozzle 40, and a control unit 42.
- the main body 30 has a housing 31, and a base 33 is provided on the bottom surface of the body 30, which can move from one end side to the other end side in the housing 31 via a rail 32 extending in the Y direction.
- a substrate holding part 35 configured to be movable via a rail 34 extending in the X direction is provided on the upper surface of the base 33, and the substrate holding part 35 sucks the wafer W from the back side at the upper end thereof. Configured to hold horizontally. That is, the wafer W held by the substrate holding unit 35 can freely change the position in the X and Y directions in the housing 31 via the base 33 and the substrate holding unit 35 by the action of the drive mechanism 36.
- a mask support member 37 is provided which is integrally formed with the substrate holding portion 35 and is raised to a level slightly higher than the surface of the wafer W, and is supplied to the upper end from above.
- a removable mask member 38 having a large opening at the center is supported so as to prevent the liquid to be deposited from adhering to a region other than the region where the liquid on the wafer W is to be supplied.
- an opening (not shown) for carrying in and out the wafer W is formed on the side of the mask support member 37 and the housing 31, for example.
- the liquid supply nozzle 40 is held by a linear slide mechanism 41 that is installed above the housing 31 along the X direction. Further, the tip of the liquid supply nozzle 40 protrudes to the inside of the casing 31 through a slit 31 a (FIG. 4) formed in the ceiling portion of the casing 31.
- the liquid supply nozzle 40 can move in the X direction by driving the linear slide mechanism 41 under the control of the control unit 42.
- a liquid supply unit 43 connected to a liquid supply source (not shown) is connected to the liquid supply nozzle 40. For example, based on a control signal transmitted from the control unit 42 to the liquid supply unit 43, the liquid supply unit 43 supplies the liquid.
- a liquid is supplied to the nozzle 40.
- the liquid supply nozzle 40 is provided with a nozzle portion 44 composed of an inkjet nozzle having a large number of ejection holes.
- the large number of discharge holes of the nozzle portion 44 can be arranged in a square shape or in a line so as to discharge liquid at, for example, 180 dpi for each electrode pad among the large number of electrode pads formed on the surface of the wafer W.
- the ejection hole may be an ink jet nozzle called a shear type that is provided with piezo elements facing each other so as to sandwich the liquid flow path, and deforms both piezo elements to push the coating liquid outward.
- the liquid supply nozzle 40 is moved by the linear slide mechanism 41 while discharging the liquid from the liquid supply nozzle 40. Reciprocate in the X direction. In this case, when the liquid supply nozzle 40 turns back at one end of the first wafer 11, the substrate 33 is moved by a small amount, for example, 0.5 mm in the Y direction. Thus, the liquid supply nozzle 40 can be supplied to the entire surface of the first wafer 11 by scanning the liquid supply nozzle 40 above the first wafer 11 while discharging the liquid from the liquid supply nozzle 40.
- FIG. 5 is a plan view showing an example of the wafer reversing device
- FIG. 6 is a side view of the wafer reversing device of FIG.
- the wafer reversing device 50 includes a wafer relay unit 51 that transfers the wafer W to and from a main wafer transfer mechanism (not shown), an elevating mechanism 52 that moves the wafer relay unit 51 up and down, and a wafer W held by the wafer relay unit 51. And a wafer reversing mechanism 53 that reverses the wafer W gripped by rotation and transfers the wafer W to the wafer relay unit 51 again.
- the wafer relay portion 51 has a substantially H-shaped support base 54 and two support arms 55a and 55b for holding the support base 54 horizontally.
- Legs 54b (FIG. 6) are disposed at the four ends of the support base 54, and a holding member 54a having a substantially L-shaped cross-sectional shape is disposed on the leg 54b.
- the holding member 54a supports the peripheral portion of the wafer W with a substantially L-shaped horizontal portion, and guides the wafer W supported by the horizontal portion with a substantially L-shaped vertical portion.
- the base ends of the support arms 55a and 55b are fixed to a block 58 attached to the elevating mechanism 52.
- the block 58 is connected to an air cylinder 59 that expands and contracts in the Z direction. According to the raising / lowering operation of (FIG. 5), it raises / lowers along the guide 60 provided extending in the Z direction.
- the elevating mechanism 52 is not limited to the structure using the air cylinder 59, but by transmitting the rotation using a rotation driving mechanism such as a motor to the block 58 using a pulley and a belt. Alternatively, a mechanism for performing an up / down operation may be used.
- the wafer reversing mechanism 53 has a set of two wafer gripping arms 61a and 61b that are openable and closable in the X direction, and a bottom portion of the wafer reversing mechanism 53 has a V groove along the side surface of the wafer W.
- a gripping member 61c is provided. When the wafer gripping arms 61a and 61b are closed, the peripheral edge of the wafer W is sandwiched between the V grooves. Further, the wafer gripping arms 61 a and 61 b are coupled to the rotation driving mechanism 62 at the base end portion, and can be rotated around the horizontal axis by the rotation driving mechanism 62.
- FIG. 6 shows the wafer gripping arms 61a and 61b rotated about 90 ° by the rotation driving mechanism 62 and the wafer 21 gripped by the wafer gripping arms 61a and 61b and maintained vertically by dotted lines.
- the substrate reversing step (S14 in FIG. 1) is performed as follows. First, the second wafer 21 that has undergone the second hydrophilization treatment step (S13 in FIG. 1) is transferred from the wafer transfer mechanism (not shown) with the surface on which the second electrode pads 22 are formed facing upward. It is conveyed to the reversing unit 50 and received by the support member 54a on the support base 54. Then, the support base 54 that supports the second wafer 21 is raised to the position of the wafer gripping arms 61a and 61b that are horizontally held in the open leg state by the lifting mechanism 52, and the wafer gripping arms 61a and 61b are closed. The second wafer 21 is held by the wafer holding arms 61a and 61b.
- the support base 54 and the holding member 54 a are retracted downward so as not to interfere with the wafer gripping arms 61 a and 61 b that reverse the second wafer 21, and the second wafer 21 is rotated 180 ° by the rotation drive mechanism 62.
- the support base 54 is raised again to the position of the wafer gripping arms 61a and 61b, and the wafer gripping arms 61a and 61b are opened to receive the second wafer 21 by the support base 54.
- the support base 54 that supports the second wafer 21 is lowered, and the second wafer 21 is transferred from the support base 54 to the wafer transport mechanism.
- a placement step (S15 in FIG. 1) is performed on the second wafer 21 that is turned upside down.
- FIG. 7 is a side view showing an example of an alignment apparatus.
- the alignment device 70 is provided in the wafer transfer arm 71 that transfers the second wafer 21 that is turned upside down, the chamber 72 into which the wafer transfer arm 71 can enter, and the alignment of the first wafer 11.
- a mounting table 78 on which the first wafer 11 and the second wafer 21 which are disposed below and aligned with each other are mounted.
- the chamber 72 has a substantially cylindrical shape having an open lower end and a closed upper end, and can be moved up and down by a lifting mechanism (not shown).
- a loading / unloading port 72a for loading / unloading the second wafer 21 via the wafer transfer arm 71 is formed, and the loading / unloading port 72a can be opened and closed by a gate valve 72b.
- the gate valve 72 b hermetically closes the loading / unloading port 72 a after the wafer transfer arm 71 is loaded into the chamber 72.
- a gas supply port 72c connected to a gas supply pipe (not shown) and a gas discharge port 72d connected to a gas discharge pipe (not shown) are formed on the upper wall of the chamber 72.
- a flange 72e is provided at the lower end of the chamber 72.
- the flange 72 e has an opening having an inner diameter larger than the outer diameters of the first wafer 11 and the second wafer 21.
- a position adjustment mechanism 73 for aligning the first wafer 11 is provided on the flange 72e of the chamber 72.
- An O-ring 75 is disposed on the upper surface of the position adjustment mechanism 73. That is, the position adjustment mechanism 73 supports the surface of the second wafer 21 carried in by the wafer transfer arm 71 via the O-ring 75. Further, when the wafer transfer arm 71 holding the second wafer 21 enters the chamber 72 and the second wafer 21 is placed on the O-ring 75, the O-ring 75 causes the second wafer 21 to move.
- a sealed space 76 is formed above.
- the position adjustment mechanism 73 includes guide rails in the X direction, the Y direction, and the ⁇ direction, and piezoelectric elements provided corresponding to the guide rails. Thereby, the position adjusting mechanism 73 can move in a small distance in the X direction, the Y direction, and the ⁇ direction, and can adjust the position of the first wafer 11. Specifically, as will be described later, the position adjustment mechanism 73 is operated by the position adjustment mechanism 73 based on the amount of displacement between the first wafer 11 and the second wafer 21 obtained by the alignment mechanisms 79a and 79b. 11, so that the first electrode pad 12 of the first wafer 11 and the second electrode pad 22 of the second wafer 21 are aligned.
- the second wafer 21 and the first wafer 11 are aligned by the following procedure, and the second wafer 21 is placed on the first wafer 11. Placed.
- the first wafer 11 that has undergone the liquid supply step (S ⁇ b> 12) is held by the position adjustment mechanism 73 of the chamber 72.
- the second wafer 21 turned upside down by the substrate turning step (S ⁇ b> 14) is held (vacuum suction) by the wafer transfer arm 71 and carried into the chamber 72. While observing with the alignment mechanisms 79a and 79b, the wafer transfer arm 71 stops at a position where the center of the second wafer 21 and the center of the first wafer 11 substantially coincide.
- the wafer transfer arm 71 descends, stops at a position where the second wafer 21 comes into contact with the O-ring 75, stops vacuum suction of the wafer transfer arm 71, and places the second wafer 21 on the O-ring 75. Place. Thereafter, the gate valve 72b is closed.
- the alignment mechanism 79 a and 79 b align the first dummy pad 14 for alignment provided on the peripheral edge of the first wafer 11 and the alignment for positioning provided on the peripheral edge of the second wafer 21.
- the second dummy pad 24 is imaged, the X coordinate and the Y coordinate are read, and the amount of positional deviation between them is obtained.
- the position adjustment mechanism 73 finely adjusts the position of the first wafer 11, and the X direction, the Y direction, and / or the ⁇ direction between the first wafer 11 and the second wafer 21. Perform alignment.
- the chamber 72 is lowered toward the mounting table 78, and the first wafer 11 is brought into contact with the stage 78 a of the mounting table 78.
- the stage 72 is further lowered, and the second wafer 21 is placed on the first wafer 11.
- the flange 72e of the chamber 72 is in contact with the mounting table 78 via an O-ring (not shown) or the like, so that the inside of the chamber 72 can be kept airtight.
- an exhaust device not shown
- the subsequent solder supply process S18 and S19
- the alignment device described above is merely an example, and other various alignment devices can be used.
- the second wafer 21 when the second wafer 21 is placed on the first wafer 11, the surface 13 of the first electrode pad 12 of the first wafer 11 that has been hydrophilized is treated. Since the droplets 15 are concentrated between the surface 13 and the corresponding surface 23 of the second electrode pad 22 of the second wafer 21 that has been hydrophilized, the second wafer 21 becomes the second wafer. 11 is aligned in a self-aligned manner. Therefore, although the alignment apparatus 70 for coarse alignment is required, a highly accurate alignment mechanism can be dispensed with. Further, even when the electrode pads are miniaturized and the pitch is reduced, the wafer can be aligned with high accuracy, and the two wafers can be electrically connected reliably.
- the first electrode pad 12 and the second electrode pad 22 are electrically connected by pouring solder into the through hole 26 formed in the second wafer 21.
- the material poured into the through hole 26 may be any material having fluidity and conductivity, and is not limited to solder.
- solder ink, paste liquid, or the like (metal fine particle mixture) in which gold, silver, platinum or other conductive metal fine particles are dispersed in a solvent is used. Also good.
- FIGS. 8A to 9B a method for manufacturing a semiconductor device according to the second embodiment will be described.
- 8A and 8B are flowcharts for explaining the procedure of each step of the stacking step of the semiconductor device manufacturing method according to this embodiment.
- 9A and 9B are cross-sectional views schematically showing the structure of the substrate in each step of the stacking step of the semiconductor device manufacturing method according to the present embodiment.
- the members or parts described above may be denoted by the same reference numerals and description thereof may be omitted.
- a metal fine particle mixed solution in which silver fine particles are dispersed in a predetermined solvent is used as a liquid, and solder is not used.
- the semiconductor device manufacturing method includes a first hydrophilization treatment step (S21 in FIG. 8A), a liquid supply step (S22), and a second hydrophilization treatment.
- a process (S23), a mounting process (S24 to S27), and a liquid evaporation process (S28) are included.
- the placement process includes a substrate inversion step (S24), a placement step (S25), an alignment step (S26 in FIG. 8B), and an etching step (S27).
- the steps from the first hydrophilization treatment step to the placement step (S21 to S27) are the same as those in the first embodiment except that silver ink is used as the liquid to be the droplet 15. This is the same as the corresponding steps from the first hydrophilization treatment step to the placement step (S11 to S17).
- FIG. 9A (a) to FIG. 9B (h) schematically shows the first wafer 11 and the second wafer 21a after going through the steps S21 to S27.
- the second wafer 21a since no solder is used, as shown in FIG. 9A (c), the second wafer 21a may not have a through hole.
- the solder supply process (S18) and the solder solidification process (S19) in the first embodiment are not performed, and the liquid evaporation process (S28) is performed.
- the silver ink is solidified by evaporating the solvent of the silver ink, and the first electrode pad 12 and the second electrode pad 22 Are electrically connected.
- the metal fine particle mixed liquid instead of silver ink, a liquid in which gold, silver, platinum or other conductive metal is dispersed in a liquid such as ink or paste can be used.
- the second wafer 21 when the second wafer 21 is placed on the first wafer 11, the surface 13 of the first electrode pad 12 of the first wafer 11 subjected to the hydrophilic treatment, As the silver ink droplet 15 moves so as to come into contact with the corresponding surface 23 of the second electrode 21 that has been hydrophilized, the second wafer 21 is moved to the first wafer 21. This is because the silver ink droplets 15 themselves remain between the surfaces 13 and 23 due to surface tension without spreading.
- first electrode pad 12 and the second electrode pad 22 can be electrically connected by drying the silver ink having conductivity, so that the number of steps can be reduced.
- 10A and 10B are flowcharts for explaining the procedure of each step of the stacking step of the semiconductor device manufacturing method according to the present embodiment.
- 11A and 11B are cross-sectional views schematically showing the structure of the substrate in each step of the stacking step of the semiconductor device manufacturing method according to the present embodiment.
- a molten solder is used instead of a liquid, and alignment is performed using the molten solder.
- the semiconductor device manufacturing method includes a first wettability treatment step (S31 in FIG. 10A), a solder supply step (S32), and a second wettability treatment.
- a process (S33), a mounting process (S34 in FIG. 10A to S36 in FIG. 10B), and a solder solidifying process (S37 in FIG. 10B) are included.
- the placement process includes a substrate inversion step (S34), a placement step (S35), and an alignment step (S36).
- the first wettability treatment step is a step of preparing the first wafer 11b on which the first electrode pads 12 are formed and performing the wettability treatment of the first electrode pads 12.
- FIG. 11A (a) schematically shows the first wafer 11b after the wettability treatment process.
- the surface of the first electrode pad 12 that has undergone the wettability treatment is denoted by reference numeral 13.
- the wettability treatment can be performed, for example, by applying a flux.
- the wettability treatment of the first electrode pad 12 may be performed, and the coating treatment for covering the region other than the first electrode pad 12 with, for example, a solder resist may be performed.
- a solder resist for example, a solder resist
- the first dummy pads 14 may be formed on the first wafer 11b, as in the first embodiment.
- the solder supplying step is a step of supplying the melted solder 27 onto the first wafer 11b in which the surface 13 of the first electrode pad 12 has been wetted and the region other than the surface 13 is covered with the solder resist 18. .
- molten solder 27 is supplied onto and around the surface 13 of the first electrode pad 12 that has been wettable.
- the molten solder 27 is not particularly limited, and can be supplied by various supply methods such as coating, spraying, and discharging the molten solder.
- the first wafer 11b is held at a temperature at which the solder does not melt, a solder ball is placed on or in the vicinity of the surface 13 of the wettable first electrode pad 12, and then the temperature of the first wafer 11b. May be raised to melt the solder. As shown in FIG. 11A (b), since the surface 13 of the first electrode pad 12 is wetted and the region other than the surface 13 is covered with the solder resist 18, the supplied molten solder 27 is It remains on and around the surface 13 of the first electrode pad 12.
- the molten solder 27 is also applied to the first dummy pad 14.
- the second wettability treatment step is a step of preparing the second wafer 21b and performing the wettability treatment of the second electrode pad 22 formed on the second wafer 21b.
- FIG. 11A (c) schematically shows the second wafer 21b after the process of S33.
- the surface of the second electrode pad 22 that has undergone the wettability treatment is denoted by reference numeral 23.
- the wettability treatment is not particularly limited, and can be performed by applying a flux as in the first wettability treatment step.
- the wettability treatment of the second electrode pad 22 and the coating treatment of covering the region other than the surface 23 with, for example, the solder resist 28 may be performed. is there.
- a second dummy pad 24 may be formed on the second wafer 21b.
- a placement process is performed (S34 to S36).
- the placing step the second wafer 21b is turned upside down, the second wafer 21b is placed on the first wafer 11b supplied with the melted solder 27, and the first electrode pad 12 and the second wafer 21b are placed.
- This is a step of performing alignment with the electrode pad 22.
- the placement process includes a substrate inversion step (S34), a placement step (S35), and an alignment step (S36). Further, the substrate after each step from the substrate inversion step to the alignment step is schematically shown in FIGS. 11A (d) to 11B (f).
- a substrate inversion step is performed (S34). As shown in FIG. 11A (d), the substrate inversion step can be performed in the same manner as the substrate inversion step (S14) in the first embodiment.
- a placement step is performed (S35).
- the melted solder 27 is applied on and around the surface of the first electrode pad 12 that has been subjected to the wettability treatment.
- the surface on which the first electrode pad 12 is formed and the surface on which the second electrode pad 22 of the second wafer 21b is formed face each other, and the second wafer 21b is placed on the first wafer 11. .
- the second wafer 21b may be mounted on the first wafer 11b after performing alignment by an alignment apparatus having an alignment mechanism or the like as in S15 in the first embodiment. It is the same.
- the second wafer 21b placed on the first wafer 11b in the placing step (S35) is aligned with the first wafer 11b in a self-aligned manner as shown in FIG. 11B (f). Is performed (S36). This contacts the surface 13 having wettability of the first electrode pad 12 of the first wafer 11b and the corresponding surface 23 having wettability of the second electrode pad 22 of the second wafer 21b. This is because the second wafer 21b can move so as to align with the first wafer 11b as it moves, and the molten solder 27 remains between the surface 13 and the surface 23 due to surface tension. is there.
- the first dummy pad 14 and the second dummy pad 24 are both melted.
- the solder 27 is aligned.
- the solder solidification step is a step of solidifying the solder 27 and soldering the first electrode pad 12 and the second electrode pad 22 together.
- FIG. 11B (g) schematically shows the first wafer 11 and the second wafer 21 after undergoing the solder solidification step.
- the second wafer 21 and the first wafer 11 on which the second wafer 21 is placed are intentionally or naturally cooled.
- the solder 27 is solidified, and the first electrode pad 12 and the second electrode pad 22 are electrically connected.
- liquid is not used, but alignment is performed using melted solder, and then the solder is solidified to align the first electrode pad and the second electrode pad. Can be connected.
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Abstract
Description
始めに、図1Aから図2Bを参照し、第1の実施形態に係る半導体装置の製造方法について説明する。
図1Aおよび1Bは、本実施形態に係る半導体装置の製造方法の積層工程の各工程の手順を説明するためのフローチャートである。図2Aから2Cは、本実施形態に係る半導体装置の製造方法の積層工程の各工程における基板の構造を模式的に示す断面図である。
なお、減圧状態では、図2C(i)に示すように、第1の電極パッド12と第2の電極パッド22との間の液滴15が蒸発する。
次に、供給ステップにおいて、図2B(h)に示すように、第2のウェハ21における第1のウェハ11に対向する面の反対面に溶融したハンダ27を供給する。具体的には、その反対面における貫通孔26の開口部の近傍に溶融したハンダ27が供給される。
この後、上下反転された第2のウェハ21に対し、載置ステップ(図1のS15)が行われる。
まず、液体供給工程(S12)を経た第1のウェハ11が、チャンバー72の位置調整機構73に保持される。次に、基板反転ステップ(S14)により上下反転された第2のウェハ21が、ウェハ搬送アーム71により保持(真空吸着)され、チャンバー72内に搬入される。アライメント機構79a、79bにより観察しながら、第2のウェハ21の中心と第1のウェハ11の中心とがほぼ一致する位置でウェハ搬送アーム71が停止する。次いで、ウェハ搬送アーム71は、下降し、第2のウェハ21がOリング75と接触した位置で停止し、ウェハ搬送アーム71の真空吸着を停止して第2のウェハ21をOリング75上に載置する。その後、ゲートバルブ72bが閉じる。
なお、上述した位置合わせ装置は、一例にすぎず、他の種々の位置合わせ装置を用いることができる。
次に、図8Aから図9Bを参照し、第2の実施形態に係る半導体装置の製造方法について説明する。
図8Aおよび8Bは、本実施形態に係る半導体装置の製造方法の積層工程の各工程の手順を説明するためのフローチャートである。図9Aおよび図9Bは、本実施形態に係る半導体装置の製造方法の積層工程の各工程における基板の構造を模式的に示す断面図である。なお、以下、先に説明した部材または部品には同一の符号を付し、説明を省略する場合がある。
次に、図10Aから図11Bを参照し、第3の実施形態に係る半導体装置の製造方法について説明する。
Claims (10)
- 第1の電極パッドが形成される第1の基板と、前記第1の電極パッドに対応する第2の電極パッドが形成される第2の基板とを積層し、前記第1の電極パッドと、対応する前記第2の電極パッドとを電気的に接続することにより半導体装置を形成する、半導体装置の製造方法であって、
前記第1の電極パッドを親水化処理する第1の親水化処理工程と、
前記第1の基板上の前記第1の電極パッドの形成された面に液体を供給する液体供給工程と、
前記液体の供給された前記第1の基板上に、前記第1の電極パッドの形成された面と前記第2の電極パッドの形成された面とを対向させて前記第2の基板を載置し、親水化処理された前記第1の電極パッドに集まる前記液体により前記第1の電極パッドと前記第2の電極パッドとを位置合わせする載置工程と、
を含む、半導体装置の製造方法。 - 前記第2の電極パッドを親水化処理する第2の親水化処理工程を更に含む、請求項1に記載の半導体装置の製造方法。
- 前記液体は、前記第1の電極パッド表面または前記第2の電極パッド表面に形成された酸化膜をエッチングする性質を有する、請求項1に記載の半導体装置の製造方法。
- 前記液体が導電性を有する、請求項1に記載の半導体装置の製造方法。
- 前記第2の基板は、前記第2の電極パッドと接する開口部を有する貫通孔を有し、
前記載置工程の後、前記第2の基板における前記第1の基板と対向する面の反対面に開口する前記貫通孔の開口部から、溶融したハンダを流し込むことにより、前記第1の電極パッドと前記第2の電極パッドとを電気的に接続するハンダ供給工程を更に含む、請求項1に記載の半導体装置の製造方法。 - 前記載置工程は減圧状態で行われ、
前記ハンダ供給工程において、ハンダを供給した後に、大気圧に戻す、請求項5に記載の半導体装置の製造方法。 - 前記第1の基板には、第1のダミーパッドが形成されており、
前記第2の基板には、前記第1のダミーパッドに対応する第2のダミーパッドが形成されており、
前記第1の親水化処理工程において、前記第1のダミーパッドを親水化処理する、請求項1に記載の半導体装置の製造方法。 - 前記第2のダミーパッドを親水化処理する、請求項7に記載の半導体装置の製造方法。
- 第1の電極パッドが形成される第1の基板と、前記第1の電極パッドに対応する第2の電極パッドが形成される第2の基板とを積層し、前記第1の電極パッドと、対応する前記第2の電極パッドとを電気的に接続することにより半導体装置を形成する、半導体装置の製造方法であって、
前記第1の電極パッドにおけるハンダ濡れ性を高める第1の濡れ性処理工程と、
前記第1の基板上の前記第1の電極パッドの形成された面に溶融したハンダを供給するハンダ供給工程と、
前記溶融したハンダの供給された前記第1の基板上に、前記第1の電極パッドの形成された面と前記第2の電極パッドの形成された面とを対向させて前記第2の基板を載置し、濡れ性処理された前記第1の電極パッドに集まる前記溶融したハンダにより前記第1の電極パッドと前記第2の電極パッドとを位置合わせする載置工程と、
を含む、半導体装置の製造方法。 - 前記第2の電極パッドにおけるハンダ濡れ性を高める第2の濡れ性処理工程を更に含む、請求項9に記載の半導体装置の製造方法。
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US13/394,573 US8664106B2 (en) | 2009-09-09 | 2010-09-07 | Method of manufacturing semiconductor device |
KR1020127008986A KR101330969B1 (ko) | 2009-09-09 | 2010-09-07 | 반도체 장치의 제조 방법 |
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JP2004320064A (ja) * | 2001-11-15 | 2004-11-11 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2003332371A (ja) * | 2002-05-17 | 2003-11-21 | Tamura Seisakusho Co Ltd | 突起電極の形成方法およびその装置 |
JP2004327908A (ja) * | 2003-04-28 | 2004-11-18 | Ricoh Co Ltd | 光学電子デバイスの接合方法及び接合構造 |
JP2005203468A (ja) * | 2004-01-14 | 2005-07-28 | Seiko Epson Corp | 電子装置及びその製造方法 |
JP2005203664A (ja) * | 2004-01-19 | 2005-07-28 | Citizen Watch Co Ltd | 半導体装置の実装方法 |
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CN102842514A (zh) * | 2011-06-20 | 2012-12-26 | 华新丽华股份有限公司 | 芯片结合方法 |
Also Published As
Publication number | Publication date |
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JP2011060941A (ja) | 2011-03-24 |
KR20120062888A (ko) | 2012-06-14 |
US8664106B2 (en) | 2014-03-04 |
KR101330969B1 (ko) | 2013-11-18 |
JP5307669B2 (ja) | 2013-10-02 |
CN102498565A (zh) | 2012-06-13 |
TWI437649B (zh) | 2014-05-11 |
CN102498565B (zh) | 2014-10-22 |
TW201131674A (en) | 2011-09-16 |
US20120171858A1 (en) | 2012-07-05 |
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