Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
  • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2668—Details of algorithms
  • H04L27/2673—Details of algorithms characterised by synchronisation parameters
  • H04L27/2676—Blind, i.e. without using known symbols
  • H04L27/2678—Blind, i.e. without using known symbols using cyclostationarities, e.g. cyclic prefix or postfix
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2668—Details of algorithms
  • H04L27/2673—Details of algorithms characterised by synchronisation parameters
  • H04L27/2676—Blind, i.e. without using known symbols
  • H04L27/2679—Decision-aided
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W56/00—Synchronisation arrangements
  • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
  • H04W56/005—Synchronisation arrangements compensating for timing error of reception due to propagation delay compensating for timing error by adjustment in the receiver
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04H—BROADCAST COMMUNICATION
  • H04H40/00—Arrangements specially adapted for receiving broadcast information
  • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
  • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
  • H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
  • H04L2027/0044—Control loops for carrier regulation
  • H04L2027/0053—Closed loops
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
  • H04L2027/0044—Control loops for carrier regulation
  • H04L2027/0063—Elements of loops
  • H04L2027/0067—Phase error detectors
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
  • H04L7/042—Detectors therefor, e.g. correlators, state machines
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/10—Arrangements for initial synchronisation

Definitions

• the present principles relate to course and fine symbol timing recovery in phase shift keying systems.
• Digital Video Broadcasting has developed digital broadcast standards for cable, terrestrial, and satellite transmission.
• the second generation digital video broadcasting standard for satellite transmission (DVB-S2) was developed and ratified by the European Telecommunications Standards Institute (ETSI).
• ETSI European Telecommunications Standards Institute
• One of the features of the DVB-S2 standard is backward compatibility with DVB-S, the first generation standard.
• DVB-S2 also includes adaptive coding and modulation, LDPC coding together with an outer BCH code, and several coding rates.
• a further feature is four modulation modes (QPSK, 8PSK, 16APSK, and 32APSK). Future generations of the standards may expand on these key features and it is conceivable that backward compatibility will be included.
• STR symbol timing recovery
• RRC root raised cosine
• FTN Nyquist
• Timing offset estimation in satellite receivers is normally done using a classical feedback solution with a Gardner timing error detector.
• Other solutions are also known, like the M&M detector, which uses post matched filtered samples and which is more insensitive to ISI but is very sensitive to phase and frequency errors.
• the coarse outer timing estimate can be followed by a loop for fine symbol timing recovery, or each idea may be implemented separately.
• the fine symbol timing recovery methods discussed herein help the symbol timing recovery system lock under adverse conditions, including low SNR, low excess bandwidth, and when faster than Nyquist (FTN) signaling is used.
• FTN Nyquist
• Each of these approaches creates difficulties in symbol timing recovery.
• Symbol timing recovery was one of the limiting factors to the adoption of these capacity enhancing options.
• a novel symbol timing offset detection algorithm for data aided symbol timing estimation is used for coarse timing adjustment using pre-known data embedded in a DVB-S2 like transmission stream, which may be followed by a method for fine symbol timing recovery.
• Feed forward recovery relies on pre-known data symbols (e.g. pilot or sync symbols) embedded in the data stream.
• the coarse timing recovery idea described herein solves the problem of a traditional feeback approach of decreasing acquisition range as ISI gets more severe. It achieves this solution by using a data aided feed forward symbol timing recovery method that provides a very robust recovery method, even to the ISI caused by FTN transmission.
• One advantage of the proposed coarse symbol timing offset detector presented herein is insensitivity to phase and frequency offsets and ISI.
• the proposed method uses pre-known data in the DVB-S2-like transmission stream to estimate the timing offset when a classical timing recovery scheme using feedback is not applicable due to large ISI.
• the proposed detector relies on pre-known symbols, but for modern communications designs, Turbo-codes, or LDPC codes with large frame length, are used which makes the insertion of pre-known symbols for frame synchronization mandatory. Also, for operation in low SNR, additional pilot information is often added to a signal to aid in demodulation.
• the fine symbol timing recovery methods discussed herein help the symbol timing recovery system achieve and maintain lock under adverse conditions, including those used to increase the channel capacity of satellite channels, such as operating a lower SNR thresholds, reducing excess bandwidth, and when faster than Nyquist (FTN) signaling is used, which often make symbol timing recovery difficult.
• FTN Nyquist
• a method for symbol timing recovery comprises the steps of performing one or more differential correlation operations, measuring a time difference between peak values of the correlation result, using this time difference as an estimate of symbol timing offset to determine coarse symbol timing and receiving further digital signals using the coarse symbol timing.
• an apparatus for symbol timing recovery comprises a processing circuit for performing the one or more differential correlation operations, time difference measurement circuitry for measuring the time difference between correlation peaks, a timing error detector for determining a coarse symbol timing and a receiver for receiving further digital signals using the coarse symbol timing.
• another method for symbol timing recovery there is provided another method for symbol timing recovery.
• the method comprises interpolating a received digital signal through control of a numerically controlled delay, filtering the interpolated result using at least one of a matched filter or a second filter, and using the result to find the timing error for fine symbol timing, which is then filtered and used by the numerically controlled delay for fine symbol timing.
• the apparatus comprises an interpolator for interpolating a received digital signal, wherein interpolating is controlled by a numerically controlled delay, a loop filter for filtering a time difference signal, a controller for controlling the numerically controlled delay using output of the loop filter, another filter for filtering the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter, a timing error detector for using the time difference signal as an estimate of symbol timing offset to determine symbol timing, and a receiver for receiving a further digital signal using the fine symbol timing.
• an interpolator for interpolating a received digital signal, wherein interpolating is controlled by a numerically controlled delay
• a loop filter for filtering a time difference signal
• a controller for controlling the numerically controlled delay using output of the loop filter
• another filter for filtering the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter
• a timing error detector for using
• the method comprises performing one or more differential correlation operations on a received signal, measuring a time difference between peak values of the correlation function, using the time difference as an estimate of symbol timing offset to determine a coarse symbol timing, using said coarse symbol timing to receive a further digital signal, interpolating further received digital signal, wherein interpolating is controlled by a numerically controlled delay, filtering a timing error detection signal with a loop filter, controlling the numerically controlled delay using output of said loop filter, filtering of the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter.finding the timing error of the filtered interpolated signal as a further estimate of symbol timing offset to determine a fine symbol timing, and using said fine symbol timing to receive a subsequent digital signal.
• the apparatus comprises a processing circuit for performing one or more differential correlation operations on a received signal, circuitry for measuring a time difference between peak values of the correlation function, a timing error detector for determining coarse symbol timing using the time difference as an estimate of symbol timing offset, a receiver for receiving a further digital signal using said coarse symbol timing, an interpolator for interpolating said further received digital signal, wherein interpolating is controlled by a numerically controlled delay, a loop filter for filtering a time difference signal, a controller for controlling the numerically controlled delay using output of said loop filter, a filter for filtering the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter, a timing error detector for calculating the timing error of the filtered interpolated signal as an estimate of symbol timing offset to determine the symbol timing, and a receiver for receiving a subsequent digital signal using said fine symbol timing.
• Figure 1 shows the Root Mean Square Error of Estimation (RMSEE) of Gardner's timing error detection signal after matched filtering.
• FIG. 2 shows the Root Mean Square Error of Estimation (RMSEE) of M&M timing error detection signal after matched filtering.
• FIG 3 shows one implementation of a coarse timing offset detector using T 3 spaced using the present principles.
• RMSEE Root Mean Square Error of Estimation
• Figure 6 shows the DVB-S2 frame structure, sync, and pilot information.
• Figure 7 shows a typical feedback timing recovery circuit.
• Figure 8 shows a symbol timing recovery system loop filter.
• Figure 9 shows frequency response of a symbol timing recovery prefilter and matched filter.
• Figure 10 shows the symbol timing recovery circuit of the present principles in acquisition mode.
• Figure 11 shows the symbol timing recovery circuit of the present principles in tracking mode.
• Figure 12 shows an n-delay moving time average function.
• Figure 13 shows one possible embodiment of a matched filter.
• Figure 14 shows graphs of an LDPC iteration counter value and a BER counter value.
• Figure 15 shows the gain of a loop filter integrator with small integral gain.
• Figure 16 shows the gain of a loop filter integrator with high integral gain.
• Figure 17 shows a loop filter output with a 21 -tap moving time average filter following the timing error detector.
• Figure 18 shows a first exemplary method under the present principles.
• Figure 19 shows a first exemplary apparatus under the present principles.
• Figure 20 shows a second exemplary method under the present principles.
• Figure 21 shows a second exemplary apparatus under the present principles.
• Figure 22 shows a third exemplary method under the present principles.
• Figure 23 shows a third exemplary apparatus under the present principles.
• the coarse symbol timing offset estimator presented herein improves the symbol timing recovery operation by using a two step approach with two different timing offset detectors.
• the timing offset is estimated by using pre-known symbols, SYNC symbols in the DVB-S2 like frame structure given in figure 6.
• the SYNC symbols are built by pi/2 BPSK modulation.
• the most important advantage of the differential correlation in the receiver is the robustness against phase and frequency offset errors of the carrier. As the phase and frequency carrier offset compensation could be done after the timing is locked, in this case the differential correlation receiver is very suitable for satellite receiver design.
• the differential correlation is improved using a T s spaced double correlation, wherein T 5 indicates the sample interval of an ADC. Furthermore the T s spaced double correlation is done twice.
• the first T s spaced double correlation block is fed using the matched filtered samples v[n( 7Vt-T 0 //)] and the second T s spaced double correlation block is fed with the Tg/2 shifted matched filter sample v[n(T s +T off )+T s /2].
• the time constant T off indicates the timing offset which has to be estimated by the timing offset detector described herein. This modification could be done easily, as the Gardner TED already uses a two sample per symbol system.
• the matched filtered samples y[nT s ] are then preprocessed by using a differential conjugate complex multiplier to derive the two T 3 spaced matched filtered differential signals, dy ⁇ and dy 2 , as shown in equation (2).
• Equation 3 is then used to implement the cross correlation function, wherein s mag is the so-called sync peak at time nT 3 .
• the T s spaced differential cross correlation is done twice on the matched filter output tf.n(T s +T off )] and the Tg/2 shifted matched filter output y[n(T s +T Off )+T s /2] to detect a proper sync peak, forming s ma J[n(T s +T Off )] and s ma Jin ⁇ T s +T off )+T s /2], even if the optimum timing phase is moving relative to T off between two sync symbols.
• a max device followed by a comparator are used to indicate the likelihood sync peak time location s' mag .
• the comparator compares the incoming likelihood sync location against a threshold to indicate the sync peaks on the noise floor.
• the distance between two consecutive sync peaks is used to estimate the timing offset using the equation: ⁇ _ C (* - D - * 'êt ⁇ , ( *) , (A ⁇ o ff ⁇ dflength ⁇ W where dflength indicates the data and sync field length, fs indicates the sampling rate, and s'mag is the most likelihood sync peak location.
• Figure 3 shows one embodiment of the coarse timing offset detector.
• a first estimate of a timing offset, TO 0 ⁇ is used to adjust the digital time oscillator (DTO, a.k.a.
• the interpolation filter and the matched filter are merged.
• the post matched filter samples y(nT s ) are then passed through the timing offset detection device as described to build the two estimated sync locations s0 ma J[nTs] and sO ma jLnT s + 7V2] .
• a window of confidence around the expected sync peak separation is used to help verify syncrhonization.
• a confidence interval is used which indicates the limits of the distance between two syncs with [dflength-confidence , dflength+ confidence] .
• This coarse STR system may be followed by a fine STR loop to track out residual timing offsets using traditional STR methods, such as Gardner, M&M or other algorithms. Gardner's approach is a method of timing error detection to use twice the symbol rate sample to estimate timing offset.
• Gardner's approach is a method of timing error detection to use twice the symbol rate sample to estimate timing offset.
• a symbol timing offset detection algorithm for data aided symbol timing estimation by using pre-known data embedded in a DVB-S2 like transmission stream can also be used.
• the following principles describe additional improvement to a fine STR loop design for low excess bandwidth and low SNR operation that may be used following the course loop.
• the proposed method and apparatus for fine loop design considers several factors to improve the performance of the STR function.
• the proposed fine loop may be augmented by a coarse outer timing estimate to expand the acquisition range and increase acquisition speed in practice.
• Figure 7 shows a typical symbol timing recovery loop.
• Signal X(nTs) is resampled by an interpolator, which is controlled by a numerically controlled delay (NCD), which in turn is controlled by the resampled output through a timing error detector (TED) filtered by the loop filter.
• NCD numerically controlled delay
• TED timing error detector
• nTs is the sample rate of the input signal, which is typically greater than Ts, the symbol rate.
• n can be either slightly greater than 2, or slightly greater than 4, depending on whether the interpolator output is 2 or 4 samples per symbol.
• Figure 8 illustrates a typical proportional-integral (Pl) 2 nd order loop filter, typically employed in timing recovery loops.
• Impairments in satellite systems are primarily AWGN and nonlinearity caused by satellite TWT amplifiers. Because of this channel, the traditional matched filter receiver architecture is ideal for satellite receivers. In the implementation of low excess bandwidth systems, the sharp rolloff of the pulse shaping filter requires a long impulse response, which greatly increases delay in the STR loop. Without the pulse shaping filter, ISI is greatly increased at low excess bandwidth. Both of these issues lead to acquisition problems in the STR loop. These problems are addressed in two ways. First, in acquisition, the matched filter is bypassed in the STR loop. A prefilter is added to the loop which emphasizes the band edge, which contains the timing information. This provides a twofold benefit - the narrowband timing signal is enhanced, while noise is reduced.
• FIG. 9 shows an example of the frequency response of a prefilter and pulse shaping filter.
• a further embodiment of the principles described herein uses two matched filters - a full-length filter which accurately recovers the pulse train, and a truncated filter which improves the ISI problem with substantially less delay. This is beneficial in the low EB case, since ISI is severe without the matched filter. The short matched filter helps the loop by attenuating ISI, while not impairing the loop performance with large delays.
• a near minimum phase pulse shaping filter could also be used in an embodiment as the matched filter in the loop to reduce ISI and keep loop delay down.
• Figure 13 illustrates one embodiment of a dual output matched filter, one path y with low delay, and the full path wwith minimal ISI.
• An additional embodiment comprises the addition of a moving time average (MTA) filter after the timing error detector. While this could be done by further narrowing of the loop filter bandwidth, the FIR MTA filter is stable compared to the narrowband loop filter with poles practically on the unit circle.
• the MTA filter helps to remove jitter from the symbol tinning loop.
• Figure 12 illustrates one embodiment of the MTA filter.
• Figures 10 and 11 show the STR system in acquisition mode ( Figure 10) and tracking mode ( Figure 11). In practice, this transition would be performed with multiplexers and related design techniques, or could be implemented in a Digital Signal Processor. Loop filter parameters would also be changed in the transition from acquisition to tracking. Transition from acquisition to tracking is accomplished when a downstream receiver function indicates that the loops are locked, such as convergence of the LDPC decoder.
• An LDPC iteration counter is a rough estimate of the quality of the received signal.
• the LDPC iteration counter indicates a value that is less than a prescribed number of iterations (63 in our example)
• the timing loop can be considered locked, and the loop switches to tracking mode.
• Figure 14 shows the LDPC iteration counter and bit error rate count as a function of frame number when the receiver is properly locked.
• Figure 15 shows tracking mode with high integral gain
• Figure 16 shows tracking mode with low integral gain.
• the transition from acquisition to tracking mode occurs at about 1.4 million symbols.
• tracking mode there is an oscillation in the loop filter output, which will be translated into timing jitter in the interpolator.
• the inclusion of the MTA filter attenuates this jitter, allowing the STR loop to converge, as illustrated in Figure 17.
• FTN Nyquist
• Figure 18 shows a first exemplary method 1800 for symbol timing recovery. Differential correlation is performed on a received signal in step 1810. A measurement of time difference between peaks of the correlation output is performed in step 1820. The symbol timing offset is estimated in step 1830, and that offset is used in order to receive additional digital signals in step 1840.
• FIG 19 shows a first exemplary apparatus 1900 for symbol timing recovery.
• a processing circuit 1910 is used for performing one or more differential correlation operations on a received signal.
• Time difference measurement circuitry 1920 calculates the time difference between peak values of the correlation output.
• a Timing Error Detector (TED) 1930 determines a coarse symbol timing using the time difference from the measurement circuitry 1920.
• a receiver 1940 inputs subsequent digital signals using the coarse symbol timing for synchronization.
• TED Timing Error Detector
• FIG. 20 shows a second exemplary method 2000 for symbol timing recovery.
• a received digital signal is interpolated in step 2010.
• the interpolated received signal is filtered in step 2040, and a timing error is estimated in step 2050.
• the timing error signal is filtered in step 2020, and the filtered output is used to control a numerically controlled delay and fed back to the timing error detector filter in step 2030.
• the timing error signal is also used to receive further digital signals in step 2060.
• FIG. 21 shows a second exemplary apparatus for symbol timing recovery.
• An interpolator 2110 is used to interpolate a received digital signal and is controlled by a controller 2130.
• a loop filter 2120 is used to filter a timing error signal and is also controlled by controller 2130.
• a filter 2140 is used to filter the interpolator 2110 output, and is also controlled by controller 2130.
• a timing error detector 2150 receives the filtered interpolated received signal and uses a timing error as an estimate of fine symbol timing offset to determine symbol timing, which is used by receiver 2160 for subsequent digital signals.
• FIG. 22 shows a third exemplary method 2200 for symbol timing recovery.
• Differential correlation is performed on a received signal in step 2210.
• a measurement of time difference between peaks of the correlation output is performed in step 2220.
• the coarse symbol timing offset is estimated in step 2230, and that coarse symbol timing offset is used in order to receive further digital signals in step 2240.
• the further received digital signals are interpolated in step 2250.
• the interpolated received signal is filtered in step 2280, and a fine timing error is estimated in step 2290.
• the fine timing error signal is filtered in step 2260, and the filtered output is used to control a numerically controlled delay and fed back to the timing error detector filter in step 2270.
• the fine timing error signal is also used to receive further digital signals in step 2295.
• FIG 23 shows a third exemplary apparatus 2300 for symbol timing recovery.
• a processing circuit 2310 is used for performing one or more differential correlation operations on a received signal.
• Time difference measurement circuitry 2320 calculates the time difference between peak values of the correlation output.
• a Timing Error Detector (TED) 2330 determines a coarse symbol timing using the time difference from the measurement circuitry 2320.
• a receiver 2340 inputs further received digital signals using the coarse symbol timing for synchronization.
• An interpolator 2350 is used to interpolate the further received digital signal and is controlled by a controller 2370.
• a loop filter 2360 is used to filter a timing error signal and is also controlled by controller 2370.
• a filter 2380 is used to filter the interpolator 2350 output, and is also controlled by controller 2370.
• a timing error detector 2390 receives the filtered interpolated received signal and uses a timing error as an estimate of fine symbol timing offset to determine symbol timing, which is used by receiver 2395 for subsequent digital signals.
• the functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared.
• processor or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (“DSP”) hardware, read-only memory (“ROM”) for storing software, random access memory (“RAM”), and non-volatile storage.
• DSP digital signal processor
• ROM read-only memory
• RAM random access memory
• any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
• a description will now be given of the many attendant advantages and features of the present principles, some of which have been described above.
• a method of symbol timing recovery that performs one or more differential correlation operations on a received digital signal, measures the time difference between correlation peak values, uses that difference to estimate symbol timing offset as a basis for coarse symbol timing.
• Another feature is performing the above method on a signal having repeated known symbols.
• Another feature is that same method described above wherein the correlation operation is performed twice.
• Another feature is that same method described above using a data aided feed forward symbol recovery method using known synchronization symbols embedded in a signal.
• an apparatus to perform the methods described above comprising a processing circuit for performing the one or more differential correlation operations, time difference measurement circuitry for measuring the time difference between correlation peaks, a timing error detector for determining a coarse symbol timing and a receiver for receiving further digital signals using the coarse symbol timing.
• the processing circuit performs correlation on a signal having repeated known symbols.
• Another feature is the apparatus above, wherein the processing circuit performs correlation twice.
• the processing circuit performs the correlation operation by using a data aided feed forward symbol timing recovery method using known synchronization signals embedded in a signal.
• Another feature of the present principles is a method of improved symbol timing recovery wherein a received digital signal is interpolated through control of a numerically controlled delay, filtered using at least one of a matched filter or a second filter, and used to find the timing error for fine symbol timing, which is then filtered and used by the numerically controlled delay for symbol timing.
• a received digital signal is interpolated through control of a numerically controlled delay, filtered using at least one of a matched filter or a second filter, and used to find the timing error for fine symbol timing, which is then filtered and used by the numerically controlled delay for symbol timing.
• Another feature is the above method wherein the timing error is filtered by a moving time average filter prior to filtering by the loop filter.
• an iteration counter is used to determine an acquisition time and a tracking time.
• the interpolated output is filtered by a second filter during acquisition phase and filtered by a matched filter during a tracking phase.
• Another feature is the above method wherein the interpolated output is unfiltered during an acquisition phase and filtered by a matched filter during a tracking phase. Another feature is the above method wherein a low delay matched filter is used for timing recovery and a different matched filter is used for data.
• Yet another feature is an apparatus to perform the above method, comprising an interpolator for interpolating a received digital signal, wherein interpolating is controlled by a numerically controlled delay, a loop filter for filtering a time difference signal, a controller for controlling the numerically controlled delay using output of the loop filter, another filter for filtering the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter, a timing error detector for using the time difference signal as an estimate of symbol timing offset to determine symbol timing, and a receiver for receiving a further digital signal using the fine symbol timing.
• the timing error is filtered by a moving time average filter prior to filtering by the loop filter.
• Another feature is the above apparatus wherein an iteration counter is used to determine an acquisition time and a tracking time. Another feature is the above apparatus wherein the interpolated output is filtered by a second filter during acquisition phase and filtered by a matched filter during a tracking phase. Another feature is the above apparatus wherein the interpolated output is unfiltered during an acquisition phase and filtered by a matched filter during a tracking phase. Another feature is the above apparatus wherein a low delay matched filter is used for timing recovery and a different matched filter is used for data.
• Another feature of the present principles is a method of symbol timing recovery comprising performing one or more differential correlation operations on a received signal, measuring a time difference between peak values of the correlation function, using the time difference as an estimate of symbol timing offset to determine a coarse symbol timing, using said coarse symbol timing to receive a further digital signal, interpolating further received digital signal, wherein interpolating is controlled by a numerically controlled delay, filtering a timing error detection signal with a loop filter, controlling the numerically controlled delay using output of said loop filter, filtering of the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter,finding the timing error of the filtered interpolated signal as a further estimate of symbol timing offset to determine a fine symbol timing, and using said fine symbol timing to receive a subsequent digital signal.
• Yet another feature is an apparatus to perform the above method comprising a processing circuit for performing one or more differential correlation operations on a received signal, circuitry for measuring a time difference between peak values of the correlation function, a timing error detector for determining coarse symbol timing using the time difference as an estimate of symbol timing offset, a receiver for receiving a further digital signal using said coarse symbol timing, an interpolator for interpolating said further received digital signal, wherein interpolating is controlled by a numerically controlled delay, a loop filter for filtering a time difference signal, a controller for controlling the numerically controlled delay using output of said loop filter, a filter for filtering the interpolated output using at least one of a matched filter or a second filter, wherein the second filter can also be a matched filter, a timing error detector for calculating the timing error of the filtered interpolated signal as an estimate of symbol timing offset to determine the symbol timing, and a receiver for receiving a subsequent digital signal using said fine symbol timing.
• a processing circuit for performing one or more differential correlation operations on a received signal
• any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
• any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function.
• the present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
• Circuits Of Receivers In General (AREA)
• Radio Relay Systems (AREA)
• Error Detection And Correction (AREA)

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• 2010
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