WO2010134263A1 - Dispositif d'affichage et son procédé de commande - Google Patents

Dispositif d'affichage et son procédé de commande Download PDF

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Publication number
WO2010134263A1
WO2010134263A1 PCT/JP2010/002858 JP2010002858W WO2010134263A1 WO 2010134263 A1 WO2010134263 A1 WO 2010134263A1 JP 2010002858 W JP2010002858 W JP 2010002858W WO 2010134263 A1 WO2010134263 A1 WO 2010134263A1
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Prior art keywords
terminal
transistor
light emitting
gate
voltage
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PCT/JP2010/002858
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English (en)
Japanese (ja)
Inventor
松井雅史
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パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN201080011557.5A priority Critical patent/CN102388414B/zh
Priority to JP2011514305A priority patent/JP5562327B2/ja
Publication of WO2010134263A1 publication Critical patent/WO2010134263A1/fr
Priority to US13/288,142 priority patent/US8633874B2/en

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Definitions

  • the present invention relates to an active matrix type image display device using a current-driven self-luminous element such as an organic electroluminescence (EL) element.
  • a current-driven self-luminous element such as an organic electroluminescence (EL) element.
  • An organic EL element expresses gradation by current control.
  • an active matrix organic EL display device has uneven luminance even when the same signal voltage is applied due to a variation in threshold voltage of a driving transistor that drives each organic EL element.
  • Compensating the threshold value of the driving transistor of the organic EL element is necessary for eliminating the luminance unevenness and creating a uniform screen.
  • As a threshold value compensation circuit for suppressing variations in threshold values of driving transistors there is a method of detecting threshold values of driving transistors by using four transistors per pixel (see, for example, Non-Patent Document 1). Further, there is a method of detecting the threshold value of the driving transistor by using three transistors per pixel and scanning the voltage of the power supply line (see, for example, Patent Document 1).
  • Non-Patent Document 1 uses four transistors per pixel, and there is a concern that the yield may decrease due to an increase in the number of integrated transistors with an increase in the size of the display.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display device that compensates a threshold voltage of a drive element without scanning a power supply line with a small number of elements. It is also included in the present invention to provide a method for driving such a display device.
  • a display device of the present invention is a display device including a plurality of light emitting pixels arranged in a matrix, and the display device corresponds to each row of the plurality of light emitting pixels.
  • a gate line, a reset line, and a signal line provided corresponding to each column of the plurality of light emitting pixels, and each of the plurality of light emitting pixels includes a gate terminal, a source terminal, and a drain terminal.
  • a first switching transistor in which one of the source terminal and the drain terminal is connected to the signal line, and the gate terminal is connected to the gate line; a light emitting element that emits light when current flows; and a gate terminal; A source terminal and a drain terminal, the gate terminal being connected to the other of the source terminal and the drain terminal of the first switching transistor; And one of the drain terminals is connected to the light emitting element, and includes a driving transistor that supplies current to the light emitting element, a gate terminal, a source terminal, and a drain terminal, and the gate terminal is connected to the reset line, One of the source terminal and the drain terminal is connected to the one of the source terminal and the drain terminal of the driving transistor, one end is connected to the gate terminal of the driving transistor, and the other end is the source of the driving transistor.
  • a gate line provided corresponding to one of the rows of the plurality of light emitting pixels, wherein the other of the source terminal and the drain terminal of the reset transistor is provided with a capacitor connected to the one of the terminal and the drain terminal. It is
  • the threshold voltage of the driving transistor can be detected with three transistors per light emitting pixel without scanning the power supply line, and the light emitting element can emit light by compensating for the threshold voltage. In this way, variations in the threshold voltage of the drive transistor are compensated, so that uneven brightness can be eliminated.
  • the reset transistor is connected to the reset line while the gate line connected to the other of the source terminal and the drain terminal of the reset transistor is in an inactive state in which the first switching transistor is turned off. You may provide the drive part made into the active state which turns on.
  • the voltage of the source terminal of the driving transistor can be made the same as the voltage of the gate line to which the other of the source terminal and the drain terminal of the reset transistor is connected. Can be set.
  • the driver further selectively supplies a reference voltage and a signal voltage higher than the reference voltage to the plurality of signal lines, and a voltage in an inactive state of each gate line is a threshold value of the drive transistor.
  • the voltage may be lower than the reference voltage by a voltage or more.
  • the voltage of the source terminal of the drive transistor can be surely set to be equal to or higher than the threshold voltage of the drive transistor and lower than the reference voltage. Therefore, the threshold voltage of the driving transistor can be reliably detected.
  • the other of the source terminal and the drain terminal of the reset transistor may be connected to a gate line provided in the same row.
  • the driving unit further includes an active state in which the first switching transistor is turned on before the gate line provided in the same row is inactivated, and the reset line is set to the reset transistor. It may be in an inactive state that turns off.
  • the light emitting element can be quenched. Specifically, if the voltage at the gate terminal of the immediately preceding drive transistor is sufficient to supply the current necessary for the light emitting element to emit light, the voltage is applied even after the gate line is deactivated. As a result, the light emitting element emits light. Thus, by setting the gate line in an active state and the reset line in an inactive state in this way, the light emitting element can be surely extinguished by applying a voltage at the time of extinction to the gate terminal of the driving transistor.
  • the other of the source terminal and the drain terminal of the reset transistor may be connected to a gate line provided in the next row.
  • the threshold voltage of the driving transistor can be reliably detected by setting the voltage of the gate line of the next row to a voltage lower than the reference voltage by the threshold voltage of the driving transistor. That is, as compared with the case where the reset transistor is connected to the gate line of the same row, the light emitting element can be extinguished and the voltage of the source terminal of the driving transistor can be set at the same time. It can be assigned to the detection of the threshold voltage of the driving transistor.
  • the one of the source terminal and the drain terminal of the reset transistor and the other end of the capacitor may be connected to the one of the source terminal and the drain terminal of the driving transistor via a predetermined element. Good.
  • the potential at the connection point between the light emitting element and the driving transistor is defined by the capacitance distribution between the parasitic capacitance of the light emitting element and the capacitance of the capacitive element.
  • the connection point between the light emitting element and the driving transistor of each light emitting pixel is determined. The potentials are not the same and have variations. Therefore, the current supplied to the light emitting element varies due to variations in potential at the connection point between the light emitting element and the driving transistor.
  • the influence of the parasitic capacitance of the light emitting element on the potential of the other end of the capacitive element is reduced by connecting the other end of the capacitive element and the connection point between the light emitting element and the driving transistor via a predetermined element. it can. Therefore, it is possible to reduce the influence of the parasitic capacitance of the light emitting element on the holding voltage of the capacitive element, which is a potential difference between one end and the other end of the capacitive element.
  • the influence of the parasitic capacitance of the light emitting element can be reduced, and the light emitting element can emit light with high accuracy according to the signal voltage.
  • Each of the plurality of light emitting pixels further includes a gate terminal, a source terminal, and a drain terminal, and one of the source terminal and the drain terminal is connected to the one of the source terminal and the drain terminal of the reset transistor and the capacitor.
  • a second switching transistor connected to the other end of the element and having the other of the source terminal and the drain terminal connected to the one of the source terminal and the drain terminal of the driving transistor may be provided.
  • each of the driving transistor, the first switching transistor, and the reset transistor may be an n-type transistor element.
  • the light emitting element may be an organic EL (Electro Luminescence) element.
  • the driving method of the present invention includes a plurality of light emitting pixels arranged in a matrix, a gate line and a reset line provided corresponding to each row of the plurality of light emitting pixels, and a column of the plurality of light emitting pixels.
  • Each of the plurality of light emitting pixels includes a gate terminal, a source terminal, a drain terminal, and a signal line that is selectively provided to a reference voltage and a signal voltage higher than the reference voltage.
  • a first switching transistor in which one of the source terminal and the drain terminal is connected to the signal line and the gate terminal is connected to the gate line, a light emitting element that emits light when current flows, and a gate terminal And a source terminal and a drain terminal, and the gate terminal is connected to the other of the source terminal and the drain terminal of the first switching transistor, and the source One of a child and the drain terminal is connected to the light emitting element, and includes a driving transistor that supplies current to the light emitting element, a gate terminal, a source terminal, and a drain terminal, and the gate terminal is connected to the reset line, One of the source terminal and the drain terminal is connected to the one of the source terminal and the drain terminal of the drive transistor, one end is connected to the gate terminal of the drive transistor, and the other end is connected to the drive transistor.
  • a capacitor connected to the one of the source terminal and the drain terminal, and the other of the source terminal and the drain terminal of the reset transistor is a gate line provided corresponding to one of the rows of the plurality of light emitting pixels
  • a display device connected to the first switching transistor Off register, and by turning on the reset transistor comprises a reset step of the source terminal and the reference voltage lower than the voltage threshold voltage or more of the said driving transistor one of the drain terminal of the driving transistor.
  • the first switching transistor is turned on to detect the threshold voltage of the driving transistor, and the capacitance element holds the threshold voltage detected in the detection step.
  • the driving transistor supplies a current corresponding to the voltage obtained by adding the signal voltage and the threshold voltage to the light emitting element, so that the light emitting pixel emits light with a luminance corresponding to the signal voltage without being affected by the threshold voltage. it can.
  • the detecting step includes a first sub-step for turning on the first switching transistor, and a second sub-step for turning off the first switching transistor after the first sub-step. Thereafter, the first sub-step and the second sub-step may be repeated at least once.
  • the threshold voltage of the driving transistor can be detected over a plurality of horizontal periods, so that the threshold voltage can be detected with high accuracy.
  • the reference voltage is supplied to the signal line provided in the same column as the first switching transistor.
  • the signal voltage or the signal voltage is supplied to the signal line.
  • a reference voltage may be supplied.
  • the voltage of the signal line in the first sub step can be used as a voltage for detecting the threshold voltage of the driving transistor in the column corresponding to the signal line
  • the voltage of the signal line in the second sub step corresponds to the voltage.
  • This can be the signal voltage of the light emitting pixels in the column.
  • the signal line voltage is used as the reference voltage in the first half of one horizontal period and the signal line voltage is used as the signal voltage in the second half of one horizontal period, so that one horizontal period is divided and the threshold voltage is detected in the first half.
  • the second period can be a signal voltage writing period.
  • Each of the plurality of light emitting pixels further includes a gate terminal, a source terminal, and a drain terminal, and one of the source terminal and the drain terminal is connected to the one of the source terminal and the drain terminal of the reset transistor and the capacitor.
  • a second switching transistor connected to the other end of the element, the other of the source terminal and the drain terminal being connected to the one of the source terminal and the drain terminal of the drive transistor; With the two switching transistors turned on, the first switching transistor is turned on to detect a threshold voltage of the driving transistor, and in the holding step, the second switching transistor is switched from on to off. Detected in In the write step, the signal voltage is supplied to the signal line while the first switching transistor is on with the value voltage held in the capacitor element and the second transistor is turned off in the writing step.
  • the second switching transistor is switched from off to on, A current corresponding to a potential difference between the gate terminal and the source terminal of the driving transistor is supplied to the light emitting element to cause the light emitting element to emit light.
  • the signal voltage is supplied to the gate terminal of the driving transistor while the second switching transistor is off, the potential at the other end of the capacitive element is not affected by the parasitic capacitance of the light emitting element. . That is, the influence of the parasitic capacitance of the light emitting element on the holding voltage of the capacitive element can be reliably reduced. In other words, the influence of the parasitic capacitance of the light emitting element can be prevented, and the light emitting element can be made to emit light with an accurate light emission luminance corresponding to the signal voltage.
  • the other of the source terminal and the drain terminal of the reset transistor is connected to a gate line provided in the same row, and the driving method of the display device further includes the first switching transistor before the reset step.
  • a quenching step of quenching the light emitting element by turning on and turning off the reset transistor may be included.
  • the display device can compensate the threshold voltage of the drive element without scanning the power supply line with a small number of elements.
  • FIG. 1 is a block diagram illustrating a configuration of the display device according to the first embodiment.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the light emitting pixel.
  • FIG. 3 is a timing chart showing the operation of the display device.
  • FIG. 4 is a diagram schematically showing the current flow of the light emitting pixels.
  • FIG. 5 is a timing chart showing the operation of the display device when the threshold voltage is detected over a plurality of horizontal periods.
  • FIG. 6 is a block diagram illustrating a configuration of the display device according to the second embodiment.
  • FIG. 7 is a circuit diagram showing a detailed configuration of the light emitting pixel.
  • FIG. 8 is a timing chart showing the operation of the display device.
  • FIG. 1 is a block diagram illustrating a configuration of the display device according to the first embodiment.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the light emitting pixel.
  • FIG. 3 is a timing chart showing the operation of the display device.
  • FIG. 9 is a timing chart showing the operation of the display device when the threshold voltage is detected over a plurality of horizontal periods.
  • FIG. 10 is a circuit diagram illustrating a detailed configuration of the light-emitting pixel included in the display device according to Embodiment 3.
  • FIG. 11 is a timing chart showing the operation of the display device.
  • FIG. 12 is a diagram schematically illustrating the current flow of the light emitting pixels.
  • FIG. 13 is an external view of a thin flat TV incorporating the display device according to the present invention.
  • the display device is a display device including a plurality of light emitting pixels arranged in a matrix, and the display device is provided corresponding to each row of the plurality of light emitting pixels.
  • the threshold voltage of the driving transistor can be detected with three transistors per light emitting pixel without scanning the power supply line, and the light emitting element can emit light by compensating for the threshold voltage. In this way, since the variation in the threshold voltage of the driving transistor is compensated, the luminance unevenness can be eliminated.
  • FIG. 1 is a block diagram illustrating a configuration of a display device according to the first embodiment.
  • the display device 100 shown in the figure is, for example, an active matrix organic EL display device using organic EL elements, and includes a plurality of light emitting pixels 110 arranged in a matrix, a row scanning unit 120, and a signal line drive. Unit 130 and a timing control unit 140.
  • the light emitting pixels 110 are arranged in a matrix of, for example, n rows ⁇ m columns, and gate pulses and resets output from the row scanning unit 120 and the signal line driving unit 130 via the signal lines 111, the gate lines 112, and the reset lines 113. Light is emitted by compensating the threshold voltage of the driving transistor in accordance with the pulse and the signal voltage.
  • the row scanning unit 120 is connected to the gate line 112 and the reset line 113 provided corresponding to each row of the plurality of light emitting pixels 110, and outputs a scanning signal to each gate line 112 and each reset line 113.
  • the plurality of light emitting pixels 110 are sequentially scanned in units of rows.
  • the row scanning unit 120 includes a gate line driving unit 121 that scans each gate line 112 and a reset line driving unit 122 that scans each reset line 113.
  • the gate line driving unit 121 outputs a gate pulse Gate [k] corresponding to each gate line 112 (k is an integer satisfying 1 ⁇ k ⁇ m), whereby the light emitting pixel 110 corresponding to each gate line 112 is output.
  • the reset line driving unit 122 outputs a reset pulse Rst [k] corresponding to each reset line 113, whereby the voltage of the gate line 112, that is, the gate pulse Gate [k], to the light emitting pixel 110 corresponding to each reset line 113.
  • the timing of applying the high level voltage or the low level voltage is controlled.
  • the signal line driver 130 is connected to each signal line 111, and a signal voltage Vdata (for example, 2 to 8 V) or a reset voltage Vreset (for example, 0 V) corresponding to each signal line 111 is applied to the signal line voltage Sig [j] ( j is supplied as an integer satisfying 1 ⁇ k ⁇ n).
  • the signal voltage Vdata is a voltage corresponding to the light emission luminance of the light emitting pixel 110
  • the reset voltage Vreset is a voltage for quenching the light emitting pixel 110 or detecting the threshold voltage of the driving transistor.
  • the timing control unit 140 instructs the drive timing to the row scanning unit 120 and the signal line driving unit 130.
  • the row scanning unit 120, the signal line driving unit 130, and the timing control unit 140 are driving units of the present invention.
  • each of the plurality of light emitting pixels 110 illustrated in FIG. 1 has the same configuration.
  • the gate pulse Gate [k] output from the gate line driver 121 to the gate line 112 corresponding to the light emitting pixel 110 is simply referred to as the gate pulse Gate, and the reset line 113 corresponding to the light emitting pixel 110 is set.
  • the reset pulse Rst [k] output from the reset line driving unit 122 is simply set as the reset pulse Rst, and the signal line voltage Sig [j] supplied to the signal line 111 corresponding to the light emitting pixel 110 is simply set as the signal line voltage. Sig.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the light emitting pixel 110 shown in FIG. In the figure, a signal line 111, a gate line 112, and a reset line 113 corresponding to the light emitting pixel 110 are also shown.
  • the light emitting pixel 110 includes a light emitting element OLED, a row selection transistor T1, a reset transistor T2, a driving transistor T3, and a capacitive element CS.
  • the light emitting element OLED is an element that emits light when a current flows, and is, for example, an organic EL element in which an anode is connected to a source terminal of a driving transistor and a cathode is connected to a power supply line of a voltage VSS (for example, 0 V). .
  • VSS for example, 0 V
  • the light emitting element OLED emits light by a current flowing when a signal voltage Vdata is applied to the gate terminal of the driving transistor T3 via the signal line 111 and the row selection transistor T1. Therefore, the luminance of the light emitting element OLED corresponds to the magnitude of the signal voltage Vdata applied to the signal line 111.
  • the row selection transistor T1, the reset transistor T2, and the drive transistor T3 are, for example, n-type TFTs (thin film transistors).
  • the row selection transistor T1 is a first switching transistor of the present invention, and switches whether to apply a signal voltage to the gate terminal which is the control terminal of the driving transistor T3, according to the voltage of the gate line 112. Specifically, in the row selection transistor T1, the gate terminal is connected to the gate line 112, one of the source terminal and the drain terminal is connected to the signal line 111, and the other of the source terminal and the drain terminal is the gate terminal of the driving transistor T3. It is connected to the. Therefore, the row selection transistor T1 switches between conduction and non-conduction between the signal line 111 and the gate terminal of the drive transistor T3 in accordance with the voltage applied to the gate line 112. That is, the row selection transistor T1 supplies the reference voltage Vreset or the signal voltage Vdata applied to the signal line 111 to the gate terminal of the driving transistor T3 while the gate pulse Gate is at a high level.
  • the reset transistor T2 sets V2, which is the voltage of the source terminal of the drive transistor T3, in order to detect the threshold voltage of the drive transistor T3.
  • the reset transistor T2 has a gate terminal connected to the reset line 113, one of the source terminal and the drain terminal connected to the gate line 112, and the other of the source terminal and the drain terminal connected to the source terminal of the drive transistor T3. It is connected. Therefore, the reset transistor T2 sets the voltage of the gate line 112 to the voltage V2 by conducting the gate line 112 and the source terminal of the drive transistor T3 during the period when the reset pulse Rst is at a high level.
  • the driving transistor T3 supplies a current to the light emitting element OLED.
  • the drive transistor T3 has a gate terminal connected to the signal line 111 via the row selection transistor T1, a drain terminal connected to a power supply line having a voltage VDD (for example, 10V), and a source terminal connected to the light emitting element OLED. Connected to the anode.
  • the driving transistor T3 converts the voltage supplied to the gate terminal into a current corresponding to the magnitude of the voltage. Therefore, the driving transistor T3 supplies a voltage corresponding to the voltage supplied to the signal line 111 during the period when the voltage of the gate line 112 is high, that is, a current corresponding to the reference voltage Vreset or the signal voltage Vdata to the light emitting element OLED.
  • the current corresponding to the reference voltage Vreset is insufficient to cause the light emitting element OLED to emit light, and the light emitting element OLED does not emit light when the voltage V1 of the gate terminal of the driving transistor T3 is the reference voltage Vreset.
  • V1 is the signal voltage Vdata
  • a sufficient current flows for the light emitting element OLED to emit light, and the light emitting element OLED emits light with a luminance corresponding to the signal voltage Vdata.
  • the capacitor element CS has one end connected to the gate terminal of the driving transistor T3 and the other end connected to the source terminal of the driving transistor T3, thereby holding the voltage between the gate and the source of the driving transistor T3. That is, the capacitive element CS can hold the threshold voltage of the drive transistor T3.
  • FIG. 3 is a timing chart showing the operation of the display device 100 according to the first embodiment.
  • the horizontal axis indicates time, and in the vertical direction, in order from the top, the gate pulse Gate, the reset pulse Rst, the voltage V1 of the gate terminal of the driving transistor T3, and the voltage of the source terminal of the driving transistor T3.
  • the waveforms of V2 and the signal line voltage Sig applied to the signal line 111 are shown.
  • FIG. 4 is a diagram schematically showing a current flow in the light emitting pixel 110 of the display device 100 according to the first embodiment.
  • the high level voltage of the gate pulse Gate is VGate (H)
  • the low level voltage of the gate pulse Gate is VGate (L)
  • the high level voltage of the reset pulse Rst is VRst (H)
  • the low level voltage of the reset pulse Rst is VRst (L).
  • the light emitting element OLED emits light according to the signal voltage Vdata in the immediately preceding vertical period.
  • V1 is the signal voltage Vdata in the immediately preceding vertical period
  • the driving transistor T3 supplies a driving current to the light emitting element OLED by the signal voltage Vdata.
  • VGate (L) is, for example, ⁇ 5V
  • VGate (H) is, for example, 12V.
  • Vreset which is a reference voltage
  • V1 transitions to Vreset during the reset [1] period.
  • Vth (EL) is a light emission start voltage of the light emitting element OLED
  • Vth (TFT) is a threshold voltage between the gate terminal and the source terminal of the driving transistor T3.
  • Vreset ⁇ Vth (EL) + Vth (TFT) (Formula 1) That is, Vreset is a voltage that reliably extinguishes the light emitting element OLED.
  • the gate pulse Gate is set to the low level and the reset pulse Rst is set to the high level.
  • the gate pulse Gate becomes a low level
  • the row selection transistor T1 is turned off, and the signal line 111 and the gate terminal of the driving transistor T3 become non-conductive.
  • the reset pulse Rst becomes high level
  • the reset transistor T2 is turned on, and the gate line 112 and the source terminal of the drive transistor T3 are conducted. Therefore, V2 becomes the low level voltage VGate (L) of the gate pulse Gate.
  • VGate (L) is a voltage satisfying the following Expression 2.
  • VGate (L) ⁇ Vreset ⁇ Vth (TFT) (Formula 2)
  • the voltage V1 is the same as the voltage fluctuation of V2 from the reset [1] period to the reset [2] period due to the capacitive element CS inserted between the gate terminal of the driving transistor T3 and the anode of the light emitting element OLED. Change. Specifically, since the voltage of V2 fluctuated by VGate (L) ⁇ Vth (EL) from the reset [1] period to the reset [2] period, the voltage of V1 is changed to the voltage of the reset [1] period. Vreset + VGate (L) ⁇ Vth (EL) obtained by adding the variation.
  • the reset transistor R2 is turned off by the reset pulse Rst being at a low level, so that the gate line 112 and the source terminal of the drive transistor T3 are not conductive. Become. Accordingly, the potential difference between V1 and V2 at this time is held in the capacitive element CS.
  • a reference voltage Vreset is set from one end of the capacitive element CS from the signal line 111, and a fixed voltage is set to the other end of the capacitive element CS. It is necessary to set a voltage having a predetermined potential difference.
  • This reset period is divided into two periods, a T1 period (time t0 to t1) which is a reset [1] period and a T2 period (time t1 to t2) which is a reset [2] period.
  • T1 period time t0 to t1
  • T2 period time t1 to t2
  • a reference voltage Vreset is set at one end of the capacitor, and a fixed voltage is set at the other end of the capacitive element CS in the period T2.
  • the period T1 in order to set the reference voltage Vreset from the signal line 111 to one end of the capacitive element CS, it is necessary to supply the high level voltage VGate (H) to the gate line 112 to turn on the row selection transistor T1. is there.
  • the low level voltage VGate (L) in order to fix the reference voltage Vreset set at one end of the capacitive element CS in the period T2, it is necessary to supply the low level voltage VGate (L) to the gate line 112 to turn off the row selection transistor T1.
  • the low-level voltage VGate (L) is supplied in units of rows because the gate lines 112 are arranged in units of rows. This means that the fixed voltage VGate (L) is set in a row unit during the T2 period.
  • the gate line 112 is also used as a power supply line for supplying a fixed potential VGate (L), and the fixed potential VGate (L) is supplied to the other end of the capacitive element CS via the gate line 112. Therefore, the number of power supply lines for supplying the fixed potential VGate (L) to the other end of the capacitor element CS can be reduced. As a result, the fixed potential VGate (L) can be set at the other end of the capacitive element CS with a simple configuration.
  • V2 becomes a value as shown in Expression 3.
  • V2 ⁇ VGate (L) + (1 ⁇ ) Vth (EL) (Formula 3)
  • ⁇ Cel / (Cs + Cel).
  • Cs is a capacitance of the capacitive element CS
  • Cel is a parasitic capacitance between the anode and the cathode of the light emitting element OLED.
  • each voltage and capacity satisfy the following equations 4 and 5.
  • Equation 4 shows a condition in which, even when a potential fluctuation corresponding to the capacitance ratio occurs at V2 at time t3, the current flowing through the OLED can be ignored when the potential of V2 is equal to or lower than the threshold voltage Vth (EL) of the OLED.
  • Formula 5 shows a condition in which the potential difference equal to or higher than the threshold voltage Vth (TFT) is held in the capacitor element CS in the driving transistor T3 even if the potential fluctuation of V2 occurs at time t3.
  • TFT threshold voltage
  • the drive transistor T3 is turned on, and a current flows through the drive transistor T3. That is, when V2 satisfies Expression 2 in the reset [2] period and Expression 4 and Expression 5 are satisfied at time t3, a current flows through the driving transistor T3. This current flows until the potential difference between V1 and V2 reaches the threshold voltage Vth (TFT) of the drive transistor T3.
  • the signal voltage Vdata is applied to the signal line 111 in the writing period from time t5 to t6. Thereby, the voltage of V1 becomes Vdata, and V2 at time t5 becomes Expression 6.
  • V2 (1- ⁇ ) ⁇ (Vdata ⁇ Vreset) + Vreset ⁇ Vth (TFT) (Formula 6) Therefore, the potential difference between V1 and V2, that is, the voltage Vgs between the gate and the source terminal of the driving transistor T3 is expressed by Expression 7.
  • Vgs ⁇ (Vdata ⁇ Vreset) + Vth (TFT) (Formula 7) That is, in the writing period, a voltage obtained by adding the threshold voltage Vth (TFT) to the difference between the signal voltage Vdata and the reference voltage Vreset, that is, a voltage that compensates for the threshold voltage Vth (TFT) is written in Vgs.
  • the display device 100 detects the threshold voltage of the driving transistor T3 with three transistors per light emitting pixel 110 without scanning the power supply line, and compensates the threshold voltage to emit the light emitting element.
  • the OLED can emit light.
  • the variation in the threshold voltage of the driving transistor T3 is compensated, the luminance unevenness can be eliminated.
  • the threshold voltage Vth (TFT) of the driving transistor T3 can be set to a voltage lower than the reference voltage Vreset. That is, the voltage V2, that is, VGate (L) during the reset [2] period can be lower than Vreset ⁇ Vth (TFT). Therefore, in the subsequent Vth detection period, the threshold voltage Vth (TFT) of the drive transistor T3 can be reliably detected.
  • the gate pulse Gate is set to high level and the reset pulse Rst is set to low level in the reset [1] period. Thereby, the light emitting element OLED can be quenched.
  • the signal voltage Vdata in the immediately previous frame period is applied to the gate terminal of the drive transistor T3.
  • the voltage between the gate and source terminals of the drive transistor T3 remains equal to or higher than the threshold voltage Vth (TFT), and a current corresponding to Vdata flows. As a result, the light emitting element OLED cannot be quenched.
  • the voltage of the gate terminal of the drive transistor T3 is set to the reference voltage Vreset. Therefore, the voltage between the gate and source terminals of the drive transistor T3 is set to the threshold value in the reset [2] period.
  • the voltage of V2 can be reliably set to the low level voltage VGate [L] of the gate pulse Gate while being in the off state that is equal to or lower than the voltage Vth (TFT).
  • FIG. 5 is a timing chart showing the operation of the display device 100 when the threshold voltage is detected over a plurality of horizontal periods.
  • the horizontal axis represents time, and in order from the top, the gate pulse Gate [1] applied to the gate line 112 corresponding to the light emitting pixels in the first row, and the reset pulse Rst [1] applied to the reset line 113.
  • the signal line driver 130 supplies the reference voltage Vreset to the signal line 111 in the second half of each horizontal period, and supplies the signal voltage Vdata of the display pixel in the column corresponding to each signal line 111 in the first half of each horizontal period. . Further, the gate line driving unit 121 and the reset line driving unit 122 are shifted by one horizontal period, and the gate pulses Gate [1] to [6] and the reset pulses Rst [1] to [6] are transferred to the gate lines 112, respectively. And supplied to each reset line 113.
  • the gate line driver 121 and the reset line driver 122 apply the gate pulse Gate [1] once as described in the first embodiment.
  • the voltage of V2 [1] is set lower than the reference voltage Vreset by a threshold voltage Vth (TFT). Note that at time t1 one horizontal period after the gate line driving time t0, the gate pulse Gate [2] of the second row becomes high level, and the reset [1] period of the second row starts.
  • V1 becomes the reference voltage, and a current flows through the driving transistor T3. Therefore, V2 starts to rise.
  • V2 transitions to Vreset-Vth (TFT) when the gate pulse Gate [1] becomes high level only in the second half of each horizontal period.
  • the signal line 111 is supplied with Vreset, which is a reference voltage, in the second half of each horizontal period, and Vdata corresponding to the luminance of the light emitting pixels 110 in the corresponding column in the first half of each horizontal period. ing.
  • each gate pulse Gate [1] to Gate [6] is set to a high level in the second half of each horizontal period, so that the reference voltage Vreset is supplied to V1, and thus the threshold voltage of the driving transistor T3 is set. A part of the period necessary for detection can be secured.
  • each gate pulse Gate [1] to Gate [6] has a sufficient time required for detecting the threshold voltage by repeating the operation of becoming a high level in the second half of the horizontal period over a plurality of horizontal periods. Can be secured.
  • the gate pulses Gate [1] to Gate [6] are at a low level in the first half of each horizontal period, so that the signal line 111 and the gate terminal of the driving transistor T3 are made non-conductive in the first half of each horizontal period.
  • the signal voltage Vdata is not supplied.
  • the display device uses the second half of each horizontal period as the threshold voltage Vth (TFT) detection period, and repeats it for a plurality of horizontal periods, thereby obtaining the threshold voltage Vth (TFT).
  • TFT threshold voltage
  • the period necessary for detection is secured. Therefore, the voltage held in the capacitive element CS is stabilized, and as a result, highly accurate threshold voltage compensation can be performed.
  • the Vth detection period is four horizontal periods.
  • the horizontal period required for the Vth detection period is not limited to four horizontal periods, and is sufficient for detecting the threshold voltage Vth (TFT) of the drive transistor T3. It is sufficient if sufficient time is secured.
  • the display device of the second embodiment is almost the same as the display device 100 of the first embodiment, but a reset transistor is inserted between the source terminal of the driving transistor and the gate line provided in the next row. The point is different. As a result, even when the gate line is in the active state and the reset line is in the active state, the voltage of the source terminal of the driving transistor can be the voltage of the gate line of the next row.
  • the threshold voltage of the driving transistor can be reliably detected by setting the voltage of the driving transistor to a voltage lower than the reference voltage by the threshold voltage of the driving transistor.
  • the light emitting element can be extinguished and the voltage of the source terminal of the driving transistor can be set at the same time. It can be assigned to the detection of the threshold voltage of the driving transistor.
  • the difference between the display device according to the second embodiment and the display device 100 according to the first embodiment will be mainly described.
  • FIG. 6 is a block diagram illustrating a configuration of the display device according to the second embodiment.
  • the display device 200 shown in the figure is different from the display device 100 shown in FIG. 1 in that each light emitting pixel 210 is connected to the gate line 112 in the next row.
  • the display device 200 further includes a dummy gate line 201.
  • the dummy gate line 201 is connected to the light emitting pixels 210 in the last row of the plurality of light emitting pixels 210 and is scanned by the gate line driving unit 121 in the same manner as the gate lines 112.
  • the gate line driver 121 outputs a gate pulse Gate [d] that is a pulse obtained by delaying the gate pulse Gate [m] by one horizontal period to the dummy gate line 201.
  • FIG. 7 is a circuit diagram showing a detailed configuration of the light emitting pixel 210 shown in FIG. Note that the light emitting pixel 210 shown in the figure is the light emitting pixel 210 provided in the k-th row. In the same figure, the signal line 111 corresponding to the light emitting pixel 210, the gate line 112 (k) which is the gate line of the kth row, and the gate line 112 (k + 1) which is the gate line of the k + 1th row are reset. Line 113 is also shown.
  • the light emitting pixel 210 shown in the figure includes a reset transistor T2 'instead of the reset transistor T2 as compared with the light emitting pixel 110 shown in FIG.
  • the reset transistor T2 ′ is inserted between the source terminal of the driving transistor T3 and the gate line 112 (k + 1) of the next row, compared to the reset transistor T2 of the light emitting pixel 110 shown in the first embodiment. Yes.
  • the light emitting pixel 210 of the display device 200 uses the potential of the source terminal of the driving transistor T3, that is, V2, as the voltage of the gate line 112 (k + 1) in the next row. Can be set using.
  • FIG. 8 is a timing chart showing the operation of the display device 200 according to the second embodiment.
  • the vertical axis of the figure shows the gate pulse Gate [k + 1] supplied to the gate line 112 (k + 1) in the next row as compared with the timing chart of FIG.
  • the low level voltage of the gate pulse Gate [k + 1] is a voltage indicating a value lower than Vreset ⁇ Vth (TFT).
  • the gate pulse Gate [k] rises from the low level to the high level.
  • the reset pulse Rst also rises from the low level to the high level.
  • the row selection transistor T1 is turned on, and at the same time, the reset transistor T2 'is also turned on.
  • the reset transistor T2 ′ conducts the gate line 112 (k + 1) of the next row and the source terminal of the driving transistor T3, so that V2 is the gate supplied to the gate line 112 (k + 1) of the next row.
  • the voltage is the pulse Gate [k + 1].
  • the gate pulse Gate [k + 1] in the next row is at a low level, so V2 becomes VGate (L).
  • V1 becomes the voltage of the signal line 111 when the row selection transistor T1 is turned on.
  • V1 transitions to Vreset.
  • the drive transistor T3 The voltage of the source terminal can be the voltage of the gate line 112 (k + 1) in the next row.
  • the gate pulse Gate [k + 1] of the next row is at a low level, and the low level voltage is lower than Vreset ⁇ Vth (TFT), so that the threshold voltage Vth (TFT) of the drive transistor T3 is reached. Can be reliably detected.
  • the reset [1] period and the reset [2] period are necessary before the Vth detection period, but in the display device 200 according to the present embodiment, the display device 200 Compared to 100, the preliminary operation for detecting the threshold voltage can be performed in a half period.
  • the reference voltage Vreset is set from the signal line 111 to one end of the capacitive element CS, and the fixed voltage is set to the other end of the capacitive element CS. Therefore, it is necessary to set a voltage having a predetermined potential difference in the capacitive element CS.
  • the time t0 to t1 in FIG. 3 which is a reset [1] period and the reset [2] period in FIG.
  • the time period t1 to t2 is divided into a period in which the reference voltage Vreset is set at one end of the capacitive element CS and a period in which the fixed voltage is set at the other end of the capacitive element CS.
  • the period for setting the reference voltage Vreset at one end of the capacitive element CS and the period for setting the fixed voltage at the other end of the capacitive element CS can be simultaneously performed.
  • the preliminary operation for detecting the threshold voltage is performed by a power source for supplying the fixed potential VGate (L) to the gate line 112 corresponding to the row to which the light emitting pixel 110 performing the operation belongs. Also used as a line.
  • the fixed potential VGate (L) is supplied to the gate line 112 corresponding to the next row to which the light emitting pixel 210 performing the preliminary operation for detecting the threshold voltage belongs. Also used as a power line.
  • the display device 200 of the present embodiment can set the fixed potential VGate (L) to the other end of the capacitor element CS in half the period compared to the display device 100 of the first embodiment. That is, as compared with the display device 100, the preliminary operation for detecting the threshold voltage can be performed in a half period.
  • the reset transistor R2 ′ is turned off when the reset pulse Rst becomes low level, so that the gate line 112 (k + 1) and the source terminal of the drive transistor T3 are not conductive. It becomes. Accordingly, the potential difference between V1 and V2 at this time is held in the capacitive element CS.
  • the gate pulse Gate [k + 1] in the next row is not limited to the drive timing of FIG. 8 as long as the reset pulse Rst is at a high level, that is, at least during the reset period.
  • the display device 200 of the present embodiment may detect the threshold voltage over a plurality of horizontal periods as in the modification of the first embodiment.
  • FIG. 9 is a timing chart showing the operation of the display device 200 when the threshold voltage is detected over a plurality of horizontal periods.
  • the period required for resetting is one horizontal period compared to the timing chart shown in FIG. In this way, by performing the preliminary operation for threshold voltage detection in half the period, the Vth detection period can be made longer than in the first embodiment, so that highly accurate threshold voltage compensation is performed. Can be realized.
  • the Vth detection period is 5 horizontal periods.
  • the horizontal period required for the Vth detection period is not limited to 5 horizontal periods, and is sufficient for detecting the threshold voltage Vth (TFT) of the drive transistor T3. It is sufficient if sufficient time is secured.
  • Embodiment 3 The display device of Embodiment 3 is substantially the same as the display device 100 of Embodiment 1, except that one of the source terminal and the drain terminal of the reset transistor and the other end of the capacitor are connected to the source terminal of the drive transistor and The difference is that it is connected to one of the drain terminals via a predetermined element.
  • each of the plurality of light-emitting pixels included in the display device of this embodiment is further compared with each of the plurality of light-emitting pixels included in the display device 100 of Embodiment 1, and further includes a gate terminal and a source terminal. And one of the source terminal and the drain terminal is connected to one of the source terminal and the drain terminal of the reset transistor and the other end of the capacitor, and the other end of the source terminal and the drain terminal is connected to the drive transistor.
  • a second switching transistor connected to one of the source terminal and the drain terminal;
  • FIG. 10 is a circuit diagram illustrating a detailed configuration of the light-emitting pixel included in the display device according to the third embodiment.
  • a signal line 111, a gate line 112, a reset line 113, and a merge line 301 corresponding to the light emitting pixel 310 are also shown.
  • FIG. 10 illustrates a structure of one light-emitting pixel among a plurality of light-emitting pixels included in the display device according to this embodiment, but the other light-emitting pixels have the same structure.
  • the display device has substantially the same configuration as the display device 100 illustrated in FIG. 1, but has a light emitting pixel 310 instead of the light emitting pixel 110 as compared with the display device 100, and The difference is that a merge line 301 is provided corresponding to each row of the light emitting pixels 310.
  • the merge line 301 is provided corresponding to each row of the plurality of light emitting pixels 310, and a merge pulse Merge is output from the row scanning unit 120.
  • the row scanning unit in the display device of the present embodiment further outputs a merge pulse Merge to each merge line 301 as compared to the row scanning unit 120 in the display device 100 of the first embodiment.
  • a plurality of light emitting pixels 310 are sequentially scanned in units of rows.
  • the light-emitting pixel 310 compared to the light-emitting pixel 110 included in the display device 100 according to Embodiment 1, one of the source terminal and the drain terminal of the reset transistor T2 and the other end of the capacitor CS are connected to the drive transistor T3. The difference is that the source terminal is connected via a merge transistor Tm.
  • the light emitting pixel 310 further includes a merge transistor Tm and a merge capacitor CSm, as compared with the light emitting pixel 110.
  • the merge transistor Tm is the second switching transistor of the present invention, and includes a gate terminal, a source terminal, and a drain terminal, and one of the source terminal and the drain terminal is one of the source terminal and the drain terminal of the reset transistor T2.
  • an n-type TFT is connected to the other end of the capacitive element CS, and the other of the source terminal and the drain terminal is connected to the source terminal of the driving transistor T3.
  • the gate terminal of the merge transistor Tm is connected to the merge line 301. That is, the merge transistor Tm is turned on and off according to the merge pulse Merge supplied to the merge line 301.
  • the merge capacitor CSm is inserted between the connection point of the merge transistor Tm, the capacitor element CS, and the reset transistor T2 and the power supply line of the voltage VSS.
  • the display device having a plurality of light-emitting pixels 310 has a pixel that is a current that the driving transistor T3 supplies to the light-emitting element OLED due to variations in parasitic capacitance of the light-emitting element OLED.
  • Current fluctuation can be suppressed.
  • the signal line driving unit 130 supplies the same signal voltage to the plurality of light emitting pixels 310, it is possible to suppress variation in potential at the connection point between the light emitting element OLED and the driving transistor T3 of each light emitting pixel 310. It becomes. Therefore, the influence of the parasitic capacitance of the light emitting element OLED can be reduced, and the light emitting element OLED can be caused to emit light with accurate light emission luminance according to the signal voltage.
  • FIG. 11 is a timing chart showing the operation of the display device according to the third embodiment.
  • the vertical axis of the figure shows a merge pulse Merge supplied to the merge line 301 as compared with the timing chart of FIG.
  • V2 is the potential of the source terminal of the drive transistor T3.
  • V2 is a connection between one of the source terminal and the drain terminal of the reset transistor T2 and the other end of the capacitor CS. This is the potential of the point.
  • the waveforms of the gate pulse Gate, the reset pulse Rst, and the signal line voltage Sig are the gate pulse Gate, the reset pulse Rst, and the signal line of the display device 100 according to the first embodiment shown in FIG. It is the same as the waveform of the voltage Sig. Therefore, the description will be focused on the merge pulse Merge and the waveforms of V1 and V2.
  • the merge transistor Tm is turned on by setting the merge pulse Merge to the high level. Since the merge transistor Tm is on, the source terminal of the drive transistor T3 and the other end of the capacitive element CS are electrically connected. That is, the light emitting pixel 310 is equivalent to the light emitting pixel 110 in the period up to time t5.
  • FIG. 12 is a diagram schematically showing a current flow in the light emitting pixel 310 of the display device according to the third embodiment.
  • the high level voltage of the merge pulse Merge is VMerge (H)
  • the low level voltage of the merge pulse Merge is VMerge (L).
  • the operation of the light emitting pixel 310 up to the time t5 is the same as the operation of the light emitting pixel 110 shown in FIG. 3 up to the time t5, and the current flow in FIGS. This is the same as the current flow shown in 4 (a) to (c).
  • the merge pulse Merge falls from the high level to the low level.
  • the merge transistor Tm is turned off.
  • the timing at which the merge pulse Merge falls from the high level to the low level may be any time after the potential difference between V1 and V2 becomes Vth (TFT) and the current flowing through the driving transistor T3 stops. The timing shown in FIG. Not exclusively.
  • the signal voltage is applied to the signal line 111 while the merge pulse Merge is kept at the low level.
  • V2 which is the potential of the other end of the capacitive element CS is the signal voltage applied to one end of the capacitive element CS and the power supply line connected to the merge capacitor CSm.
  • the potential of V2 is the signal voltage applied to V1, the power supply connected to the cathode of the light emitting element OLED. It is determined by the line voltage VSS, the capacitance Cs of the capacitive element CS, and the parasitic capacitance of the light emitting element OLED. That is, the potential of V2 is defined by the capacitance Cs of the capacitive element CS and the parasitic capacitance of the light emitting element OLED.
  • the parasitic capacitance between the anode and the cathode of the light emitting element OLED varies for each light emitting element OLED, even when the same signal voltage is supplied to the plurality of light emitting pixels 110, the light emission between the light emitting pixels 110 is reduced.
  • the potential at the connection point between the element OLED and the drive transistor T3 is not the same, and varies. Therefore, the current supplied to the light emitting element OLED varies due to variations in potential at the connection point between the light emitting element OLED and the driving transistor T3.
  • the light emitting pixel 310 of the display device connects the other end of the capacitive element CS and the source terminal of the driving transistor T3 via the merge transistor Tm, and emits light during the period when the merge transistor Tm is off.
  • the influence of the parasitic capacitance of the light-emitting element OLED on the potential of V2 can be reduced.
  • the merge transistor Tm is off during the period in which the signal voltage is written to the light emitting pixel 310, the self-discharge current of the capacitive element CS can be suppressed. Therefore, the threshold value of the driving transistor T3 can be detected and corrected more accurately than the light emitting pixel in the display device 100 of the first embodiment.
  • a current according to the potential difference between the potential V1 and the potential V1 in which the influence of the parasitic capacitance of the light emitting element OLED is reduced flows through the light emitting element OLED in the writing period from time t6 to t7.
  • the influence of the parasitic capacitance of the light emitting element OLED is reduced, and a current that accurately corresponds to the signal voltage flows to the light emitting element OLED. Therefore, the light emitting element can emit light with high accuracy according to the signal voltage.
  • the merge transistor Tm is continuously turned on from time t3 to t4, which is a period for detecting the threshold value of the drive transistor T3, and is switched from on to off at time t5 after detection of the threshold value, and is the time for the writing period. It is continuously turned off from t6 to t7 and switched from off to on at time t8 after the writing period (after time t7).
  • each of the plurality of light-emitting pixels 310 included in the display device of this embodiment is further compared with each of the plurality of light-emitting pixels 110 included in the display device 100 of Embodiment 1, and further includes a gate terminal.
  • a source terminal and a drain terminal, and one of the source terminal and the drain terminal is connected to one of the source terminal and the drain terminal of the reset transistor T2 and the other end of the capacitor CS,
  • the other includes a merge transistor Tm connected to the source terminal of the drive transistor T3.
  • the influence of the parasitic capacitance of the light emitting element OLED can be prevented, and the light emitting element OLED can emit light with high accuracy according to the signal voltage.
  • the merge capacitor CSm is inserted between the connection point of the merge transistor Tm, the capacitor element CS, and the reset transistor T2 and the power supply line of the voltage VSS. Not only VSS but a fixed potential may be used.
  • the merge capacitor CSm may be inserted between the connection point of the merge transistor Tm, the capacitor element CS, and the reset transistor T2 and the power supply line of the voltage VDD.
  • the reset transistor T2 'shown in the light emitting pixel 210 of the display device of the second embodiment may be provided. That is, a reset transistor T2 'inserted between the gate line 112 corresponding to the next row of the light emitting pixel and the connection point of the capacitor element CS, the merge capacitor CSm, and the merge transistor Tm may be provided.
  • the threshold voltage is detected in one horizontal period.
  • the threshold voltage may be detected over a plurality of horizontal periods as in the modification of the second embodiment.
  • each of the first switching transistor and the reset transistor is an n-type transistor that is turned on when a pulse applied to the gate terminal is at a high level.
  • the polarity of the gate line and the reset line may be reversed.
  • the merge capacitor CSm is inserted between the connection point of the merge transistor Tm, the capacitor element CS, and the reset transistor T2 and the power supply line of the voltage VSS.
  • CSm is not necessarily connected to the power supply line.
  • the merge line CSm may be connected to the reset line by regarding the low-level output period of the reset line as a power supply line.
  • the display device according to the present invention is built in a thin flat TV as shown in FIG.
  • a thin flat TV capable of displaying images with high accuracy without luminance unevenness is realized.
  • the display device according to each of the above embodiments is typically realized as one LSI which is an integrated circuit.
  • Each processing unit included in the display device according to each embodiment may be individually made into one chip, or may be made into one chip so as to include some or all of them.
  • LSI is used, but depending on the degree of integration, it may be called IC, system LSI, super LSI, or ultra LSI.
  • circuit integration is not limited to LSI, and a part of the processing unit included in the display device can be integrated on the same substrate as the light emitting pixels. Moreover, you may implement
  • An FPGA Field Programmable Gate Array
  • a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.
  • a part of the function of the drive unit included in the display device according to each embodiment may be realized by a processor such as a CPU executing a program.
  • the present invention may be realized as a display device driving method including characteristic steps realized by the driving unit.
  • the present invention may be the above program or a recording medium on which the above program is recorded.
  • the program can be distributed via a transmission medium such as the Internet.
  • the display device is an active matrix type organic EL display device
  • the present invention may be applied to an organic EL display device other than the active matrix type, or a current drive type.
  • the present invention may be applied to a display device other than the organic EL display device using the light emitting element, or may be applied to a display device using a voltage driven light emitting element such as a liquid crystal display device.
  • the second half of each horizontal period is a threshold voltage detection period and the first half is a signal voltage writing period.
  • the duty ratio is not limited to 50%.
  • the writing period may be 10% of one horizontal period
  • the detection period may be 90% of one horizontal period.
  • the reset transistor T2 ′ of the light emitting pixel 110 in the m-th row is connected to the dummy gate line 201.
  • the reset transistor T2 ′ is connected to any one of the gate lines 112 from the first row to the m-th row. It may be connected.
  • a capacitive element may be provided between the source terminal of the driving transistor T3 and the power supply line.
  • the display device according to the present invention is particularly useful for application to a large screen active matrix type organic EL display panel combined with a TFT.
  • Display device 110 210, 310 Light emitting pixel 111 Signal line 112, 112 (k), 112 (k + 1) Gate line 113 Reset line 120 Row scanning unit 121 Gate line driving unit 122 Reset line driving unit 130 Signal line driving unit 140 Timing Control Unit 201 Dummy Gate Line 301 Merge Line CS Capacitor Element CSm Merge Capacitor OLED Light Emitting Element T1 Row Select Transistor T2, T2 ′ Reset Transistor T3 Drive Transistor Tm Merge Transistor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention porte sur un dispositif d'affichage qui comporte : une pluralité de pixels émettant de la lumière (110) qui sont agencés selon une matrice ; une ligne de grille (112) et une ligne de réinitialisation (113) qui correspondent à chacune des rangées ; et une ligne de signal (111) qui correspond à chacune des colonnes. Chacun des éléments émettant de la lumière (110) comporte : un élément électroluminescent (OLED) ; un transistor d'attaque (T3) qui alimente l'élément électroluminescent (OLED) avec un courant ; un transistor de sélection de colonne (T1) ; un transistor de réinitialisation (T2), la borne de grille étant connectée à une ligne de réinitialisation (113) et la borne de source et l'une des bornes de drain étant connectées à la borne de source du transistor d'attaque (T3) ; et un élément capacitif (CS) qui est introduit entre la borne de grille et la borne de source du transistor d'attaque (T3). La borne de source et l'autre borne de drain du transistor de réinitialisation (T2) sont connectées à la ligne de grille (112) qui correspond à l'une des rangées des pixels émettant de la lumière (110).
PCT/JP2010/002858 2009-05-22 2010-04-21 Dispositif d'affichage et son procédé de commande WO2010134263A1 (fr)

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US13/288,142 US8633874B2 (en) 2009-05-22 2011-11-03 Display device and method of driving the same

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KR20120022720A (ko) 2012-03-12
US8633874B2 (en) 2014-01-21
JP5562327B2 (ja) 2014-07-30
US20120050350A1 (en) 2012-03-01
CN102388414B (zh) 2014-12-31
JPWO2010134263A1 (ja) 2012-11-08
KR101646812B1 (ko) 2016-08-08

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