WO2010103752A1 - 発光ダイオード、発光ダイオードランプ及び照明装置 - Google Patents
発光ダイオード、発光ダイオードランプ及び照明装置 Download PDFInfo
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- WO2010103752A1 WO2010103752A1 PCT/JP2010/001476 JP2010001476W WO2010103752A1 WO 2010103752 A1 WO2010103752 A1 WO 2010103752A1 JP 2010001476 W JP2010001476 W JP 2010001476W WO 2010103752 A1 WO2010103752 A1 WO 2010103752A1
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
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Definitions
- the present invention relates to a light emitting diode, a light emitting diode lamp, and a lighting device, and more particularly, to a high-power red light emitting diode, a light emitting diode lamp and a lighting device using the same.
- This application claims priority based on Japanese Patent Application No. 2009-056780 filed in Japan on March 10, 2009, and Japanese Patent Application No. 2009-089300 filed on April 1, 2009 in Japan. , The contents of which are incorporated herein.
- a compound semiconductor LED provided with a light emitting layer made of aluminum phosphide, gallium, indium (composition formula (Al X Ga 1-X ) Y In 1-YP ; 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1)
- the wavelength of the light emitting layer having the composition of Ga 0.5 In 0.5 P is the longest, and the peak wavelength obtained in this light emitting layer is around 650 nm. For this reason, in the region having a wavelength longer than 655 nm, it has been difficult to put the compound semiconductor LED into practical use and to increase the brightness.
- a light emitting unit including a light emitting layer made of (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1) generally emits light emitted from the light emitting layer.
- a gallium arsenide (GaAs) single crystal substrate that is optically opaque and not mechanically strong. Therefore, research has been conducted for the purpose of obtaining a brighter visible LED and for the purpose of further improving the mechanical strength of the element. That is, after removing an opaque substrate material such as GaAs, a so-called junction type LED in which a support layer made of a transparent material that can transmit light emission and has higher mechanical strength than a conventional material is joined again.
- Patent Document 4 The technology to constitute is disclosed (for example, refer to Patent Document 4).
- a light-emitting layer having a strain has been studied.
- a light-emitting diode a light-emitting layer having a strain has not been put into practical use (for example, Patent Document 5). reference).
- the lighting method it has been studied to reduce the power consumption by using a high-speed pulse method, and a light-emitting diode with a high response speed is required.
- Recent research has confirmed that plant growth lighting can be energy-saving by turning off the light during the photosynthesis reaction time after irradiation.
- the response speed of the light emitting diode is 1000 ns or less, preferably 100 ns or less.
- the light emitting layer composed of (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1) having high luminous efficiency, it matches the lattice constant of the GaAs substrate used for epitaxial growth.
- the composition of the light emitting layer having the longest wavelength (small band gap) is Ga 0.5 In 0.5 P.
- the emission wavelength of this light emitting layer is 650 nm, and a longer wavelength of 650 nm or more cannot be achieved.
- a technique for increasing the output has not been established.
- the emission intensity at 700 nm has an emission spectrum of less than 10% with respect to the intensity of the peak emission wavelength.
- the present invention has been made in view of the above circumstances, and provides a light-emitting diode having an emission wavelength of 655 nm or more, excellent monochromaticity, high output, and / or high efficiency, and high response speed. For the purpose. It is another object of the present invention to provide a light-emitting diode lamp suitable for plant growing lighting and a lighting device equipped with the light-emitting diode lamp.
- the strain adjusting layer is transparent with respect to an emission wavelength and has a lattice constant smaller than lattice constants of the strained light emitting layer and the barrier layer.
- the above-mentioned item 1 is characterized in that the composition formula of the strained light emitting layer is Ga Y In 1-YP (where Y is a numerical value satisfying 0.39 ⁇ Y ⁇ 0.45).
- the light emitting diode as described.
- the composition formula of the barrier layer is (Al X Ga 1-X ) Y In 1-YP (where X and Y are 0.3 ⁇ X ⁇ 0.7 and 0.48 ⁇ , respectively) 5.
- the light emitting unit has a cladding layer on one or both of the upper surface and the lower surface of the strained light emitting layer, and the composition formula of the cladding layer is (Al X Ga 1-X ) Y In 1-YP (here Wherein X and Y are numerical values satisfying 0.5 ⁇ X ⁇ 1 and 0.48 ⁇ Y ⁇ 0.52, respectively.
- the composition formula of the strain adjustment layer is (Al X Ga 1-X ) Y In 1-YP (where X and Y are 0 ⁇ X ⁇ 1 and 0.6 ⁇ Y ⁇ 1 respectively)
- the composition formula of the strain adjusting layer is Al X Ga 1-X As 1-Y P Y (where X and Y satisfy 0 ⁇ X ⁇ 1 and 0.6 ⁇ Y ⁇ 1 respectively) 7.
- first and second electrodes provided on the light extraction surface side of the compound semiconductor layer; 15.
- the first and second electrodes are ohmic electrodes.
- the light extraction surface includes a rough surface.
- a light-emitting diode lamp comprising the light-emitting diode according to any one of the preceding items 1 to 21.
- An illuminating device comprising the light-emitting diode lamp according to item 22 or 23.
- the light-emitting diode according to the present invention has a composition formula of (Al X Ga 1-X ) Y In 1-Y P (where X and Y are 0 ⁇ X ⁇ 0.1 and 0.39 ⁇ Y ⁇ 0, respectively). And a compound semiconductor layer including a light emitting portion having a strained light emitting layer.
- AlGaInP as the material of the strained light emitting layer, the light emission efficiency and response speed from the light emitting part can be improved.
- a light emitting diode having an emission wavelength of 655 nm or more can be obtained.
- a strain adjusting layer is provided on the light emitting portion. Since this strain adjustment layer is transparent to the emission wavelength, it can be a high-power and / or high-efficiency light-emitting diode without absorbing light emitted from the light-emitting portion. Further, since the strain adjustment layer has a lattice constant smaller than that of the GaAs substrate, the occurrence of warpage of the semiconductor compound layer can be suppressed. Thereby, since the variation in the strain amount of the strained light emitting layer is reduced, a light emitting diode excellent in monochromaticity can be obtained.
- the present invention it is possible to provide a light emitting diode having an emission wavelength of 655 nm or more, excellent monochromaticity, high output, and / or high efficiency, and high response speed.
- a high-power light-emitting diode having a light emission efficiency of about 4 times or more as compared with a conventional AlGaAs-based light-emitting diode.
- the light-emitting diode lamp of the present invention includes the light-emitting diode having an emission wavelength of 655 nm or more, excellent monochromaticity, high output and / or high efficiency, and high response speed. Therefore, it is possible to provide a light emitting diode lamp suitable for lighting for plant growth and a lighting device including the light emitting diode lamp.
- FIG. 2 is a schematic cross-sectional view taken along line A-A ′ shown in FIG. 1 of a light-emitting diode lamp using a light-emitting diode according to an embodiment of the present invention. It is a top view of the light emitting diode which is one Embodiment of this invention.
- FIG. 4 is a schematic cross-sectional view of the light emitting diode according to the embodiment of the present invention, taken along line B-B ′ shown in FIG. 3.
- FIG. 1 and 2 are diagrams for explaining a light-emitting diode lamp using a light-emitting diode according to an embodiment to which the present invention is applied.
- FIG. 1 is a plan view, and FIG. It is sectional drawing along the A 'line.
- one or more light-emitting diodes 1 are mounted on the surface of a mount substrate 42. More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42.
- the n-type ohmic electrode 4 that is the first electrode of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding).
- the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46.
- a third electrode 6 is provided on the surface of the light emitting diode 1 opposite to the surface on which the n-type and p-type ohmic electrodes 4 and 5 are provided.
- the light emitting diode 1 is connected to the n electrode terminal 43 by the electrode 6 and fixed to the mount substrate 42.
- the n-type ohmic electrode 4 and the third electrode 6 are electrically connected by the n-pole electrode terminal 43 so as to be equipotential or substantially equipotential.
- the surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general epoxy resin 47.
- the light emitting diode 1 of the present embodiment is a light emitting diode in which a compound semiconductor layer 2 and a functional substrate 3 are joined.
- the light emitting diode 1 includes an n-type ohmic electrode (first electrode) 4 and a p-type ohmic electrode (second electrode) 5 provided on the main light extraction surface, the compound semiconductor layer 2 of the functional substrate 3, and the like.
- a third electrode 6 provided on the opposite side to the joint surface.
- the main light extraction surface in this embodiment is a surface of the compound semiconductor layer 2 opposite to the surface to which the functional substrate 3 is attached.
- the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 has a structure in which a pn junction type light emitting portion 7 and a strain adjustment layer 8 are sequentially laminated as shown in FIG.
- a known functional layer can be appropriately added to the structure of the compound semiconductor layer 2.
- the compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.
- the light emitting unit 7 is configured by sequentially laminating at least a p-type lower cladding layer 9, a light emitting layer 10, and an n-type upper cladding layer 11 on a strain adjustment layer 8. That is, the light emitting unit 7 includes a lower cladding (clad) disposed on the lower side and the upper side of the light emitting layer 10 in order to “confine” light emission in the light emitting layer 10 and carriers that cause radiative recombination. ) It is preferable to obtain a so-called double hetero (abbreviation: DH) structure including the layer 9 and the upper cladding layer 11 in order to obtain high intensity light emission.
- DH double hetero
- the light emitting layer 10 preferably has a well structure in order to control the light emission wavelength of a light emitting diode (LED). That is, the light emitting layer 10 has a multilayer structure of a strained light emitting layer 12 and a barrier layer (also referred to as a barrier layer) 13 having a strained light emitting layer (also referred to as a well layer or a well layer) 12 at both ends. Is preferred.
- the layer thickness of the light emitting layer 10 is preferably in the range of 0.02 to 2 ⁇ m.
- the conductivity type of the light emitting layer 10 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the light emission efficiency, it is desirable to have an undoped crystallinity with a good crystallinity or a carrier concentration of less than 3 ⁇ 10 17 cm ⁇ 3 .
- the strained light emitting layer 12 has a composition of (Al X Ga 1-X ) Y In 1-Y P (where X and Y are values satisfying 0 ⁇ X ⁇ 1, and 0 ⁇ Y ⁇ 1, respectively). have. X is preferably 0.1 or less, and more preferably 0. Y is preferably in the range of 0.37 to 0.46, and more preferably in the range of 0.39 to 0.45.
- the emission wavelength can be set in the range of 655 to 675 nm.
- the strained light emitting layer 12 has a structure having a lattice constant different from that of the other structural portions, and strain is generated in the compound semiconductor layer 2. For this reason, there is a possibility that an adverse effect of generation of crystal defects may occur.
- the layer thickness of the strained light emitting layer 12 is preferably in the range of 8 to 30 nm.
- the layer thickness of the strained light emitting layer 12 is desirably 8 nm or more in consideration of the variation of the layer thickness so that the quantum effect does not appear.
- 10 nm or more is preferable.
- the thickness of the strained light emitting layer 12 exceeds 30 nm, the amount of strain becomes too large, and therefore crystal defects and surface abnormalities tend to occur, which is not preferable.
- the barrier layer 13 has a composition of (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1).
- X is preferably in the range of 0.3 to 0.7, more preferably in the range of 0.4 to 0.6.
- Y is preferably in the range of 0.48 to 0.52, more preferably in the range of 0.49 to 0.51.
- the lattice constant of the barrier layer 13 can be equal to or smaller than that of the GaAs substrate.
- the barrier layer 13 is preferably thicker than the strained light emitting layer 12. Thereby, the luminous efficiency of the strained light emitting layer 12 can be increased. Moreover, it is necessary to optimize the light emission efficiency by the barrier layer 13 and relieve the strain generated in the strained light emitting layer 12. Therefore, the barrier layer 13 preferably has a layer thickness of at least 15 nm, more preferably 20 nm or more. On the other hand, when the thickness of the barrier layer 13 exceeds 50 nm, it becomes close to the wavelength of the emission wavelength, and optical influences such as light interference and Bragg reflection occur. Therefore, the barrier layer 13 preferably has a layer thickness of 50 nm or less, more preferably 40 nm or less. As described above, when the strained light emitting layer 12 is thinner and the barrier layer 13 is thicker, the strain of the strained light emitting layer 12 is absorbed by the barrier layer 13 and crystal defects are generated in the strained light emitting layer 12. Hateful.
- the number of pairs in which the strained light emitting layer 12 and the barrier layer 13 are alternately stacked is not particularly limited, but is 8 pairs or more and 40 pairs or less. Is preferred. That is, the light emitting layer 10 preferably includes 8 to 40 strained light emitting layers 12. Here, as a suitable range of the luminous efficiency of the light emitting layer 10, the strained light emitting layer 12 is eight or more layers. On the other hand, since the strained light emitting layer 12 and the barrier layer 13 have a low carrier concentration, the number of pairs increases the forward voltage (VF). For this reason, it is preferable that it is 40 pairs or less, and it is more preferable that it is 30 pairs or less.
- VF forward voltage
- the strain of the strained light emitting layer 12 is a stress generated in the light emitting layer 10 because the lattice constants of the epitaxial growth substrate and the light emitting portion 7 are different. For this reason, when the number of pairs in which the strained light emitting layers 12 and the barrier layers 13 are alternately stacked, that is, the number of the strained light emitting layers 12 included in the light emitting layer 10 exceeds the above range, the light emitting layer 10 becomes distorted. A crystal defect occurs without being able to endure, and problems such as deterioration of the surface state and reduction in luminous efficiency occur.
- the light-emitting layer 10 (light-emitting portion 7) preferably has a peak emission wavelength in the emission spectrum of 655 to 675 nm, preferably in the range of 660 to 670 nm, by defining the material of the strained light-emitting layer 12 in the above range. More preferably. This is because the emission wavelength in the above range is one of the emission wavelengths suitable for light sources for plant growth (photosynthesis) and has high reaction efficiency for photosynthesis.
- the half width needs to be narrow.
- the half-value width is narrowed near the quantization condition that may cause a large wavelength variation, and as a result, the half-value width of the emission spectrum is preferably in the range of 10 to 40 nm.
- the emission intensity of the emission spectrum at an emission wavelength of 700 nm is less than 10% of the emission intensity at the peak emission wavelength.
- the response speed (rise time: Tr) of the light emitting layer 10 is preferably 100 ns or less.
- the light-emitting diode 1 having the light-emitting layer 10 having such characteristics can be suitably used as illumination (light-emitting diode lamp or illumination device equipped with a light-emitting diode lamp) used for promoting photosynthesis for plant growth.
- the lighting device includes a substrate on which wiring, through-holes, etc. are formed, a plurality of light-emitting diode lamps attached to the surface of the substrate, and a light-emitting diode lamp having a concave cross-sectional shape at the bottom inside the recess.
- a lighting device including at least a reflector or a shade configured to be attached.
- the illumination device 100 illustrated in FIG. 10 is schematically configured from a circuit board 200, a light-emitting diode lamp 41 mounted on the circuit board 200, and a reflector 400 installed on the circuit board 200.
- the circuit board 200 is generally configured by a substrate body made of aluminum, an insulating layer laminated on the substrate body, and a wiring pattern made of a conductor such as Cu formed on the insulating layer. Further, the circuit board 200 has one side 200a protruding from the reflector 400, whereby a part of the surface of the circuit board 200 is exposed.
- the wiring pattern is composed of a pair of extraction electrode patterns and six terminal electrode patterns extending from one end side of each extraction electrode pattern toward substantially the center of the circuit board 200.
- Three light emitting diode lamps 41 are connected to each of the terminal electrode patterns, whereby the light emitting diode lamps 41 are connected in parallel to each other.
- the other end side of each of the extraction electrode patterns extends to the side 200a side of the circuit board 200 and is exposed, and this exposed portion serves as an external terminal 230c.
- the light emitting diode lamps 41 have a total of three light emitting diode lamps 41 mounted almost at the center of the circuit board 200. It is arranged on a straight line. The positive electrode and the negative electrode of the light emitting diode lamp 41 are electrically connected to the terminal electrode pattern.
- the reflector 400 is schematically configured by providing a reflective surface 420 on a substantially cubic reflector body 410 made of, for example, aluminum or an aluminum alloy.
- the reflecting surface 420 is composed of a pair of semi-rotating paraboloids 420a and a parabolic column surface 420b disposed between the semi-rotating paraboloids 420a.
- the thickness of the reflector body 410 in other words, the height of the reflecting surface 420 along the light emission direction is appropriately set depending on the size of the light emitting diode lamp 41 and the interval between the light emitting diode lamps 41, for example, 5.0 mm. It is preferable to set in the range of ⁇ 20.0 mm.
- FIG. 11 is a perspective view showing another example of the lighting device of the present embodiment.
- An illumination device 101 illustrated in FIG. 11 is schematically configured from a circuit board 102, a light-emitting diode lamp 41 mounted on the circuit board 102, and a reflector 104 installed on the circuit board 102.
- the illumination device 101 of this example includes a reflector 104 having 30 reflecting surfaces 142 in total of 10 rows ⁇ 3 rows.
- three light-emitting diode lamps 41 are provided for each reflecting surface inside each reflecting surface 142.
- the entire lighting device 101 includes 90 light emitting diode lamps 41 in total.
- the detailed shape of the reflecting surface 142 is substantially the same as in the case of the previous lighting device 100, and includes a pair of semi-rotating paraboloids and a parabolic column surface disposed between the semi-rotating paraboloids. It is configured.
- composition, the layer thickness, and the number of layers of the structure of the light emitting layer 10 can be appropriately selected so as to satisfy the above characteristics.
- the lower clad layer 9 and the upper clad layer 11 are provided on the lower surface and the upper surface of the light emitting layer 10, respectively, as shown in FIG. Specifically, the lower cladding layer 9 is provided on the lower surface of the light emitting layer 10, and the upper cladding layer 11 is provided on the upper surface of the light emitting layer 10.
- a material having a band gap larger than that of the strained light emitting layer 12 of the light emitting layer 10 is preferable, and a material having a band gap larger than that of the barrier layer 13 is more preferable.
- the material include a compound having a composition of Al X Ga 1-X As, (Al X Ga 1-X ) Y In 1-Y P (where X and Y are 0 ⁇ X ⁇ 1 respectively) And a compound satisfying 0 ⁇ Y ⁇ 1).
- the lower limit of the value of X is preferably 0.3 or more, and more preferably 0.5 or more.
- the value of Y is preferably in the range of 0.48 to 0.52, more preferably in the range of 0.49 to 0.51.
- the lower cladding layer 9 and the upper cladding layer 11 are configured to have different polarities.
- the carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 11 can be in a known suitable range, and the conditions are preferably optimized so that the light emission efficiency of the light emitting layer 10 is increased. Further, by controlling the composition of the lower clad layer 9 and the upper clad layer 11, the warpage of the compound semiconductor layer 2 can be reduced.
- the lower cladding layer 9 for example, p-type (Al X Ga 1-X ) Y In 1-Y P doped with Mg (where X and Y are 0.3 ⁇ X ⁇ It is desirable to use a semiconductor material having a composition of 1 and 0 ⁇ Y ⁇ 1.
- the carrier concentration is preferably in the range of 2 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3
- the layer thickness is preferably in the range of 0.5 to 5 ⁇ m.
- the upper clad layer 11 for example, n-type (Al X Ga 1-X ) Y In 1- YP doped with Si (where X and Y are 0.3 ⁇ X ⁇ 1, respectively) And a semiconductor material having a composition of 0 ⁇ Y ⁇ 1) is desirable.
- the carrier concentration is preferably in the range of 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3
- the layer thickness is preferably in the range of 0.5 to 2 ⁇ m.
- the polarities of the lower cladding layer 9 and the upper cladding layer 11 can be selected in consideration of the element structure of the compound semiconductor layer 2.
- each intermediate layer is preferably composed of a semiconductor material having a band gap between the two layers.
- a contact layer for lowering the contact resistance of the ohmic electrode a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely
- a known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.
- the strain adjustment layer 8 is provided below the light emitting unit 7.
- the strain adjusting layer 8 is provided to alleviate strain generated by the strained light emitting layer 12 when the compound semiconductor layer 2 is epitaxially grown on the GaAs substrate.
- the strain adjustment layer 8 is transparent to the emission wavelength from the light emitting unit 7 (light emitting layer 10). Further, the strain adjustment layer 8 has a lattice constant smaller than that of the strained light emitting layer 12 and the barrier layer 13. Furthermore, the strain adjustment layer 8 has a lattice constant smaller than that of the GaAs substrate used for forming the compound semiconductor layer 2 (formation by epitaxial growth).
- each lattice constant is A ⁇ B ⁇ C.
- the strain adjustment layer 8 is a numerical value satisfying (Al X Ga 1-X) Y In 1-Y P ( where, X and Y are each 0 ⁇ X ⁇ 1, and 0.6 ⁇ Y ⁇ 1 A material having a composition of) can be applied.
- X depends on the element structure of the compound semiconductor layer 2, it is preferably 0.5 or less and more preferably 0 because a material having a low Al concentration is chemically stable.
- it is preferable that the said lower limit of Y is 0.6 or more.
- the strain adjusting effect of the strain adjusting layer 8 becomes smaller when the value of Y is smaller.
- the value of Y is preferably 0.6 or more. More preferably, it is 0.8 or more.
- the strain adjusting layer 8 is transparent to the emission wavelength, and Al X Ga 1-X As 1-Y P Y (where X and Y are 0 ⁇ X ⁇ 1 and 0.6, respectively).
- a group III-V semiconductor material having a composition satisfying ⁇ Y ⁇ 1 can also be preferably used.
- the lattice constant varies depending on the value of Y. The larger the Y value, the smaller the lattice constant. Further, since the transparency with respect to the emission wavelength is related to both the values of X and Y, the values of X and Y may be selected so as to be a transparent material.
- the strain adjustment layer 8 it is preferable to use GaP, preferably, for example, Mg-doped p-type GaP.
- This GaP is most suitable as a material for the strain adjusting layer 8 from the viewpoint of productivity and stability because it requires no composition adjustment and has a large strain adjusting effect.
- the strain adjustment layer 8 Since the strain adjustment layer 8 has a lattice constant smaller than the lattice constant of the GaAs substrate which is the substrate used when the compound semiconductor layer 2 is epitaxially grown, variation in the amount of strain included in the strained light emitting layer 12 is alleviated. It has a function to do. For this reason, the provision of the strain adjustment layer 8 has the effect of uniforming the characteristics such as the emission wavelength and preventing the occurrence of crystal defects such as cracks.
- the thickness of the strain adjusting layer 8 is preferably in the range of 0.5 to 20 ⁇ m, and more preferably in the range of 3 to 15 ⁇ m. When the layer thickness is less than 0.5 ⁇ m, it is not sufficient to alleviate the variation in the strain amount of the strained light emitting layer 12, and when the layer thickness exceeds 20 ⁇ m, the growth time becomes long and the manufacturing cost increases. Absent.
- the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the strain adjusting layer 8, the light-emitting diode 1 having a small in-plane wavelength distribution can be manufactured. Further, even in the case where the functional substrate 3 and the compound semiconductor layer 2 are joined as in the present embodiment, if the warpage of the compound semiconductor layer 2 is large, a problem such as cracking occurs. It is desirable to reduce the warpage of the layer 2.
- the lattice constant of the strain adjustment layer 8 is on the side smaller than the lattice constant of the reference GaAs substrate. This state is defined as ⁇ (minus) distortion.
- the lattice constant of the strained light emitting layer 12 in the light emitting layer 10 is on the larger side than the lattice constant of the reference GaAs substrate. This is defined as + (plus) strain.
- the presence of ⁇ strain caused by the strain adjusting layer 8 has an effect of reducing the variation of + strain that needs to be introduced into the strained light emitting layer 12 in order to increase the emission wavelength.
- the emission wavelength of the strained light emitting layer 12 is determined by the layer thickness, composition, and strain amount of the strained light emitting layer 12. As described above, since there are many elements that affect the light emission wavelength of the strained light emitting layer 12, there is a tendency that the variation in wavelength tends to increase due to the synergistic effect of the variation of each element.
- the thickness of the strained light emitting layer 12 is preferably a thin film of 30 nm or less, but it is difficult to control the layer thickness uniformly because it is a thin film. Since there is a correlation between the layer thickness and the strain amount to be introduced, the strain amount to be introduced varies as the layer thickness of the strained light emitting layer 12 varies, and as a result, the emission wavelength of the strained light emitting layer 12 varies. Therefore, when forming the compound semiconductor layer 2, by providing the strain adjustment layer 8 above the light emitting portion 7 including the strained light emitting layer 12 having + strain (below the light emitting portion 7 in FIG.
- the conventional light emitting diode without the strain adjusting layer 8 has a large variation in characteristics such as the emission wavelength, and thus cannot satisfy the required quality.
- the light emitting diode 1 of the present embodiment has an element structure in which the strain adjustment layer 8 is provided below the light emitting portion 7. As a result, the strain amount of the strained light emitting layer 12 required for increasing the wavelength is made uniform in the light emitting layer 10, and variations in the light emission wavelength and output characteristics are reduced. Moreover, the surface state of the compound semiconductor layer 2 is also improved.
- the functional substrate 3 is bonded to the strain adjustment layer 8 side constituting the compound semiconductor layer 2.
- This functional substrate 3 has sufficient strength to mechanically support the light emitting unit 7 and has a wide band for allowing the light emitted from the light emitting unit 7 to pass therethrough. It is made of a material that is optically transparent to the wavelength.
- III-V group compound semiconductor crystal such as gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), II-VI such as zinc sulfide (ZnS) and zinc selenide (ZnSe)
- GaP gallium phosphide
- AlGaAs aluminum gallium arsenide
- GaN gallium nitride
- II-VI such as zinc sulfide (ZnS) and zinc selenide (ZnSe)
- a group compound semiconductor crystal, a group IV semiconductor crystal such as hexagonal or cubic silicon carbide (SiC)
- an insulating substrate such as glass or sapphire, GaP or the like is preferable.
- a functional substrate having a highly reflective surface on the bonding surface can also be selected.
- a metal substrate or an alloy substrate such as silver, gold, copper, or aluminum on the surface, or a composite substrate in which a metal mirror structure is formed on a semiconductor can be selected. It is most desirable to select from the same material as the strain adjustment layer that is not affected by the strain caused by bonding.
- the functional substrate 3 preferably has a thickness of, for example, about 50 ⁇ m or more in order to support the light emitting portion 7 with sufficient mechanical strength. In order to facilitate the mechanical processing of the functional substrate 3 after bonding to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 ⁇ m. That is, the functional substrate 3 is optimally composed of an n-type GaP substrate having a thickness of about 50 ⁇ m or more and about 300 ⁇ m or less.
- the side surface of the functional substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2.
- the inclined surface 3b is inclined inward with respect to the main light extraction surface.
- the light emitted from the light emitting layer 10 to the functional substrate 3 side can be efficiently extracted to the outside.
- part of the light emitted from the light emitting layer 10 to the functional substrate 3 side is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b.
- the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a.
- the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.
- the angle ⁇ formed by the inclined surface 3b and the surface parallel to the light emitting surface is preferably in the range of 55 degrees to 80 degrees.
- the width (thickness direction) of the vertical surface 3a is preferably in the range of 30 ⁇ m to 100 ⁇ m.
- the inclined surface 3b of the functional substrate 3 is preferably roughened.
- an effect of increasing the light extraction efficiency at the inclined surface 3b can be obtained. That is, by roughening the inclined surface 3b, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.
- the bonding interface between the compound semiconductor layer 2 and the functional substrate 3 may be a high resistance layer. That is, a high resistance layer (not shown) may be provided between the compound semiconductor layer 2 and the functional substrate 3. This high resistance layer exhibits a higher resistance value than that of the functional substrate 3, and when the high resistance layer is provided, the compound semiconductor layer 2 has a reverse direction from the strain adjustment layer 8 side to the functional substrate 3 side. It has a function of reducing current. Moreover, although the junction structure which exhibits voltage resistance with respect to the voltage of the reverse direction applied carelessly from the functional board
- the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are low-resistance ohmic contact electrodes provided on the main light extraction surface of the light-emitting diode 1.
- the n-type ohmic electrode 4 is provided above the upper cladding layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used.
- the p-type ohmic electrode 5 can use an alloy made of AuBe / Au on the exposed surface of the strain adjustment layer 8.
- the p-type ohmic electrode 5 is formed on the strain adjustment layer 8 as the second electrode. With such a configuration, the operating voltage can be lowered. In addition, by forming the p-type ohmic electrode 5 on the strain adjustment layer 8 made of p-type GaP, a good ohmic contact can be obtained, so that the operating voltage can be lowered.
- the polarity of the first electrode is n-type and the polarity of the second electrode is p-type.
- the first electrode is p-type, current diffusion is deteriorated, resulting in a decrease in luminance.
- the first electrode n-type current diffusion is improved, and high luminance of the light emitting diode 1 can be achieved.
- the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are arranged at diagonal positions as shown in FIG.
- the p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2. With such a configuration, the operating voltage can be lowered. Further, by enclosing the four sides of the p-type ohmic electrode 5 with the n-type ohmic electrode 4, the current easily flows in the four directions, and as a result, the operating voltage decreases.
- the n-type ohmic electrode 4 has a network such as a honeycomb or a lattice shape. With such a configuration, reliability can be improved. Further, by using the lattice shape, a current can be uniformly injected into the light emitting layer 10, and as a result, reliability can be improved.
- the n-type ohmic electrode 4 is preferably composed of a pad-shaped electrode (pad electrode) and a linear electrode (linear electrode) having a width of 10 ⁇ m or less. With such a configuration, high luminance can be achieved. Furthermore, by reducing the width of the linear electrode, the opening area of the light extraction surface can be increased, and high luminance can be achieved.
- the third electrode 6 is provided on the bottom surface of the functional substrate 3 and has a function of improving the brightness, conductivity, and stabilization of the mounting process.
- the material of the 3rd electrode 6 is not specifically limited, For example, a silver (Ag) paste with a high reflectance can be used.
- a stacked structure including a reflective layer, a barrier layer, and a connection layer can be used.
- metals having high reflectivity such as silver, gold, aluminum, platinum, and alloys of these metals can be used.
- An oxide film made of a transparent conductive film such as indium tin oxide (ITO) and indium zinc oxide (IZO) can be provided between the functional substrate 3 and the reflective layer.
- ITO indium tin oxide
- IZO indium zinc oxide
- barrier layer for example, a refractory metal such as tungsten, molybdenum, titanium, platinum, chromium, or tantalum can be used.
- connection layer for example, a low-melting eutectic metal such as AuSn, AuGe, or AuSi can be used.
- the third electrode 6 may be an ohmic electrode or a Schottky electrode. However, when the third electrode 6 forms an ohmic electrode on the bottom surface of the functional substrate 3, light from the light emitting layer 10 is emitted. It is preferable to use a Schottky electrode.
- the thickness of the third electrode 6 is not particularly limited, but is preferably in the range of 0.2 to 5 ⁇ m, more preferably in the range of 1 to 3 ⁇ m, and particularly preferably in the range of 1.5 to 2.5 ⁇ m. Here, if the thickness of the third electrode 6 is less than 0.2 ⁇ m, an advanced film thickness control technique is required, which is not preferable.
- the thickness of the third electrode 6 exceeds 5 ⁇ m, it is difficult to form a pattern, which is not preferable because of high cost.
- the thickness of the third electrode 6 be in the above range because both the stability of quality and the cost can be achieved.
- FIG. 7 is a cross-sectional view of an epi-wafer used for the light-emitting diode 1 of the present embodiment.
- FIG. 8 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.
- the compound semiconductor layer 2 includes a GaAs substrate 14, a buffer layer 15 made of GaAs, an etching stop layer (not shown) provided for selective etching, and a contact layer 16 made of n-type AlGaInP doped with Si.
- the n-type upper cladding layer 11, the light emitting layer 10, the p-type lower cladding layer 9, and the strain adjusting layer 8 made of Mg-doped p-type GaP are sequentially stacked.
- the GaAs substrate 14 a commercially available single crystal substrate manufactured by a known manufacturing method can be used.
- the surface of the GaAs substrate 14 on which the epitaxial growth is performed is desirably smooth.
- the plane orientation of the surface of the GaAs substrate 14 is easy to epi-grow, and it is preferable from the aspect of quality stability that it is off within ⁇ 20 ° from the (100) plane and (100) that are mass-produced.
- the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ⁇ 5 ° from the (100) direction to the (0-1-1) direction.
- the dislocation density of the GaAs substrate 14 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm ⁇ 2 or less, preferably 1,000 pieces cm ⁇ 2 or less are suitable.
- the GaAs substrate 14 may be n-type or p-type.
- the carrier concentration of the GaAs substrate 14 can be appropriately selected from desired electrical conductivity and element structure.
- the carrier concentration is preferably in the range of 1 ⁇ 10 17 to 5 ⁇ 10 18 cm ⁇ 3 .
- the carrier concentration is preferably in the range of 2 ⁇ 10 18 to 5 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the GaAs substrate 14 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 14 is thinner than an appropriate range, the compound semiconductor layer 2 may be broken during the manufacturing process. On the other hand, if the thickness of the GaAs substrate 14 is thicker than an appropriate range, the material cost increases. Therefore, when the substrate size of the GaAs substrate 14 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 ⁇ m is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 ⁇ m is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 ⁇ m is desirable.
- the warpage of the compound semiconductor layer 2 due to the strained light emitting layer 7 can be reduced.
- the in-plane wavelength distribution of the light emitting layer 10 can be reduced.
- the shape of the GaAs substrate 14 is not particularly limited to a circle, and may be a rectangle or the like.
- the buffer layer 15 is provided to alleviate a lattice mismatch between the semiconductor substrate 14 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 15 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected.
- the buffer layer 15 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 15 as with the GaAs substrate 14.
- the buffer layer 15 can also be a multilayer film made of a material different from that of the GaAs substrate 14 in order to reduce the propagation of defects.
- the thickness of the buffer layer 15 is preferably 0.1 ⁇ m or more, and more preferably 0.2 ⁇ m or more.
- the contact layer 16 is provided to reduce the contact resistance with the electrode.
- the material of the contact layer 16 is preferably a material having a band gap larger than that of the strained light emitting layer 12, and Al X Ga 1-X As or (Al X Ga 1-X ) Y In 1-YP (where X and Y are preferably materials having a composition of 0 ⁇ X ⁇ 1, and 0 ⁇ Y ⁇ 1.
- the lower limit value of the carrier concentration of the contact layer 16 is preferably 5 ⁇ 10 17 cm ⁇ 3 or more and more preferably 1 ⁇ 10 18 cm ⁇ 3 or more in order to reduce the contact resistance with the electrode.
- the upper limit value of the carrier concentration is desirably 2 ⁇ 10 19 cm ⁇ 3 or less at which the crystallinity is likely to decrease.
- the thickness of the contact layer 16 is preferably 0.5 ⁇ m or more, and optimally 1 ⁇ m or more.
- the upper limit value of the thickness of the contact layer 16 is not particularly limited, but is desirably 5 ⁇ m or less in order to bring the cost for epitaxial growth to an appropriate range.
- a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied.
- MBE molecular beam epitaxial method
- MOCVD method low pressure metal organic chemical vapor deposition method
- the MOCVD method which is excellent in mass productivity.
- the GaAs substrate 14 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film.
- Each layer constituting the compound semiconductor layer 2 can be laminated by setting eight or more GaAs substrates 14 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing them.
- the MOCVD apparatus a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.
- examples of the group III constituent material include trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) or the like can be used.
- a Mg doping material for example, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) or the like can be used.
- a Si doping material for example, disilane (Si 2 H 6 ) or the like can be used.
- phosphine (PH 3 ), arsine (AsH 3 ), or the like can be used as a raw material for the group V constituent element.
- each layer As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the strain adjustment layer 8, and 600 to 700 ° C. can be applied to the other layers. Furthermore, the carrier concentration, layer thickness, temperature conditions, and the like of each layer can be selected as appropriate.
- the compound semiconductor layer 2 thus produced has a good surface state with few crystal defects despite having the strained light emitting layer 12.
- the compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.
- the compound semiconductor layer 2 and the functional substrate 3 are bonded.
- the surface of the strain adjusting layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished.
- a functional substrate 3 to be attached to the surface of the mirror-polished strain adjusting layer 8 is prepared.
- the surface of the functional substrate 3 is polished to a mirror surface before being bonded to the strain adjustment layer 8.
- the compound semiconductor layer 2 and the functional substrate 3 are carried into a general semiconductor material pasting apparatus, and electrons are collided with both surfaces which are mirror-polished in a vacuum to make the neutral (neutral) Ar beam. Irradiate. Then, it can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 8).
- an n-type ohmic electrode 4 that is a first electrode and a p-type ohmic electrode 5 that is a second electrode are formed.
- the GaAs substrate 14 and the buffer layer 15 are selectively removed from the compound semiconductor layer 2 bonded to the functional substrate 3 with an ammonia-based etchant.
- the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 16.
- AuGe or Ni alloy / Pt / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography method to form an n-type ohmic electrode 4 shape is formed.
- the p-type ohmic electrode 5 is formed. Specifically, for example, AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography method to form the shape of the p-type ohmic electrode 5. . Thereafter, the low resistance n-type ohmic electrode 4 and p-type ohmic electrode 5 can be formed, for example, by alloying by heat treatment at 400 to 500 ° C. for 5 to 20 minutes.
- the third electrode 6 is formed on the side opposite to the bonding surface of the functional substrate 3 with the compound semiconductor layer 2.
- a silver paste is used as the third electrode 6, the silver paste is applied to the surface of the functional substrate.
- a laminated structure as a 3rd electrode, specifically, after forming 0.1 micrometer of ITO film
- a tungsten film having a thickness of 0.1 ⁇ m is formed on the reflective layer as a barrier layer.
- connection layer is formed on the barrier layer by sequentially forming A ⁇ of 0.5 ⁇ m, AuSn (eutectic: melting point 283 ° C.) of 1 ⁇ m, and Au of 0.1 ⁇ m.
- the third electrode 6 is formed by patterning into an arbitrary shape by a normal photolithography method.
- the functional substrate 3 and the third electrode 6 are in a Schottky contact with little light absorption.
- the shape of the functional substrate 3 is processed.
- V-shaped grooving is performed on the surface where the third electrode 6 is not formed.
- the inner surface of the V-shaped groove on the third electrode 6 side becomes an inclined surface 3b having an angle ⁇ formed with a surface parallel to the light emitting surface.
- dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips.
- the vertical surface 3a of the functional substrate 3 is formed by dicing at the time of chip formation.
- the method for forming the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in appropriate combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.
- the method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by a scribe break method or a dicing method.
- the manufacturing cost can be reduced. That is, since it is not necessary to provide a margin for chip separation and many light emitting diodes can be manufactured, the manufacturing cost can be reduced.
- the dicing method the light extraction efficiency from the vertical surface 3a is increased, and high brightness can be achieved.
- the crushed layer and dirt due to dicing are removed by etching with a sulfuric acid-hydrogen peroxide mixture as required. In this way, the light emitting diode 1 can be manufactured.
- a manufacturing method of the light emitting diode lamp 41 using the light emitting diode 1, that is, a mounting method of the light emitting diode 1 will be described.
- a predetermined number of light emitting diodes 1 are mounted on the surface of the mount substrate 42.
- the mounting substrate 42 and the light emitting diode 1 are aligned, and the light emitting diode 1 is disposed at a predetermined position on the surface of the mounting substrate 42.
- connection layer constituting the third electrode 6 and the n-electrode terminal 43 provided on the surface of the mount substrate 42 are eutectic metal bonded (eutectic metal die bond).
- the light emitting diode 1 is fixed to the surface of the mount substrate 42.
- the n-type ohmic electrode 4 of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding).
- the p-type ohmic electrode 5 of the light emitting diode 1 and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46.
- the surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general epoxy resin 47. In this way, the light emitting diode lamp 41 using the light emitting diode 1 is manufactured.
- a case where a voltage is applied to the n-electrode terminal 43 and the p-electrode terminal 44 in the light-emitting diode lamp 41 having the above configuration will be described.
- a forward voltage is applied to the light emitting diode lamp 41.
- the forward current first flows from the p-type electrode terminal 44 connected to the anode to the p-type ohmic electrode 5 through the gold wire 46.
- the p-type ohmic electrode 5 sequentially flows from the strain adjustment layer 8, the lower cladding layer 9, the light emitting layer 10, the upper cladding layer 11, and the n-type ohmic electrode 4.
- the light-emitting diode 1 is provided with a high resistance layer, forward current does not flow from the strain adjustment layer 8 to the functional substrate 3 made of an n-type GaP substrate.
- the light emitting layer 10 emits light.
- the light emitted from the light emitting layer 10 is emitted from the main light extraction surface.
- the light emitted from the light emitting layer 10 toward the functional substrate 3 is reflected by the shape of the functional substrate 3 and the third electrode 6, and thus is emitted from the main light extraction surface. Therefore, high brightness of the light emitting diode lamp 41 (light emitting diode 1) can be achieved (see FIGS. 2 and 4).
- the emission spectrum of the light-emitting diode lamp 41 has a peak emission wavelength in the range of 655 to 675 nm because the composition of the light-emitting layer 10 is adjusted. Further, since the strain adjustment layer 8 suppresses the variation in the strain amount of the strained light emitting layer 12 in the light emitting layer 10, the half width of the emission spectrum is in the range of 10 to 40 nm. Further, the emission intensity at the emission wavelength of 700 nm is less than 10% of the emission intensity at the peak emission wavelength. Therefore, the light-emitting diode lamp 41 produced using the light-emitting diode 1 can be suitably used as illumination used for promoting photosynthesis for plant growth.
- the light-emitting diode 1 of the present embodiment has a composition formula of (Al X Ga 1-X ) Y In 1-YP (where X and Y are 0 ⁇ X ⁇ 0.1, And the compound semiconductor layer 2 including the light-emitting portion 7 having the strained light-emitting layer 12 which is a numerical value satisfying 0.39 ⁇ Y ⁇ 0.45.
- AlGaInP as the material of the strained light emitting layer 12
- the light emission efficiency and response speed from the light emitting unit 7 can be improved.
- the composition of the strained light emitting layer 12 in the above range, the light emitting diode 1 having an emission wavelength of 655 nm or more can be manufactured.
- the light-emitting diode 1 of the present embodiment is provided with a strain adjustment layer 8 on the light-emitting portion 7. Since the strain adjustment layer 8 is transparent to the emission wavelength, the light-emitting diode 1 with high output and / or high efficiency can be manufactured without absorbing the light emitted from the light-emitting portion 7. Further, since the strain adjustment layer 8 has a lattice constant smaller than that of the GaAs substrate 14, the occurrence of warpage of the semiconductor compound layer 2 can be suppressed. Thereby, since the dispersion
- the present embodiment it is possible to provide the light-emitting diode 1 having a light emission wavelength of 655 nm or more, excellent monochromaticity, high output, and / or high efficiency, and high response speed.
- the light-emitting diode lamp 41 of the present embodiment includes the light-emitting diode 1 having an emission wavelength of 655 nm or more, excellent monochromaticity, high output, and / or high efficiency, and high response speed. . For this reason, the light emitting diode lamp 41 suitable for the illumination for plant cultivation can be provided.
- the light emitting diode manufactured in this example is a red light emitting diode having an AlGaInP light emitting portion.
- a light emitting diode was fabricated by bonding a compound semiconductor layer grown on a GaAs substrate and a functional substrate made of GaP. Then, a light-emitting diode lamp having a light-emitting diode chip mounted on a substrate was prepared for characteristic evaluation.
- Example 1 In the light emitting diode of Example 1, first, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of n-type GaAs single crystal doped with Si. In the GaAs substrate, the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 ⁇ 10 18 cm ⁇ 3 . The layer thickness of the GaAs substrate was about 0.5 ⁇ m.
- the compound semiconductor layer is an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P, Si N-type upper cladding layer made of (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P doped with bismuth , undoped Ga 0.44 In 0.56 P / (Al 0.53 Ga 0.
- strained light emitting layer / barrier layer made of 47 versus the 0.5 in 0.5 P, doped with Mg (Al 0.7 Ga 0.3) p-type lower cladding consisting of 0.5 an in 0.5 P A layer, a thin film intermediate layer made of (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P, and a strain adjusting layer made of Mg-doped p-type GaP.
- a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 ⁇ m using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer.
- MOCVD apparatus metal organic chemical vapor deposition apparatus method
- trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw material for the group III constituent element did.
- biscyclopentadienyl magnesium bis- (C 5 H 5 ) 2 Mg
- disilane Si 2 H 6
- phosphine PH 3
- arsine AsH 3
- the growth temperature of each layer was 750 ° C. for the strain adjustment layer made of p-type GaP; and 700 ° C. for the other layers.
- the buffer layer made of GaAs has a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
- the contact layer had a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 3.5 ⁇ m.
- the upper cladding layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
- the strained light emitting layer is undoped and has a thickness of Ga 0.44 In 0.56 P of about 17 nm
- the barrier layer is undoped and has a thickness of about 19 nm (Al 0.53 Ga 0.47 ) 0.5 In 0. .5 P.
- the lower cladding layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
- the intermediate layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.05 ⁇ m.
- the strain adjusting layer made of GaP has a carrier concentration of about 3 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 9 ⁇ m.
- the strain adjusting layer was polished to a region extending from the surface to a depth of about 1 ⁇ m and mirror-finished. By this mirror finishing, the surface roughness of the strain adjustment layer was set to 0.18 nm.
- a functional substrate made of n-type GaP to be attached to the mirror-polished surface of the strain adjustment layer was prepared. A single crystal having a plane orientation of (111) was added to the functional substrate for sticking to which Si was added so that the carrier concentration was about 2 ⁇ 10 17 cm ⁇ 3 .
- the functional substrate had a diameter of 76 mm and a thickness of 250 ⁇ m.
- the surface of this functional substrate was polished to a mirror surface before being bonded to the strain adjusting layer, and finished to a square average square root value (rms) of 0.12 nm.
- the functional substrate and the epitaxial wafer having the strain adjustment layer were carried into a general semiconductor material pasting apparatus, and the inside of the apparatus was evacuated to 3 ⁇ 10 ⁇ 5 Pa.
- the surface of both the functional substrate and the strain adjustment layer was irradiated with an Ar beam neutralized by colliding electrons for 3 minutes. Thereafter, the surfaces of the functional substrate and the strain adjustment layer were superposed in a sticking apparatus maintained in vacuum, a load was applied so that the pressure on each surface was 50 g / cm 2, and both were bonded at room temperature. In this way, a bonded wafer was formed.
- the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant.
- a first electrode was formed on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 ⁇ m, Pt was 0.2 ⁇ m, and Au was 1 ⁇ m.
- patterning was performed using a general photolithography method, and an n-type ohmic electrode was formed as the first electrode.
- the surface of the light extraction surface which is the surface from which the GaAs substrate was removed, was roughened.
- the epi layer in the region where the p-type ohmic electrode is formed as the second electrode was selectively removed to expose the strain adjustment layer.
- a p-type ohmic electrode was formed on the exposed surface of the strain adjustment layer by vacuum deposition so that AuBe was 0.2 ⁇ m and Au was 1 ⁇ m. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.
- a third electrode for connection of 0.2 ⁇ m thick Au, 0.2 ⁇ m thick Pt, and 1.2 ⁇ m thick AuSn was formed on the back surface of the functional substrate.
- the region where the third electrode is not formed from the back surface of the functional substrate is set so that the angle ⁇ of the inclined surface becomes 70 ° and the thickness of the vertical surface becomes 80 ⁇ m.
- a letter-shaped grooving was performed.
- a dicing saw was used to cut from the compound semiconductor layer side at 350 ⁇ m intervals to form chips. The crushed layer and dirt due to dicing were removed by etching with a sulfuric acid-hydrogen peroxide mixture to produce a light emitting diode of Example 1.
- 100 light-emitting diode lamps each having the light-emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled.
- the light emitting diode chip is heated and supported (mounted) on a mount substrate by a eutectic die bonder, and an n-type ohmic electrode of the light emitting diode and an n electrode terminal provided on the surface of the mount substrate And a p-type ohmic electrode and a p-electrode terminal were wire-bonded with a gold wire, and then sealed with a general epoxy resin.
- the results of evaluating the characteristics of this light emitting diode are shown in Table 1.
- Table 1 when a current was passed between the n-type and p-type ohmic electrodes, red light having a peak wavelength of 660 nm was emitted.
- the light emission output when the forward current was 20 mA was 20 mW.
- the variation (maximum-minimum) of the peak wavelength in all assembled light-emitting diode chips was 2.1 nm.
- the response speed (Tr) of the rise of light emission was 70 ns.
- the light emission spectrum of the light emitting diode lamp of Example 1 has a half width of 18 nm and a light emission intensity at a wavelength of 700 nm of almost 0.
- Example 2 The light emitting diode of Example 2 is obtained by changing only the configurations of the strained light emitting layer and the barrier layer in the light emitting diode of Example 1.
- the strained light emitting layer in Example 1 was changed to Ga 0.42 In 0.58 P having an undoped and thickness of about 10 nm, and the barrier layer in Example 1 was undoped.
- the layer thickness was changed to (Al 0.53 Ga 0.47 ) 0.5 In 0.5 P with a layer thickness of about 30 nm, and 22 pairs of strained light emitting layers and barrier layers were alternately laminated.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 2 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 2 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Example 3 The light-emitting diode of Example 3 is obtained by changing only the configuration of the strained light-emitting layer in the light-emitting diode of Example 2.
- the strained light-emitting layer in Example 2 was changed to Ga 0.41 In 0.59 P with an undoped layer thickness of about 15 nm.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 3 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 3 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Example 4 The light emitting diode of Example 4 is obtained by changing only the configuration of the strained light emitting layer in the light emitting diode of Example 2. Here, in the light emitting diode of Example 4, the well layer in Example 2 was changed to Ga 0.45 In 0.55 P with an undoped and thickness of about 25 nm.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 4 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 4 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Example 5 The light-emitting diode of Example 5 is obtained by changing only the configuration of the strained light-emitting layer in the light-emitting diode of Example 2.
- the strained light-emitting layer in Example 2 was changed to Ga 0.39 In 0.61 P with an undoped layer thickness of about 10 nm.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 5 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Example 5 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Comparative Example 1 The light emitting diode of Comparative Example 1 is obtained by changing the surface layer in the light emitting diode of Example 2 to a layer without distortion.
- the strain adjustment layer in Example 2 was changed to an (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P layer.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp mounted with the light-emitting diode of Comparative Example 1.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp mounted with the light-emitting diode of Comparative Example 1.
- Comparative Example 2 The light emitting diode of Comparative Example 2 is obtained by changing only the configuration of the strained light emitting layer in the light emitting diode of Example 2. Here, in the light emitting diode of Comparative Example 2, the strained light emitting layer in Example 2 was changed to Ga 0.38 In 0.62 P having an undoped and thickness of about 5 nm.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 2 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 2 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Comparative Example 3 The light emitting diode of Comparative Example 3 is obtained by changing only the configuration of the strained light emitting layer in the light emitting diode of Example 2. Here, in the light emitting diode of Comparative Example 3, the composition of the strained light emitting layer in Example 2 was changed to Ga 0.37 In 0.63 P.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 3 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 3 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V 2.2 volts
- the light emission output when the forward current was 20 mA was 5 mW.
- the variation of the peak wavelength in all the assembled light emitting diode lamps was 3.8 nm.
- the response speed (Tr) of the rise of light emission was 45 ns.
- the light emission output was low due to the occurrence of the defects of the strain adjusting layer described above, and the characteristics could not be satisfied.
- Comparative Example 4 The light emitting diode of Comparative Example 4 is obtained by changing only the configuration of the strained light emitting layer in the light emitting diode of Example 1. Here, in the light emitting diode of Comparative Example 4, the composition of the strained light emitting layer in Example 1 was changed to Ga 0.48 In 0.52 P.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 4 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 4 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- the light emitting diode of Comparative Example 5 is obtained by changing only the configurations of the strained light emitting layer and the barrier layer in the light emitting diode of Example 2.
- the strained light emitting layer in Example 2 was changed to Ga 0.44 In 0.56 P with an undoped and thickness of about 30 nm, and the barrier layer in Example 1 was undoped.
- the layer thickness was changed to (Al 0.53 Ga 0.47 ) 0.5 In 0.5 P with a layer thickness of about 30 nm, and 12 pairs of strained light emitting layers and barrier layers were alternately laminated.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 5 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 5 was mounted.
- Vf forward voltage
- mA current of 20 mA
- V voltage
- Tr response speed
- Comparative Example 6 The light emitting diode of Comparative Example 6 was formed by a liquid phase epitaxial method which is a conventional technique. This is a light-emitting diode having a double heterostructure light-emitting portion with an Al 0.35 Ga 0.65 As light-emitting layer on a GaAs substrate.
- the light-emitting diode of Comparative Example 6 was manufactured by forming an n-type upper cladding layer made of Al 0.7 Ga 0.3 As on an n-type (100) GaAs single crystal substrate with a thickness of 20 ⁇ m, Al An undoped light-emitting layer made of 0.35 Ga 0.65 As is 2 ⁇ m, a p-type lower cladding layer made of Al 0.7 Ga 0.3 As is 20 ⁇ m, and Al 0.6 Ga 0 is transparent to the light emission wavelength.
- a p-type thick film layer made of .4 As was prepared by a liquid phase epitaxial method so as to be 120 ⁇ m. After this epitaxial growth, the GaAs substrate was removed.
- an n-type ohmic electrode having a diameter of 100 ⁇ m was formed on the surface of the n-type AlGaAs.
- p-type ohmic electrodes having a diameter of 20 ⁇ m were formed on the back surface of the p-type AlGaAs at intervals of 80 ⁇ m.
- the crushed layer was removed by etching to produce a light emitting diode chip of Comparative Example 6.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 6 was mounted.
- Table 1 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 6 was mounted.
- Vf forward voltage
- mA milliamperes
- V light emission output
- Tr response speed
- the light emitting diode lamp described in the first embodiment is selected, and the lamp is used as a reflector for a lighting device in accordance with the content described in Japanese Patent Application Laid-Open No. 2008-16412.
- a lighting device including a substrate on which a power supply wiring, a through hole, and the like are formed
- Japanese Unexamined Patent Publication No. 2008-16412 is hereby incorporated by reference.
- the light-emitting diode of the present invention achieves red light of 660 nm and high-efficiency, and can be used as a high-power light-emitting diode product that has not been obtained with conventional AlGaAs LEDs, such as a light source for plant growth.
- conventional AlGaAs LEDs such as a light source for plant growth.
Abstract
Description
本願は、2009年3月10日に、日本に出願された特願2009-056780号、及び2009年4月1日に、日本に出願された特願2009-089300号に基づき優先権を主張し、その内容をここに援用する。
そこで、より高輝度の可視LEDを得ることを目的として、また、更なる素子の機械的強度の向上を目的として研究が進められている。すなわち、GaAsのような不透明な基板材料を除去した後、発光を透過できると共に従来の材料よりも機械的強度に優れた透明な材料からなる支持体層を改めて接合させた、いわゆる接合型LEDを構成する技術が開示されている(例えば、特許文献4参照)。一方、発光メカニズムの異なるレーザー素子においては、歪のある発光層について検討されているが、発光ダイオードにおいては、歪のある発光層について実用化されていないのが実状である(例えば、特許文献5参照)。
特に、植物育成用LED照明の実用化のためには、使用電力の低減、コンパクト化、及びコストダウンが強く望まれており、従来の660nmの波長帯の発光ダイオードであるAlGaAs系のLEDに対して、高出力化、高効率化、波長のバラツキ低減、及び/又は高速化等の特性向上が望まれている。
(1) pn接合型の発光部と、前記発光部に積層された歪調整層とを少なくとも含む化合物半導体層を備え、前記発光部は、組成式が(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0≦X≦0.1、及び0.39≦Y≦0.45を満たす数値である)である歪発光層とバリア層との積層構造を有しており、前記歪調整層は、発光波長に対して透明であると共に前記歪発光層及び前記バリア層の格子定数よりも小さい格子定数を有することを特徴とする発光ダイオード。
(2) 前記歪発光層の組成式が、GaYIn1-YP(ここで、Yは0.39≦Y≦0.45を満たす数値である)であることを特徴とする前項1に記載の発光ダイオード。
(3) 前記歪発光層の厚さが、8~30nmの範囲であることを特徴とする前項1又は2に記載の発光ダイオード。
(4) 前記歪発光層が8~40層含まれていることを特徴とする前項1乃至3のいずれか一項に記載の発光ダイオード。
(6) 前記発光部は、前記歪発光層の上面及び下面の一方又は両方にクラッド層を有し、前記クラッド層の組成式が(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0.5≦X≦1、及び0.48≦Y≦0.52を満たす数値である)であることを特徴とする前項1乃至5のいずれか一項に記載の発光ダイオード。
(8) 前記歪調整層の組成式が、AlXGa1-XAs1-YPY(ここで、X及びYは、それぞれ0≦X≦1、及び0.6≦Y≦1を満たす数値である)であることを特徴とする前項1乃至6のいずれか一項に記載の発光ダイオード。
(9) 前記歪調整層の材質が、GaPであることを特徴とする前項1乃至6のいずれか一項に記載の発光ダイオード。
(10) 前記歪調整層の厚さが、0.5~20μmの範囲であることを特徴とする前項1乃至9のいずれか一項に記載の発光ダイオード。
(12) 前記機能性基板が、透明であることを特徴とする前項11に記載の発光ダイオード。
(13) 前記機能性基板の材質がGaPであることを特徴とする前項11又は12に記載の発光ダイオード。
(14) 前記機能性基板の側面が、前記化合物半導体層に近い側において前記光取り出し面に対して略垂直である垂直面と、前記化合物半導体層に遠い側において前記光取り出し面に対して内側に傾斜した傾斜面とを有することを特徴とする前項11乃至13のいずれか一項に記載の発光ダイオード。
前記機能性基板の裏面に設けられた接続用の第3の電極と、をさらに備えることを特徴とする前項11乃至14のいずれか一項に記載の発光ダイオード。
(16) 前記第1及び第2の電極がオーミック電極であることを特徴とする前項15に記載の発光ダイオード。
(17) 前記光取り出し面は、粗い面を含むことを特徴とする前項11乃至16のいずれか一項に記載の発光ダイオード。
(19) 前記発光スペクトルの半値幅が、10~40nmの範囲であることを特徴とする前項18に記載の発光ダイオード。
(20) 前記発光スペクトルの発光波長700nmにおける発光強度が、前記ピーク発光波長における発光強度の10%未満であることを特徴とする前項18又は19に記載の発光ダイオード。
(21) 前記発光部の応答速度(Tr)が、100ns以下であることを特徴とする前項1乃至20のいずれか一項に記載の発光ダイオード。
(23) 前記発光ダイオードの前記光取り出し面側に設けられた前記第1又は第2の電極と、前記第3の電極とが、略同電位に接続されていることを特徴とする前項22に記載の発光ダイオードランプ。
(24) 前項22又は23に記載の発光ダイオードランプを備えることを特徴とする照明装置。
また、本発明の発光ダイオードには、発光部上に歪調整層が設けられている。この歪調整層は、発光波長に対して透明であるため、発光部からの発光を吸収することなく高出力、及び/又は高効率の発光ダイオードとすることができる。さらに、この歪調整層は、GaAs基板の格子定数よりも小さい格子定数を有しているため、この半導体化合物層の反りの発生を抑制することができる。これにより、歪発光層の歪量のばらつきが低減されるため、単色性に優れた発光ダイオードとすることができる。
したがって、本発明によれば、655nm以上の発光波長を有し、単色性に優れると共に、高出力、及び/又は高効率であって応答速度が速い発光ダイオードを提供することができる。また、本発明によれば、従来のAlGaAs系の発光ダイオードと比較して、約4倍以上の発光効率を有する高出力発光ダイオードを提供することができる。
図1及び図2は、本発明を適用した一実施形態である発光ダイオードを用いた発光ダイオードランプを説明するための図であり、図1は平面図、図2は図1中に示すA-A’線に沿った断面図である。
図3及び図4は、本発明を適用した一実施形態である発光ダイオードを説明するための図であり、図3は平面図、図4は図3中に示すB-B’線に沿った断面図である。図3及び図4に示すように、本実施形態の発光ダイオード1は、化合物半導体層2と機能性基板3とが接合された発光ダイオードである。そして、発光ダイオード1は、主たる光取り出し面に設けられたn型オーミック電極(第1の電極)4及びp型オーミック電極(第2の電極)5と、機能性基板3の化合物半導体層2との接合面と反対側に設けられた第3の電極6とを備えて概略構成されている。なお、本実施形態における主たる光取り出し面とは、化合物半導体層2において、機能性基板3を貼り付けた面の反対側の面である。
上述したように、歪発光層12の層厚が薄く、バリア層13の層厚が厚いほうが、歪発光層12の歪をバリア層13によって吸収すると共に、歪発光層12に結晶欠陥が発生しにくい。
図10に、本実施形態の照明装置の一例を斜視図で示す。
図10に示す照明装置100は、回路基板200と、回路基板200に実装された発光ダイオードランプ41と、回路基板200上に設置されたリフレクタ400とから概略構成されている。
回路基板200は、アルミニウムからなる基板本体と、前記基板本体上に積層された絶縁層と、前記絶縁層上に形成されたCu等の導体からなる配線パターンとから概略構成されている。また、この回路基板200は、その一辺200a側がリフレクタ400から突き出されており、これにより回路基板200の表面の一部が露出されている。
また、前記配線パターンは、一対の取出電極パターンと、前記の各取出電極パターンの一端側から回路基板200のほぼ中央に向かって延在する6本の端子電極パターンとから構成されている。前記の各端子電極パターンには、3つの発光ダイオードランプ41がそれぞれ接続されており、これにより各発光ダイオードランプ41が相互に並列に接続されている。また、前記の各取出電極パターンの他端側は、回路基板200の一辺200a側に延在して露出しており、この露出部分が外部端子230cになっている。
反射面420は、図10に示すように、一対の半回転放物面420aと、半回転放物面420a同士の間に配置された放物柱面420bとから構成されている。
また、リフレクタ本体410の厚みは、換言すると光の出射方向に沿う反射面420の高さは、発光ダイオードランプ41のサイズ及び発光ダイオードランプ41同士の間隔によって適宜設定されるが、例えば5.0mm~20.0mmの範囲に設定することが好ましい。
図11には、本実施形態の照明装置の別の例を斜視図で示す。
図11に示す照明装置101は、回路基板102と、回路基板102に実装された発光ダイオードランプ41と、回路基板102上に設置されたリフレクタ104とから概略構成されている。本例の照明装置101には、10列×3列の合計で30個の反射面142を有するリフレクタ104が備えられている。そして、各反射面142の内側には、一つの反射面につき3つの発光ダイオードランプ41が備えられている。照明装置101全体では合計で90個の発光ダイオードランプ41が備えられている。
反射面142の詳細な形状は、先の照明装置100の場合とほぼ同様であり、一対の半回転放物面と、この半回転放物面同士の間に配置された放物柱面とから構成されている。
また、歪調整層8は、発光部7(発光層10)からの発光波長に対して透明である。
さらに、歪調整層8は、歪発光層12及びバリア層13の格子定数よりも小さい格子定数を有している。更にまた、歪調整層8は、化合物半導体層2の形成(エピタキシャル成長による形成)に用いたGaAs基板の格子定数よりも小さい格子定数を有している。より具体的には、後述する組成から得られる歪調整層8の格子定数をA、バリア層13の格子定数をB、歪発光層12の格子定数をCとした場合に、各格子定数は、A<B<Cの関係を有している。
図6に示すように、歪調整層8の格子定数は、基準となるGaAs基板の格子定数より小さい側にある。この状態を-(マイナス)歪とする。これに対して、発光層10における歪発光層12の格子定数は、基準となるGaAs基板の格子定数よりも大きい側にある。これを+(プラス)歪とする。本発明では、歪調整層8に起因する-歪の存在が、発光波長を長波長化するために歪発光層12に導入が必要な+歪のバラツキを小さくする効果があることを見出した。上述したように、歪発光層12の発光波長は、歪発光層12の層厚、組成及び歪量によって決定される。このように、歪発光層12の発光波長に影響を与える要素が多いため、各要素のばらつきの相乗効果によって波長のバラツキが大きくなりやすい傾向がある。
一方、接合面に反射率の高い表面を有する機能性基板も選択できる。例えば、表面に銀、金、銅、若しくはアルミニウムなどの金属基板又は合金基板や、半導体に金属ミラー構造を形成した複合基板なども選択できる。接合による歪の影響がない歪調整層と同じ材質から選択することが、最も望ましい。
また、垂直面3aの幅(厚さ方向)を、30μm~100μmの範囲内とすることが好ましい。垂直面3aの幅を上記範囲内にすることで、機能性基板3の底部で反射された光を垂直面3aにおいて効率よく発光面に戻すことができ、さらには、主たる光取り出し面から放出させることが可能となる。このため、発光ダイオード1の発光効率を高めることができる。
次に、本実施形態の発光ダイオード1の製造方法について説明する。図7は、本実施形態の発光ダイオード1に用いるエピウェーハの断面図である。また、図8は、本実施形態の発光ダイオード1に用いる接合ウェーハの断面図である。
先ず、図7に示すように、化合物半導体層2を作製する。化合物半導体層2は、GaAs基板14上に、GaAsからなる緩衝層15、選択エッチングに利用するために設けられたエッチングストップ層(図示略)、Siをドープしたn型のAlGaInPからなるコンタクト層16、n型の上部クラッド層11、発光層10、p型の下部クラッド層9、及びMgドープしたp型GaPからなる歪調整層8を順次積層して作製する。
次に、化合物半導体層2と機能性基板3とを接合する。化合物半導体層2と機能性基板3との接合は、先ず、化合物半導体層2を構成する歪調整層8の表面を研磨して、鏡面加工する。次に、この鏡面研磨した歪調整層8の表面に貼付する機能性基板3を用意する。
なお、この機能性基板3の表面は、歪調整層8に接合させる以前に鏡面に研磨する。次に、一般の半導体材料貼付装置に、化合物半導体層2と機能性基板3とを搬入し、真空中で鏡面研磨した双方の表面に電子を衝突させて中性(ニュートラル)化したArビームを照射する。その後、真空を維持した貼付装置内で双方の表面を重ね合わせて荷重をかけることで、室温で接合することができる(図8参照)。
次に、第1の電極であるn型オーミック電極4及び第2の電極であるp型オーミック電極5を形成する。n型オーミック電極4及びp型オーミック電極5の形成は、先ず、機能性基板3と接合した化合物半導体層2から、GaAs基板14及び緩衝層15をアンモニア系エッチャントによって選択的に除去する。次に、露出したコンタクト層16の表面にn型オーミック電極4を形成する。具体的には、例えば、AuGe、又はNi合金/Pt/Auを任意の厚さとなるように真空蒸着法により積層した後、一般的なフォトリソグラフィー法を利用してパターニングを行ってn型オーミック電極4の形状を形成する。
次に、機能性基板3の化合物半導体層2との接合面と反対側に第3の電極6を形成する。第3の電極6として銀ペーストを用いる場合は、機能性基板の表面に銀ペーストを塗布する。また、第3の電極として積層構造体を用いる場合は、具体的には、例えば機能性基板3の表面にスパッタ法によって酸化膜として透明導電膜であるITO膜を0.1μm成膜した後に、銀合金膜を0.1μm成膜して反射層を形成する。次に、この反射層の上にバリア層として例えばタングステンを0.1μm成膜する。次に、このバリア層の上にAμを0.5μm、AuSn(共晶:融点283℃)を1μm、及びAuを0.1μm順次成膜して接続層を形成する。そして、通常のフォトリソグラフィー法により、任意の形状にパターニングして第3の電極6を形成する。なお、機能性基板3と第3の電極6とは、光吸収の少ないショットキー接触である。
次に、機能性基板3の形状を加工する。機能性基板3の加工は、先ず、第3の電極6を形成していない表面にV字状の溝入れを行う。この際、V字状の溝の第3の電極6側の内側面が発光面に平行な面とのなす角度αを有する傾斜面3bとなる。次に、化合物半導体層2側から所定の間隔でダイシングを行ってチップ化する。なお、チップ化の際のダイシングによって機能性基板3の垂直面3aが形成される。
次に、上記発光ダイオード1を用いた発光ダイオードランプ41の製造方法、すなわち、発光ダイオード1の実装方法について説明する。
図1及び図2に示すように、マウント基板42の表面に所定の数量の発光ダイオード1を実装する。発光ダイオード1の実装は、先ず、マウント基板42と発光ダイオード1との位置合せを行い、マウント基板42の表面の所定の位置に発光ダイオード1を配置する。次に、第3の電極6を構成する接続層とマウント基板42の表面に設けられたn電極端子43とを共晶金属接合(共晶金属ダイボンド)する。これにより、発光ダイオード1がマウント基板42の表面に固定される。次に、発光ダイオード1のn型オーミック電極4とマウント基板42のn電極端子43とを金線45を用いて接続する(ワイヤボンディング)。次に、発光ダイオード1のp型オーミック電極5とマウント基板42のp電極端子44とを金線46を用いて接続する。最後に、マウント基板42の発光ダイオード1が実装された表面を、一般的なエポキシ樹脂47によって封止する。このようにして、発光ダイオード1を用いた発光ダイオードランプ41を製造する。
先ず、発光ダイオードランプ41に順方向の電圧が印加された場合について説明する。
順方向の電圧が印加された場合に順方向電流は、先ず、陽極に接続されたp型電極端子44から金線46を経てp型オーミック電極5へと流通する。次に、p型オーミック電極5から歪調整層8、下部クラッド層9、発光層10、上部クラッド層11、及びn型オーミック電極4へと順次流通する。次に、n型オーミック電極4から金線45を経て陰極に接続されたn型電極端子43に流通する。なお、発光ダイオード1には高抵抗層が設けられているため、順方向電流は、歪調整層8からn型GaP基板からなる機能性基板3へと流通しない。このように、順方向電流が流れる際に、発光層10から発光する。また、発光層10から発光した光は、主たる光取り出し面から放出される。一方、発光層10から機能性基板3側へと放出された光は、機能性基板3の形状及び第3の電極6によって反射されるため、主たる光取り出し面から放出される。したがって、発光ダイオードランプ41(発光ダイオード1)の高輝度化を達成することができる(図2及び図4を参照)。
実施例1の発光ダイオードは、先ず、Siをドープしたn型のGaAs単結晶からなるGaAs基板上に、化合物半導体層を順次積層してエピタキシャルウェーハを作製した。
GaAs基板は、(100)面から(0-1-1)方向に15°傾けた面を成長面とし、キャリア濃度を2×1018cm-3とした。また、GaAs基板の層厚は、約0.5μmとした。化合物半導体層とは、SiをドープしたGaAsからなるn型の緩衝層、Siをドープした(Al0.7Ga0.3)0.5In0.5Pからなるn型のコンタクト層、Siをドープした(Al0.7Ga0.3)0.5In0.5Pからなるn型の上部クラッド層、アンドープのGa0.44In0.56P/(Al0.53Ga0.47)0.5In0.5Pの対からなる歪発光層/バリア層、Mgをドープした(Al0.7Ga0.3)0.5In0.5Pからなるp型の下部クラッド層、(Al0.5Ga0.5)0.5In0.5Pからなる薄膜の中間層、及びMgドープしたp型GaPからなる歪調整層である。
実施例2の発光ダイオードは、実施例1の発光ダイオードにおける歪発光層及びバリア層の構成だけを変更したものである。ここで、実施例2の発光ダイオードは、上記実施例1における歪発光層をアンドープで層厚が約10nmのGa0.42In0.58Pに変更し、上記実施例1におけるバリア層をアンドープで層厚が約30nmの(Al0.53Ga0.47)0.5In0.5Pに変更し、歪発光層とバリア層とを交互に22対積層した。
また、順方向電流を20mAとした際の発光出力は、18mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、2.3nmであった。発光の立ち上がりの応答速度(Tr)は、68nsであった。
実施例3の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、実施例3の発光ダイオードは、上記実施例2における歪発光層をアンドープで層厚が約15nmのGa0.41In0.59Pに変更した。
また、順方向電流を20mAとした際の発光出力は、19mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、2.5nmであった。発光の立ち上がりの応答速度(Tr)は、71nsであった。
実施例4の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、実施例4の発光ダイオードは、上記実施例2における井戸層をアンドープで層厚が約25nmのGa0.45In0.55Pに変更した。
また、順方向電流を20mAとした際の発光出力は、20mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、2.1nmであった。発光の立ち上がりの応答速度(Tr)は、66nsであった。
実施例5の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、実施例5の発光ダイオードは、上記実施例2における歪発光層をアンドープで層厚が約10nmのGa0.39In0.61Pに変更した。
また、順方向電流を20mAとした際の発光出力は、18mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、2.9nmであった。発光の立ち上がりの応答速度(Tr)は、65nsであった。
比較例1の発光ダイオードは、実施例2の発光ダイオードにおける表面層を歪のない層に変更したものである。ここで、比較例1の発光ダイオードは、上記実施例2における歪調整層を(Al0.7Ga0.3)0.5In0.5P層に変更した。
比較例2の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、比較例2の発光ダイオードは、上記実施例2における歪発光層をアンドープで層厚が約5nmのGa0.38In0.62Pに変更した。
また、順方向電流を20mAとした際の発光出力は、16mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、5.1nmであった。発光の立ち上がりの応答速度(Tr)は、42nsであった。量子効果によって発光波長が655nm未満となり、特性を満足することができなかった。
比較例3の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、比較例3の発光ダイオードは、上記実施例2における歪発光層の組成をGa0.37In0.63Pに変更した。
また、順方向電流を20mAとした際の発光出力は、5mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、3.8nmであった。発光の立ち上がりの応答速度(Tr)は、45nsであった。上述した歪調整層の欠陥の発生により発光出力が低く、特性を満足することができなかった。
比較例4の発光ダイオードは、実施例1の発光ダイオードにおける歪発光層の構成だけを変更したものである。ここで、比較例4の発光ダイオードは、上記実施例1における歪発光層の組成をGa0.48In0.52Pに変更した。
また、順方向電流を20mAとした際の発光出力は、16mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、2.7nmであった。発光の立ち上がりの応答速度(Tr)は、62nsであった。発光波長が655nm未満となり、特性を満足することができなかった。
比較例5の発光ダイオードは、実施例2の発光ダイオードにおける歪発光層及びバリア層の構成だけを変更したものである。ここで、比較例5の発光ダイオードは、上記実施例2における歪発光層をアンドープで層厚が約30nmのGa0.44In0.56Pに変更し、上記実施例1におけるバリア層をアンドープで層厚が約30nmの(Al0.53Ga0.47)0.5In0.5Pに変更し、歪発光層とバリア層とを交互に12対積層した。
また、順方向電流を20mAとした際の発光出力は、3mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、4.1nmであった。発光の立ち上がりの応答速度(Tr)は、43nsであった。欠陥の発生により発光出力が低く、特性を満足することができなかった。
比較例6の発光ダイオードは、従来技術である液相エピタキシャル法で形成した。GaAs基板にAl0.35Ga0.65As発光層とするダブルヘテロ構造の発光部を有する発光ダイオードに変更したものである。
また、順方向電流を20mAとした際の発光出力は、4mWであった。組み立てたすべての発光ダイオードランプにおけるピーク波長のバラツキは、6.7nmであった。出力が低く、また、応答速度(Tr)は、150nsで、特性を満足することができなかった。
前記実施例1~5に記載の発光ダイオードランプのうち、前記実施例1に記載の発光ダイオードランプを選択し、当該ランプを特開2008-16412号公報に記載の内容に準じて照明装置用リフレクタ内に固定し、複数の当該リフレクタを備えた照明装置(電源配線やスルーホール等が形成された基板等を含む)を製作した。ここに特開2008-16412号公報を引用して、本明細書の一部となす。
2・・・化合物半導体層
3・・・機能性基板
3a・・・垂直面
3b・・・傾斜面
4・・・n型オーミック電極(第1の電極)
5・・・p型オーミック電極(第2の電極)
6・・・第3の電極
7・・・発光部
8・・・歪調整層
9・・・下部クラッド層
10・・・発光層
11・・・上部クラッド層
12・・・歪発光層
13・・・バリア層
14・・・GaAs基板
15・・・緩衝層
16・・・コンタクト層
41・・・発光ダイオードランプ
42・・・マウント基板
43・・・n電極端子
44・・・p電極端子
45,46・・・金線
47・・・エポキシ樹脂
α・・・傾斜面と発光面に平行な面とのなす角度
100,101・・・照明装置
Claims (24)
- pn接合型の発光部と、前記発光部に積層された歪調整層とを少なくとも含む化合物半導体層を備え、
前記発光部は、組成式が(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0≦X≦0.1、及び0.39≦Y≦0.45を満たす数値である)である歪発光層とバリア層との積層構造を有しており、
前記歪調整層は、発光波長に対して透明であると共に前記歪発光層及び前記バリア層の格子定数よりも小さい格子定数を有することを特徴とする発光ダイオード。 - 前記歪発光層の組成式が、GaYIn1-YP(ここで、Yは0.39≦Y≦0.45を満たす数値である)であることを特徴とする請求項1に記載の発光ダイオード。
- 前記歪発光層の厚さが、8~30nmの範囲であることを特徴とする請求項1又は2に記載の発光ダイオード。
- 前記歪発光層が8~40層含まれていることを特徴とする請求項1乃至3のいずれか一項に記載の発光ダイオード。
- 前記バリア層の組成式が、(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0.3≦X≦0.7、及び0.48≦Y≦0.52を満たす数値である)であることを特徴とする請求項1乃至4のいずれか一項に記載の発光ダイオード。
- 前記発光部は、前記歪発光層の上面及び下面の一方又は両方にクラッド層を有し、
前記クラッド層の組成式が(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0.5≦X≦1、及び0.48≦Y≦0.52を満たす数値である)であることを特徴とする請求項1乃至5のいずれか一項に記載の発光ダイオード。 - 前記歪調整層の組成式が、(AlXGa1-X)YIn1-YP(ここで、X及びYは、それぞれ0≦X≦1、及び0.6≦Y≦1を満たす数値である)であることを特徴とする請求項1乃至6のいずれか一項に記載の発光ダイオード。
- 前記歪調整層の組成式が、AlXGa1-XAs1-YPY(ここで、X及びYは、それぞれ0≦X≦1、及び0.6≦Y≦1を満たす数値である)であることを特徴とする請求項1乃至6のいずれか一項に記載の発光ダイオード。
- 前記歪調整層の材質が、GaPであることを特徴とする請求項1乃至6のいずれか一項に記載の発光ダイオード。
- 前記歪調整層の厚さが、0.5~20μmの範囲であることを特徴とする請求項1乃至9のいずれか一項に記載の発光ダイオード。
- 前記化合物半導体層の光取り出し面と反対側の面に、機能性基板が接合されていることを特徴とする請求項1乃至10のいずれか一項に記載の発光ダイオード。
- 前記機能性基板が、透明であることを特徴とする請求項11に記載の発光ダイオード。
- 前記機能性基板の材質がGaPであることを特徴とする請求項11又は12に記載の発光ダイオード。
- 前記機能性基板の側面が、前記化合物半導体層に近い側において前記光取り出し面に対して略垂直である垂直面と、前記化合物半導体層に遠い側において前記光取り出し面に対して内側に傾斜した傾斜面とを有することを特徴とする請求項11乃至13のいずれか一項に記載の発光ダイオード。
- 前記化合物半導体層の前記光取り出し面側に設けられた第1及び第2の電極と、
前記機能性基板の裏面に設けられた接続用の第3の電極と、をさらに備えることを特徴とする請求項11乃至14のいずれか一項に記載の発光ダイオード。 - 前記第1及び第2の電極がオーミック電極であることを特徴とする請求項15に記載の発光ダイオード。
- 前記光取り出し面は、粗い面を含むことを特徴とする請求項11乃至16のいずれか一項に記載の発光ダイオード。
- 植物育成の光合成の促進に使用するための発光ダイオードであって、
前記発光部の発光スペクトルのピーク発光波長が、655~675nmの範囲であることを特徴とする請求項1乃至17のいずれかに記載の発光ダイオード。 - 前記発光スペクトルの半値幅が、10~40nmの範囲であることを特徴とする請求項18に記載の発光ダイオード。
- 前記発光スペクトルの発光波長700nmにおける発光強度が、前記ピーク発光波長における発光強度の10%未満であることを特徴とする請求項18又は19に記載の発光ダイオード。
- 前記発光部の応答速度(Tr)が、100ns以下であることを特徴とする請求項1乃至20のいずれか一項に記載の発光ダイオード。
- 請求項1乃至21のいずれか一項に記載の発光ダイオードを備えることを特徴とする発光ダイオードランプ。
- 前記発光ダイオードの前記光取り出し面側に設けられた前記第1又は第2の電極と、前記第3の電極とが、略同電位に接続されていることを特徴とする請求項22に記載の発光ダイオードランプ。
- 請求項22又は23に記載の発光ダイオードランプを備えることを特徴とする照明装置。
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EP2595203A4 (en) * | 2010-07-13 | 2015-09-23 | Showa Denko Kk | LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE LAMP |
US9184345B2 (en) | 2010-07-13 | 2015-11-10 | Showa Denko K.K | Light emitting diode and light emitting diode lamp |
TWI451037B (ja) * | 2012-06-04 | 2014-09-01 |
Also Published As
Publication number | Publication date |
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EP2408027A4 (en) | 2015-05-27 |
US8901584B2 (en) | 2014-12-02 |
TW201041182A (en) | 2010-11-16 |
JP2010239098A (ja) | 2010-10-21 |
KR101419105B1 (ko) | 2014-07-11 |
EP2408027A1 (en) | 2012-01-18 |
CN102414847B (zh) | 2014-09-03 |
CN102414847A (zh) | 2012-04-11 |
KR20110120360A (ko) | 2011-11-03 |
US20120007114A1 (en) | 2012-01-12 |
TWI458120B (zh) | 2014-10-21 |
EP2408027B1 (en) | 2019-05-08 |
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