WO2010073889A1 - 歪補償回路、送信装置、および歪補償方法 - Google Patents
歪補償回路、送信装置、および歪補償方法 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
- H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
- H04L27/367—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
- H04L27/368—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
Definitions
- the present invention relates to a technique for compensating for distortion generated in a signal by an amplifier.
- CDMA Code Division Multiple Access
- OFDM Orthogonal Frequency Division Multiplexing
- the transmission power amplifier mounted in the transmission unit of the wireless communication device is required to suppress the leakage power to the adjacent channel when a signal is amplified. Therefore, the transmission power amplifier is required to maintain linearity up to a very high output level and suppress the spread of the transmission spectrum due to nonlinear distortion.
- a power amplifier having nonlinearity if the back-off is increased, the linearity of the operation region can be maintained, but the efficiency is not good. Conversely, if the back-off is reduced, the efficiency is improved, but the waveform of the output signal is distorted. As a result, the distortion component of the radio transmission signal leaks to the adjacent channel.
- Distortion compensation by the digital predistortion method compensates for nonlinear distortion in the AM / AM characteristic (amplitude characteristic) and AM / PM characteristic (phase characteristic) generated in the power amplifier.
- the distortion compensation circuit obtains the nonlinear characteristic of the power amplifier by digitally comparing the transmission signal and the feedback signal. Then, a distortion compensation coefficient representing the inverse characteristic of the nonlinear characteristic is obtained, and the transmission signal is complex multiplied by the distortion compensation coefficient. The signal obtained by this complex multiplication is input to the power amplifier. As a result, the characteristic of the signal output from the power amplifier becomes nearly linear.
- Japanese Unexamined Patent Application Publication Nos. 2004-32609 and 2008-258714 disclose circuits that compensate for nonlinear distortion by a digital predistortion method.
- the nonlinear distortion compensation circuit described in Japanese Patent Application Laid-Open No. 2004-32609 compensates for nonlinear distortion by multiplying an input signal by a compensation value corresponding to the input amplitude.
- this nonlinear distortion compensation circuit only one distortion compensation coefficient to be skipped is held in advance, and the memory capacity is reduced by interpolating an intermediate distortion compensation coefficient between the held distortion compensation coefficients. .
- the power amplifying device described in Japanese Patent Application Laid-Open No. 2008-258714 performs compensation using compensation data output from a lookup table in accordance with the amplitude of input data.
- the dynamic range of the amplifier is expanded by using different lookup tables for the large signal region and the small signal region according to the amplitude of the input data.
- the compression amount is a compression amount from an ideal linear gain to an actual gain. If the compression amount at the saturation output point is different, the characteristic of the signal output from the power amplifier is different, and therefore the power value of the signal after distortion compensation calculation to be input to the power amplifier is different. Therefore, if the compression amount at the saturation output point is different, the range of numerical values to be expressed as the amplitude of the digital signal is different.
- a digital signal used for distortion compensation by the digital predistortion method is expressed by a predetermined number of bits in the digital circuit.
- the signal amplitude is digitally expressed by a predetermined number of bits
- the accuracy of the expression and the range of numerical values that can be expressed are a trade-off. Increasing the number of bits makes it possible to achieve both the accuracy of expression and the range of numerical values that can be expressed, but increases the circuit scale and cost.
- the nonlinear characteristics of the power amplifier are verified in advance, and the number of bits and the bit format are determined based on the result.
- prior verification is important because the result may be saturated beyond the range that can be expressed and a correct result may not be obtained.
- FIG. 1 is a diagram showing a signed Q13 format in a 16-bit fixed point format.
- this bit format 1 bit is used to represent the code, 2 bits are used to represent the integer part, and 13 bits are used to represent the fractional part. According to this bit format, numerical values in the range of ⁇ 3.99 to +3.99 can be expressed.
- FIG. 2 is a diagram showing a signed Q12 format in a 16-bit fixed point format.
- this bit format 1 bit is used to represent the code, 3 bits are used to represent the integer part, and 12 bits are used to represent the fractional part. According to this bit format, numerical values in the range of ⁇ 7.99 to +7.99... Can be expressed.
- FIG. 3 is a graph showing nonlinear characteristics and signal characteristics after nonlinear distortion compensation in the power amplifier of the first example.
- FIG. 4 is a graph showing nonlinear characteristics and signal characteristics after nonlinear distortion compensation in the power amplifier of the second example. 3 and 4, the horizontal axis represents the input amplitude, and the vertical axis represents the output amplitude. The input amplitude and output amplitude are normalized with an average input amplitude of 1.0.
- the upper limit input amplitude capable of distortion compensation in the input / output characteristics of the power amplifier is about 2.5. And it saturates with the input amplitude 3.5 of a power amplifier. As can be seen from FIG. 3, the amount of compression at the saturation output point of the power amplifier is about 3 dB at the power level.
- the bit format that can be expressed with the highest accuracy is the signed Q13 format in FIG.
- the upper limit input amplitude capable of distortion compensation in the input / output characteristics of the power amplifier is about 2.5.
- saturation occurs at the input amplitude 5.0 of the power amplifier. Therefore, as can be seen from FIG. 4, the amount of compression at the saturation output point of the power amplifier is about 6 dB at the power level.
- the input / output characteristics of the distortion compensation calculation are as shown in FIG.
- This amplitude 5.0 cannot be expressed in the signed Q13 format of FIG.
- the bit format that can represent the amplitude 5.0 with the highest accuracy is the signed Q12 format of FIG.
- the appropriate bit format of the distortion compensation circuit changes depending on the characteristics of the power amplifier, and it may not be possible to perform distortion compensation with a desired accuracy. For example, in order to change the specifications of the power amplifier, the distortion compensation circuit itself must be changed.
- the look-up table is changed according to the amplitude of the input data, but it cannot cope with the change in the characteristics of the power amplifier. Therefore, the entire distortion compensation circuit may need to be changed as the power amplifier is changed.
- An object of the present invention is to provide a technique that makes it possible to apply an appropriate bit format according to the characteristics of an amplifier for distortion compensation of the amplifier.
- a distortion compensation circuit of the present invention is a distortion compensation circuit that compensates for distortion characteristics of an amplifier,
- a distortion compensation coefficient calculating means for calculating a distortion compensation coefficient used for compensation of the distortion characteristics by comparing an input signal and an output signal amplified by the amplifier;
- Distortion compensation calculation means for calculating the distortion compensation for the input signal using the bit format set to be changeable and the distortion compensation coefficient calculated by the distortion compensation coefficient calculation means.
- the transmission device of the present invention is a transmission device that transmits a signal with compensated distortion characteristics, Distortion compensation coefficient calculation means for calculating a distortion compensation coefficient used for compensation of the distortion characteristics by comparing an input signal and a signal obtained by feeding back a transmission signal;
- the distortion compensation calculation is performed on the input signal using the bit format set so as to be changeable and the distortion compensation coefficient calculated by the distortion compensation coefficient calculation means, and the signal after the distortion compensation calculation Distortion compensation calculation means for outputting And an amplifier that generates the transmission signal by amplifying the signal after the distortion compensation calculation output from the distortion compensation calculation means.
- a distortion compensation method of the present invention is a distortion compensation method for compensating for distortion characteristics of an amplifier, By comparing the input signal and the output signal amplified by the amplifier, to calculate a distortion compensation coefficient used for compensation of the distortion characteristics, The distortion compensation calculation is performed on the input signal using the bit format set so as to be changeable and the calculated distortion compensation coefficient.
- FIG. 5 is a block diagram showing a schematic configuration of the distortion compensation circuit according to the present embodiment.
- the distortion compensation circuit 100 includes a distortion compensation coefficient calculation unit 101 and a distortion compensation calculation unit 102.
- the distortion compensation circuit 100 is a circuit that compensates for distortion characteristics of the amplifier 103.
- the distortion compensation coefficient calculation unit 101 calculates a distortion compensation coefficient used for compensation of distortion characteristics by comparing the input signal and the output signal amplified by the amplifier 103.
- the distortion compensation calculation unit 102 calculates distortion compensation for the input signal using the bit format set so as to be changeable and the distortion compensation coefficient calculated by the distortion compensation coefficient calculation unit 101.
- the distortion compensation calculation is performed using the set bit format, it is possible to set an appropriate bit format according to the characteristics of the amplifier 103 and apply the bit format to the distortion compensation. Is possible.
- the above-described distortion compensation circuit 100 of the present embodiment may be configured to determine and set an appropriate bit format by itself or may be configured to be set from the outside.
- the distortion compensation circuit 100 When determining the bit format by itself, the distortion compensation circuit 100 is input to the amplifier 103, which is determined according to the compression amount at the saturation output point of the amplifier 103 based on the distortion compensation coefficient calculated by the distortion compensation coefficient calculation unit 101. What is necessary is just to further comprise a configuration for calculating the maximum amplitude of the distortion-compensated signal and setting the bit format so that the calculated maximum amplitude can be expressed. According to this, since the bit format that can express the maximum amplitude of the signal after distortion compensation input to the amplifier 103 is automatically set, it can be appropriately set according to the characteristics of the amplifier 103 without setting by the user. Various bit formats can be applied to distortion compensation.
- the distortion compensation circuit 100 is capable of expressing the amplitude with the highest accuracy among the plurality of candidates of a predetermined bit format that can express the maximum amplitude. You just have to set it. According to this, it is possible to set a format capable of expressing the maximum amplitude of the signal after distortion compensation input to the amplifier 103 and expressing the amplitude with high accuracy.
- the distortion compensation circuit 100 may adaptively control the bit format used in the nonlinear distortion compensation calculation unit 102 continuously while performing distortion compensation. According to this, when the amplifier 103 is changed or when the characteristic of the amplifier 103 changes, a bit format suitable for the characteristic of the amplifier 103 can be used in accordance with the change or change.
- FIG. 6 is a block diagram showing the configuration of the transmission apparatus according to the first embodiment.
- the transmission device 30 includes a distortion compensation circuit 20, a transmission data generation unit 21, a quadrature modulator 22, a reference signal generation unit 23, and a power amplifier 24.
- the distortion compensation circuit 20 includes an amplitude limiting circuit 1, a nonlinear distortion compensation calculation unit 7, a DAC (Digital-Analog Converter) 13, a nonlinear distortion compensation calculation unit 7, a directional coupler 25, an orthogonal demodulator 26, an ADC (Analog-Digital).
- the digital signal processing operation in the distortion compensation circuit 20 is in a fixed point format.
- the fixed-point format has a narrow range of values that can be expressed compared to the floating-point format, but can be processed at high speed because it is easy to process.
- the amplitude limiting circuit 1 limits the digital quadrature baseband signals I and Q from the transmission data generation unit 21 to be equal to or lower than a certain power threshold value Pth.
- the amplitude limiting circuit 1 may use a general amplitude limiting method. As examples of general amplitude limiting methods, a method using circular clipping and a method using a window function are well known.
- the power values of the orthogonal baseband signals I and Q are calculated, and the amplitude of the signal exceeding the power threshold is limited while maintaining the signal phase.
- the nonlinear distortion compensation calculation unit 7 performs distortion compensation calculation by complex multiplication on the orthogonal baseband signals I ′ and Q ′ whose amplitude is limited by the amplitude limiting circuit 1.
- the signal amplitude is expressed in the bit format S set from the distortion compensation coefficient updating unit 28, and the distortion compensation coefficients K and ⁇ from the distortion compensation coefficient updating unit 28 are used for complex multiplication.
- the DAC 13 generates an analog quadrature baseband signal by converting the quadrature baseband signals I ′′ and Q ′′ after the distortion compensation computation by the nonlinear distortion compensation computation unit 7 to analog signals. Since the orthogonal baseband signals I ′′ and Q ′′ input to the DAC 13 are expressed in the bit format S set from the distortion compensation coefficient update unit 28, the DAC 13 performs a conversion process according to the bit format S.
- the quadrature modulator 22 converts the analog quadrature baseband signal generated by the DAC 13 into a quadrature modulation signal by quadrature modulation using the reference signal from the reference signal generation unit 23.
- the power amplifier 24 amplifies the power of the quadrature modulation signal generated by the quadrature modulator 22 and outputs it as an RF (Radio Frequency) signal. A part of the output of the power amplifier 24 is fed back to the quadrature demodulator 26 via the directional coupler 25.
- RF Radio Frequency
- the quadrature demodulator 26 demodulates the RF signal fed back by the directional coupler 25 into an analog quadrature baseband signal using the reference signal from the reference signal generator 23.
- the ADC 27 generates the digital quadrature baseband feedback signals Ib and Qb by converting the analog quadrature baseband signal from the quadrature demodulator 26 into a digital signal.
- the distortion compensation coefficient update unit 28 compares the digital orthogonal baseband feedback signals Ib and Qb from the ADC 27 with the orthogonal baseband signals I ′ and Q ′ from the amplitude limiting circuit 1 and updates the distortion compensation coefficients K and ⁇ . . Further, the distortion compensation coefficient updating unit 28 calculates the maximum amplitude of the signal after distortion compensation based on the distortion compensation coefficients K and ⁇ , and determines the bit format S so that the maximum amplitude can be expressed. . The distortion compensation coefficients K and ⁇ and the bit format S from the distortion compensation coefficient update unit 28 are notified to the nonlinear distortion compensation calculation unit 7.
- the distortion compensation coefficients K and ⁇ calculated by the distortion compensation coefficient update unit 28 are stored in the memory in the form of distortion compensation coefficients K and ⁇ for the power value.
- the power calculator 6 calculates the power values of the orthogonal baseband signals I ′ and Q ′ from the amplitude limiting circuit 1.
- the nonlinear distortion compensation calculation unit 7 accesses the memory using the power value from the power calculation unit 6 as an address, and acquires distortion compensation coefficients K and ⁇ .
- the distortion compensation coefficients K and ⁇ are used for distortion compensation calculation.
- FIG. 6 shows one configuration example of the present invention, and the present invention can be applied to other configurations.
- quadrature modulation and quadrature demodulation may be performed in a digital manner.
- frequency conversion may be performed instead of quadrature modulation.
- an amplitude value that is a square root of the power value may be calculated, and a distortion compensation coefficient may be obtained using the amplitude value as an address.
- FIG. 7 is a block diagram showing the configuration of the main part of the distortion compensation circuit according to the first embodiment.
- the amplitude limiting circuit 1 of the present embodiment is an example of a circular clipping method.
- the power calculating unit 2, the amplitude limiting determination and coefficient calculating unit 3, the threshold setting unit 4, and the maximum amplitude limiting unit 5 are included.
- the distortion compensation coefficient update unit 28 includes a distortion compensation coefficient calculation unit 9, a distortion compensation coefficient data memory 10, a distortion compensation calculation maximum power value calculation unit 11, and a bit format determination unit 12.
- the amplitude limiting circuit 1 limits the digital orthogonal baseband signals I and Q to the power threshold Pth or less by using a circular clipping method as an example.
- the amplitude limit determination and coefficient calculation unit 3 compares the power value P from the power calculation unit 2 with the power threshold value Pth given from the threshold setting unit 4, and calculates a coefficient that makes the power value P equal to or less than the power threshold value Pth. Calculate and output to the maximum amplitude limiter 5. For example, when the power value P is less than or equal to the power threshold value Pth, the amplitude limit determination and coefficient calculation unit 3 determines not to limit the amplitude and outputs 1 as a multiplication coefficient. On the other hand, when the power value P is larger than the power threshold value Pth, the amplitude limit determination and coefficient calculation unit 3 determines to limit the amplitude, and outputs (Pth / P) 1/2 as a multiplication coefficient.
- the maximum amplitude value limiting unit 5 limits the maximum amplitude value by multiplying each of the I component and Q component of the orthogonal baseband signal by the multiplication coefficient from the amplitude limit determination and coefficient calculation unit 3.
- the nonlinear distortion compensation calculation unit 7 applies the distortion compensation coefficient K, calculated by the distortion compensation coefficient update unit 28 to the orthogonal baseband signals I ′ and Q ′ after the limitation by the amplitude maximum value limiting unit 5.
- Complex multiplication (distortion compensation calculation) based on ⁇ and the bit format control signal S is performed, and the signals I ′′ and Q ′′ after the distortion compensation calculation are output to the DAC 13.
- the DAC 13 recognizes the bit format of the digital signals I ′′ and Q ′′ after the distortion compensation calculation according to the bit format control signal S notified from the bit format determination unit 12.
- the DAC 13 converts the digital signals I ′′ and Q ′′ expressed in the bit format into analog signals and outputs the analog signals to an analog signal processing unit (not shown).
- the analog signal processing unit is not shown in FIG. 7, but is an analog circuit portion including the quadrature modulator 22 and the power amplifier 24 shown in FIG.
- the DAC 13 is a type that can change the bit format of the DAC input unit as appropriate. Therefore, the DAC 13 sets the bit format indicated in the bit format control signal S notified from the bit format determination unit 12, and performs digital-analog conversion at a correct level conforming to the bit format.
- the present invention is not limited to this example.
- the DAC 13 may be a fixed type that cannot change the bit format of the DAC input unit. In that case, the DAC 13 performs conversion processing on the input signal by recognizing that the input signal is a signal of the fixed bit format determined regardless of the bit format of the input signal. Until the signal output from the DAC 13 is input to the power amplifier 24, the level difference due to the difference between the fixed bit format and the bit format of the actual input signal is changed to the bit format notified from the bit format determination unit 12. You may adjust based on.
- the distortion compensation coefficient calculation unit 9 compares the orthogonal baseband input signals I ′ and Q ′ with the orthogonal baseband feedback signals Ib and Qb, in which a part of the output of the power amplifier is modulated into a digital signal, on polar coordinates. An amplitude error and a phase error are calculated, and a distortion compensation coefficient is calculated based on the error. The amplitude error and the phase error on the polar coordinates correspond to the compression amount.
- the distortion compensation coefficient data memory 10 stores the distortion compensation coefficient calculated by the distortion compensation coefficient calculation unit 9 in association with the power value P ′ calculated by the power calculation unit 6.
- the maximum power value calculation unit 11 after distortion compensation calculation refers to the distortion compensation coefficient data memory 10 and calculates the power value after distortion compensation calculation for the power threshold value Pth given from the threshold setting unit 4. Since the input power is limited to the power threshold Pth or less, the power value after the distortion compensation calculation with respect to the power threshold Pth becomes the maximum power value Pmax after the distortion compensation calculation. The maximum power value calculation unit 11 after distortion compensation calculation outputs this maximum power value Pmax to the bit format determination unit 12.
- the bit format determination unit 12 obtains a bit format that can represent the maximum power value Pmax with the highest accuracy among the predetermined number of bits.
- the bit format in which the integer part of the maximum power value Pmax is expressed by the smallest possible number of bits and the remaining number of bits is assigned to the decimal part of the maximum power value Pmax is the most accurate bit format.
- the bit format determination unit 12 notifies the determined bit format information to the nonlinear distortion compensation calculation unit 7 and the DAC 13 as a bit format control signal.
- FIG. 8 is a flowchart showing an example of specific processing for determining the bit format in the first embodiment. Here, a 16-bit fixed-point operation is illustrated, but the processing procedure is the same for other numbers of bits.
- step 201 the bit format determination unit 12 obtains the integer part n of the maximum power value Pmax after the distortion compensation calculation.
- the function floor () shown in step 201 of FIG. 8 is a function that truncates the first decimal place of the argument and returns the maximum integer value less than or equal to the argument. Since the maximum power value Pmax is 0 or more, the integer n is a positive integer including 0.
- bit format determination unit 12 initializes the variable x with 0 in step 202. Subsequently, in step 203, the bit format determination unit 12 obtains a magnitude relationship between the power of 2 and the integer n. This is a process of calculating how many bits are required to represent the integer n.
- bit format determination unit 12 transitions to step 205 to determine the bit format. If 2 x ⁇ n, the bit format determination unit 12 transitions to step 204 to increment the variable x, and returns to step 203.
- n is the smallest number of bits representing the integer part of the maximum power value Pmax. If the integer part is expressed by the smallest possible number of bits and the sign and the fractional part are expressed by the remaining number of bits, the precision of the expressed numerical value becomes the highest.
- step 205 the bit format determination unit 12 obtains a signed Q (16-x-1) format in which the integer part is x bits and the decimal part is (16-x-1) bits.
- bit format may be obtained directly from the integer part of the maximum power value Pmax.
- a table in which an integer part of Pmax is associated with a bit format is prepared in advance, and the bit format may be determined by referring to the table.
- the present embodiment it is possible to adaptively obtain the most accurate bit format that can express the maximum power value for any compression characteristic that varies depending on the power amplifier 24. As a result, it is possible to realize highly accurate distortion compensation without causing saturation due to distortion compensation calculation and minimizing the influence of rounding error.
- the basic configuration of the transmission apparatus according to the second embodiment is the same as that of the transmission apparatus according to the first embodiment shown in FIGS. However, in the first embodiment, the bit format is determined by the processing shown in FIG. 8, but in the second embodiment, the bit format is determined by processing different from that of the first embodiment.
- bit format is determined by the cooperative operation of the distortion-compensated maximum power value calculation unit 11 and the bit format determination unit 12.
- FIG. 9 is a flowchart showing an example of specific processing for determining the bit format in the second embodiment. Here, a 16-bit fixed-point operation is illustrated, but the processing procedure is the same for other numbers of bits.
- step 303 the distortion-compensated maximum power value calculation unit 11 calculates a distortion-compensated maximum power value Pmax expressed in the signed Q (16-x) format selected in step 302.
- bit format determination unit 12 compares the maximum power value Pmax calculated by the distortion-compensated maximum power value calculation unit 11 with 0x4000 in step 304.
- bit format determination unit 12 determines that the Q (16-x + 1) format is used by the nonlinear distortion compensation calculation unit 7 (step 306). If Pmax ⁇ 0x4000, the bit format determination unit 12 increments the variable x in step 305 and then returns to step 302.
- 0x4000 represents a power value in which only the most significant bit among the bits representing the integer part is 1 and the other bits are 0.
- the actual value represented by 0x4000 varies depending on the position of the decimal point.
- the maximum power value Pmax expressed in a certain bit format is 0x4000 or more means that the maximum power value Pmax cannot be expressed unless the bit format or the bit format having more integer bits than the bit format. means. On the contrary, the fact that the maximum power value Pmax expressed in a certain bit format is smaller than 0x4000 means that the maximum power value Pmax can be expressed in a bit format in which one bit of the integer part is less than that bit format. To do.
- the integer part of the maximum power value Pmax is reduced as much as possible by increasing the number of bits of the integer part until the maximum power value Pmax can be expressed from the signed Q14 format. What is necessary is just to obtain a bit format that can be expressed by the number of bits.
- step 306 when the maximum power value Pmax ⁇ 0x4000 is satisfied in step 304, in step 306, if the signed Q (16-x + 1) format is determined using the variable x at that time, the format is determined.
- the bit format can represent the maximum power value Pmax with the highest accuracy.
- bit format can be determined by the same procedure even if the number of bits is other than the above.
- a numerical value in which only the most significant bit among the bits representing the integer part is set to 1 and the other bits are set to 0 may be used.
- the present invention is not limited to this.
- the distortion compensation circuit only needs to have a function that makes it possible to use a bit format that matches the compression characteristics of the power amplifier, and does not necessarily update the bit format adaptively.
- the bit format may be determined only at startup.
- the bit format may be determined at the time of start-up, and thereafter, the bit format may be updated only when a factor that changes the compression characteristics of the power amplifier occurs.
- FIG. 10 is a block diagram showing the configuration of the main part of the distortion compensation circuit according to the third embodiment.
- the distortion compensation circuit according to the third embodiment is replaced with the maximum power value calculation unit 11 after distortion compensation calculation and the bit format determination unit 12 in the distortion compensation circuit according to the first embodiment shown in FIG.
- a bit format control unit 14 is provided. Otherwise, the configuration of the third embodiment is the same as that of the first embodiment.
- Bit format control unit 14 has a bit format set in advance. This bit format setting can be changed as appropriate.
- the bit format control unit 14 notifies the set bit format S to the nonlinear distortion compensation unit 7 and the DAC 13 by a bit format control signal.
- the nonlinear distortion compensator 7 and the DAC 13 use the bit format S notified by the bit format control signal as in the first embodiment.
- the bit format cannot be adaptively changed, but by setting the bit format according to the characteristics of the power amplifier, an appropriate bit with high accuracy that does not cause saturation in distortion compensation calculation.
- the format can be easily applied to amplifier distortion compensation.
- the circuit scale can be reduced when the characteristics of the power amplifier do not vary greatly during operation.
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Abstract
Description
入力信号と前記増幅器で増幅された出力信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出する歪補償係数算出手段と、
変更できるように設定されたビットフォーマットと、前記歪補償係数算出手段で算出された前記歪補償係数とを用いて、前記入力信号に対する前記歪補償の演算を行う歪補償演算手段と、を有している。
入力信号と、送信信号をフィードバックした信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出する歪補償係数算出手段と、
変更できるように設定されたビットフォーマットと、前記歪補償係数算出手段で算出された前記歪補償係数とを用いて、前記入力信号に対して前記歪補償の演算を行い、歪補償演算後の信号を出力する歪補償演算手段と、
前記歪補償演算手段から出力された前記歪補償演算後の信号を増幅することにより、前記送信信号を生成する増幅器と、を有している。
入力信号と前記増幅器で増幅された出力信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出し、
変更できるように設定されたビットフォーマットと、算出した前記歪補償係数とを用いて、前記入力信号に対する前記歪補償の演算を行うものである。
図6は、第1の実施例による送信装置の構成を示すブロック図である。図6を参照すると、送信装置30は、歪補償回路20、送信データ生成部21、直交変調器22、基準信号生成部23、および電力増幅器24を有している。歪補償回路20は、振幅制限回路1、非線形歪補償演算部7、DAC(Digital-Analog Converter)13、非線形歪補償演算部7、方向性結合器25、直交復調器26、ADC(Analog-Digital Converter)27、および歪補償係数更新部28、および電力計算部6を有している。なお、本実施例では、歪補償回路20におけるディジタル信号処理演算は固定小数点形式であるものとする。固定小数点形式は、浮動小数点形式と比べると、表現できる値の範囲が狭いが、処理が容易なので高速な演算が可能である。
第2の実施例による送信装置の基本的な構成は、図5~7に示した第1の実施例による送信装置と同様である。ただし、第1の実施例は、図8に示した処理によりビットフォーマットが決定したが、第2の実施例は、ビットフォーマットを第1の実施例と異なる処理でビットフォーマットを決定する。
第1、2の実施例では、歪補償回路が歪補償を行っている間、ビットフォーマットを適応的に制御する例を示したが、本発明はこれに限定されるものではない。歪補償回路は、電力増幅器のコンプレッション特性に合ったビットフォーマットを使用することを可能にする機能を有していればよく、必ずしも適応的にビットフォーマットを更新するものでなくてもよい。
Claims (21)
- 増幅器の歪特性を補償する歪補償回路であって、
入力信号と前記増幅器で増幅された出力信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出する歪補償係数算出手段と、
変更できるように設定されたビットフォーマットと、前記歪補償係数算出手段で算出された前記歪補償係数とを用いて、前記入力信号に対する前記歪補償の演算を行う歪補償演算手段と、を有する歪補償回路。 - 前記歪補償係数算出手段で算出された前記歪補償係数に基づいて、前記増幅器の飽和出力点におけるコンプレッション量に応じて決まる、前記増幅器へ入力される歪補償後の信号の最大振幅を算出する歪補償演算後最大振幅算出手段と、
前記歪補償演算後最大振幅算出手段で算出された前記最大振幅を表現することができるように前記ビットフォーマットを設定するビットフォーマット決定手段と、を更に有する、請求項1に記載の歪補償回路。 - 前記ビットフォーマット決定手段は、ビットフォーマットの複数の候補のうち、前記最大振幅を表現することができるものの中で最も高い精度で振幅を表現することができるものを設定する、請求項2に記載の歪補償回路。
- 前記ビットフォーマット決定手段は、前記ビットフォーマットを決定するとき、変数xを1ずつインクリメントしていき、2のx乗が前記最大振幅の整数部より大きくなったときの変数xの値を、前記ビットフォーマットの整数部のビット数に確定する、請求項2または3に記載の歪補償回路。
- 前記歪補償演算後最大振幅算出手段は、変数x-1を整数部のビット数とするビットフォーマットで前記最大振幅を表現し、
前記ビットフォーマット決定手段は、前記ビットフォーマットを決定するとき、前記変数xを1ずつインクリメントしていき、前記歪補償演算後最大振幅算出手段によって前記最大振幅が表現された値が、前記歪補償後の信号の振幅を表現するビットのうち最上位ビットだけを1とし他のビットを0とした値よりも小さくなったときの前記変数x-2を、前記ビットフォーマットの整数部のビット数に確定する、請求項2または3に記載の歪補償回路。 - 前記歪補償回路が歪補償を行っている間、前記歪補償演算後最大振幅算出手段と前記ビットフォーマット決定手段が継続的に動作することにより、前記非線形歪補償演算手段で用いるビットフォーマットを適応的に制御する、請求項2から5のいずれか1項に記載の歪補償回路。
- 前記ビットフォーマットは固定小数点形式のビットフォーマットである、請求項1から6のいずれか1項に記載の歪補償回路。
- 歪特性を補償した信号を送信する送信装置であって、
入力信号と、送信信号をフィードバックした信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出する歪補償係数算出手段と、
変更できるように設定されたビットフォーマットと、前記歪補償係数算出手段で算出された前記歪補償係数とを用いて、前記入力信号に対して前記歪補償の演算を行い、歪補償演算後の信号を出力する歪補償演算手段と、
前記歪補償演算手段から出力された前記歪補償演算後の信号を増幅することにより、前記送信信号を生成する増幅器と、を有する送信装置。 - 前記歪補償係数算出手段で算出された前記歪補償係数に基づいて、前記増幅器の飽和出力点におけるコンプレッション量に応じて決まる、前記増幅器へ入力される歪補償後の信号の最大振幅を算出する歪補償演算後最大振幅算出手段と、
前記歪補償演算後最大振幅算出手段で算出された前記最大振幅を表現することができるように前記ビットフォーマットを設定するビットフォーマット決定手段と、を更に有する、請求項8に記載の送信装置。 - 前記ビットフォーマット決定手段は、ビットフォーマットの複数の候補のうち、前記最大振幅を表現することができるものの中で最も高い精度で振幅を表現することができるものを設定する、請求項9に記載の送信装置。
- 前記ビットフォーマット決定手段は、前記ビットフォーマットを決定するとき、変数xを1ずつインクリメントしていき、2のx乗が前記最大振幅の整数部より大きくなったときの変数xの値を、前記ビットフォーマットの整数部のビット数に確定する、請求項9または10に記載の送信装置。
- 前記歪補償演算後最大振幅算出手段は、変数x-1を整数部のビット数とするビットフォーマットで前記最大振幅を表現し、
前記ビットフォーマット決定手段は、前記ビットフォーマットを決定するとき、前記変数xを1ずつインクリメントしていき、前記歪補償演算後最大振幅算出手段によって前記最大振幅が表現された値が、前記歪補償後の信号の振幅を表現するビットのうち最上位ビットだけを1とし他のビットを0とした値よりも小さくなったときの前記変数x-2を、前記ビットフォーマットの整数部のビット数に確定する、請求項9または10に記載の送信装置。 - 前記送信装置が歪補償を行っている間、前記歪補償演算後最大振幅算出手段と前記ビットフォーマット決定手段が継続的に動作することにより、前記非線形歪補償演算手段で用いるビットフォーマットを適応的に制御する、請求項8から12のいずれか1項に記載の送信装置。
- 前記ビットフォーマットは固定小数点形式のビットフォーマットである、請求項8から13のいずれか1項に記載の送信装置。
- 増幅器の歪特性を補償するための歪補償方法であって、
入力信号と前記増幅器で増幅された出力信号とを比較することにより、前記歪特性の補償に用いる歪補償係数を算出し、
変更できるように設定されたビットフォーマットと、算出した前記歪補償係数とを用いて、前記入力信号に対する前記歪補償の演算を行う、
歪補償方法。 - 算出した前記歪補償係数に基づいて、前記増幅器の飽和出力点におけるコンプレッション量に応じて決まる、前記増幅器へ入力される歪補償後の信号の最大振幅を算出し、
算出した前記最大振幅を表現することができるように前記ビットフォーマットを設定する、請求項15に記載の歪補償方法。 - ビットフォーマットの複数の候補のうち、前記最大振幅を表現することができるものの中で最も高い精度で振幅を表現することができるものを、前記ビットフォーマットとして設定する、請求項16に記載の歪補償方法。
- 前記ビットフォーマットを決定するとき、変数xを1ずつインクリメントしていき、2のx乗が前記最大振幅の整数部より大きくなったときの変数xの値を、前記ビットフォーマットの整数部のビット数に確定する、請求項16または17に記載の歪補償方法。
- 前記ビットフォーマットを決定するとき、変数xを1ずつインクリメントしていき、前記変数x-1を整数部のビット数とするビットフォーマットで前記最大振幅を表現した値が、前記歪補償後の信号の振幅を表現するビットのうち最上位ビットだけを1とし他のビットを0とした値よりも小さくなったときの前記変数x-2を、前記ビットフォーマットの整数部のビット数に確定する、請求項16または17に記載の歪補償方法。
- 歪補償を行っている間継続してビットフォーマットを適応的に制御する、請求項15から19のいずれか1項に記載の歪補償方法。
- 前記ビットフォーマットは固定小数点形式のビットフォーマットである、請求項15から20のいずれか1項に記載の歪補償方法。
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