WO2010067516A1 - Soiウェーハの製造方法 - Google Patents
Soiウェーハの製造方法 Download PDFInfo
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- WO2010067516A1 WO2010067516A1 PCT/JP2009/006007 JP2009006007W WO2010067516A1 WO 2010067516 A1 WO2010067516 A1 WO 2010067516A1 JP 2009006007 W JP2009006007 W JP 2009006007W WO 2010067516 A1 WO2010067516 A1 WO 2010067516A1
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- thickness
- oxide film
- soi
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000010438 heat treatment Methods 0.000 claims description 80
- 238000005468 ion implantation Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 10
- 239000012298 atmosphere Substances 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000009826 distribution Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 129
- 239000010410 layer Substances 0.000 description 63
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 8
- 238000011282 treatment Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- -1 oxygen ions Chemical class 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 239000012300 argon atmosphere Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000001698 pyrogenic effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Definitions
- the present invention relates to a method for manufacturing an SOI wafer having an SOI (Silicon On Insulator) structure in which a silicon single crystal layer is formed on an insulator.
- SOI Silicon On Insulator
- the bonding method is a method in which an oxide film is formed on at least one of a bond wafer for forming an SOI layer and a base wafer to be a support substrate, and the bond wafer and the base wafer are bonded to each other through the oxide film and then bonded.
- This is a method of manufacturing an SOI wafer in which an SOI layer is formed on a buried oxide film that is an insulator by thinning the wafer.
- the buried oxide film is formed by growing an oxide film on the wafer before bonding, and the thickness of the oxide film is controlled during the growth of the oxide film before bonding.
- the thickness of the buried oxide film of the SOI wafer can be controlled, and the control range can be widely implemented.
- the bonding tends to be difficult, and defects called voids and blisters tend to occur on the SOI wafer, and the bonding is not performed and the SOI layer is not formed. There was a problem that it was not formed.
- the present invention has been made in view of the above circumstances.
- a method for manufacturing an SOI wafer by subjecting an SOI wafer material having an SOI layer formed on a buried oxide film to a heat treatment that reduces the thickness of the buried oxide film, Deterioration of the in-plane distribution of the buried oxide film caused by non-uniformity of the heat treatment temperature, etc., when the heat treatment is performed to reduce the thickness of the oxide film, is controlled within a predetermined range.
- An object is to manufacture an SOI wafer excellent in thickness uniformity.
- an oxide film is formed on at least one surface of a bond wafer and a base wafer, the bond wafer and the base wafer are bonded together through the formed oxide film, and then the bond wafer is bonded.
- the SOI wafer material obtained by thinning the film is subjected to a heat treatment for reducing the thickness of the buried oxide film on the SOI wafer material in which the SOI layer is formed on the buried oxide film, thereby obtaining an SOI having a predetermined buried oxide film thickness.
- the thickness of the SOI layer of the SOI wafer material subjected to heat treatment for reducing the thickness of the buried oxide film, the thickness of the buried oxide film reduced by the heat treatment, and the thickness of the buried oxide film generated by the heat treatment It is calculated according to the ratio of the in-plane range change amount to the allowable value, and the calculated thickness of the SOI layer is obtained.
- the bond wafer in the SOI wafer material obtained by thinning to provide a method for manufacturing an SOI wafer, comprising performing a heat treatment to reduce the thickness of the buried oxide film.
- the thickness of the SOI layer of the SOI wafer material subjected to the heat treatment for reducing the thickness of the buried oxide film is reduced by the thickness of the buried oxide film reduced by the heat treatment and the in-plane range of the buried oxide film generated by the heat treatment (buried oxide film).
- the value obtained by subtracting the minimum film thickness from the maximum film thickness) and the allowable value of the change amount was obtained by thinning the bond wafer so that the calculated SOI layer thickness was obtained.
- the thickness of the SOI layer of the SOI wafer material by setting the thickness of the buried oxide film reduced by the heat treatment to 40 nm or less.
- An attempt to reduce the thickness exceeding 40 nm requires a high temperature and long time heat treatment, or the thickness of the SOI layer during the heat treatment needs to be extremely thin, which is not practical. Is preferably 40 nm or less.
- the predetermined buried oxide film thickness can be 30 nm or less.
- the method for manufacturing an SOI wafer according to the present invention can be suitably used for manufacturing an SOI wafer having a buried oxide film of 30 nm or less, and produces an SOI wafer excellent in the thickness uniformity of the buried oxide film. be able to.
- the heat treatment for reducing the thickness of the buried oxide film is preferably performed at a temperature of 1000 ° C. or higher in an atmosphere of hydrogen gas, argon gas, or a mixed gas thereof. In this way, the heat treatment for reducing the thickness of the buried oxide film can be performed at a temperature of 1000 ° C. or higher in an atmosphere of hydrogen gas, argon gas, or a mixed gas thereof.
- the SOI wafer material can be produced by an ion implantation separation method. In this manner, an SOI layer with excellent film thickness uniformity can be formed by thinning a bond wafer using an ion implantation separation method to produce an SOI wafer material.
- the in-plane range of the buried oxide film reduced to a predetermined thickness by the heat treatment can be controlled within a desired range.
- An SOI wafer having excellent film thickness uniformity can be provided.
- a bond wafer having an oxide film formed on at least one surface is bonded to a base wafer so that the buried oxide film is thicker than the final target thickness, and then the bond wafer is thinned.
- a method of manufacturing an SOI wafer with few defects such as voids and blisters has been performed by subjecting the obtained SOI wafer material to a heat treatment that reduces the thickness of the buried oxide film.
- this method has a problem in that the in-plane distribution of the buried oxide film is deteriorated due to in-plane non-uniformity such as the heat treatment temperature in the heat treatment for reducing the thickness of the buried oxide film.
- the present inventors have conducted extensive research and found that the deterioration of the in-plane distribution of the buried oxide film also changes according to the thickness of the surface SOI layer. Then, the thickness of the SOI layer of the SOI wafer material according to the ratio between the thickness of the buried oxide film reduced by the heat treatment and the allowable value of the amount of change in the in-plane range of the thickness of the buried oxide film that is changed (deteriorated) by the heat treatment.
- the buried oxide generated by the heat treatment is calculated by performing heat treatment to reduce the thickness of the buried oxide film on the SOI wafer material obtained by thinning the bond wafer so that the calculated SOI layer thickness is obtained.
- the present inventors have found that the amount of change (deterioration) in the in-plane range of the film can be adjusted within a desired range.
- the final thickness of the SOI layer is originally determined by the required specifications according to the purpose of the user using the SOI wafer, but in the process of reducing the buried oxide film during the SOI wafer manufacturing process.
- the thickness of the SOI layer (the thickness of the SOI layer of the SOI wafer material) itself has room to be determined at the discretion of the manufacturer when setting the conditions of the SOI wafer manufacturing process. In particular, since the thickness of the SOI layer can be adjusted according to the required specifications, there is no influence on the degree of freedom in determining the final required film thickness on the user side.
- the thickness of the buried oxide film reduced by the heat treatment and the in-plane range of the buried oxide film generated by the heat treatment are determined.
- the relationship between the ratio of the change amount and the thickness of the SOI layer is calculated.
- An example for obtaining the relationship between the ratio of the thickness of the buried oxide film reduced by the heat treatment to the amount of change in the in-plane range of the buried oxide film generated by the heat treatment and the thickness of the SOI layer will be shown below.
- a mirror-polished wafer made of a silicon single crystal having a diameter of 300 mm is used, and an SOI wafer material (implanted oxide film by heat treatment (implanted ions: hydrogen ions 8 ⁇ 10 16 / cm 2 )) is formed by an ion implantation separation method (implanted ions: hydrogen ions 8 ⁇ 10 16 / cm 2 ) BOX) is manufactured under various conditions, and heat treatment at 1200 ° C. is performed in a 100% argon atmosphere to reduce the thickness of the BOX (buried oxide film). 11 sheets are produced.
- Table 1 shows the measured values of the BOX thickness, BOX thickness range, BOX thickness reduction amount (S), and BOX thickness range change amount (N) before and after the heat treatment to reduce the SOI film thickness and buried oxide film thickness of each sample. Indicates.
- the SOI film thickness and the BOX thickness are average values in the plane, and the BOX thickness range indicates the difference between the maximum value and the minimum value of the in-plane film thickness.
- Table 1 shows the result of calculating d S / N [dB] by the following formula 1 from the ratio (S / N) of the reduction amount (S) of the BOX thickness and the change amount (N) of the BOX thickness range.
- the thickness of the SOI layer (SOI film thickness T) of the SOI wafer material subjected to the heat treatment for reducing the thickness of the buried oxide film is reduced by the thickness of the buried oxide film (BOX thickness reduction amount S) reduced by the heat treatment.
- d S / N [dB] calculated from the ratio to the amount of change (N) in the in-plane range of the buried oxide film generated by the heat treatment is used to have the above correlation.
- the manufacturing method of the present invention after the correlation between d S / N [dB] and the thickness (T) of the SOI layer is obtained will be described in more detail.
- a preferred embodiment of the manufacturing method of the present invention a case where an SOI wafer is manufactured by an ion implantation separation method will be described.
- two mirror-polished wafers made of silicon single crystal are prepared. Of these two silicon wafers, one wafer is a base wafer serving as a support substrate that meets the device specifications, and the other is a bond wafer serving as an SOI layer. Next, an oxide film is formed on at least one of the surfaces. Subsequently, hydrogen ions are implanted into the surface layer portion of the bond wafer to form an ion implantation layer parallel to the wafer surface at an average ion penetration depth. At this time, ions implanted into the bond wafer may be rare gas ions.
- the surface of the bond wafer into which hydrogen ions are implanted is brought into close contact with the base wafer via the oxide film.
- the wafers can be bonded to each other without using an adhesive or the like.
- the bond wafer is thinned to form an SOI layer. Thinning of the bond wafer is performed by, for example, applying an exfoliation heat treatment at a temperature of about 500 ° C. in an inert gas atmosphere, and exfoliating the ion implantation layer formed on the bond wafer by hydrogen ion implantation as a boundary surface.
- the material can be easily manufactured.
- the thickness of the SOI layer depends on the ratio between the thickness of the buried oxide film reduced by the heat treatment performed later and the allowable value of the amount of change in the in-plane range of the buried oxide film generated by the heat treatment.
- the bond wafer is thinned so as to have the calculated thickness of the SOI layer.
- sacrificial oxidation treatment may be performed in order to remove the damaged layer on the separation surface and increase the bonding strength.
- the thinning of the bond wafer can also be performed by grinding / polishing or etching.
- the SOI layer thickness is adjusted by sacrificial oxidation treatment or vapor phase etching.
- the in-plane range of the buried oxide film reduced to the desired thickness can be controlled to the desired range, and finally Can manufacture an SOI wafer excellent in film thickness uniformity of the buried oxide film.
- the SOI wafer manufacturing method of the present invention can be suitably used mainly when manufacturing a product having a buried oxide film thickness of 100 nm or less as a final product.
- a product having a buried oxide film thickness of 100 nm or less As described in Japanese Patent Application Laid-Open No. 2004-221198, when an SOI wafer having a buried oxide film thickness of 100 nm or less is manufactured by a method for controlling the thickness of the oxide film before bonding, voids or Bonding defects called blisters frequently occur and the production yield is extremely reduced. If plasma treatment is performed on the bonding surface, the bonding strength at room temperature increases, so that even if the thickness of the buried oxide film is 100 nm or less, bonding can be performed without generating voids or blisters.
- the minimum thickness limit is about 30 nm, when an SOI wafer having a buried oxide film thickness less than that is manufactured at a high yield, high-temperature heat treatment is performed on the SOI wafer material as in the present invention. It is effective to apply and reduce the thickness of the buried oxide film.
- the thickness of the buried oxide film of the final SOI wafer is 10 nm
- the in-plane uniformity required when the thickness of the buried oxide film is 10 nm is ⁇ 5%
- the allowable in-plane range is 1 nm, but considering the variation between product wafers, the in-plane range is It is preferable to control to half of 0.5 nm.
- the thickness of the buried oxide film of the SOI wafer material can be reduced to about 30 nm by performing plasma treatment on the bonding surface.
- an oxide film of 30 nm is formed and bonded to at least one wafer.
- the in-plane range of the formed oxide film is at least about 0.15 nm at present, it is allowed when the SOI wafer material having a buried oxide film thickness of 30 nm is heat-treated to reduce the thickness by 20 nm.
- the SOI wafer material may be manufactured so that the SOI film thickness of the SOI wafer material (the thickness of the SOI layer when the heat treatment for reducing the thickness of the buried oxide film) is 450 nm.
- the thickness of the SOI layer of the SOI wafer material can be set using the correlation between the SOI layer thickness and d S / N [dB] obtained in advance.
- the thickness S of the buried oxide film is preferably 40 nm or less. It is not practical to reduce the thickness exceeding 40 nm because heat treatment for a long time at a high temperature is required or the thickness of the SOI layer at the time of heat treatment needs to be extremely reduced.
- the thickness of the SOI layer of the SOI wafer material subjected to the heat treatment to reduce the thickness of the buried oxide film the thickness of the buried oxide film reduced by the heat treatment, and the amount of change in the in-plane range of the buried oxide film generated by the heat treatment
- the heat treatment for reducing the thickness of the buried oxide film is performed on the SOI wafer material obtained by thinning the bond wafer so that the calculated thickness of the SOI layer becomes the thickness of the SOI layer.
- the in-plane range of the buried oxide film can be controlled to a desired range, and finally, an SOI wafer excellent in film thickness uniformity of the buried oxide film can be manufactured.
- a thermal oxide film of 35 nm (in-plane range 0.2 nm) is formed on one silicon single crystal wafer (bond wafer), hydrogen ions are implanted through the oxide film, and nitrogen plasma treatment (treatment conditions: room temperature, gas flow rate 115 sccm, pressure) Bonded to the other silicon single crystal wafer (base wafer) subjected to 0.4 Torr (53.3 Pa), output 100 W, 15 seconds) at room temperature, and subjected to heat treatment at 500 ° C. for 30 minutes, and then peeled off by the ion implantation layer. .
- the SOI film thickness of the wafer after peeling was 300 nm, and the thickness of the buried oxide film was 35 nm.
- the SOI wafer material manufactured above was subjected to a thinning heat treatment at 1200 ° C. for 2 hours in a 100% argon atmosphere.
- the thickness of the buried oxide film after the heat treatment was 25.2 nm and the in-plane range was 0.95 nm.
- the SOI film thickness of the wafer after peeling was 140 nm, and the thickness of the buried oxide film was 35 nm.
- a thermal oxide film is formed on the surface of the SOI layer by performing a heat treatment at 900 ° C. in an oxidizing atmosphere, and the thermal oxide film is removed with an HF aqueous solution.
- an SOI wafer material having an SOI film thickness of 100 nm and a buried oxide film thickness of 35 nm was produced.
- the SOI wafer material manufactured above was subjected to a thinning heat treatment at 1200 ° C. for 1 hour in a 100% argon atmosphere.
- the thickness of the buried oxide film after the heat treatment was 24.6 nm and the in-plane range was 3.5 nm.
- the in-plane range of the buried oxide film is increased.
- the target value product standard value
- the SOI film thickness was set to a relatively thin SOI layer.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
Abstract
Description
このように、SOIウェーハを作製する際に埋め込み酸化膜の厚さを減ずるための熱処理を行って埋め込み酸化膜の厚さを調整する方法として、特許文献1、特許文献2の方法が知られている。
40nmを超える厚さを減厚しようとすると、高温長時間の熱処理が必要とされたり、あるいは、熱処理時のSOI層の厚さを極めて薄くする必要があり現実的ではないため、減ずる埋め込み酸化膜の厚さは、40nm以下が好ましい。
このように、本発明のSOIウェーハの製造方法は、30nm以下の埋め込み酸化膜を有するSOIウェーハを製造する場合に好適に利用でき、埋め込み酸化膜の膜厚均一性に優れたSOIウェーハを製造することができる。
このように、埋め込み酸化膜の厚さを減ずる熱処理を、水素ガス、アルゴンガス、またはこれらの混合ガス雰囲気下で1000℃以上の温度で行うことができる。
このように、イオン注入剥離法を用いてボンドウェーハの薄膜化を行いSOIウェーハ材料を作製することによって、膜厚均一性が優れているSOI層を形成することができる。
前述のように、従来、埋め込み酸化膜を最終目標厚さよりも厚くなるよう、少なくとも一方の表面に酸化膜が形成されたボンドウェーハとベースウェーハとを貼り合わせ、その後ボンドウェーハを薄膜化することで得られたSOIウェーハ材料に、埋め込み酸化膜の厚さを減ずる熱処理を行うことによって、ボイドやブリスターといった欠陥の少ないSOIウェーハを作製する方法が行われていた。しかしながら、この方法では、埋め込み酸化膜の厚さを減ずる熱処理における熱処理温度等の面内での不均一性が原因となり、結果として埋め込み酸化膜の面内分布が悪化するという問題が発生した。
以下に、熱処理により減ずる埋め込み酸化膜の厚さと熱処理により発生する埋め込み酸化膜の面内レンジの変化量との比と、SOI層の厚さの関係を求めるための一例を示す。
尚、SOI膜厚及びBOX厚は面内の平均値であり、BOX厚レンジは面内膜厚の最大値と最小値の差を示している。
また、BOX厚の減少量(S)とBOX厚レンジの変化量(N)との比(S/N)から、dS/N[dB]を下記の式1より算出した結果を表1中に示し、dS/N[dB]とSOI膜厚との関係を、図1に記した。
dS/N[dB]=20×log(S/N) (式1)
また、ボンドウェーハの薄膜化は、研削・研磨あるいはエッチング等をすることによっても行うことができる。
(設定条件)
以下のように、熱処理により減ずる埋め込み酸化膜の厚さ(S)と、熱処理により発生する埋め込み酸化膜の面内レンジの変化量の許容値(N)を決定し、dS/N[dB]を算出した。
熱処理により減ずる埋め込み酸化膜の厚さ(S):10nm
熱処理により発生する埋め込み酸化膜の面内レンジの変化量の許容値(N):0.8nm
dS/N[dB]=20×log(10/0.8)=22dB
図1の近似線よりSOIウェーハ材料のSOI膜厚を270nmに設定した。
一方のシリコン単結晶ウェーハ(ボンドウェーハ)に熱酸化膜を35nm(面内レンジ0.2nm)形成し、酸化膜を通して水素イオンを注入し、窒素プラズマ処理(処理条件:室温、ガス流量115sccm、圧力0.4Torr(53.3Pa)、出力100W、15秒)を施した他方のシリコン単結晶ウェーハ(ベースウェーハ)と室温で貼り合わせ、500℃、30分の熱処理を加えてイオン注入層で剥離した。
剥離後のウェーハのSOI膜厚は300nm、埋め込み酸化膜の厚さが35nmであった。
その後、剥離面のダメージ層の除去と貼り合わせ強度を高めるため、酸化性雰囲気下、900℃の熱処理を行ってSOI層表面に熱酸化膜を形成し、形成した熱酸化膜をHF水溶液により除去する処理(犠牲酸化処理)を行うことによって、SOI膜厚270nm、埋め込み酸化膜厚35nmのSOIウェーハ材料を作製した。
上記で製造したSOIウェーハ材料に、100%アルゴン雰囲気下で1200℃、2時間の減厚熱処理を行った。熱処理後の埋め込み酸化膜の厚さは25.2nm、面内レンジ0.95nmであった。
1000℃のパイロジェニック酸化によりSOI表面に熱酸化膜を490nm形成後、HF水溶液にて酸化膜を除去することにより、SOI膜厚を50nmに調整した。
(SOIウェーハ材料の作製)
一方のシリコン単結晶ウェーハ(ボンドウェーハ)に熱酸化膜を35nm(面内レンジ0.2nm)形成し、その酸化膜を通して水素イオン注入し、窒素プラズマ処理(処理条件:室温、ガス流量115sccm、圧力0.4Torr(53.3Pa)、出力100W、15秒)を施した他方のシリコン単結晶ウェーハ(ベースウェーハ)と室温で貼り合わせ、500℃、30分の熱処理を加えてイオン注入層で剥離した。
剥離後のウェーハのSOI膜厚は140nm、埋め込み酸化膜の厚さは35nmであった。その後、剥離面のダメージ層の除去と貼り合わせ強度を高めるため、酸化性雰囲気下、900℃の熱処理を行ってSOI層表面に熱酸化膜を形成し、その熱酸化膜をHF水溶液により除去する処理(犠牲酸化処理)を行う事によって、SOI膜厚100nm、埋め込み酸化膜厚35nmのSOIウェーハ材料を作製した。
上記で製造したSOIウェーハ材料に、100%アルゴン雰囲気下で1200℃、1時間の減厚熱処理を行った。熱処理後の埋め込み酸化膜の厚さは、24.6nm、面内レンジ3.5nmであった。
1000℃のパイロジェニック酸化によりSOI表面に熱酸化膜を110nm形成後、HF水溶液にて酸化膜除去することにより、SOI膜厚を50nmに調整した。
一方、比較例では、埋め込み酸化膜の減厚を行う際のSOI層の厚さの設定に本発明を適用することなく、後の工程の犠牲酸化処理によるSOI膜厚調整を容易にするため、SOI膜厚として比較的薄いSOI層の厚さに設定したが、その結果、熱処理後の埋め込み酸化膜の面内レンジが極めて悪化し、製品の規格値を満足することができなかった。
Claims (5)
- ボンドウェーハとベースウェーハの少なくとも一方の表面に酸化膜を形成し、該形成した酸化膜を介して前記ボンドウェーハとベースウェーハとを貼り合わせ、その後ボンドウェーハを薄膜化することで得られた、埋め込み酸化膜上にSOI層が形成されたSOIウェーハ材料に、前記埋め込み酸化膜の厚さを減ずる熱処理を行うことによって、所定の埋め込み酸化膜厚を有するSOIウェーハを製造する方法において、
前記埋め込み酸化膜の厚さを減ずる熱処理を行うSOIウェーハ材料のSOI層の厚さを、前記熱処理により減ずる埋め込み酸化膜の厚さと、前記熱処理により発生する埋め込み酸化膜の面内レンジの変化量の許容値との比に応じて算出し、該算出されたSOI層の厚さとなるように前記ボンドウェーハを薄膜化して得られたSOIウェーハ材料に、埋め込み酸化膜の厚さを減ずる熱処理を行うことを特徴とするSOIウェーハの製造方法。
- 前記熱処理により減ずる埋め込み酸化膜の厚さを、40nm以下として前記SOIウェーハ材料のSOI層の厚さを算出することを特徴とする請求項1に記載のSOIウェーハの製造方法。
- 前記所定の埋め込み酸化膜厚を、30nm以下とすることを特徴とする請求項1又は請求項2に記載のSOIウェーハの製造方法。
- 前記埋め込み酸化膜の厚さを減ずる熱処理を、水素ガス、アルゴンガス、またはこれらの混合ガス雰囲気下で1000℃以上の温度で行うことを特徴とする請求項1乃至請求項3のいずれか一項に記載のSOIウェーハの製造方法。
- 前記SOIウェーハ材料は、イオン注入剥離法によって作製することを特徴とする請求項1乃至請求項4のいずれか一項に記載のSOIウェーハの製造方法。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242154A (ja) * | 1997-02-24 | 1998-09-11 | Mitsubishi Materials Shilicon Corp | 薄膜半導体基板の表面処理方法 |
JP2000036445A (ja) * | 1998-07-21 | 2000-02-02 | Sumitomo Metal Ind Ltd | 貼り合わせ半導体基板及びその製造方法 |
JP2004221198A (ja) | 2003-01-10 | 2004-08-05 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
JP2006156770A (ja) | 2004-11-30 | 2006-06-15 | Shin Etsu Handotai Co Ltd | 直接接合ウェーハの製造方法及び直接接合ウェーハ |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US6759282B2 (en) * | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
JP2004031715A (ja) * | 2002-06-27 | 2004-01-29 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
CN100418194C (zh) * | 2003-02-19 | 2008-09-10 | 信越半导体股份有限公司 | Soi晶片的制造方法及soi晶片 |
JP4509488B2 (ja) * | 2003-04-02 | 2010-07-21 | 株式会社Sumco | 貼り合わせ基板の製造方法 |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
JP5493345B2 (ja) * | 2008-12-11 | 2014-05-14 | 信越半導体株式会社 | Soiウェーハの製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242154A (ja) * | 1997-02-24 | 1998-09-11 | Mitsubishi Materials Shilicon Corp | 薄膜半導体基板の表面処理方法 |
JP2000036445A (ja) * | 1998-07-21 | 2000-02-02 | Sumitomo Metal Ind Ltd | 貼り合わせ半導体基板及びその製造方法 |
JP2004221198A (ja) | 2003-01-10 | 2004-08-05 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
JP2006156770A (ja) | 2004-11-30 | 2006-06-15 | Shin Etsu Handotai Co Ltd | 直接接合ウェーハの製造方法及び直接接合ウェーハ |
Non-Patent Citations (1)
Title |
---|
See also references of EP2357659A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141127A (ja) * | 2008-12-11 | 2010-06-24 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
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