WO2010061826A1 - リードフレーム、このリードフレームを用いた半導体装置及びその中間製品、並びにこれらの製造方法 - Google Patents
リードフレーム、このリードフレームを用いた半導体装置及びその中間製品、並びにこれらの製造方法 Download PDFInfo
- Publication number
- WO2010061826A1 WO2010061826A1 PCT/JP2009/069814 JP2009069814W WO2010061826A1 WO 2010061826 A1 WO2010061826 A1 WO 2010061826A1 JP 2009069814 W JP2009069814 W JP 2009069814W WO 2010061826 A1 WO2010061826 A1 WO 2010061826A1
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- WIPO (PCT)
- Prior art keywords
- lead frame
- resin
- terminal
- sealed
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 239000013067 intermediate product Substances 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 13
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 28
- 230000001788 irregular Effects 0.000 claims abstract description 17
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000007747 plating Methods 0.000 description 15
- 238000007789 sealing Methods 0.000 description 15
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 229910000510 noble metal Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009407 construction method and process Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/495—Lead-frames or other flat leads
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Definitions
- the present invention relates to a lead frame used in a semiconductor device having improved adhesion to a sealing resin, a semiconductor device using the lead frame, an intermediate product thereof, and a manufacturing method thereof.
- a resist film is formed by performing noble metal plating on a region where a bonding terminal or the like on the surface of a plate-like lead frame material is formed, and etching (1st etching) is performed from the surface side to about half the thickness. After the semiconductor element is mounted, wire bonding is performed, the resin is sealed leaving the back half of the lead frame material, and the adjacent terminals are separated by selectively etching (2nd etching) from the back side to manufacture a semiconductor device. This method is disclosed.
- a semiconductor device manufactured by the method described in Patent Document 1 is characterized in that a terminal independent of a plate-like lead frame material is formed.
- Each terminal is fixed with a sealing resin, and the adhesion strength between the terminal and the sealing resin depends on the contact area between the terminal and the sealing resin.
- the terminal has a circular or square cross section.
- the package thickness and lead frame thickness are reduced, or the standoff (the distance from the bottom surface of the sealing resin to the mounting substrate surface) is increased. Since the adhesion between the resin and the terminal is reduced, the strength of the terminal is not ensured, and the terminal is lost and the reliability of the semiconductor device is lowered.
- the present invention has been made in view of such circumstances, and a lead frame capable of obtaining a highly reliable semiconductor device by improving the adhesion between a terminal and a sealing resin, and the lead frame.
- An object of the present invention is to provide a semiconductor device using the above, an intermediate product thereof, and a manufacturing method thereof.
- the present invention provides the following. (1) Provided with a plurality of terminals having resin-sealed portions, at least one portion of the terminals being resin-sealed is a pentagonal or more polygonal column shape, or at least one notch or groove extending along the vertical direction A lead frame for a semiconductor device, characterized in that the lead frame has a shape of a deformed column having a periphery thereof.
- the resin-sealed portions are in the shape of polygonal columns or irregular columns.
- the plurality of terminals sealed with the resin have two or more different shapes of the polygonal columnar or irregular columnar terminals.
- the terminal has a different cross-sectional shape between the resin-sealed portion and the non-resin-sealed portion.
- the intermediate product of the semiconductor device refers to a product generated in the process of manufacturing a semiconductor device as a final product.
- it refers to a product in which terminals that should protrude to the back side are not separated, and etching or the like is required to separate the back side plate portion using a pre-formed resist film in the final process.
- a plurality of terminals having resin-sealed portions at least one portion of the terminals being resin-sealed is a pentagonal or more polygonal column shape, or at least one notch or groove extending along the vertical direction
- the entire resin-sealed portion is in the shape of a polygonal column or an irregular column.
- the plurality of terminals sealed with the resin have two or more different shapes of the polygonal columnar or irregular columnar terminals.
- An upper terminal forming step of forming an upper terminal which is a polygonal column shape of five or more pentagons on the upper side of the lead frame material, or a deformed column shape having at least one notch or groove extending around in the vertical direction, and the lead frame material
- a semiconductor element is mounted on the element mounting portion, and the upper terminal and the electrode of the semiconductor element are connected by a bonding wire, and then the semiconductor element, the bonding wire, and the upper terminal are sealed with a resin.
- a method for manufacturing an intermediate product of a semiconductor device comprising: an intermediate product forming step for manufacturing a semiconductor device.
- a semiconductor element is mounted on the element mounting portion, and the upper terminal and the electrode of the semiconductor element are connected by a bonding wire, and then the semiconductor element, the bonding wire, and the upper terminal are sealed with a resin.
- a method for manufacturing a semiconductor device comprising: an intermediate product forming step for manufacturing the semiconductor device; and a terminal independent step for making a lower terminal of the intermediate product independent.
- the semiconductor device using the lead frame, the intermediate product thereof, and the manufacturing method thereof at least one of the resin-sealed portions of the terminals extends in a polygonal column shape of five or more corners or in the vertical direction. Since it has a deformed columnar shape having two notches or grooves around it, the contact area between the terminal and the resin can be increased. Therefore, even if the package thickness is reduced, the lead frame thickness is reduced, or the standoff is increased, the terminal bonding strength can be ensured, and terminal loss can be prevented. As a result, the reliability of the semiconductor device as a product can be improved.
- the present invention can be implemented without changing the conventional construction method and process flow by changing the pattern of etching and pressing, and can improve the bonding strength of terminals without adversely affecting the mounting reliability. Can be planned. Furthermore, depending on the case, by changing the shape for each independent terminal, it is possible to partially improve the bonding strength, particularly at the portion where the adhesion with the sealing resin is inferior. In addition, since the shapes of the terminals are different from each other, image recognition of the semiconductor device at the time of wire bonding is facilitated, and wiring errors can be prevented.
- FIG. 1 is a front sectional view of a semiconductor device according to a first embodiment of the present invention.
- (A) is a perspective view of a terminal of the semiconductor device, and
- (B) is a perspective view of a modification thereof.
- FIG. 6 is a front sectional view of a semiconductor device according to a second embodiment of the present invention. It is a perspective view of the terminal of the semiconductor device.
- (A) to (C) are a bottom view and a perspective view of a resin-sealed portion of a terminal of a semiconductor device according to a modification of the first and second embodiments of the present invention.
- (A) is a surface view of a lead frame used in a semiconductor device according to a third embodiment of the present invention
- (B) is an enlarged plan view of terminals of the lead frame
- (C) is a lead frame. It is an expansion perspective view of the terminal of a frame
- (D) is an expansion side view of the corner
- the semiconductor device 10 has a plurality of semiconductor elements 12 mounted on a central element mounting portion 11 and a plurality of semiconductor elements 12 arranged around the semiconductor elements 12.
- a terminal 13 a bonding wire 14 that connects the surface of the terminal 13 and the electrode pad of the semiconductor element 12, and a substantially upper half of the terminal 13, a sealing resin 15 that seals the bonding wire 14 and the semiconductor element 12. is doing.
- the shape of the portion 16 surrounded and encapsulated by the sealing resin 15 in the substantially upper half of the terminal 13 is a hexagonal column shape (an example of a polygonal column shape of pentagon or more), and the exposed portion 18 in the substantially lower half is It is cylindrical.
- the polygonal column shape referred to here does not only refer to the shape of a perfect polygonal column, but also includes a shape in which the central part in the vertical direction is slightly narrower than both ends in the vertical direction.
- the terminal 13 according to the first embodiment of the present invention has a resin-sealed portion 16 having a polygonal columnar shape, so that the contact area with the sealing resin 15 is increased and the terminal 13 is firmly sealed. It is fixed to the resin 15.
- FIG. 2B shows a terminal 13 ′ according to a modification.
- the terminal 13 ′ according to the modification has a deformed column shape in which a groove portion 33 including a plurality of concave portions and convex portions extending in the vertical direction is formed around the resin-sealed portion 16 ′.
- the upper surface (front surface) 19 of the terminal 13 serving as the wire bonding portion is subjected to, for example, gold plating (an example of noble metal plating) on a nickel-plated layer, and the lower surfaces of the terminal 13 and the element mounting portion 11.
- the (bottom surfaces) 21 and 22 are also subjected to gold plating (an example of noble metal plating) on a nickel-plated layer, for example.
- the element mounting portion 11 is about half the thickness of the terminal 13, and the semiconductor element 12 is mounted via the conductive adhesive 23.
- the semiconductor device 25 according to the second embodiment shown in FIGS. 3 and 4 will be described.
- the semiconductor device 25 according to the second embodiment is different from the semiconductor device 10 according to the first embodiment in that the terminals 26 and 27 are arranged in four rows on one side and the terminals 26 having different shapes are provided. 27, the same components are denoted by the same reference numerals, and detailed description thereof is omitted (hereinafter the same).
- the resin-sealed portion 28 of the terminal 26 used in the semiconductor device 25 has a hexagonal column shape, and the hexagonal shape of the upper surface 29 is the same as the cross-sectional shape of the resin-sealed portion 26. That is, the resin-sealed portion 28 has a certain thickness unlike the first embodiment.
- the terminal 27 has a deformed column shape in which a groove portion 33 including a plurality of concave portions and convex portions extending in the vertical direction is formed.
- the exposed portions 30 and 34 are circular in cross section, and the central portion in the vertical direction is slightly thinner than the both ends in the vertical direction, as in the first embodiment.
- the cross-sectional shape of the resin-sealed portions 28 and 32 of the terminals 26 and 27 is changed, and two or more kinds of polygonal columnar shapes or irregular columnar shapes are selected. Terminals with different shapes can be used, and the shape of the wire bonding portion can be changed according to the application.
- the shapes of the resin-sealed portions 16, 28, and 32 are not limited to the shapes exemplified in the semiconductor devices 10 and 25 described above.
- the terminals 13, 26, and 27 have a predetermined terminal height and a predetermined terminal pitch, and the length of the circumference of the cross section is longer than the circumference of a circle or a rectangle, any shape can be applied.
- the contact area between the terminal and the resin can be increased, so that the adhesion between the sealing resin 15 and the terminals 13, 26, 27 is improved.
- a notch or groove 47 is formed as shown in FIG. 5A, and recesses (or grooves) 48 and 49 are formed in the periphery as shown in FIGS. Good.
- reference numerals 50, 51, and 52 denote only portions that are resin-sealed, and the exposed portions are omitted.
- the cross-sectional shape of the exposed portions 18, 30, and 34 is circular, but the present invention is not limited to a circular shape, and is a triangle, a polygon including a quadrangle, an ellipse, an ellipse, or a concave or convex portion around it. Any of the shapes having
- FIG. 6 shows a lead frame 36 (material is copper or copper alloy) used in the semiconductor device according to the third embodiment.
- the lead frame 36 has terminals 37 which are resin-sealed in an area array with the element mounting portion 11 at the center.
- the resin-sealed terminal 37 has a deformed columnar shape in which the cross section is formed by providing a cut-out 38 of a circular arc (1/4 circle) at a rectangular corner. It has become.
- a flat plate 39 is formed as shown in FIG.
- FIG. 7A a plate-like lead frame material 41 is prepared.
- FIG. 7B the pattern 42 on the upper surface 19 of the terminal 13 and the front and back surfaces of the lead frame material 41 are arranged.
- a pattern 43 having the lower surface 21 of the terminal 13 and the lower surface 22 of the element mounting portion 11 is formed.
- a single semiconductor device is described for ease of explanation, but in reality, a plurality of semiconductor devices are formed side by side on a single lead frame material 41.
- the shape of the space portion of the pattern on the upper surface 19 of the terminal 13 is not a circle or a quadrangle, but is a pentagon or more polygon or a shape having one or a plurality of notches or grooves on the periphery. (That is, a region where a wire bonding portion is formed).
- etching resistant plating 44, 45 is performed.
- the etching-resistant plating 44 has a polygon having a pentagon or more or a shape having one or a plurality of notches or grooves around the polygon.
- etching resistant film 46 is attached to the back surface of the lead frame material 41 so that the back surface of the lead frame material 41 is not eroded by the etching solution.
- half etching (1st etching) is performed on the surface side of the lead frame material 41 to form a resin-encapsulated portion 16 (upper half of the terminal 13, upper terminal).
- the cover sheet 46 is removed.
- the cover sheet 46 may be removed at any time before the second etching (2nd etching).
- the lead frame is manufactured through the steps so far.
- the semiconductor element 12 is mounted via the conductive adhesive 23 in the center of the element mounting portion 11 formed by half-etching the lead frame material 41, and the peripheral terminals
- the wire bonding portion formed on the upper surface 19 of 13 and the electrode pad of the semiconductor element 12 are wire bonded.
- the upper half of the lead frame material 41 that is, the portion 16 of the terminal 13 that is resin-sealed, the bonding wire 14, and the semiconductor element 12 are resin-sealed.
- Each terminal 13 is connected by a flat plate in the lower half, which is an intermediate product in the present invention.
- the lower half of the lead frame material 41 is etched (2nd etching) to form exposed portions 18 (lower terminals) on the terminals 13, and each terminal 13 is electrically connected. Make them independent. As a result, the semiconductor device 10 shown in FIG. 1 is obtained.
- the entire resin-sealed portion 16 (that is, from the upper end to the lower end of the resin-sealed portion of the terminal 13) has a polygonal column shape or an irregular column shape, and the sealing resin 15 The more exposed part is cylindrical, but the entire terminal 13 including the part that is not resin-sealed from the upper end to the lower end can also be formed into a polygonal columnar shape or an irregular columnar shape.
- the resin-sealed part 16 of the terminal 13 has a substantially constant thickness.
- the upper part of the element mounting part is half-etched.
- the present invention is not limited to this form, and the element mounting part may be left at the same height as the terminal without being half-etched by 1st etching.
- the periphery of the element mounting portion is also formed in the same shape as the periphery of the terminal.
- the contact area between the terminal and the resin can be enlarged, even if the package thickness is reduced, the lead frame thickness is reduced, or the standoff is increased, Terminal strength can be ensured, and loss of terminals can be prevented. As a result, the reliability of the semiconductor device as a product can be improved.
- SYMBOLS 10 Semiconductor device, 11: Element mounting part, 12: Semiconductor element, 13, 13 ': Terminal, 14: Bonding wire, 15: Sealing resin, 16, 16': Resin-sealed part, 18, 18 ' : Exposed portion, 19: upper surface, 21, 22: lower surface, 23: conductive adhesive, 25: semiconductor device, 26, 27: terminal, 28: resin-sealed portion, 29: upper surface, 30: exposed portion, 32: Resin-sealed portion, 33: Groove portion, 34: Exposed portion, 36: Lead frame, 37: Terminal, 38: Notch, 39: Flat plate, 41: Lead frame material, 42, 43: Pattern, 44, 45: Etching-resistant plating, 46: Cover sheet, 47: Groove, 48, 49: Recess (or groove), 50, 51, 52: Resin-sealed portion
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
(1)樹脂封止される部分を有する複数の端子を備え、前記端子の少なくとも樹脂封止される部分が、五角以上の多角柱状、又は、上下方向に沿ってのびる少なくとも1つの切欠き若しくは溝部を周囲に有する異形柱状であることを特徴とする半導体装置用のリードフレーム。
(3)(1)のリードフレームにおいて、前記樹脂封止される複数の端子が、2種類以上の異なる形状の前記多角柱状又は異形柱状の端子を有する。
(4)(1)のリードフレームにおいて、前記端子は前記樹脂封止される部分と樹脂封止されない部分とで異なる断面形状を有する。
(9)(7)のリードフレームの製造方法において、前記樹脂封止される複数の端子が、2種類以上の異なる形状の前記多角柱状又は異形柱状の端子を有する。
また、本発明は、エッチングやプレスのパターンを変更することで、従来の工法や工程フローを変えることなく実施することができ、実装信頼性に悪影響を与えることなく、端子の接合強度の向上を図ることができる。
さらに、場合によっては、独立端子毎に形状を変えることで、特に封止樹脂との密着が劣る部位の接合強度を部分的に向上させることが可能となる。そのうえ、端子の形状が互いに異なるので、ワイヤボンディングの際の半導体装置の画像認識が容易になり、配線ミスを防止することができる。
このように、本発明の第1の実施形態に係る端子13は、樹脂封止される部分16が多角柱状となっているので、封止樹脂15との接触面積が増加し、強固に封止樹脂15に固定される。
また、図2の(B)には変形例に係る端子13´を示す。変形例に係る端子13´は、樹脂封止される部分16´の周囲に上下方向にのびる複数の凹部及び凸部からなる溝部33が形成された異形柱状となっている。この変形例でもまた、樹脂封止される部分16´をエッチングによって形成することによって、その側面も侵食されて、上下方向の中央部が上下方向の両端部よりも若干細くなる。なお、18´は端子13´の円柱状の露出部分である。
また、前記実施の形態では、素子搭載部の上部がハーフエッチングされているが、この形態に限られず、1stエッチングで素子搭載部をハーフエッチングせずに端子と同じ高さに残してもよい。この場合、素子搭載部の周囲も端子周囲と同じ形状に形成する。これにより、素子搭載部と封止樹脂との密着性が増して、より信頼性が向上する。
本出願は、2008年11月25日出願の日本特許出願(特願2008-299726)に基づくものであり、その内容はここに参照として取り込まれる。
Claims (11)
- 樹脂封止される部分を有する複数の端子を備え、前記端子の少なくとも樹脂封止される部分が、五角以上の多角柱状、又は、上下方向に沿ってのびる少なくとも1つの切欠き若しくは溝部を周囲に有する異形柱状であることを特徴とする半導体装置用のリードフレーム。
- 請求項1記載のリードフレームにおいて、前記樹脂封止される部分の全部が前記多角柱状又は異形柱状である。
- 請求項1記載のリードフレームにおいて、前記樹脂封止される複数の端子が、2種類以上の異なる形状の前記多角柱状又は異形柱状の端子を有する。
- 請求項1記載のリードフレームにおいて、前記端子は前記樹脂封止される部分と樹脂封止されない部分とで異なる断面形状を有する。
- 請求項1記載のリードフレームを有する半導体装置の中間製品。
- 請求項1記載のリードフレームを有する半導体装置。
- 樹脂封止される部分を有する複数の端子を備え、前記端子の少なくとも樹脂封止される部分が、五角以上の多角柱状、又は、上下方向に沿ってのびる少なくとも1つの切欠き若しくは溝部を周囲に有する異形柱状であるリードフレームの製造方法であって、前記多角柱状又は異形柱状の端子を、エッチング加工又はプレス加工によって形成することを特徴とするリードフレームの製造方法。
- 請求項7記載のリードフレームの製造方法において、前記樹脂封止される部分の全部が前記多角柱状又は異形柱状である。
- 請求項7記載のリードフレームの製造方法において、前記樹脂封止される複数の端子が、2種類以上の異なる形状の前記多角柱状又は異形柱状の端子を有する。
- リードフレーム材の上側に五角以上の多角柱状、又は上下方向にのびる少なくとも1つの切欠き若しくは溝部を周囲に有する異形柱状である上側端子を形成する上側端子形成工程と、前記リードフレーム材の素子搭載部に半導体素子を搭載して前記上側端子と前記半導体素子の電極との間をボンディングワイヤで連結した後、前記半導体素子、前記ボンディングワイヤ及び前記上側端子を樹脂封止して中間製品を製造する中間製品形成工程とを有することを特徴とする半導体装置の中間製品の製造方法。
- リードフレーム材の上側に五角以上の多角柱状、又は上下方向にのびる少なくとも1つの切欠き若しくは溝部を周囲に有する異形柱状である上側端子を形成する上側端子形成工程と、前記リードフレーム材の素子搭載部に半導体素子を搭載して前記上側端子と前記半導体素子の電極との間をボンディングワイヤで連結した後、前記半導体素子、前記ボンディングワイヤ及び前記上側端子を樹脂封止して中間製品を製造する中間製品形成工程と、前記中間製品の下側端子を独立させる端子独立工程とを有することを特徴とする半導体装置の製造方法。
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CN200980146480XA CN102224587A (zh) | 2008-11-25 | 2009-11-24 | 引线框、使用该引线框的半导体装置、该半导体装置的中间产品以及它们的制造方法 |
US13/129,649 US8680657B2 (en) | 2008-11-25 | 2009-11-24 | Lead frame, semiconductor apparatus using this lead frame, intermediate product thereof and manufacturing method thereof |
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US8916421B2 (en) * | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
CN104659006B (zh) * | 2013-11-19 | 2017-11-03 | 西安永电电气有限责任公司 | 一种塑封式ipm引线框架结构 |
JP6770853B2 (ja) * | 2016-08-31 | 2020-10-21 | 新光電気工業株式会社 | リードフレーム及び電子部品装置とそれらの製造方法 |
JP6757274B2 (ja) * | 2017-02-17 | 2020-09-16 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
US11211320B2 (en) * | 2019-12-31 | 2021-12-28 | Texas Instruments Incorporated | Package with shifted lead neck |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015668A (ja) * | 1999-07-02 | 2001-01-19 | Mitsubishi Electric Corp | 樹脂封止型半導体パッケージ |
JP2003174136A (ja) * | 2001-12-07 | 2003-06-20 | Aoi Electronics Co Ltd | 樹脂モールド半導体装置 |
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JP3937265B2 (ja) * | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
US7049177B1 (en) * | 2004-01-28 | 2006-05-23 | Asat Ltd. | Leadless plastic chip carrier with standoff contacts and die attach pad |
JP3780122B2 (ja) | 1999-07-07 | 2006-05-31 | 株式会社三井ハイテック | 半導体装置の製造方法 |
JP3778773B2 (ja) | 2000-05-09 | 2006-05-24 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP3668101B2 (ja) * | 2000-07-05 | 2005-07-06 | 三洋電機株式会社 | 半導体装置 |
JP2005303039A (ja) * | 2004-04-13 | 2005-10-27 | Matsushita Electric Ind Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP4091050B2 (ja) * | 2005-01-31 | 2008-05-28 | 株式会社三井ハイテック | 半導体装置の製造方法 |
JP4032063B2 (ja) * | 2005-08-10 | 2008-01-16 | 株式会社三井ハイテック | 半導体装置の製造方法 |
JP4205135B2 (ja) | 2007-03-13 | 2009-01-07 | シャープ株式会社 | 半導体発光装置、半導体発光装置用多連リードフレーム |
JP2008263018A (ja) * | 2007-04-11 | 2008-10-30 | Sumitomo Metal Mining Package Materials Co Ltd | 半導体装置用基板及び半導体装置 |
US20090230524A1 (en) * | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Semiconductor chip package having ground and power regions and manufacturing methods thereof |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015668A (ja) * | 1999-07-02 | 2001-01-19 | Mitsubishi Electric Corp | 樹脂封止型半導体パッケージ |
JP2003174136A (ja) * | 2001-12-07 | 2003-06-20 | Aoi Electronics Co Ltd | 樹脂モールド半導体装置 |
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